JP2009124017A - Ferroelectric memory device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device which can be obtained by a simple process, and to provide a method for manufacturing the same. <P>SOLUTION: A ferroelectric memory device 100 includes: a semiconductor layer 10; a transistor 20 formed on the semiconductor layer 10, and equipped with a diffusion layer 22 configuring a source 22a or a drain 22b and a gate 24; a protection layer 28 formed at the upper part of a diffusion layer 22 and a gate 24, and equipped with an opening 28a at the upper part of the diffusion layer 22; and a ferroelectric capacitor 30 formed by successively laminating a lower electrode layer 32, a ferroelectric layer 34 and an upper electrode layer 36 on the opening 28a. The lower electrode layer 32 is directly connected to the diffusion layer 22. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device and a method for manufacturing the same.

As a ferroelectric capacitor having a stack structure, a structure in which a ferroelectric capacitor is formed on a contact portion connected to one side of a selection transistor and a bit wiring is formed on a contact portion connected to the other side of the selection transistor is known. It has been. However, in this structure, it is necessary to form a contact portion in order to connect the ferroelectric capacitor and the select transistor. For this reason, the manufacturing process may be complicated.
JP 2004-6593 A

  An object of the present invention is to provide a ferroelectric memory device that can be obtained by a simple process and a method for manufacturing the same.

A ferroelectric memory device according to the present invention includes:
A semiconductor layer;
A diffusion layer formed in the semiconductor layer and constituting a source or drain, and a transistor having a gate;
A protective layer formed above the diffusion layer and the gate and having an opening above the diffusion layer;
A ferroelectric capacitor having a lower electrode layer, a ferroelectric layer and an upper electrode layer in the opening, and
The lower electrode layer is directly connected to the diffusion layer.

  The ferroelectric memory device according to the present invention can be obtained by a simple process because the lower electrode layer is directly connected to the diffusion layer.

  In the description of the present invention, the word “upper” is, for example, “forms another specific thing (hereinafter referred to as“ B ”)“ above ”a specific thing (hereinafter referred to as“ A ”)”. Etc. In the description according to the present invention, in the case of this example, the case where B is directly formed on A and the case where B is formed on A via another are included. The word “upward” is used.

In the ferroelectric memory device according to the present invention,
A silicide layer formed above the diffusion layer;
The lower electrode layer may be connected to the diffusion layer through the silicide layer.

In the ferroelectric memory device according to the present invention,
A barrier metal layer may be provided under the lower electrode layer.

In the ferroelectric memory device according to the present invention,
An element isolation region defining a region in which the transistor is formed;
A contact portion formed above the upper electrode layer,
The contact portion may be located above the element isolation region.

In the ferroelectric memory device according to the present invention,
The isolation region may be a trench insulating layer or a semi-recessed LOCOS layer.

A ferroelectric memory device according to the present invention includes:
A semiconductor layer;
An element isolation region formed in the semiconductor layer;
A diffusion layer formed in the semiconductor layer and constituting a source or drain, and a transistor having a gate;
An interlayer insulating layer formed on the transistor;
A ferroelectric capacitor formed in the interlayer insulating layer and having a lower electrode layer, a ferroelectric layer and an upper electrode layer;
And a contact portion formed on the ferroelectric capacitor and above the element isolation region.

In the ferroelectric memory device according to the present invention,
A silicide layer formed in contact with the diffusion layer;
A barrier metal layer formed so as to be in contact with the silicide layer,
The lower electrode layer may be in contact with the barrier metal layer.

In the ferroelectric memory device according to the present invention,
A contact part may not be formed between the lower electrode layer and the diffusion layer.

In the ferroelectric memory device according to the present invention,
The interlayer insulating layer may be formed in the same layer as the transistor.

In the ferroelectric memory device according to the present invention,
The interlayer insulating layer may be a first interlayer insulating layer.

A method for manufacturing a ferroelectric memory device according to the present invention includes:
Forming a transistor having a diffusion layer constituting a source or a drain and a gate in a semiconductor layer;
Forming a protective layer above the semiconductor layer;
In the protective layer, forming an opening above the diffusion layer;
Forming a ferroelectric capacitor by sequentially laminating a lower electrode layer, a ferroelectric layer and an upper electrode layer in the opening, and
The lower electrode layer is formed so as to be directly connected to the diffusion layer.

  Preferred embodiments of the present invention will be described below with reference to the drawings.

1. 1. First embodiment 1.1. 1 is a cross-sectional view schematically showing a ferroelectric memory device 100 according to a first embodiment.

  As shown in FIG. 1, the ferroelectric memory device 100 includes a semiconductor layer 10, a transistor 20, a protective layer 28, and a ferroelectric capacitor 30. The semiconductor device 100 can further include an element isolation region 12, a silicide layer 26, a barrier metal layer 31, and a hydrogen barrier layer 38.

  As the semiconductor layer 10, for example, a single crystal silicon substrate can be used.

  The element isolation region 12 is formed in the semiconductor layer 10. The element isolation region 12 can be formed of, for example, a trench insulating layer, a semi-recessed LOCOS (Local Oxidation of Silicon) layer, and a LOCOS layer. However, the ferroelectric capacitor 30 may be formed above the element isolation region 12. In view of this, it is preferable that the surface is made of a trench insulating layer or a semi-recessed LOCOS layer having high surface flatness. The element isolation region 12 has a function of electrically insulating and isolating the semiconductor layer 10.

  The transistor 20 is formed in a region defined by the element isolation region 12. The transistor has a diffusion layer 22 constituting a source 22a or a drain 22b, and a gate 24. The diffusion layer 22 is, for example, a region where impurities of a predetermined conductivity type are diffused. The gate 24 is formed on the semiconductor layer 10 between the source 22a and the drain 22b. The gate 24 can include, for example, a gate insulating layer 24a, a gate electrode 24b formed on the gate insulating layer 24a, and a sidewall 24c formed on a side surface of the gate electrode 24b. The gate insulating layer 24a and the sidewalls 24c can be made of, for example, silicon oxide. The gate electrode 24b can be made of polysilicon, for example. The transistor 20 has a function of controlling, for example, a current flowing in a channel formed in the semiconductor layer 10 between the source 22a and the drain 22b by the potential applied to the gate electrode 24b.

  The silicide layer 26 is formed on the diffusion layer 22. The silicide layer 26 is made of, for example, a compound of a silicide material such as cobalt, titanium, or nickel and silicon. The thickness of the silicide layer 26 can be set to, for example, 20 nm to 50 nm.

  The protective layer 28 is formed on the gate 22 and the silicide layer 26. The protective layer 28 may be formed on the element isolation region 12. The protective layer 28 can be made of, for example, silicon nitride or silicon oxynitride. The thickness of the protective layer 28 can be set to, for example, 50 nm to 200 nm. The protective layer 28 has a function of preventing the gate 22 from being oxidized by, for example, heat treatment in an oxidizing atmosphere for crystallizing the ferroelectric layer 34 described later. The protective layer 28 has an opening 28 a formed on the silicide layer 26. One opening 28a may be formed above either the source 22a or the drain 22b, or although not shown, one opening 28a may be formed above each of the source 22a and the drain 22b.

  Note that contact holes 52 and 53 described later can be formed in the protective layer 28.

  The ferroelectric capacitor 30 is formed in the opening 28a. The ferroelectric capacitor 30 can be formed on the interlayer insulating layer 40. The ferroelectric capacitor 30 has a lower electrode layer 32, a ferroelectric layer 34, and an upper electrode layer 36.

  The lower electrode layer 32 is formed on the silicide layer 26. The lower electrode layer 32 is directly connected to the diffusion layer 22 through the silicide layer 28. Here, “directly connected” means that the lower electrode layer 32 is electrically connected to the diffusion layer 22 without using, for example, a contact portion or wiring. The width of the lower electrode layer 32 may be larger or smaller than the width of the opening 28a. The lower electrode layer 32 can also be formed on the protective layer 28 as shown. The lower electrode layer 32 can be made of, for example, platinum, iridium, alloys thereof, or conductive oxides thereof. The lower electrode layer 32 may be a single layer of the exemplified materials or a structure in which a plurality of materials are stacked. The thickness of the lower electrode layer 32 can be set to, for example, 50 nm to 500 nm.

  Under the lower electrode layer 32, a barrier metal layer 31 may be formed. The barrier metal layer 31 can be made of, for example, titanium aluminum or titanium aluminum nitride. The thickness of the barrier metal layer 31 can be set to, for example, 50 nm to 100 nm. For example, the barrier metal layer 31 has a function of preventing a substance constituting the lower electrode layer 32 and a substance constituting the silicide layer 26 from reacting with each other. The barrier metal layer 31 has a function of improving the adhesion between the lower electrode layer 32 and the silicide layer 26, for example.

The ferroelectric layer 34 is formed on the lower electrode layer 32. The ferroelectric layer 34 can be made of a perovskite oxide ferroelectric material. The ferroelectric layer 34 is made of, for example, lead zirconate titanate (Pb (Zr, Ti) O ₃ : PZT) or lead zirconate titanate niobate (Pb (Zr, Ti, Nb) O ₃ : PZTN). be able to. The thickness of the ferroelectric layer 34 can be set to, for example, 50 nm to 500 nm.

  The upper electrode layer 36 is formed on the ferroelectric layer 34. The upper electrode layer 36 can be made of, for example, platinum, iridium, alloys thereof, conductive oxides thereof, or the like. The upper electrode layer 36 may be a single layer made of the materials exemplified above, or may have a structure in which a plurality of materials are laminated. The thickness of the upper electrode layer 36 can be set to, for example, 50 nm to 500 nm.

  The hydrogen barrier layer 38 is formed so as to cover the upper surface of the upper electrode layer 36 and the side surfaces of the upper electrode layer 36, the ferroelectric layer 34, the lower electrode layer 32, and the barrier metal layer 31. The hydrogen barrier layer 38 may be formed on the protective layer 28. The hydrogen barrier layer 38 can be made of, for example, aluminum oxide or titanium oxide. The thickness of the hydrogen barrier layer 38 can be set to, for example, 10 nm to 100 nm. The hydrogen barrier layer 38 has a function of protecting the ferroelectric capacitor 30 from reducing species such as hydrogen.

  Note that a contact hole 51 described later can be formed in the hydrogen barrier layer 38.

  The ferroelectric memory device 100 can further include an interlayer insulating layer 40, contact holes 51 to 53, contact barrier layers 61 to 63, contact portions 71 to 73, and wirings 81 to 83.

  The interlayer insulating layer 40 is formed on the entire surface so as to cover the transistor 20 and the ferroelectric capacitor 30. Specifically, the interlayer insulating layer 40 can be formed on the protective layer 28 and the hydrogen barrier layer 38. The interlayer insulating layer 40 can be formed in the same layer as the transistor 20 and can be a first interlayer insulating layer. The interlayer insulating layer 40 can be made of, for example, silicon oxide. The thickness of the interlayer insulating layer 40 can be set to 1 μm to 2 μm, for example.

  The contact hole 51 is formed through the interlayer insulating layer 40 and the hydrogen barrier layer 38 on the upper electrode layer 36. The contact hole 52 is formed through the interlayer insulating layer 40 and the protective layer 28 on the gate electrode 24b. The contact hole 53 is formed through the interlayer insulating layer 40 and the protective layer 28 on the silicide layer 26.

  The contact barrier layers 61 to 63 are respectively formed on the inner surfaces of the contact holes 51 to 53, the upper surface of the upper electrode layer 36 that is the bottom surface of the contact holes 51 to 53, the upper surface of the gate electrode 24b, and the upper surface of the silicide layer 26. The The contact barrier layers 61 to 63 can be made of, for example, titanium nitride. The thickness of the contact barrier layers 61 to 63 can be set to 10 nm to 100 nm, for example. For example, the contact barrier layers 61 to 63 have a function of preventing a substance constituting the contact portions 71 to 73 from reacting with a substance constituting the upper electrode layer 36 and the like. Further, the contact barrier layers 61 to 63 have a function of preventing the contact portions 71 to 73 from being oxidized, for example.

  The contact parts 71 to 73 are formed in the contact holes 51 to 53 covered with the contact barrier layers 61 to 63, respectively. On the contact portions 71 to 73, wirings 81 to 83 are formed, respectively. The contact portions 71 to 73 and the wirings 81 to 83 can be made of a conductive material containing aluminum, for example. By the contact portions 71 to 73, the wirings 81 to 83 can be electrically connected to the upper electrode layer 36, the gate electrode 24b, and the silicide layer 26, respectively.

  The ferroelectric memory device 100 according to the first embodiment has the following features, for example.

  In the ferroelectric memory device 100, the ferroelectric capacitor 30 is formed in the opening 28 a of the protective layer 28, and the lower electrode layer 32 can be directly connected to the diffusion layer 22. That is, the lower electrode layer 32 can be electrically connected to the diffusion layer 22 without using a contact portion or a wiring. Therefore, the ferroelectric memory device 100 has a simple structure and can be formed at low cost.

  The ferroelectric memory device 100 may have a protective layer 28 formed above the diffusion layer 22 and the gate 24. Thereby, for example, the gate 22 can be prevented from being oxidized by heat treatment in an oxidizing atmosphere for crystallization of the ferroelectric layer 34.

  The ferroelectric memory device 100 can have a barrier metal layer 31 under the lower electrode layer 32. Thereby, for example, it is possible to prevent the substance constituting the lower electrode layer 32 from reacting with the substance constituting the silicide layer 26. Further, for example, the adhesion between the lower electrode layer 32 and the silicide layer 26 can be improved.

1.2. Method for Manufacturing Ferroelectric Memory Device According to First Embodiment Next, a method for manufacturing a ferroelectric memory device according to the first embodiment will be described with reference to the drawings. 2 to 8 are cross-sectional views schematically showing the manufacturing process of the ferroelectric memory device 100 according to the first embodiment.

  As shown in FIG. 2, the element isolation region 12 is formed in the semiconductor layer 10. The element isolation region 12 can be formed by, for example, a known STI (Shallow Trench Isolation) method, a semi-recessed LOCOS method, or a LOCOS method. When the ferroelectric capacitor 30 is formed above the element isolation region 12 In view of the above, it is preferable to include a trench insulating layer formed by an STI method having a high surface flatness or a semi-recessed LOCOS layer formed by a semi-recessed LOCOS method.

  Next, the transistor 20 having the diffusion layer 22 and the gate 24 is formed in a region defined by the element isolation region 12. The diffusion layer 22 can be formed by a known technique so as to constitute the source 22a and the drain 22b. The gate 24 can be formed by a known technique so as to include the gate insulating layer 24a, the gate electrode 24b, and the sidewalls 24c.

  Next, a silicide layer 26 is formed on the diffusion layer 22. In forming the silicide layer 26, first, a silicide metal is formed on the entire surface. Thereafter, a heat treatment for causing a silicidation reaction is performed. Then, the silicide layer 26 can be formed by removing the unreacted metal.

  Note that the silicide layer 26 may be formed before the transistor 20 is formed.

  As shown in FIG. 3, a protective layer 28 is formed on the entire surface. The protective layer 28 is formed by, for example, a sputtering method or a CVD (Chemical Vapor Deposition) method.

  As shown in FIG. 4, the protective layer 28 on the silicide layer 26 is patterned to form an opening 28a. The patterning is performed by, for example, a known photolithography technique and etching technique.

  As shown in FIG. 5, a lower electrode layer 32a, a ferroelectric layer 34a, and an upper electrode layer 36a are formed in this order on the entire surface. The lower electrode layer 32a and the upper electrode layer 36a are formed by, for example, a sputtering method, a plating method, or a vacuum evaporation method. The ferroelectric layer 34a is formed by, for example, a sol-gel method, a CVD method, a MOD (Metal Organic Deposition) method, or a sputtering method. The ferroelectric layer 34a can be heat-treated in an oxidizing atmosphere for crystallization. The temperature of the heat treatment can be about 700 ° C., for example. The heat treatment may be performed after patterning the ferroelectric layer 34a.

  Note that the barrier metal layer 31a can be formed on the entire surface before the lower electrode layer 32a is formed. The barrier metal layer 31a is formed by, for example, a sputtering method or a CVD method.

  As shown in FIG. 6, the upper electrode layer 36a, the ferroelectric layer 34a, and the lower electrode layer 32a are patterned to form a ferroelectric capacitor 30 having the upper electrode layer 36, the ferroelectric layer 34, and the lower electrode layer 32. Form. Further, the barrier metal layer 31a is formed by patterning the barrier metal layer 31a. The patterning is performed by, for example, a known photolithography technique and etching technique. The patterning may be performed on the upper electrode layer 36a, the ferroelectric layer 34a, the lower electrode layer 32a, and the barrier metal layer 31a all at once or after the formation of each layer.

  As shown in FIG. 7, a hydrogen barrier layer 38 is formed so as to cover the upper surface of the upper electrode layer 36 and the side surfaces of the upper electrode layer 36, the ferroelectric layer 34, the lower electrode layer layer 32, and the barrier metal layer 31. Form. The hydrogen barrier layer 38 is formed by, for example, an ALCVD (Atomic Layer CVD) method or a CVD method. Although not shown, the hydrogen barrier layer 38 may be formed so as to cover the entire surface of the protective layer 28.

  Next, an interlayer insulating layer 40 is formed on the entire surface so as to cover the transistor 20 and the ferroelectric capacitor 30. The interlayer insulating layer 40 is formed by, for example, a spin coating method.

  As shown in FIG. 8, the interlayer insulating layer 40, the hydrogen barrier layer 38 on the upper electrode layer 36, the protective layer 28 on the gate electrode 24b, and the protective layer 28 on the silicide layer 26 are patterned to form contact holes. 51-53 are formed. The patterning is performed by, for example, a known photolithography technique and etching technique.

  As shown in FIG. 1, the contact barrier layer 61 is formed on the side surfaces of the contact holes 51 to 53, the upper surface of the upper electrode layer 36 that is the bottom surface of the contact holes 51 to 53, the upper surface of the gate electrode 24 b, and the upper surface of the diffusion layer 22. To 63 are formed. The contact barrier layers 61 to 63 are formed by, for example, a sputtering method or a CVD method.

  Next, contact portions 71 to 73 are formed in the contact holes 51 to 53 covered with the contact barrier layers 61 to 63, respectively. The contact parts 71 to 73 are formed by, for example, a sputtering method or a plating method.

  Next, wirings 81 to 83 are formed on the contact portions 71 to 73, respectively. The wirings 81 to 83 are formed by, for example, a sputtering method or a plating method.

  As described above, the ferroelectric memory device 100 can be manufactured.

  The manufacturing method of the ferroelectric memory device 100 according to the first embodiment has the following features, for example.

  According to the method for manufacturing the ferroelectric memory device 100, the ferroelectric capacitor 30 is formed in the opening 28 a of the protective layer 28, and the lower electrode layer 32 is formed so as to be directly connected to the diffusion layer 22. be able to. That is, for example, there is no need to form a contact portion or wiring for electrically connecting the lower electrode layer 32 and the diffusion layer 22. Therefore, the ferroelectric memory device 100 can be manufactured by a simple process.

2. Second Embodiment 2.1. 9. Ferroelectric Memory Device According to Second Embodiment FIG. 9 is a cross-sectional view schematically showing a ferroelectric memory device 200 according to the second embodiment. Hereinafter, substantially the same material as that of the ferroelectric memory device 100 according to the first embodiment is denoted by the same reference numeral, and detailed description thereof is omitted.

  In the ferroelectric memory device 200, as shown in FIG. 9, the ferroelectric capacitor 230 is formed in the first region 201 above the diffusion layer 22 and the second region 202 above the element isolation region 12, and contact is made. Unlike the ferroelectric memory device 100, the portion 71 is formed in the second region 202. Here, for example, the ferroelectric capacitor 30 of the ferroelectric memory device 100 can also be formed in the first region 201 and the second region 202, but the ferroelectric capacitor 230 is, for example, a ferroelectric capacitor. Compared to 30, the ratio formed in the second region 202 is larger. That is, the width of the ferroelectric capacitor 230 can be made larger than that of the ferroelectric capacitor 30, for example.

  The protective layer 28 formed in the second region 202 can have no opening. Therefore, the lower electrode layer 232 formed in the second region 202 has higher surface flatness than the lower electrode layer 232 formed in the first region 201. Accordingly, the ferroelectric layer 234 formed on the lower electrode layer 232 formed in the second region 202 has higher crystallinity than the ferroelectric layer 234 formed in the first region 201, and is reduced. It can be difficult to receive damage from seeds.

  As described above, the element isolation region 12 is preferably formed of a trench insulating layer or a semi-recessed LOCOS layer having a high surface flatness.

  The ferroelectric memory device 200 according to the second embodiment has the following features, for example.

  In the ferroelectric memory device 200, the contact portion 71 can be formed in the second region 202 above the element isolation region 12. The ferroelectric layer 234 formed in the second region 202 is formed on the lower electrode layer 232 having higher flatness than the ferroelectric layer 234 formed in the first region 201. Thereby, for example, even if reducing species or the like is mixed from the contact hole 51 where the contact portion 71 is formed, the ferroelectric layer 234 below the contact portion 71 is not easily damaged and has high reliability. A ferroelectric capacitor 230 can be obtained.

  In the ferroelectric memory device 200, the ferroelectric layer 234 can be formed on the lower electrode layer 232 formed in the second region 202 having a higher surface flatness than the first region 201. Therefore, the ferroelectric layer 234 as a whole can have high crystallinity, and the ferroelectric capacitor 230 with excellent ferroelectric characteristics can be obtained.

  In the ferroelectric memory device 200, the element isolation region 12 may be formed of a trench insulating layer or a semi-recessed LOCOS layer having a high surface flatness. Therefore, the ferroelectric layer 234 can be formed on the lower electrode layer 232 having a high surface flatness.

2.2. Ferroelectric Memory Device According to Second Embodiment The ferroelectric memory device manufacturing method according to the second embodiment includes a ferroelectric capacitor 230, a first region above the diffusion layer 22, and an element isolation region. 12 is basically the same as the manufacturing method of the ferroelectric memory device according to the first embodiment except that the contact portion 71 is formed in the second region above the first region and the contact region 71 is formed in the second region. Therefore, the description is omitted.

  Although the embodiments of the present invention have been described in detail as described above, it will be readily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the scope of the present invention.

1 is a cross-sectional view schematically showing a ferroelectric memory device according to a first embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the manufacturing process of the ferroelectric memory device which concerns on 1st Embodiment. Sectional drawing which shows typically the ferroelectric memory device which concerns on 2nd Embodiment.

Explanation of symbols

10 semiconductor layer, 12 element isolation region, 20 transistor, 22 diffusion layer, 22a source, 22b drain, 24 gate, 24a gate insulating layer, 24b gate electrode, 24c sidewall, 26 silicide layer, 28 protective layer, 28a opening, 30 Ferroelectric capacitor, 31 Barrier metal layer, 32 Lower electrode layer, 34 Ferroelectric layer, 36 Upper electrode layer, 38 Hydrogen barrier layer, 40 Interlayer insulating layer, 51-53 contact hole, 61-63 Contact barrier layer, 71-73 contact portion, 81-83 wiring, 100 ferroelectric memory device, 200 ferroelectric memory device, 201 first region, 202 second region, 230 ferroelectric capacitor, 232 lower electrode layer, 234 ferroelectric Layer, 236 Upper electrode layer

Claims (11)

A semiconductor layer;
A diffusion layer formed in the semiconductor layer and constituting a source or drain, and a transistor having a gate;
A protective layer formed above the diffusion layer and the gate and having an opening above the diffusion layer;
A ferroelectric capacitor having a lower electrode layer, a ferroelectric layer and an upper electrode layer in the opening, and
The ferroelectric memory device, wherein the lower electrode layer is directly connected to the diffusion layer. In claim 1,
A silicide layer formed above the diffusion layer;
The ferroelectric memory device, wherein the lower electrode layer is connected to the diffusion layer through the silicide layer. In claim 1 or 2,
A ferroelectric memory device having a barrier metal layer under the lower electrode layer. In any of claims 1 to 3,
An element isolation region defining a region in which the transistor is formed;
A contact portion formed above the upper electrode layer,
The ferroelectric memory device, wherein the contact portion is located above the element isolation region. In claim 4,
The ferroelectric memory device, wherein the element isolation region includes a trench insulating layer or a semi-recessed LOCOS layer. A semiconductor layer;
An element isolation region formed in the semiconductor layer;
A diffusion layer formed in the semiconductor layer and constituting a source or drain, and a transistor having a gate;
An interlayer insulating layer formed on the transistor;
A ferroelectric capacitor formed in the interlayer insulating layer and having a lower electrode layer, a ferroelectric layer and an upper electrode layer;
A ferroelectric memory device comprising: a contact portion formed on the ferroelectric capacitor and above the element isolation region. In claim 6,
A silicide layer formed in contact with the diffusion layer;
A barrier metal layer formed so as to be in contact with the silicide layer,
The ferroelectric memory device, wherein the lower electrode layer is in contact with the barrier metal layer. In claim 6 or 7,
A ferroelectric memory device, wherein a contact portion is not formed between the lower electrode layer and the diffusion layer. In any of claims 6 to 8,
The ferroelectric memory device, wherein the interlayer insulating layer is formed in the same layer as the transistor. In any of claims 6 to 9,
The ferroelectric memory device, wherein the interlayer insulating layer is a first interlayer insulating layer. Forming a transistor having a diffusion layer constituting a source or a drain and a gate in a semiconductor layer;
Forming a protective layer above the semiconductor layer;
In the protective layer, forming an opening above the diffusion layer;
Forming a ferroelectric capacitor by sequentially laminating a lower electrode layer, a ferroelectric layer, and an upper electrode layer in the opening, and
The method of manufacturing a ferroelectric memory device, wherein the lower electrode layer is formed so as to be directly connected to the diffusion layer.

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