JP2009121978A - Semiconductor testing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing apparatus capable of shortening the total time for self-diagnosis. <P>SOLUTION: The semiconductor testing apparatus has a TSC (tester controller) for performing self-diagnosis of a plurality of devices while testing an object and detects breakdown of the devices. The TSC includes: a calibration performing means for calibrating the plurality of devices; a diagnosis performing means for diagnosing the plurality of devices calibrated by this calibration performing means; a control part for controlling the calibration performing means and the diagnosis performing means; and a plurality of BUSY lines that are installed on the plurality of devices respectively and connected to the TSC. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus having a self-diagnosis function, and more particularly to a semiconductor test apparatus that can shorten the total time of self-diagnosis.

  Generally, a semiconductor test apparatus determines whether a DUT is good or bad based on the output of the DUT obtained by giving a test signal to an IC, LSI, or the like to be tested (hereinafter also referred to as a DUT).

  By the way, such a semiconductor test apparatus has a self-diagnosis function for testing / determining whether each unit operates within a specification range. In other words, the semiconductor test equipment periodically performs self-diagnosis (calibration and diagnosis) to ensure calibration traceability, perform measurement in a state where accuracy is guaranteed, and quickly detect abnormal points in the system. It has been calibrated so that The following is a prior art document of a semiconductor test apparatus having such a self-diagnosis function.

JP 2007-33072 A

  A conventional semiconductor test apparatus will be described below. FIG. 6 is a time chart of calibration and diagnosis performed during a wafer test according to the prior art. As shown in FIG. 6, when an event for executing calibration and diagnosis occurs between Wafer Tests, first, only calibration is executed, and then diagnosis is executed. In other words, calibration and diagnosis need to be executed efficiently in a short time between wafer tests.

FIG. 7 is a time chart of calibration performed during the Wafer Test according to the prior art. In FIG. 7, A calibration is first performed, then B calibration is performed, and C calibration and D calibration are subsequently performed in this order. That is, the execution timings of the calibrations do not overlap each other, and the separated processes are performed one after another. Therefore, while the A calibration is being executed, the B calibration to the D calibration are not performed, and the later-described B card 20 to D card 40 are idle time.

  FIG. 8 is a configuration diagram of a conventional semiconductor test apparatus. A tester controller (hereinafter referred to as “TSC”) 1 controls execution of calibration / diagnosis, and includes a calibration execution means 2 and a diagnosis execution means 3 in addition to a CPU, RAM, and ROM (not shown).

  The calibration execution means 2 executes calibration for each card (reference numeral 10 to numeral 40) described later during the wafer test. The diagnosis execution means 3 executes diagnosis for each card that has been calibrated.

The BUSY line 312 to the BUSY line 315 execute a test program and transmit test data. The BUSY line is used for calibration and diagnosis by self-diagnosis. The BUSY line 312 to the BUSY line 315 share the BUSY line 311.

That is, when the calibration execution means 2 of the TSC1 sends a command to the B card 20, for example, the B card 20 is controlled 4 by the control unit of the TSC1, and in the meantime, another card (for example, the D card 40) uses the BUSY line 311. The TSC 1 cannot control a plurality of cards at the same time.

  FIG. 9 is a time chart of a process using a conventional BUSY line. When controlling each card (code | symbol 10-40), process A411-process D414 are performed in order.

As described above, the conventional semiconductor test apparatus shares the BUSY line 311 with a plurality of cards.

  By the way, if the BUSY line is shared by a plurality of cards as shown in FIG. 8, there is an advantage that the amount of pattern routing can be reduced accordingly.

  However, since calibration and diagnosis need to be performed within a limited time between Wafer Tests, an efficient self-diagnosis has been conventionally required. Also, if the BUSY line is shared as shown in FIG. 8, the TSC1 cannot control a plurality of cards (reference numerals 10 to 40) at the same time, so that other cards operate while one calibration is executed. There is a problem that the total processing time becomes longer due to the unused time.

  The present invention has been made in view of these problems, and an object thereof is to provide a semiconductor test apparatus capable of shortening the total time of self-diagnosis.

In order to achieve such a problem, the invention described in claim 1
In a semiconductor test apparatus that includes a TSC that performs self-diagnosis on a plurality of devices while testing a test object, and detects a failure of the device,
The TSC is
Calibration execution means for calibrating a plurality of the devices;
Diagnosis execution means for diagnosing a plurality of the devices calibrated by the calibration execution means;
A controller for controlling the calibration execution means and the diagnosis execution means;
A plurality of BUSY lines provided in each of the plurality of devices and connected to the TSC.

The invention described in claim 2 is the semiconductor test apparatus described in claim 1,
The calibration execution unit executes calibration in parallel with respect to each of the plurality of devices, and the diagnosis execution unit executes diagnosis in order from the one of the plurality of devices that has been calibrated.

Furthermore, the invention according to claim 3 is the semiconductor test apparatus according to claim 1 or 2,
An overall BUSY line connecting the TSC and the plurality of devices;
The control unit starts or ends calibration and starts or ends diagnosis through the entire BUSY line.

  The present invention has the following effects. Since the BUSY line is mounted for each card, it is possible to provide a semiconductor test apparatus that can shorten the total time of self-diagnosis.

The data transmission apparatus of the present invention will be described below. FIG. 1 is a block diagram of a semiconductor test apparatus according to the present invention. The same components as those in FIG. The BUSY line 512 connects the card A11 and TSC1. Similarly, BUSY lines 513 to 515 connect B card 21, C card 31, D card 41 and TSC 1, respectively. Note that the entire BUSY line 511 may be provided in common with the A card 11 to the D card 41.

Next, the operation of FIG. 1 will be described with reference to the drawings. FIG. 2 is a time chart of a parallel process using a plurality of BUSY lines. The processes A to D in FIG. 2 perform parallel processing as follows by using the BUSY lines 512, 513, 514, and 515 of each card.

That is, the control unit 4 of the TSC 1 monitors the execution state (start and end) of the process A on the BUSY line 512, monitors the execution state of the process B on the BUSY line 513, and displays the execution state of the process C on the BUSY line 514. Monitor the execution status of process D on the BUSY line 515.

The TSC 1 outputs a signal to start calibration or diagnosis for each of the A card 11 to D card 41 using the entire BUSY line 511 at the start of execution in accordance with an instruction from the control unit 4. Further, after completion of the calibration or diagnosis, a signal indicating that the calibration is completed may be output from the card to the TSC 1 again using the entire BUSY line 511.

Further, the control unit 4 of the TSC 1 performs self-diagnosis by setting a flag for performing calibration and diagnosis for each card by using a memory (not shown) of the TSC 1 without using the entire BUSY line 511. You may manage cards. In this case, the entire BUSY line is not particularly necessary.

  After the completion of these processes, the TSC 1 can execute each of the cards (reference numerals 11, 21, 31, and 41) in succession as follows. That is, TSC1 continues process A'611 after completion of process A for card A11, continues process B'612 after completion of process B for card B21, and process C'for card C31. After the completion, the process A′613 is continued, and with respect to the card D41, the process D′ 614 is continued after the process D is finished.

  Thus, by providing the BUSY line in parallel, each process can be performed in parallel. Hereinafter, it will be described that calibration and diagnosis can be performed in parallel by using the parallel process described above.

FIG. 3 is a time chart of calibration performed in parallel processing. By performing the calibrations (711 to 714) corresponding to the cards in parallel, it is possible to reduce the time that was previously idle, and as a result, it is possible to reduce the total execution time of calibration.

FIG. 4 is a time chart of the diagnostic process performed in advance. As a result of the calibration being performed in parallel by the calibration execution means 2, the calibration end times of the cards (reference numerals 11, 21, 31, 41) are different. When the calibration is completed for each card, even if calibration for all the cards is not completed, the diagnosis execution unit 3 executes the diagnosis (811 to 814), thereby The total diagnosis execution time can be shortened. In FIG. 4, since C calibration is completed first, C diagnosis 813 is started first.

  FIG. 5 is a diagram comparing the calibration diagnosis execution time chart of the prior art and the present invention. By executing calibration in parallel between Wafer Tests and further executing diagnosis after the calibration of each card is completed, the total execution time of calibration and diagnosis can be shortened.

  Thus, by using the parallel process, the self-diagnosis calibration and diagnosis can be performed in parallel, and the total time required for the self-diagnosis can be shortened.

In the present invention, the semiconductor test apparatus is shown as an example. However, the present invention is not necessarily limited to this, and the present invention can be applied to any test apparatus that requires a series of processes such as calibration and diagnosis.

Further, when resources common to the respective cards are used in TSC1, the desired effect is not always obtained as parallel processing as in the present invention. However, even in such a case, if the time during which the common resource is used is short, the effect similar to the present invention can be obtained, and in any case, the total execution time of the calibration / diagnosis can be shortened. be able to.

It is a block diagram of the semiconductor test apparatus by this invention. It is a time chart of a parallel process using a plurality of BUSY lines. It is a time chart of the calibration performed by parallel processing. It is a time chart of the diagnostic process performed in advance. It is the figure which compared the prior art and the calibration diagnosis execution time chart of this invention. It is a time chart of the calibration and diagnosis performed between wafer tests by a prior art. It is a time chart of the calibration performed between wafer tests by a prior art. It is a block diagram of the semiconductor test apparatus by a prior art. It is a time chart of the process using the conventional BUSY line.

Explanation of symbols

1 TSC
2 Calibration execution means 3 Diagnosis execution means 11 A card 21 B card 31 C card 41 D card 511 Overall BUSY line 512 BUSY line 513 BUSY line 514 BUSY line 515 BUSY line

Claims (3)

In a semiconductor test apparatus that includes a TSC that performs self-diagnosis on a plurality of devices while testing a test object, and detects a failure of the device,
The TSC is
Calibration execution means for calibrating a plurality of the devices;
Diagnosis execution means for diagnosing a plurality of the devices calibrated by the calibration execution means;
A controller for controlling the calibration execution means and the diagnosis execution means;
A semiconductor test apparatus comprising a plurality of BUSY lines provided in each of the plurality of apparatuses and connected to the TSC. The calibration execution means executes calibration in parallel with respect to each of the plurality of devices, and the diagnosis execution means executes diagnosis in order from the one of the plurality of devices for which calibration has been completed. The semiconductor test apparatus according to claim 1. An overall BUSY line connecting the TSC and the plurality of devices;
3. The semiconductor test apparatus according to claim 1, wherein the control unit starts or ends calibration and starts or ends diagnosis via the entire BUSY line.

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