JP2009118599A - Pwm inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PWM inverter device that changes a carrier frequency and a voltage command synchronized with each other at the same timing, in changing the carrier frequency in operation. <P>SOLUTION: The PWM inverter device includes a command value calculation circuit 44 for calculating the voltage command and the carrier frequency for controlling driving a motor, a set value holding circuit 33 for holding the data of the voltage command and the carrier frequency from the command value calculation circuit 44, a load timing circuit 55 for fetching the data of the set value holding circuit 33, and a PWM generation circuit 70 for generating a PWM signal from the data fetched in the load timing circuit 55. When the set values of the voltage command and the carrier frequency are changed, the load timing circuit 55 changes the voltage command and the carrier frequency simultaneously synchronized with the crests or the troughs of the carrier before the change. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a carrier generation circuit of a PWM inverter device that performs variable speed drive control of an electric motor.

The conventional PWM inverter device generally maintains the output voltage accuracy by changing the carrier frequency in accordance with the output frequency, instead of a constant PWM carrier frequency.
As a means to change the carrier frequency and voltage command synchronously during operation, each carrier has a carrier counter that generates a carrier signal that is being generated and a carrier counter that generates a carrier signal to be changed. There is a method of updating the carrier frequency and the voltage command synchronously when the command calculation is completed. (For example, refer to Patent Document 1).

In FIG. 4, 1 is a changed carrier counter that generates a carrier signal to be changed, 2 is a generated carrier counter that generates a carrier signal that is being generated, 3 is a set value holding circuit, 4 is a command value calculation circuit, and 5 is a load timing. Circuit. The generating carrier signal 2c is generated by the generating carrier counter 2 based on the carrier frequency set value 3b. A voltage command 4 b corresponding to the carrier frequency is calculated by the command value calculation circuit 4. When changing the carrier frequency setting value 3b, the carrier frequency setting value to be changed and the carrier frequency correction data 3a corresponding to the carrier frequency to be changed are set in the setting value holding circuit 3. When the data is updated, the load timing circuit 5 is notified by the data set signal 3d.
Next, at the valley timing of the generated carrier signal 2c, the changed carrier counter 1 loads the carrier holding value 31b set in the set value holding circuit 3 and starts counting up. At the same time, the load timing circuit 5 receives the update start signal 1a. To notify. When the load timing circuit 5 detects the start of counting up, it outputs a latch signal 5b to the command value calculation circuit 4. The command value calculation circuit 4 loads the correction hold value 31a by the latch signal 5b and starts the voltage command calculation. When the voltage command calculation is completed, the voltage command 4b is output, and the load timing circuit 5 is notified of the calculation completion by the voltage command calculation completion signal 4a. When the load timing circuit 5 detects the completion of the calculation, it notifies the carrier counter 2 of the switching signal 5a. Then, the generating carrier counter 2 switches to the update carrier.

Since there is a time lag from the carrier frequency setting to the completion of the command calculation, a new carrier frequency setting value cannot be changed by the write permission signal 5c during the period from the carrier setting to the completion of the calculation.
As described above, even if the carrier frequency is changed during operation by the generated carrier counter 2 that generates the generated carrier signal, the changed carrier counter 1 that generates the carrier signal to be changed, and the load timing circuit 5, the carrier The frequency and voltage command are updated synchronously.
JP 2000-152642 A (page 4, FIG. 1)

FIG. 5 is a timing chart showing the operation of the carrier generation circuit unit of the conventional PWM inverter device. The problem of the conventional example will be described with reference to FIG. When the voltage command calculation completion 4a crosses the carrier valley, the carrier frequency and voltage command are updated while the carrier counter is up or down. In FIG. 5, the carrier frequency and the voltage command are updated at the timing of T0 while the carrier counter is up. At this time, since the PWM signal in one carrier cycle at the time of update is different from the voltage command, the voltage applied to the motor is distorted, and the largest distortion occurs when the command calculation is completed at the peak of the carrier. . In addition to the carrier signal counter, a change counter and a monitoring circuit for monitoring the permission signal at the time of changing the carrier frequency are required, which increases the cost and power consumption. There was a problem.
The present invention has been made in view of such problems, and an object of the present invention is to provide a PWM inverter device that can change a carrier frequency and a voltage command synchronously at the same timing when changing the carrier frequency during operation. .

In order to solve the above problems, the present invention is configured as follows.
The invention according to claim 1 is a setting for holding a voltage command for driving and controlling a motor and a command value calculation circuit for calculating a carrier frequency, and holding the voltage command and the carrier frequency data from the command value calculation circuit. In a PWM inverter device comprising: a value holding circuit; a load timing circuit that takes in the data of the set value holding circuit; and a PWM generation circuit that generates a PWM signal from the data taken in by the load timing circuit.
When the voltage command and the set value of the carrier frequency are changed, the load timing circuit simultaneously changes the voltage command and the carrier frequency in synchronization with the peak or valley of the carrier before the change.
According to a second aspect of the present invention, in the PWM inverter device according to the first aspect, when the voltage command and the carrier frequency data of the set value holding circuit are changed, the load timing circuit is loaded. An update register for updating old data by a signal and a peak / valley counter for generating a carrier synchronization signal by a predetermined peak / valley cycle of the carrier are provided.
According to a third aspect of the present invention, in the PWM inverter device according to the second aspect, the load signal is generated by a write signal of the set value holding circuit and the carrier synchronization signal, and the set value holding circuit After the setting is completed, the voltage command and the carrier frequency are updated.

  According to the present invention, when the carrier frequency and the voltage command are changed during operation, the carrier frequency and the voltage command can be changed simultaneously in synchronization with the carrier regardless of the change timing, and the PWM signal is not distorted. That is, since a voltage command corresponding to the carrier can always be output, an unintended voltage waveform is not output.

  Hereinafter, embodiments of the present invention will be described with reference to FIG. 1 and FIG.

FIG. 1 is a block diagram of a carrier generation circuit section of a PWM inverter device according to the present invention. In FIG. 1, 44 is a command value calculation circuit, 33 is a set value holding circuit, 55 is a load timing circuit, and 70 is a PWM generation circuit. The command value calculation circuit 44 calculates a voltage command, and outputs a carrier frequency, a PWM pattern value representing a pattern of the H level and L level of the U, V, and W phase PWM signals in one carrier cycle, and an instantaneous voltage or current amplitude. A carrier comparison value corresponding to the value is generated.
The set value holding circuit 33 is composed of a carrier setting register 331, a Yamatani setting register 332, a PWM pattern setting register 333, and a carrier comparison setting register 334. Data of the command value calculation circuit 44 is shared with the shared bus 44a, the carrier A write signal 44b from the setting register 331, a write signal 44c from the Yamatani setting register 332, a write signal 44d from the PWM pattern setting register 333, and a write signal 44e from the carrier comparison setting register 334 are written into each register. However, the value of the carrier comparison setting register 334 is always written last.
A carrier counter value corresponding to the carrier frequency is set in the carrier setting register 331. A counter value for the peak and valley of the carrier output is set in the peak / valley setting register 332. The PWM pattern setting register 333 is set with PWM pattern values representing the H level and L level patterns of the U, V, and W phase PWM signals in one carrier cycle. The carrier comparison setting register 334 is set with a carrier comparison value corresponding to an instantaneous value of voltage or current amplitude.
The PWM generation circuit 70 includes a carrier counter 71, a PWM comparator 72, and a PWM output circuit 73. Based on the update register 56 of the load timing circuit 55, the carrier counter value 71a and the carrier comparison value 55c are obtained by the PWM comparator 72. The PWM comparator 72 outputs an H level or L level signal when the carrier counter value 71a becomes equal to or higher than the carrier comparison value 55c according to the PWM pattern value 55b. The PWM output circuit 73 corrects the dead time and the minimum pulse width of the PWM signals 7a, 7b, and 7c, generates a PWM signal, and outputs the PWM signal to the power element.

The difference between the present invention and the prior art is that the configuration of the load timing circuit 55 is changed. Next, the load timing circuit 55 will be described.
The load timing circuit 55 holds the signal level of the write signal 44e in the carrier register 551, the Yamatani register 552, the PWM pattern register 553, the carrier comparison register 554, the Yamatani counter 558, and the carrier comparison setting register 334 for a certain period. For this purpose, a write holding circuit 557, an AND circuit 555, and an OR circuit 556 are included.
The mountain valley counter 558 counts up when the peak signal 71b of the carrier peak timing from the carrier counter 71 and the valley signal 71c of the valley timing are input by the OR circuit 556, and when it coincides with the mountain valley register value 552, the carrier synchronization signal 558a is output. And resets the valley counter 558. However, the count-up is always started by the valley signal 71c.
FIG. 3 shows the correspondence between the setting value of the Yamatani setting register 332 and the carrier synchronization signal 558a. As shown in the figure, the carrier synchronization signal generation timing can be set in four ways according to the setting contents of the Yamatani setting register 332.
The write holding circuit 557 receives the write signal 44e of the carrier comparison setting register 334 and holds the signal level of the write signal 44e until the carrier synchronization signal 558a is input.

  The AND circuit 555 receives the carrier synchronization signal 558a and the write holding signal 557a output from the write holding circuit 557, and generates a load signal 555a. The carrier register 551, the mountain valley register 552, the PWM pattern setting register 553, and the carrier constituting the update register 55 of the load timing circuit 55 at the peak or valley of the carrier set by the peak / valley setting register 332 by the load signal 555a. Setting update of the comparison register 554 is performed simultaneously.

FIG. 2 is a timing diagram showing the operation of the embodiment of the present invention. The update timing of the carrier frequency and voltage command will be described with reference to FIG. Initially, the value of the mountain valley setting register 332 is set to 1 as a default value, and the value of the mountain valley register 552 is 1, so that the carrier synchronization signal 558a is output at the timing of the valley 1 after skipping the mountain according to FIG. The
The C data (carrier frequency data) of the carrier setting register 331 is changed from 0 to 1 at the timing of T11, the YT data of the Yamatani setting register 332 is changed from the default value of 1 to 3 at the timing of T12, and the timing of T13 The P data (PWM pattern data) of the PWM pattern setting register is changed from 0 to 1, and finally the PT data (carrier comparison value data) of the carrier comparison setting register 334 at the timing across the carrier valley 1 of T14. Is changed from 0 to 1.
When the write signal 44e at the time of writing the PT data 1 is input to the write holding circuit 557, the write holding signal 557a is generated, and the timing of the carrier valley 2 is generated by the load signal 555a generated by AND with the carrier synchronization signal 558a. Thus, the carrier frequency C data 1, the PWM pattern P data 1, the carrier peak / valley YT data 3 and the carrier comparison value PT1 data are simultaneously written and updated in the update register 56.
Similarly, the C data of the carrier setting register 331 is changed from 1 to 2 at the timing of T21, the P data of the PWM pattern setting register 333 is changed from 1 to 2 at the timing of T23, and the carrier comparison setting register 334 at the timing of T24. The PT data is changed from 1 to 2. Since the valley / valley register 552 has already been updated to YT data = 3 in the valley 2 of the carrier, in this case, the carrier synchronization signal 558a is output at the timing of the valley 4, valley, and valley 4 that skips the mountain (see FIG. 3). ).
Carrier comparison between carrier frequency C data 2 and PWM pattern P data 2 at the timing of valley 4 by the write hold signal 557 a generated when writing PT data 2 in the carrier comparison setting register 334 and the load signal 555 a generated by the carrier synchronization signal 558 a The value PT data 2 is simultaneously updated to the update register 56.

The carrier frequency and voltage command are calculated and the calculation result is set based on the timing at which the carrier synchronization signal 558a becomes H level. For this reason, the setting value of the Yamatani setting register 332 needs to be longer than the calculation cycle, and is set according to the calculation cycle.
Thus, since the carrier frequency and the voltage command are always updated simultaneously in synchronization with the carrier, the PWM signal during one carrier cycle at the time of change does not cause distortion. In addition, since the setting of the voltage command and the carrier frequency is updated at the same time, there is no time lag between the carrier setting and the voltage command setting, and it is not necessary to provide a monitoring circuit for monitoring write permission outside. Furthermore, only one carrier counter is sufficient, and there is no need to provide a separate carrier counter for change.

The block diagram of the carrier generation circuit part of the PWM inverter apparatus of this invention Timing chart showing the operation of the carrier generation circuit unit of the present invention Correspondence between the setting value of the Yamatani setting register of the present invention and the generation timing of the carrier synchronization signal. Block diagram of carrier generation circuit section of conventional PWM inverter device Timing diagram showing operation of conventional carrier generation circuit

Explanation of symbols

1 changed carrier counter 2 generating carrier counter 3 set value holding circuit 4 command value calculation circuit 5 load timing circuit 1a update start 2c carrier signal 3a carrier frequency correction data 3b carrier frequency set value 3c output voltage command 3d data set signal 31a correction holding Value 31b Carrier holding value 4a Voltage command calculation completion 4b Voltage command 4c Carrier signal 5a Switching 5b Latch 5c Write permission T0 Update timing 33 Setting value holding circuit 44 Command value calculation circuit 55 Load timing circuit 56 Update register 331 Carrier setting register 332 Yamatani setting Register 333 PWM pattern setting register 334 Carrier comparison setting register 44a Shared bus 44b Carrier setting register write signal 44c Yamatani setting register write signal 44d PWM pattern Write signal 44e of carrier setting register Write signal 551 of carrier comparison setting register Carrier register 552 Yamatani register 553 PWM pattern register 554 Carrier comparison register 558 Yamatani counter 555 AND circuit 556 OR circuit 557 Write holding circuit 55b PWM pattern value 55c Carrier comparison value 558a Carrier synchronization signal 555a Load signal 557a Write hold signal 70 PWM generation circuit 71 Carrier counter 72 PWM comparator 73 PWM output circuit 71a Carrier counter value 71b Mountain signal 71c Valley signal 7a U-phase PWM signal 7b V-phase PWM signal 7c W-phase PWM signal

Claims (3)

A command value calculation circuit for calculating a voltage command and a carrier frequency for driving and controlling the electric motor, a setting value holding circuit for holding data of the voltage command and the carrier frequency from the command value calculation circuit, and the setting value holding In a PWM inverter device comprising a load timing circuit that captures the data of the circuit, and a PWM generation circuit that generates a PWM signal from the data captured by the load timing circuit,
The load timing circuit is configured to simultaneously change the voltage command and the carrier frequency in synchronization with a peak or valley of the carrier before the change when the set value of the voltage command and the carrier frequency is changed. PWM inverter device.   When the voltage command and the carrier frequency data of the set value holding circuit are changed, the load timing circuit updates an old register by a load signal, and a carrier is generated according to a predetermined carrier peak and valley cycle. The PWM inverter device according to claim 1, further comprising a mountain valley counter that generates a synchronization signal.   3. The load signal is generated by a write signal of the set value holding circuit and the carrier synchronization signal, and the voltage command and the carrier frequency are updated after the setting of the set value holding circuit is completed. The PWM inverter device described in 1.

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