JP2009118341A - Tmcc signal receiving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TMCC signal receiving apparatus capable of reducing power consumption of a receiving circuit and shortening the time for detecting a desired symbol. <P>SOLUTION: The TMCC signal receiving apparatus includes: a receiving circuit 11 for converting a received broadcast wave into an IF signal; a TMCC demodulation circuit 12 which demodulates a TMCC signal from the IF signal and outputs TMCC information; a symbol synchronizing reproduction circuit 13 for generating a symbol synchronizing signal from the IF signal; a majority decision processing circuit 14 for performing majority decision processing upon the TMCC information; a frame synchronizing reproduction circuit 15 for generating a frame synchronizing signal from the TMCCC information; a TMCC information determination circuit 16 for outputting information determining whether the TMCC information on which majority decision processing has been performed, is changed or not; and a control circuit 17 which outputs an intermittent reception control signal for controlling to switch a receiving mode based on the two synchronizing signals and the determination information. In the case where information is received which determines that the TMCC information is changed, the control circuit 17 controls to set a majority decision receiving mode. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a terrestrial digital television broadcast receiver, and more particularly to a TMCC signal receiver for terrestrial digital television broadcast.

In ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), which is a terrestrial digital television broadcasting transmission system, TMCC (Transmission and Multiplexing Configuration Signal) is used as control information to assist the demodulation and decoding processing of the receiver. It is transmitted using a carrier. FIG. 1 shows bit allocation in the TMCC signal and the contents of TMCC information to be transmitted. In the TMCC signal, as shown in FIG. 1, the first bit B ₀ is a reference for differential demodulation, bits B _{1 to} B ₁₆ are frame synchronization signals, bits B _{17 to} B ₁₉ are segment format identification, and bit B ₂₀ ˜B ₁₂₁ are TMCC information such as transmission parameters, and bits B _{122 to} B ₂₀₃ are error correction parity bits. That is, the TMCC signal is composed of 204 bits, and 1 bit is transmitted in 1 symbol and 204 bits are transmitted in 1 frame, and is repeatedly transmitted every frame.

  In a TMCC signal receiver or a terrestrial digital broadcast receiver equipped with a TMCC signal receiver, as a conventional technique for receiving a specific bit (TMCC information) of this TMCC signal with low power consumption, intra-frame intermittent reception and inter-frame intermittent reception Is known (see, for example, Patent Document 1).

A timing example of the intra-frame intermittent reception processing is shown in FIG. In this example, the desired the TMCC _information, emergency warning broadcast start flag assigned to _{B 26} is set to (hereinafter, referred to as EWS signal.). The reception circuit of the TMCC signal reception apparatus is activated near the first symbol of the OFDM frame, and the TMCC signal is received in a total of 27 symbol periods up to the E26 signal of B _{26. For} the symbols after B ₂₇ , the reception circuit is activated. Stop. The start and stop control of the receiving circuit may be performed on the entire receiving circuit, or a part of the receiving circuit with high power consumption may be started or stopped. Thereby, the power consumption of the TMCC signal receiving apparatus can be reduced as compared with the case where all symbols are received in one frame period.

  On the other hand, the intermittent reception between frames is an intermittent reception process in which the reception circuit is not activated for a few frame periods after the symbol of the EWS signal, and the TMCC signal is not received (see, for example, Patent Document 1).

  FIG. 3 shows an example of intermittent reception timing using the intra-frame intermittent reception process and the inter-frame intermittent reception process. In this way, for a certain frame, the receiving circuit is activated and received for 27 symbol periods from the beginning of the frame, and for the subsequent symbol period and n × frame period (n is a positive number) By providing the non-receiving circuit that is stopped, the power consumption of the receiving circuit can be significantly reduced.

JP 2006-319771 A

  In ISDB-T digital terrestrial broadcast reception, an emergency warning broadcast activation flag (EWS signal) included in the TMCC signal is used in order to realize automatic activation by emergency warning broadcasting with a battery-powered portable terminal or the like. It is desirable to monitor with the lowest possible power consumption.

  In the conventional TMCC signal receiving apparatus, as described above, in order to keep the power consumption of the receiving circuit low, there are proposed a method for performing intra-frame intermittent reception processing and a method for performing intra-frame intermittent reception processing. That is, in-frame intermittent reception processing is a period from the beginning of the TMCC signal, that is, the beginning of the OFDM frame (hereinafter simply referred to as a frame) to the OFDM symbol (hereinafter simply referred to as a symbol) in which the EWS signal is transmitted. Is the only way to receive. The inter-frame intermittent reception process is a method of receiving by thinning out the frame period to be received in units of frames.

  As shown in FIG. 2, when the transmission mode of digital terrestrial television broadcasting is mode 3 and the guard interval ratio (GI ratio) is 1/8, one frame is 231.336 msec. In intermittent reception within a frame, the duration of supplying power to the receiving circuit in the conventional TMCC signal receiving apparatus is, for example, 30.618 msec (for 27 symbols), and the receiving circuit is turned on from the beginning of the TMCC signal frame. When a desired symbol (for example, EWS signal) is received, the power supply is shut off. Therefore, at least one frame or more is required to receive the EWS signal. Also, as shown in FIG. 3, in intermittent reception between frames, the power-on timing of the receiving circuit is the beginning of the frame, and the ON / OFF interval is N frames (N is a natural number). In the intermittent reception between frames, there is no restriction on the power-on timing of the receiving circuit, and the on / off interval can be a predetermined value (for example, every 10 seconds).

  However, conventional intra-frame intermittent reception does not receive TMCC parity bits, and thus error correction using a shortened difference set cyclic code in the FEC (Forward Error Correction) scheme of the OFDM signal cannot be performed. .

  For this reason, in order to ensure a required bit error rate, it is necessary to perform some kind of error correction processing. Thus, it is conceivable to make a majority decision between frames as a simple method for correcting transmission path bit errors in intra-frame intermittent reception (also referred to as majority decision processing as will be described later).

As an example of the majority decision, FIG. 4 shows a majority decision process using TMCC information for three frames. The EWS signal B ₂₆ receives TMCC information in combination with three frames intermittent reception between frames within a discontinuous reception and frame, with the resulting 3-bit information bit (part of the B ₂₆ pointed to by the arrow in FIG. 4) Make a majority decision. This method can correct a bit error in the transmission path.

  However, when error correction based on the majority decision between frames is used, in order to obtain a sufficient error correction effect, it is necessary to use a large number of frames for the majority decision process, and until the majority decision process result is obtained. There is a problem that the required time becomes longer. This means that, for example, when an emergency warning broadcast starts, it takes time to detect the EWS signal, and the original purpose of the emergency warning broadcast that accurately transmits accurate information in an emergency cannot be sufficiently realized. is doing.

  Therefore, an object of the present invention is to enable further reduction of power consumption when monitoring an EWS signal by efficiently combining intermittent reception within a frame and intermittent reception between frames, and at the time of intermittent reception. Another object of the present invention is to provide a TMCC signal receiving apparatus that realizes correction of bit errors in a short time and reduces the time for detecting a desired symbol (for example, EWS signal).

  In the TMCC signal receiving apparatus of the present invention, in order to achieve both reduction in power consumption of the receiving circuit and reduction in time required for majority decision processing of TMCC information, both intra-frame intermittent reception and inter-frame intermittent reception are used together, and TMCC information is Receive or monitor with low power consumption. Furthermore, when desired TMCC information, for example, a change in the EWS signal from “0” to “1” is detected, the interframe intermittent reception processing is canceled and only the intraframe intermittent reception processing is controlled. Thus, by receiving the EWS signal, which is the desired TMCC information, every frame, it is possible to shorten the time until the prescribed number of frames required for the majority decision process is satisfied.

  That is, the TMCC signal receiving apparatus of the present invention is a TMCC signal receiving apparatus that receives a TMCC signal of terrestrial digital television broadcasting, a receiving circuit that converts a received broadcast wave into an IF signal, and outputs the IF signal. A TMCC demodulation circuit that demodulates a TMCC signal from the TMCC signal and outputs TMCC information included in the TMCC signal, a symbol synchronization reproduction circuit that generates and outputs a symbol synchronization signal that matches an OFDM symbol timing from the IF signal, and A majority decision processing circuit that performs majority decision processing on TMCC information and corrects transmission path errors; a frame synchronization reproduction circuit that generates and outputs a frame synchronization signal that is timed to an OFDM frame from the TMCC information; and Regarding TMCC information subjected to the majority decision processing by the majority decision processing circuit, The TMCC information determination circuit that determines whether or not there is an output and outputs the determination information of the determination result, and the reception so as to switch the reception mode of the reception circuit based on the two synchronization signals and the determination information A control circuit that outputs an intermittent reception control signal for controlling the supply of power to the circuit, wherein the control circuit determines a synchronization state based on the two synchronization signals and causes the reception circuit to receive intermittently. The reception is performed so as to continuously receive the number of frames necessary for the majority decision process only when the decision information indicating that the TMCC information has changed is received. An intermittent reception control signal for controlling the power supply of the circuit is output so as to shorten the majority decision processing time.

  Furthermore, in the TMCC signal receiving device of the present invention, the control circuit determines which reception mode is suitable from the two synchronization signals and the determination information, and switches the reception mode based on the determination result. A reception mode switching circuit for outputting a reception mode switching control signal; a continuous reception mode control signal generating circuit for outputting a control signal for continuously operating the reception circuit as a first reception mode; and a second reception mode A symbol decimation reception mode control signal generation circuit for outputting a control signal for intermittently operating the reception circuit in units of symbols, and a third reception mode necessary for receiving the majority of the reception circuit by determination processing Majority decision reception mode control signal generation circuit for outputting a control signal for operating to continuously receive as many frames as possible A reception mode switching switch for switching between the three reception modes, and the reception mode switching circuit receives the determination information indicating that there is a change in the TMCC information, and the number of frames required for the majority determination processing. An intermittent reception control signal for controlling the power supply of the reception circuit is output from the reception mode changeover switch so as to continuously receive the minutes, so that the majority decision processing time is shortened.

  Further, in the TMCC signal receiving device of the present invention, a majority decision determination changeover switch is further provided between the majority decision determination processing circuit and the TMCC information determination circuit, and the control circuit performs the majority decision determination processing according to the determination information. A majority decision processing control signal for controlling execution of the majority decision processing by the circuit is supplied to the majority decision changeover switch. When the majority decision decision switch receives the majority decision decision control signal, the TMCC demodulation The circuit is operated to switch the connection between the circuit and the TMCC information determination circuit to the connection between the majority determination processing circuit and the TMCC information determination circuit, and the frequency of the majority determination processing in the majority determination processing circuit is minimized. By suppressing, the time for outputting the judgment information from the TMCC information judgment circuit is shortened. It is characterized in.

  According to the TMCC signal receiving apparatus of the present invention, by including the control circuit that switches the intermittent receiving operation with respect to the receiving circuit, the power consumption of the receiving apparatus is kept low, and even during intermittent reception by the inter-frame majority decision processing. Bit error correction can be realized. In particular, it is possible to reduce the time required for determining the majority between frames, thereby reducing the time for detecting the EWS signal during emergency broadcasting. Therefore, it is possible to achieve both reduction in power consumption of the receiving apparatus and reduction in time required for detecting the EWS signal.

  Further, the time required for TMCC information determination can be shortened by switching the majority determination processing circuit that performs the majority determination processing according to the reception mode.

  First, a TMCC signal receiving apparatus according to Embodiment 1 of the present invention will be described.

Example 1
To facilitate understanding of the present invention, TMCC information B ₂₆ to Allocated emergency warning broadcast start flag for the (EWS signal) will be described symbol portion transmitted as desired symbol. The EWS signal is usually “0”, but when a warning declaration of a large-scale earthquake or a tsunami warning is issued, an emergency warning broadcast starts and changes to “1”. Is.

  FIG. 5 shows a block diagram of the TMCC signal receiving apparatus according to the first embodiment of the present invention. The TMCC signal receiving apparatus according to the first embodiment is an apparatus that receives and demodulates a TMCC signal included in an ISDB-T terrestrial digital television broadcast signal and outputs TMCC information. The TMCC signal receiving apparatus includes a receiving antenna 10, a receiving circuit 11, a TMCC demodulating circuit 12, a symbol synchronous reproducing circuit 13, a majority decision processing circuit 14, a frame synchronous reproducing circuit 15, a TMCC information determining circuit 16, a control circuit 17, and a power switch 18. And a power supply circuit 19.

  The receiving circuit 11 converts the received signal in the radio frequency (RF) band of the broadcast signal received via the receiving antenna 10 into an intermediate frequency (IF) signal and outputs it. The converted IF signal is input to the TMCC demodulation circuit 12 and the symbol synchronous reproduction circuit 13.

  The TMCC demodulation circuit 12 receives the IF signal from the reception circuit 11, extracts a TMCC signal component included in the IF signal, demodulates the extracted TMCC signal, and outputs TMCC information included in the TMCC signal. The extracted TMCC information is input to the majority decision processing circuit 14 and the frame synchronization reproduction circuit 15. Any known method can be used as a method for demodulating the TMCC signal and a method for extracting TMCC information included in the TMCC signal. The TMCC demodulation circuit 12 has a function of establishing both symbol synchronization and frame synchronization by a known method and demodulating the TMCC signal.

  The symbol synchronization reproduction circuit 13 receives the IF signal from the reception circuit 11, reproduces the symbol timing of the OFDM signal from the IF signal, and generates and outputs a symbol synchronization signal. That is, the symbol synchronization signal is a signal whose timing is matched to the OFDM symbol of the OFDM signal. The symbol synchronization signal is input to the control circuit 17. For example, for reproducing the symbol timing of an OFDM signal, the correlation between the in-phase quadrature component (I, Q signal) from the IF signal and the in-phase quadrature component (I ′, Q ′ signal) obtained by delaying them by the effective symbol length. There is a method of reproducing the symbol synchronization signal by using. The symbol synchronization signal can be a pulse signal that triggers on a symbol-by-symbol basis. The symbol synchronization reproduction circuit 13 generates, for example, a clock generator and counter with a frequency higher than or equal to the symbol synchronization signal in order to generate the symbol synchronization signal. The clock generated by the clock generator is counted by a counter, a pulse is generated every time the count value becomes a symbol unit value, and after counting 204 symbols of one frame, the count value is reset. repeat.

  The majority decision processing circuit 14 internally holds TMCC information for several frames received from the TMCC demodulation circuit 12 and performs majority decision to output a large number of values among the held TMCC information for several symbols ( Hereinafter, it is also referred to as a majority decision process), thereby correcting the transmission path error. The majority decision processing circuit 14 outputs the TMCC information subjected to the majority decision processing to the TMCC information determination circuit 16. Note that a memory that stores TMCC information for a predetermined number of frames can be used to perform majority decision processing.

The frame synchronization reproduction circuit 15 receives TMCC information from the TMCC demodulation circuit 12, reproduces the frame timing from the TMCC information, and generates and outputs a frame synchronization signal. The frame synchronization signal is input to the control circuit 17. For example, the frame timing is reproduced using a TMCC information synchronization signal (assigned to bits B _{1 to} B ₁₆ ) that is an output of the TMCC demodulation circuit 12. That is, the frame synchronization signal is a signal whose timing is matched to the OFDM frame of the OFDM signal. The frame synchronization signal can be a pulse signal that generates a trigger in units of frames, and the frame synchronization reproduction circuit 15 generates a frame synchronization signal, for example, a clock generator (preferably higher than or equal to the frame synchronization signal). The same clock as the symbol synchronous reproduction circuit 13 is used, and a counter is provided. The clock generated by the clock generator is counted by the counter, and a pulse is generated every time the count value becomes the first value of the frame. Repeatedly resetting the count value every frame.

The TMCC information determination circuit 16 inputs TMCC information in which the bit error has been corrected in the majority determination processing circuit 14 in the majority determination processing circuit 14. TMCC information determination circuit 16, for example, if the change in the EWS signal B ₂₆ is determined to not at the same time as external output as the TMCC information, supply determination information corresponding to the determination result (for example, "0") to the control circuit 17 To do. Conversely, when the B ₂₆ EWS signal detects a change from “0” to “1” or a change from “1” to “0”, the TMCC information determination circuit 16 responds to the determination result. The determination information (for example, “1”) is supplied to the control circuit 17. That is, the TMCC information determination circuit 16 monitors or determines a change in TMCC information.

The control circuit 17 inputs the symbol synchronization signal from the symbol synchronization regeneration circuit 13 receives the frame sync signal from the frame synchronous reproduction circuit 15, based on each of the synchronization signals, the desired TMCC information (e.g., the B ₂₆ An intermittent reception control signal is generated so as to activate the reception circuit 11 in the vicinity of the EWS signal). In this embodiment, in order to supply power from the power supply circuit 19 to the receiving circuit 11, the power switch 18 is controlled by an intermittent reception control signal. Further, when the control circuit 17 receives determination information indicating that there is a change in TMCC information from the TMCC information determination circuit 16, the control circuit 17 sets the number of frames necessary for the majority determination processing of the majority determination processing circuit 14 as a majority determination reception mode. An intermittent reception control signal for controlling the power supply of the reception circuit 11 is output so as to receive continuously. The control circuit 17 includes a clock generator and a counter. The control circuit 17 detects the head symbol of the frame by the frame synchronization signal, starts counting, and counts a predetermined number of symbols by the symbol synchronization signal. An intermittent reception control signal for on / off control is generated. A count corresponding to a predetermined number of symbols from the first symbol to the desired symbol (the predetermined number of symbols is known from the allocation of TMCC information defined by standards of the radio wave industry) is input to the control circuit 17. This is performed by a pulse of the symbol synchronization signal.

  Therefore, the TMCC signal receiving apparatus according to the first embodiment controls the power supply of the power supply circuit 19 that drives the receiving circuit 11 based on the intermittent reception control signal output from the control circuit 17.

  Hereinafter, the operation of the TMCC signal receiving apparatus according to the first embodiment will be described in detail.

  An ISDB-T radio frequency (RF) signal received by the receiving antenna 10 is input to the receiving circuit 11. The input RF signal is frequency-converted to an intermediate frequency (IF) signal by the receiving circuit 11 and output. The IF signal output from the reception circuit 11 is input to the TMCC demodulation circuit 12 and the symbol synchronous reproduction circuit 13.

  The TMCC demodulating circuit 12 extracts and demodulates the TMCC signal component contained in the input IF signal, and outputs the obtained TMCC information to the frame synchronization reproduction circuit 15 as well. When detecting the EWS signal included in the TMCC signal of the terrestrial digital television broadcast wave, the TMCC demodulation circuit 12 activates the terrestrial digital television broadcast tuner having the OFDM demodulation function. Digital terrestrial television broadcast receivers (including mobile phones with a one-segment reception function) are ready to receive emergency alert broadcasts for the first time.

  The symbol synchronization reproduction circuit 13 receives the IF signal output from the reception circuit 11 and generates a symbol synchronization signal synchronized with the symbol timing of the OFDM signal. Here, the generated symbol synchronization signal is supplied to the control circuit 17. As a result, the control circuit 17 can count in symbol units.

The frame synchronization reproduction circuit 15 detects a 16-bit synchronization signal assigned to the bits B _{1 to} B ₁₆ shown in FIG. 1, and generates a frame synchronization signal synchronized with the frame timing of the OFDM signal. Here, the generated frame synchronization signal is supplied to the control circuit 17 in the same manner as the symbol synchronization signal. Thereby, the timing of the first symbol of the frame can be detected by the frame synchronization signal input to the control circuit 17.

The control circuit 17, based on the symbol synchronization regeneration circuit 13 and the frame symbol synchronization signal are input from the synchronous reproduction circuit 15 and the frame sync signal, near EWS signal B ₂₆ is the desired TMCC information from the first symbol of a frame ( For example, an intermittent reception control signal for starting up the reception circuit 11 is generated and output to the power switch 18 until the timing of the EWS signal can be adjusted.

  The power switch 18 turns on / off the DC power supply (or AC power supply) supplied from the power supply circuit 19 based on the intermittent reception control signal. That is, during a period in which the power switch 18 is on, power is supplied from the power circuit 19 to the receiving circuit 11, and the receiving circuit 11 is activated and receives a signal. During the period when the power switch 18 is OFF, the power supply from the power supply circuit 19 is not supplied to the reception circuit 11, and the reception circuit 11 is not activated and does not receive a signal. Here, the power supply destination that is turned on / off by the power switch 18 has been described as the entire receiving circuit 11, but the power supply destination may be a part of the receiving circuit 11 (for example, reception of an EWS signal). It can only be a component part that is indispensable or a component that consumes a lot of power.)

  As a result, the power supply from the power supply circuit 19 that drives the receiving circuit 11 can be controlled based on the control signal output from the control circuit 15, and the EWS signal can be monitored with low power consumption, and the EWS signal detection time can be controlled. Shortening can be achieved.

  Next, an intermittent reception control signal for switching the reception mode according to the determination information of the TMCC information determination circuit 16 in the first embodiment will be described. An example of the pattern of the intermittent reception control signal generated by the control circuit 17 is shown in FIG. In the example of FIG. 6, control signal examples in three types of reception modes of “symbol thinning reception mode”, “majority determination reception mode”, and “continuous reception mode” are shown, and each will be described.

  In the “symbol decimation reception mode”, the head position of the OFDM frame is detected from the frame synchronization signal, and the symbol synchronization signal is counted by a known number of symbols (27 in the case of an EWS signal). This is a reception mode for detecting. In the vicinity of the first symbol, a control signal for energizing the receiving circuit 11 is output, and for the symbols after the EWS signal, the power supplied to the receiving circuit 11 is shut off, thereby enabling intermittent reception within the frame. In this reception mode, in-frame intermittent reception and inter-frame intermittent reception are combined, and the energization time of the reception circuit 11 can be reduced as much as possible to save power in the TMCC signal receiving apparatus during EWS signal monitoring. .

  In the “majority determination reception mode”, when the TMCC information determination circuit 16 detects a change in the TMCC information, the intermittent reception between frames is canceled and reception for receiving predetermined TMCC information (for example, EWS signal) every frame is received. Mode. By increasing the frequency of receiving EWS signals to be every frame, it is possible to greatly reduce the time required to satisfy the prescribed number of frames required for majority decision processing, and as a result, the time required for majority decision processing is reduced. Can be reduced. That is, taking the majority decision process for three frames shown in FIG. 4 as an example, in the “symbol decimation reception mode”, TMCC information for three frames cannot be received until a minimum of five frame periods have passed. If so, TMCC information for three frames can be used in a three-frame period. Therefore, in this reception mode, it is possible to significantly reduce the time until the determination information of the majority determination processing result is output.

  In the “continuous reception mode”, when out of frame synchronization or out of symbol synchronization occurs due to a change in the reception status, the receiving circuit 11 is continuously activated (energized), continuously receiving broadcast waves, This is a reception mode for applying synchronization. After the re-synchronization is established in the continuous reception mode, that is, after the symbol synchronization signal and the frame synchronization signal are re-input to the control circuit 17, the TMCC signal receiving apparatus according to the first embodiment again performs the “symbol decimation reception mode”. ”Or“ majority decision reception mode ”, and operates to receive the TMCC signal with low power consumption.

  FIG. 7 shows a block diagram of a control circuit 17 that realizes these three types of intermittent control signal patterns (that is, three reception modes). In the example of FIG. 7, the control circuit 17 includes a reception mode switching circuit 20, a symbol decimation reception mode control signal generation circuit 21, a majority decision reception mode control signal generation circuit 22, a continuous reception mode control signal generation circuit 23, and a reception mode change switch. 24.

  The reception mode switching circuit 20 determines which reception mode is suitable from the frame synchronization signal, the symbol synchronization signal, and the determination information, and sends a mode switching control signal indicating that the reception mode has been determined to the reception mode switching switch 24. Output to. Specifically, the reception mode switching circuit 20 determines the synchronization state based on the frame synchronization signal and the symbol synchronization signal and controls whether the reception circuit 11 is intermittently received or continuously received, and the TMCC information determination circuit When the determination information indicating that the TMCC information has changed from 16 is received, the mode switching control signal is received by the reception mode changeover switch 24 so as to continuously receive the number of frames necessary for the majority decision processing of the majority decision processing circuit. The reception mode changeover switch 24 outputs an intermittent reception control signal for controlling the power supply of the reception circuit 11. Note that the reception mode switching circuit 20 may control the reception mode by setting a priority according to the application when selecting the reception mode. For example, based on the frame synchronization signal, symbol synchronization signal, and determination information, continuous reception mode (first reception mode), symbol decimation reception mode (second reception mode), majority determination reception mode (third reception mode) In this order, priority can be set and controlled. The majority decision processing circuit 14 can perform majority decision processing in both the majority decision reception mode and the continuous reception mode.

  The symbol decimation reception mode control signal generation circuit 21 inputs the frame synchronization signal and the symbol synchronization signal supplied from the symbol synchronization reproduction circuit 13 and the frame synchronization reproduction circuit 15 as the second reception mode, respectively, and sets the second reception mode as the second reception mode. A control signal for intermittently operating the receiving circuit 11 in units of symbols is output. Specifically, the symbol decimation reception mode control signal generation circuit 21 intermittently turns on / off the power supply from the power supply circuit 19 supplied to the reception circuit 11 and generates a control signal for intermittently receiving broadcast waves. Generate and output.

  The majority decision reception mode control signal generation circuit 22 inputs a frame synchronization signal and a symbol synchronization signal as the third reception mode, and outputs a control signal capable of controlling on / off of power supply to the reception circuit 11 in units of frames. .

  The continuous reception mode control signal generation circuit 23 outputs a control signal for continuously operating the reception circuit 11 as the first reception mode so that broadcast waves are always received. Specifically, the continuous reception mode control signal generation circuit 23 continuously supplies power from the power supply circuit 19 to the reception circuit 11, and generates and outputs a control signal for continuously receiving broadcast waves. The control signal by the continuous reception mode control signal generation circuit 23 is used when the frame synchronization signal and the symbol synchronization signal are not input to the symbol decimation reception mode control signal generation circuit 21 and the majority decision reception mode control signal generation circuit 22 (that is, a pulse signal is used). (When not detected), that is, when the reception mode switching circuit 20 determines that the synchronization is lost.

  The reception mode changeover switch 24 receives one of the control signals from the symbol decimation reception mode control signal generation circuit 21, the majority decision reception mode control signal generation circuit 22 and the continuous reception mode control signal generation circuit 23 of the reception mode changeover circuit 20. The control signal is selected by control, and the selected control signal is output as an intermittent reception control signal.

  Both the frame synchronization signal and the symbol synchronization signal are input to the reception mode switching circuit 20, the symbol decimation reception mode control signal generation circuit 21, and the majority decision reception mode control signal generation circuit 22. Further, determination information output from the TMCC information determination circuit 16 is input to the reception mode switching circuit 20.

  The reception mode switching circuit 20 determines which reception mode is suitable from the frame synchronization signal, symbol synchronization signal, and determination information. A mode switching control signal corresponding to the determined reception mode is output to the reception mode switch 24. Note that a reception mode switching criterion for determining which reception mode is suitable will be described later.

  The operation of the reception mode switching circuit 20 in the three types of reception modes of “symbol thinning reception mode”, “majority decision reception mode” and “continuous reception mode” will be described in more detail.

  Usually, in a mobile / mobile reception environment, loss of frame synchronization or loss of symbol synchronization may occur due to reception level fluctuations, frequency shift due to the Doppler effect, multipath effects, and the like. Accordingly, the reception mode switching circuit 20 determines whether or not a synchronization loss has occurred in either or both of the symbol synchronization signal and the frame synchronization signal, and whether or not the symbol synchronization signal and the frame synchronization signal are input (that is, for synchronization). The presence or absence of a pulse signal) can be determined.

  First, the reception mode switching circuit 20 receives the signal so as to select the signal output by the symbol decimation reception mode control signal generation circuit 21 when it is determined that there is no loss of synchronization in both the symbol synchronization signal and the frame synchronization signal. The mode switch 24 is controlled.

  Next, when the determination information from the TMCC information determination circuit 16 that the desired TMCC information is changed is input, the reception mode switching circuit 20 continuously receives TMCC information for a predetermined number of frames, The reception mode changeover switch 24 that selects the control signal of the majority decision reception mode control signal generation circuit 22 is controlled.

  Next, when the reception mode switching circuit 20 determines that a synchronization loss has occurred in either or both of the symbol synchronization signal and the frame synchronization signal, the reception mode switching circuit 20 continuously receives broadcast waves and establishes synchronization again. The reception mode changeover switch 24 is controlled so as to select the control signal output from the continuous reception mode control signal generation circuit 23.

  Next, after the frame and symbol synchronization is established in the continuous reception mode (first reception mode) by the reception mode switching circuit 20, the control signal output by the symbol decimation reception mode control signal generation circuit 21 is selected again. Thus, the reception mode changeover switch 24 is switched. By selecting a control signal output from the symbol decimation reception mode control signal generation circuit 21 and operating it in the symbol decimation reception mode (second reception mode), it waits for TMCC information (or EWS signal, for example) with low power consumption. Return to the state.

  By automatically performing the operation of the reception mode switching circuit 20, the TMCC signal receiving apparatus 2 always monitors TMCC information (or EWS signal, for example) with low power consumption while maintaining synchronization with the broadcast wave to be received. And the majority decision process can be performed in a short time.

  Accordingly, when either the symbol synchronization signal or the frame synchronization signal is out of synchronization by the reception mode switching circuit 20, it is detected as out of synchronization and the power supply to the reception circuit 11 is continuously received so that the broadcast wave is continuously received until resynchronization is performed. By controlling and resynchronizing, it is possible to avoid a situation in which continuous reception is not possible due to loss of synchronization, and to significantly reduce the time until the determination information of the majority decision processing result is output.

  An example of reception mode switching criteria is shown in FIG. When the frame synchronization signal and the symbol synchronization signal are input and the determination information indicating that there is no change in the desired TMCC information is input, the control circuit 17 switches to the “symbol decimation reception mode” and performs the desired operation with low power consumption. The TMCC receiver is operated to receive and monitor the TMCC information. Further, when the frame synchronization signal and the symbol synchronization signal are input and determination information indicating that there is a change in desired TMCC information is input, the control circuit 17 switches to the “majority determination reception mode” and performs a desired determination for each frame. The TMCC information is received, and the TMCC receiver is operated so as to output the majority decision processing result information (which may be in an arbitrary format) in a short time. The control circuit 17 switches to the “continuous reception mode” when either one of the frame synchronization signal and the symbol synchronization signal is not input, that is, when the synchronization is lost, and continuously receives and resynchronizes. The TMCC receiver is operated. In the “continuous reception mode”, whether to execute the majority decision processing in the majority decision processing circuit 14 can be arbitrarily selected.

  In the above example, the normal state is a power saving and TMCC signal monitoring state, the non-normal state is a state in which the majority decision processing time is shortened, and the resynchronization is performed when the reception state deteriorates and a loss of synchronization occurs. The intended continuous reception state is achieved. Note that the strict configuration of the control circuit 17 in FIG. 7 and the switching order of the reception modes are merely examples, and the present invention is not limited to this.

  The power switch 18 switches on / off of the DC power or AC power supplied from the power circuit 19 based on the intermittent reception control signal. That is, during a period in which the power switch 18 is on, power is supplied from the power circuit 19 to the receiving circuit 11, and the receiving circuit 11 is activated and receives a signal. During the period when the power switch 18 is OFF, the power supply from the power supply circuit 19 is not supplied to the reception circuit 11, and the reception circuit 11 is not activated and does not receive a signal. Although the power supply destination to be switched by the power switch 18 has been described as the entire receiving circuit 11, a part of the receiving circuit 11 that consumes a large amount of power may be used.

  If the TMCC receiving device includes the control circuit 17 of the first embodiment, it is possible to reduce the majority decision processing time while monitoring the TMCC signal with low power consumption. In particular, during emergency broadcasting, it is possible to detect an EWS signal subjected to majority decision processing in a short time and output it to the outside.

  Next, a TMCC signal receiving apparatus according to a second embodiment of the present invention will be described.

(Example 2)
As in Example 1, TMCC information B ₂₆ to Allocated emergency warning broadcast start flag for the (EWS signal) will be described symbol portion transmitted as desired symbol. The EWS signal is usually “0”, but when a warning declaration of a large-scale earthquake or a tsunami warning is issued, an emergency warning broadcast starts and changes to “1”. Is.

  FIG. 9 shows a block diagram of a TMCC signal receiving apparatus according to the second embodiment of the present invention. FIG. 10 shows a configuration example of the control circuit 17 that outputs the majority decision processing control signal in the TMCC signal receiving apparatus according to the second embodiment. In addition, the same reference number is attached | subjected to the component similar to Example 1. FIG. The TMCC signal receiving apparatus according to the second embodiment receives the TMCC signal included in the ISDB-T terrestrial digital television broadcast signal, demodulates and outputs the TMCC information included in the TMCC signal, as in the first embodiment. Device. The TMCC signal receiving apparatus according to the second embodiment includes a receiving antenna 10, a receiving circuit 11, a TMCC demodulating circuit 12, a symbol synchronous reproduction circuit 13, a majority decision determination processing circuit 14, a frame synchronous reproduction circuit 15, a TMCC information determination circuit 16, and a control circuit 17. , A power switch 18, a power circuit 19, and a majority decision determination switch 25.

  The TMCC signal receiving apparatus according to the second embodiment is different from the TMCC signal receiving apparatus according to the first embodiment in that a majority decision determination switch 25 is further provided.

  Therefore, in the TMCC signal receiving apparatus according to the second embodiment, the receiving antenna 10, the receiving circuit 11, the TMCC demodulating circuit 12, the symbol synchronous reproduction circuit 13, the majority decision processing circuit 14, the frame synchronous reproduction circuit 15, the TMCC information determination circuit 16, the power supply The operations of the switch 18 and the power supply circuit 19 are the same as those in the first embodiment, and a detailed description thereof is omitted.

  The control circuit 17 according to the second embodiment switches the reception mode to the “majority determination reception mode” as in the first embodiment when the TMCC information determination circuit 16 receives determination information indicating that a change in TMCC information has been detected. In the second embodiment, the majority decision processing control signal for causing the majority decision processing circuit 14 to execute the majority decision processing is supplied to the majority decision changeover switch 25.

  When the majority decision determination switch 25 receives the majority decision processing control signal from the control circuit 17, the majority decision determination circuit 15 and the TMCC information decision circuit connect the connection between the TMCC demodulation circuit 12 and the TMCC information decision circuit 16. It operates to switch to the connection with 16.

  Thus, the control circuit 17 can switch the reception mode from the “symbol thinning reception mode” or the “continuous reception mode” to the “majority determination reception mode”, and the majority determination processing circuit 14 can execute the majority determination processing. .

Next, the switching reference of the majority decision changeover switch 25 will be described in more detail. FIG. 11 shows an example of switching criteria of the majority decision determination changeover switch 25. While the TMCC signal is received in the “symbol thinning reception mode”, the frame synchronization signal and the symbol synchronization signal are stably supplied to the control circuit 17. In other words, for example, the TMCC synchronization signals (B _{1 to} B ₁₆ ) are received in a good state with no bit errors. In such a good reception state, since the necessity for performing the majority decision processing is low, the majority decision changeover switch 25 selects the output side of the TMCC demodulation circuit 12. That is, since the majority decision process that is not necessary is not performed in a good reception state, TMCC information can be supplied to the TMCC information decision circuit 16 without causing a delay due to the majority decision process.

  In the case of the TMCC receiving apparatus including the control circuit 17 of the second embodiment, the time until the majority decision processing time is output while the majority decision processing time is output while the TMCC signal is monitored with low power consumption. Can be shortened.

  Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many variations and substitutions can be made within the spirit and scope of the invention. For example, a TMCC signal receiver can be combined with other signal receivers, and such a TMCC signal receiver can be provided in a terrestrial digital television broadcast receiver. Further, the element of the present invention can be applied to any system that conforms to the ISDB-T system. Accordingly, the invention should not be construed as limited by the embodiments described above, but only by the claims.

  The TMCC signal receiver according to the present invention can monitor an emergency alert broadcast signal with low power consumption, and is useful as a receiver in a transmission system using an emergency alert broadcast signal.

It is a figure which shows the bit allocation in a TMCC signal, and the content of the TMCC information to transmit. It is a figure which shows the example of a timing of the intermittent reception process in a flame | frame. It is an example of the timing of intermittent reception which used intermittent reception processing within a frame, and intermittent reception processing between frames together. It is a figure which shows the example of the majority determination process using the TMCC information for 3 frames in the TMCC signal receiver of Example 1 by this invention. It is a figure which shows the TMCC signal receiver of Example 1 by this invention. It is a figure which shows the example of a pattern of the intermittent reception control signal in the TMCC signal receiver of Example 1 by this invention. FIG. 3 is a block diagram of a control circuit for realizing three types of intermittent control signal patterns in the TMCC signal receiving apparatus according to the first embodiment of the present invention. It is a figure which shows an example of the reception mode switching reference | standard in the TMCC signal receiver of Example 1 by this invention. It is a figure which shows the TMCC signal receiver of Example 2 by this invention. It is a block diagram of the control circuit which implement | achieves three types of intermittent control signal patterns in the TMCC signal receiver of Example 2 by this invention. It is a figure which shows an example of the switching reference | standard of the majority decision determination changeover switch in the TMCC signal receiver of Example 2 by this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Reception antenna 11 Reception circuit 12 TMCC demodulation circuit 13 Symbol synchronous reproduction circuit 14 Majority decision processing circuit 15 Frame synchronous reproduction circuit 16 TMCC information determination circuit 17 Control circuit 18 Power switch 19 Power supply circuit 20 Reception mode switching circuit 21 Symbol thinning reception mode control Signal generation circuit 22 Majority determination reception mode control signal generation circuit 23 Continuous reception mode control signal generation circuit 24 Reception mode switch 25 Majority determination switch

Claims (3)

A TMCC signal receiving device for receiving a TMCC signal of terrestrial digital television broadcasting,
A receiving circuit for converting the received broadcast wave into an IF signal and outputting the IF signal;
A TMCC demodulation circuit that demodulates a TMCC signal from the IF signal and outputs TMCC information included in the TMCC signal;
A symbol-synchronized recovery circuit that generates and outputs a symbol-synchronized signal that is timed from the IF signal to an OFDM symbol;
A majority decision processing circuit that performs majority decision processing on the TMCC information and corrects transmission path errors;
A frame-synchronized reproduction circuit that generates and outputs a frame-synchronized signal whose timing is synchronized with the OFDM frame from the TMCC information
A TMCC information determination circuit that determines whether there is a change in the TMCC information subjected to the majority determination processing by the majority determination processing circuit, and outputs determination information of the determination result;
A control circuit that outputs an intermittent reception control signal for controlling the supply of power to the reception circuit so as to switch the reception mode of the reception circuit based on the two synchronization signals and the determination information;
The control circuit determines a synchronization state based on the two synchronization signals to control whether the reception circuit is intermittently received or continuously received, and receives determination information indicating that the TMCC information has changed. In such a case, an intermittent reception control signal for controlling the power supply of the receiving circuit is output so as to continuously receive the number of frames necessary for the majority decision determination process, and the majority decision determination processing time is shortened. A TMCC signal receiver characterized by the above. In the TMCC signal receiver according to claim 1,
The control circuit includes:
A reception mode switching circuit for determining which reception mode is suitable from the two synchronization signals and the determination information, and outputting a reception mode switching control signal for switching the reception mode based on the determination result;
A continuous reception mode control signal generation circuit that outputs a control signal for continuously operating the reception circuit as a first reception mode;
A symbol decimation reception mode control signal generation circuit that outputs a control signal for intermittently operating the reception circuit in units of symbols as a second reception mode;
A majority decision reception mode control signal generation circuit for outputting a control signal for operating the reception circuit to continuously receive the number of frames necessary for receiving by majority decision processing as a third reception mode; ,
A reception mode switch for switching between the three reception modes;
The reception mode switching circuit supplies power to the reception circuit so as to continuously receive the number of frames necessary for the majority determination process when receiving determination information indicating that the TMCC information has changed. A TMCC signal receiving apparatus characterized in that an intermittent reception control signal to be controlled is output from the reception mode changeover switch to shorten the majority decision processing time. In the TMCC signal receiver according to claim 1 or 2,
Between the majority decision processing circuit and the TMCC information decision circuit, further comprises a majority decision changeover switch,
The control circuit supplies a majority decision processing control signal for controlling execution of the majority decision processing by the majority decision processing circuit to the majority decision changeover switch according to the decision information,
When the majority decision determination changeover switch receives the majority decision determination processing control signal, the majority decision determination changeover switch connects the TMCC demodulation circuit and the TMCC information determination circuit between the majority decision determination processing circuit and the TMCC information determination circuit. By operating to switch to a connection and minimizing the frequency of majority decision processing in the majority decision processing circuit, the time for outputting decision information from the TMCC information decision circuit is shortened, and the TMCC receiver A TMCC signal receiver characterized in that power consumption is reduced.

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