JP2006304054A - Television receiving apparatus and receiving method of television broadcast - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To sharply reduce power consumption for extracting a start control signal for emergency broadcast, in a standby mode where television broadcast is neither viewed nor listened to. <P>SOLUTION: A CPU 3 executes, upon detecting a start control signal for emergency broadcast in a periodic broadcast period included in the receiving signal of the television broadcast, mute control of a tuner circuit 1, gain control of an AMP circuit 11, control of a local oscillation circuit 13, and control of an OFDM demodulation circuit 2 for demodulating a receiving signal from the tuner circuit 1. The CPU further, when an instruction of stopping reception from an operation part 5 during reception of the television broadcast in a normal reception mode, sets the reception capability of a receiving circuit for the reception capability of the standby mode; and, after the reception of the television broadcast is stopped, controls the tuner circuit 1 set to the reception capability of the standby mode to an operating state, in synchronism with the broadcast period of the start control signal, and controls the same to an operation stop state during other broadcast period. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a television receiver and a television broadcast receiving method, and more particularly to a television receiver and a television broadcast receiving method for receiving an emergency broadcast broadcast in the event of a natural disaster such as an earthquake or a typhoon. is there.

In BS broadcasting by broadcasting satellites, CS broadcasting by communication satellites, and terrestrial digital broadcasting that has started broadcasting in some areas from December 2003, video encoding, audio encoding, and multiplexing are used. Adopted. In the multiplexing system, there are emergency broadcasts in the event of natural disasters such as earthquakes and typhoons, in addition to video information and audio information of ordinary programs. FIG. 7 is a schematic block diagram of a general receiving circuit in a television receiver that receives terrestrial digital broadcasting. This receiving circuit receives and demodulates packetized digital broadcasting TS (transport stream) packets. In FIG. 7, the receiving circuit includes a tuner circuit 110 and an OFDM (Orthogonal Frequency Division Multiplex) demodulation circuit 120. Although not shown in the figure, the tuner circuit 110 amplifies a television broadcast high-frequency reception signal obtained from an antenna, and converts a high-frequency reception signal output from the amplifier circuit into an intermediate-frequency reception signal. A mixer circuit, a local oscillation circuit, a filter circuit that removes unnecessary components of a reception signal output from the mixer circuit, and the like are included.
The OFDM demodulation circuit 120 includes an ADC (Analog-to-Digital Converter) circuit 121, an FFT (Fast Fourier Transform) circuit 122, a demodulation circuit 123, a TMCC (Transmission & Multiplexing Configuration Control) circuit 124, an emergency broadcast decoder circuit 125, and the like. Has been. The ADC circuit 121 converts the reception signal output from the tuner circuit 110 from analog to digital. The FFT circuit 122 performs a fast Fourier transform on the reception signal output from the ADC circuit 121. The demodulating circuit 123 demodulates the received signal output from the FFT circuit 122 to reproduce the original baseband signal and separates it into video information, audio information, and character information, and a DAC (Digital-to-Analog Converter). ) Output to the next circuit block including the circuit. The TMCC circuit 124 extracts a TS packet of a transmission control signal (TMCC signal) included in the reception signal output from the FFT circuit 122.

  The TS packet of the transmission control signal includes a change instruction for notifying the change of the modulation scheme of the main signal, transmission mode / slot information for notifying the modulation scheme being transmitted, and a relative TS / slot for notifying a plurality of MPEG-TSs assigned to the slot. Information, relative TS number for reporting absolute TS number relative to relative TS number, 1-bit activation control signal for emergency broadcast, uplink control signal used by broadcast station, spare extension information, and parity code It consists of a certain RS code. That is, as shown in FIG. 8, the TS packet of the transmission control signal is composed of 204 bits consisting of 188-bit packet data and 16-bit parity. The emergency broadcast activation signal is present in the 27th bit from the beginning of the packet. In FIG. 7, the emergency broadcast decoding circuit 125 is for 1-bit emergency broadcast represented by a value of 0 (no emergency broadcast) or 1 (emergency broadcast) from the TS packet of the transmission control signal output from the TMCC circuit 124. The start control signal is extracted and output to a control circuit (not shown). When the activation control signal for emergency broadcast is 1, the control circuit displays a message indicating that the broadcast is emergency broadcast on the display and performs control to match the broadcast channel.

  By the way, in order to extract the activation control signal for emergency broadcasting, it is a necessary condition that the television receiver receives the television broadcast. When the television broadcast is not viewed, when is it broadcasted? Maintaining the television receiver in the reception state for emergency broadcasts that are not known leads to unnecessary power consumption, which is uneconomical and wasteful use of energy resources. In view of this, some proposals have been made to extract an emergency broadcast activation control signal while suppressing power consumption when the user is not viewing a television broadcast.

For example, in a proposed digital broadcast demodulation / decoding device, a power saving control unit is provided in the digital broadcast demodulation / decoding device that performs demodulation processing / decoding processing. The received signal input from the tuner is signal-processed by the PSK demodulator and the Viterbi decoder and branched to the main signal and the TMCC signal, and then the TMCC signal processing system maintains normal operation and saves power. The control unit stops clocks for the signal processing unit of the main signal, the RS decoding unit, and the TS selection unit, and performs power saving by putting these units in a dormant state. (See Patent Document 1)
In addition, in a proposed digital modulation signal receiver, a power saving mode controller is provided to process a received signal output from a tuner circuit including an AGC amplifier, a mixer, an oscillator, an LPF (low pass filter), and an AD converter. A power saving signal that operates with power saving is supplied to each circuit. Specifically, the carrier recovery circuit that controls the complex multiplier, the symbol recovery circuit that controls the interpolator, and the clock supplied to the waveform equalizer are periodically stopped, and the complex multiplier, interpolator, and waveform equalizer are Operate intermittently to reduce power consumption. Further, the clock for the AGC circuit is periodically stopped, and the AGC signal to the DA converter that controls the AGC amplifier of the tuner circuit is periodically fixed, thereby suppressing the power consumption required for the error detection processing of the AGC circuit. . (See Patent Document 2)
JP 2001-094902 A JP 2001-218129 A

However, as in Patent Document 1 and Patent Document 2 described above, there is a limit to the suppression of power consumption of the entire television receiver only by stopping the clock for a partial circuit or periodically stopping the clock. For this reason, mobile television receivers that use a battery for power supply, such as portable portable television receivers and mobile phone devices that will be able to receive terrestrial digital broadcasts in the future, are used for emergency broadcasting. Because of the power consumption for extracting the activation control signal, there is a possibility that the television broadcast cannot be received due to the influence of the battery voltage drop. In particular, when a disaster occurs when going out to a mountain or sea with such a mobile television receiver, the influence of the battery voltage drop is fatal.
The present invention is for solving such a conventional problem, and greatly reduces power consumption for extracting an emergency broadcast activation control signal when a television broadcast is not being viewed. Objective.

  The television receiver according to claim 1 includes a receiving means for receiving a television broadcast (in the embodiment, corresponding to the tuner circuit 1 and the OFDM demodulator circuit 2 in FIG. 1), and a plurality of stages (in the embodiment, 2 Receiving setting means (corresponding to the tuner RF control circuit 28 in FIG. 1 in the embodiment) that selects the receiving ability of one stage from the receiving ability of the stage) and sets it for the receiving means; , Emergency broadcast identification information (in the embodiment, 1 bit) included in the reception signal of the television broadcast received by the reception unit set to the reception capability of an arbitrary stage by the reception setting unit Detection means (corresponding to the emergency broadcast decoding circuit 25 in FIG. 1 in the embodiment) and the receiver set to the first stage reception capability. When a command to stop reception is input during reception of a television broadcast, the reception setting unit is instructed to set the reception capability of the reception unit to a second reception capability lower than the first reception capability. The setting instruction means (corresponding to the CPU 3 in FIG. 1 in the embodiment) and the receiving means set to the second receiving capability are synchronized with the broadcast period of the identification information after the reception of the television broadcast is stopped. Thus, it is configured to include reception control means (corresponding to the CPU 3 and the clock synchronization circuit 27 in FIG. 1 in the embodiment) that controls to the operation state and controls to the operation stop state during other broadcasting periods. Yes.

  In the television receiver according to claim 1, as described in claim 2, the reception control means, after the reception of the television broadcast is stopped, the demodulation function of the identification information in the reception means (in the embodiment, FIG. (Which corresponds to the function of the TMCC circuit 24 of FIG. 1) and the demodulation function of video information and audio information (corresponding to the function of the demodulation circuit 23 of FIG. 1 in the embodiment) is stopped. Also good.

Further, in the television receiver according to claim 1, as described in claim 3, the reception control means causes the tuner circuit of the reception means to receive the identification information when an instruction to stop the reception of the television broadcast is input. However, the minimum reception sensitivity may be set.
Further, in the television receiver according to claim 3, as described in claim 4, the reception control means includes power control means for controlling power supplied to the tuner circuit (in the embodiment, the clock synchronization circuit of FIG. 1). 27 and corresponding to the function of the switch circuit 16 in FIG. 2, and when a command to stop the reception of the television broadcast is input, power is supplied to the tuner circuit in synchronization with the broadcast period of the identification information, The power supply may be stopped during other broadcast periods.

  The television broadcast receiving method according to claim 5 is a receiving means for receiving a television broadcast by selecting one stage of reception capability from a plurality of stages (corresponding to two stages in the embodiment). (In the embodiment, it corresponds to the tuner circuit 1 and the OFDM demodulator circuit 2 in FIG. 1) and the television set received by the receiving means set to the receiving capability at an arbitrary stage by the step A Step B for detecting emergency broadcast identification information (corresponding to a 1-bit activation control signal in the embodiment) included in a broadcast reception signal in a periodic broadcast period, and first stage reception capability When a command to stop reception is input during reception of a television broadcast by the receiving means set to, the receiving ability of the receiving means is changed to a second receiving ability lower than the first receiving ability. After, controls the reception unit to operate in synchronization with the broadcast period of the identification information, other broadcast period executes the steps C to control the operation stop state.

  In the television broadcast receiving method according to claim 5, as described in claim 6, after the reception of the television broadcast is stopped, step C is a demodulating function of identification information in the receiving means (in the embodiment, FIG. 1 (corresponding to the function of one TMCC circuit 24) and maintaining the demodulation function of video information and audio information (corresponding to the function of the demodulation circuit 23 of FIG. 1 in the embodiment). May be.

In the television broadcast receiving method according to claim 5, as described in claim 7, when the instruction to stop the reception of the television broadcast is input, the step C receives the identification information through the tuner circuit of the receiving means. A configuration may be adopted in which the lowest possible reception sensitivity is set.
Furthermore, in the television broadcast receiving method according to claim 7, as described in claim 8, when the instruction to stop the reception of the television broadcast is input, the step C is synchronized with the broadcast period of the identification information. A configuration may be adopted in which power is supplied to the tuner circuit and the power supply is stopped during other broadcasting periods.

  According to the television receiver and the television broadcast receiving method of the present invention, it is possible to significantly reduce the power consumption for extracting the emergency broadcast activation control signal when the television broadcast is not viewed. Is obtained.

Embodiments of a television receiver according to the present invention will be described below with reference to FIGS.
FIG. 1 is a schematic block diagram illustrating a configuration of a television receiver according to the embodiment. As shown in FIG. 1, the television receiver of this embodiment includes a CPU 3, an interface circuit 4, and an operation unit 5 in addition to a tuner circuit 1 and an OFDM (Orthogonal Frequency Division Multiplex) demodulating circuit 2 that constitute a receiving circuit. ing. The tuner circuit 1, which will be described in detail later, has a function of amplifying a television broadcast high-frequency reception signal obtained from an antenna, converting the high-frequency reception signal into an intermediate-frequency reception signal, and further removing unnecessary components. It has.

  The OFDM demodulation circuit 2 includes an ADC (Analog-to-Digital Converter) circuit 21, an FFT (Fast Fourier Transform) circuit 22, a demodulation circuit 23, a TMCC (Transmission & Multiplexing Configuration Control) circuit 24, an emergency broadcast decoder circuit 25, and clock control. The circuit 26, a clock synchronization circuit 27, a tuner RF control circuit 28, a clock generation circuit 29, and the like. The ADC circuit 21 converts the reception signal output from the tuner circuit 11 from analog to digital. The FFT circuit 22 performs a fast Fourier transform on the reception signal output from the ADC circuit 21. The demodulating circuit 23 demodulates the received signal output from the FFT circuit 22 to reproduce the original baseband signal and separates it into video information, audio information, and character information, and a DAC (Digital-to-Analog Converter). ) Output to the next circuit block (not shown) including the circuit. The TMCC circuit 24 extracts a TS packet of a transmission control signal (TMCC signal) included in the reception signal output from the FFT circuit 22. The emergency broadcast decoding circuit 25 extracts a 1-bit activation control signal of b26 emergency broadcast from the 204-bit TMCC signal (b0 to b203) extracted by the TMCC circuit 24 and inputs it to the CPU 3, and also activates the activation control signal. The emergency broadcast decode signal b, which is a pulse signal synchronized with the signal, is input to the clock synchronization circuit 27. Since the emergency broadcast decode signal b corresponding to the TMCC activation control signal is inserted at a constant cycle, n other bits of the TS packet are included in the period from one emergency broadcast decode signal b to the next emergency broadcast decode signal b. Then, the emergency broadcast decode signal b is input to the clock synchronization circuit 27 at a cycle of (n + 1) bits.

  The clock generation circuit 29 generates a reference clock signal φ 1 and outputs it to the clock control circuit 26 and the clock synchronization circuit 27. The clock control circuit 26 controls input or stop of input of the clock signal to the demodulation circuit 23 according to the reference clock signal φ1 from the clock generation circuit 29 and the clock control signal from the CPU 3. The clock synchronization circuit 27 has three signals c and d in response to the reference clock signal φ1 from the clock generation circuit 29, the emergency broadcast decode signal b input from the emergency broadcast decode circuit 25, and the standby signal a from the CPU 3. , H are generated, the signal c is output to the tuner circuit 1, the signal d is output to the tuner circuit 1, the ADC circuit 21, and the FFC circuit 22, and the signal h is output to the tuner RF control circuit 28. Details of each signal will be described later. The tuner RF control circuit 28 outputs a gain control signal g to the tuner circuit 1 in response to the signal h from the clock synchronization circuit 27 and the standby signal a from the CPU 3.

  FIG. 2 (1) is a block diagram showing the internal configuration of the clock synchronization circuit 27 and the tuner RF control circuit 28 in FIG. 1, and FIG. 2 (2) shows signal waveforms thereof. In FIG. 2 (1), the internal counter circuit 701 (frequency divider) is based on the reference clock signal φ1 from the clock generation circuit 29 in FIG. 1, and a clock signal φ2 having the same frequency as the transmission clock signal of the TS packet, and Then, a clock signal φ3 for signal processing of the tuner circuit 1, ADC 21, and FFT 22 is generated and output. The AND gate circuit 702 outputs a logical product of the standby signal a input from the CPU 3 to the terminal A and the emergency broadcast decode signal b input from the emergency broadcast decode circuit 25 to the terminal B.

The bit count circuit 704 counts the clock signal φ2 in accordance with the input of the reset signal r output from the AND gate circuit 702. That is, as shown in FIG. 2 (2), the clock signal φ2 is counted in response to the input of the emergency broadcast decode signal b (k), and the pulse signal f synchronized with the jth pulse is output, and (j + 2) A pulse signal e synchronized with the eyes is output. The latch circuit 705 inputs the pulse signal e from the bit count circuit 704 and the reset signal inverted by the inverter circuit 706 to the clock terminal CK, and latches the data (1 or 0) input to the data terminal D. . As a result, the signal i output from the terminal Q of the latch circuit 705 changes from the low level to the high level in synchronization with the rising edge of the pulse signal e, and according to the input of the next emergency broadcast decode signal b (k + 1). Through the AND gate circuit 702, the high level is changed to the low level again in synchronization with the rise of the reset signal inverted by the inverter circuit 706. However, the timing at which the signal i output from the latch circuit 705 changes from the high level to the low level due to the propagation delay of the AND gate circuit 702 and the inverter circuit 706 is the emergency broadcast decode signal. Slightly behind the timing of b (k + 1).
Similarly, the latch circuit 707 inputs the pulse signal f from the bit count circuit 704 and the reset signal inverted by the inverter circuit 708 to the clock terminal CK, and the data (1 or 0) input to the data terminal D Latch. As a result, the signal h output from the terminal Q of the latch circuit 707 changes from the low level to the high level in synchronization with the rising edge of the pulse signal f, and according to the input of the next emergency broadcast decode signal b (k + 1). Then, the signal changes from the high level to the low level again in synchronization with the rising edge of the reset signal inverted by the inverter circuit 708 via the AND gate circuit 702. Also in this case, the timing at which the signal h output from the latch circuit 707 changes from the high level to the low level due to the propagation delay of the AND gate circuit 702 and the inverter circuit 708 is an emergency. Slightly behind the timing of the broadcast decode signal b (k + 1).

  The OR gate circuit 709 outputs a logical sum signal c of the pulse signal i from the latch circuit 705 and the signal obtained by inverting the standby signal a by the inverter circuit 710 to the tuner circuit 1. The AND gate circuit 711 supplies a signal d, which is a logical product of the clock signal φ3 output from the internal counter circuit 701 and the signal c output from the AND gate circuit 709, to the tuner circuit 1, the ADC circuit 21, and the FFT circuit 22. Output. The AND gate circuit 801 of the tuner RF control circuit 28 outputs to the tuner circuit 1 a signal g that is the logical product of the signal h output from the latch circuit 707 and the standby signal a from the CPU 3.

  FIG. 3 is a block diagram showing an internal configuration of the tuner circuit 11. The AMP circuit 11 amplifies and outputs a high-frequency received signal of terrestrial digital broadcasting input from an antenna. The MIXER circuit 12 combines the reception signal output from the AMP circuit 11 and the local oscillation signal from the OSC circuit 13 that oscillates the local signal in accordance with the signal d from the OFDM demodulation circuit 2 to receive an intermediate frequency. Output a signal. The FILTER circuit 14 removes unnecessary components of the reception signal output from the MIXER circuit 12 and outputs the result to the ADC circuit 21 of the OFDM demodulation circuit 2. The gain control circuit 15 lowers the reception sensitivity of the AMP circuit 11 when the signal g from the OFDM demodulation circuit 2 is high level, and increases the reception sensitivity when the signal g is low level. The switch circuit 16 supplies the voltage Vc to the tuner circuit 1 when the signal c from the OFDM demodulator circuit 2 is at a high level, and enters the operating state, but when the signal c is at a low level, the voltage Vc to the tuner circuit 1 is set. Is turned off and muted.

  Next, regarding the operation of the television receiver of FIG. 1, the flowchart of the CPU 3 shown in FIG. 5, the timing chart of the clock synchronization circuit 27 in the standby mode shown in FIG. 6, and the clock synchronization circuit 27 in the emergency broadcast detection mode shown in FIG. This will be described based on the timing chart. The CPU 3 receives a 1-bit activation control signal from the emergency broadcast decoding circuit 25 in FIG. 1 when a television broadcast is being viewed, and when the activation control signal is 0 (low level), the channel being received is received. However, when the start control signal changes to 1 (high level), the output is switched to emergency broadcast video information, audio information, and text information.

  In the flowchart of FIG. 5, the CPU 3 determines whether or not the standby mode is set from the operation unit 5 (step S1). That is, it is determined whether or not the television broadcast reception state is switched to the non-reception state by the switch operation. When the standby mode is set, the RF control (a) is set to “1” (step S2), and a signal for stopping the clock control is transmitted (step S3). As a result, the standby signal a from the CPU 3 of FIG. 1 to the clock synchronization circuit 27 and the tuner RF control circuit 28 changes from the low level to the high level, and is input from the clock generation circuit 29 to the demodulation circuit 23 by the clock control circuit 26. The clock signal φ1 is stopped and the operation of the demodulation circuit 23 is stopped. Further, the high-level standby signal a is inverted by the inverter circuit 710 illustrated in FIG. 2A and is input to the terminal A of the OR gate circuit 709. At this time, since the signal output from the terminal Q of the latch circuit 705 is at the low level, the low level signal c is input from the OR gate circuit 709 to the switch circuit 16 of the tuner circuit 1. For this reason, the switch circuit 16 is turned off and the voltage Vc to the tuner circuit 1 is cut off. That is, in the standby mode, the tuner circuit 1 is inactive and its power consumption is almost zero.

  After the low level signal c is input to the switch circuit 16 of the tuner circuit 1 and the voltage Vc to the tuner circuit 1 is cut off, the clock synchronization circuit 27 shown in FIG. As shown in the chart, the high level standby signal a and the emergency broadcast decode signal b synchronized with the TMCC activation control signal are input to the AND gate circuit 702, and the reset signal r synchronized with the emergency broadcast decode signal b is received. Input to the bit counter circuit 704. Therefore, as shown in FIG. 2B, the bit counter circuit 704 starts counting the clock signal φ2 having the same frequency as the transmission clock. As a result, every time the signal e is output from the bit counter circuit 704, the signal i which becomes high level at a timing slightly before the emergency broadcast decode signal b and becomes low level at a timing immediately after the emergency broadcast decode signal b. A signal c that is input to the terminal B of the OR gate circuit 709 and becomes high before and after the emergency broadcast decode signal b is input to the switch circuit 16 of the tuner circuit 1. As a result, the switch circuit 16 changes from off to on before and after the emergency broadcast decode signal b, and the tuner circuit 1 intermittently changes from the non-operating state to the operating state before and after the emergency broadcast decode signal b.

  Further, when the standby mode is set and the CPU 3 sets the RF control (a) to “1” (step S2) and sends a signal for stopping the clock control (step S3), in FIG. 2 (1) The high level standby signal a is input from the CPU 3 to the terminal A of the AND gate circuit 801. In this case, since the signal h of the output Q of the latch circuit 707 is low level, the low level standby signal is output from the CPU 3. As in the normal reception mode in which the signal a is input, the low level signal g is input from the AND gate circuit 801 to the gain control circuit 15 of the tuner circuit 1. As a result, the AMP circuit 11 maintains a high gain in the normal reception mode. Thereafter, in the clock synchronization circuit 27 shown in FIG. 2 (1), as shown in the timing chart of FIG. 6, the high-level standby signal a and the emergency broadcast decode signal b synchronized with the TMCC activation control signal Is input to the AND gate circuit 702, and a reset signal r synchronized with the emergency broadcast decode signal b is input to the bit counter circuit 704. Therefore, as shown in FIG. 2B, the bit counter circuit 704 starts counting the clock signal φ2 having the same frequency as the transmission clock. Therefore, every time the signal f is output from the bit counter circuit 704, the signal h which becomes high level at a timing slightly before the emergency broadcast decode signal b and becomes low level at a timing immediately after the emergency broadcast decode signal b is ANDed. Input to the terminal B of the gate circuit 801. At this time, since the high-level standby signal a is input to the terminal A of the AND gate circuit 801, the signal g which becomes high before and after the emergency broadcast decode signal b from the AND gate circuit 801 is the gain of the tuner circuit 1. Input to the control circuit 15. As a result, the gain of the AMP circuit 11 decreases before and after the emergency broadcast decode signal b.

  If the standby mode is not set in step S1 of the flowchart of FIG. 4, it is determined whether or not the standby mode has been canceled by operating the operation unit 5 (step S4). That is, it is determined whether or not the television broadcast is switched from the non-reception state to the reception state by the switch operation of the operation unit 5. If the standby mode is not canceled, it is determined whether or not an emergency code (activation control signal = 1) has been detected from the emergency broadcast decoding circuit 25 (step S5). When the switch operation switches from the non-reception state of the television broadcast to the reception state, or when an emergency code of 1 (high level) is detected, the RF control (a) is set to “0” (step S6), A signal for operating the clock control is output (step S7). As a result, the standby signal a from the CPU 3 in FIG. 1 to the clock synchronization circuit 27 and the tuner RF control circuit 28 changes from the high level to the low level, and the clock signal φ1 is sent from the clock generation circuit 29 to the demodulation circuit 23 by the clock control circuit 26. Is input, and the operation of the demodulation circuit 23 is resumed. Further, the low level standby signal a is inverted by the inverter circuit 710 shown in FIG. 2A, and the high level signal c is input to the switch circuit 16 of the tuner circuit 1 through the OR gate circuit 709. Accordingly, the switch circuit 16 is turned on and the voltage Vc is supplied to the tuner circuit 1 so that the tuner circuit 1 is continuously operated.

  FIG. 6 shows a timing chart when an emergency code is detected. When the standby mode is not canceled in the standby mode and the emergency control is not detected when the activation control signal = 0, the state shown in FIG. 5 is maintained, but when the activation control signal = 0 changes to 1 The low level standby signal a is inverted by the inverter circuit 710, and the high level signal is input to the terminal A of the OR gate circuit 709. Further, since the low level standby signal a is input to the AND gate circuit 702, the reset signal r, which is the output thereof, continuously becomes low level, and the count operation of the bit counter circuit 704 is stopped. For this reason, the signal e from the bit counter circuit 704 is also stopped, and the signal i from the output Q of the latch circuit 705 is continuously at a low level. At this time, since a high level signal is input from the inverter circuit 710 to the terminal A of the OR gate circuit 709, the OR gate circuit 709 does not depend on the signal i input to the terminal B of the OR gate circuit 709. A high level signal c is input to the switch circuit 16 of the tuner circuit 1. Therefore, the switch circuit 16 is continuously turned on regardless of the period of the emergency broadcast decode signal b, and the mute state of the tuner circuit 1 is released. That is, the tuner circuit 1 is continuously operated.

  Since the high level signal c from the OR gate circuit 709 is also input to the terminal B of the AND gate circuit 711, the clock signal φ3 from the internal counter circuit 701 is input to the terminal A of the AND gate circuit 711. The clock signal d (clock signal φ 3) is supplied from the AND gate circuit 711 to the local oscillation circuit 13, ADC circuit 21, and FFT circuit 22 of the tuner circuit 1. Further, since the low level standby signal a from the CPU 3 is input to the terminal A of the AND gate 801 and the low level signal h is input from the output Q of the latch circuit 707 to the terminal B of the AND gate circuit 801, A low level signal g is input from the AND gate circuit 801 to the gain control circuit 15 of the tuner circuit 1. Therefore, the gain of the AMP circuit 11 is continuously high.

  Note that the CPU 3 sends a signal for stopping the clock control in step S3 in FIG. 4 or after sending a signal for stopping the clock control in step S7, or when no emergency code is detected in step S5. Then, other processes are performed (step S8), the process proceeds to step S1, and the above processes are repeated. Examples of other processes include processes according to operations such as channel change and volume change from the operation unit 5.

As described above, according to this embodiment, the CPU 3 controls the mute control of the tuner circuit 1, the gain control of the AMP circuit 11, and the local oscillation circuit 13 in the receiving circuit that receives the television broadcast. The OFDM demodulating circuit 2 that demodulates the received signal is controlled to select and set one stage of receiving ability from the two stages of receiving ability of the normal receiving mode and the standby mode. When set, an emergency broadcast activation control signal in a periodic broadcast period included in a television broadcast reception signal is detected. When receiving an instruction to stop reception from the operation unit 5 while receiving a television broadcast in the normal reception mode, the CPU 3 sets the reception capability of the reception circuit to the reception capability of the standby mode, and receives the television broadcast. After being stopped, the tuner circuit 1 set to the reception capability in the standby mode is controlled to operate in synchronization with the broadcast period of the activation control signal, and is controlled to stop in other broadcast periods.
That is, after the reception of the television broadcast is stopped, the operation of the demodulation function of the activation control signal in the reception circuit is maintained, and the demodulation function of the video information and the audio information is stopped.
Further, when a command to stop the reception of the television broadcast is input, the tuner circuit 1 is set to a minimum reception sensitivity capable of receiving the activation control signal.
When a command to stop the reception of the television broadcast is input, power is supplied to the tuner circuit 1 in synchronization with the broadcast period of the activation control signal, and the power supply is stopped during other broadcast periods.
Therefore, in the standby mode, it is possible to significantly reduce the power consumption for extracting the emergency broadcast start control signal by controlling the tuner circuit 1 in the operation stop state except during the broadcast period of the start control signal.

  In the above embodiment, in the standby mode, the gain of the AMP circuit 11 is controlled during the start control signal broadcast period. However, in the standby mode, the AMP circuit is continuously set regardless of the start control signal broadcast period. A configuration in which the gain of 11 is controlled to be lowered is also possible. Even when the gain of the AMP circuit 11 is lowered and the C / N (carrier-to-noise ratio) is lowered, the activation control signal for emergency broadcasting is different from video information and audio information, and is 1 (high level) or 0 (low level). Level), it can be easily detected.

  Further, in the above embodiment, the tuner circuit 1 set to the reception capability in the standby mode is controlled to be in an operation state in synchronization with the broadcast period of the activation control signal, and is controlled to be in an operation stop state during the other broadcast periods. However, the operation state may be controlled in synchronization with the TMCC signal, and the operation stop state may be controlled during other broadcast periods. In this case, the transmission clock signal of the actual TMCC signal is counted instead of the clock signal φ2.

  In the above embodiment, the gain of the AMP circuit 11 is set to two levels, that is, the normal reception mode and the standby mode. However, the gain is set to a plurality of levels of three or more levels. Good. For example, in a configuration in which three stages are set, the AMP circuit 11 is set to the highest gain in the normal reception mode, and is set to the next highest gain in synchronization with the broadcast period of the activation control signal in the standby mode. The period other than is set to the lowest gain. Alternatively, in the configuration in which four stages are set, in the normal reception mode, the AMP circuit 11 is set to the highest gain, and in the standby mode, the next higher gain is set in synchronization with the broadcast period of the activation control signal. The TMCC signal period other than the control signal broadcast period is set to the next highest gain, and the other periods are set to the lowest gain.

In the television receiver of the above embodiment, the invention of the device that executes the control program of the reception method stored in the device in advance, that is, the invention of the product has been described, but the television broadcast that is executed in the television receiver of the above embodiment The receiving method constitutes the invention of the method.
That is, the television broadcast receiving method according to the present invention includes a step A in which one stage of reception capability is selected from a plurality of stages of reception capability and set for a receiving means for receiving a television broadcast. Step B for detecting emergency broadcast identification information in a periodic broadcast period included in a reception signal of a television broadcast received by the receiving means set at an arbitrary stage reception capability; When an instruction to stop reception is input during reception of a television broadcast by the receiving means set to the receiving ability, the receiving ability of the receiving means is changed to a second receiving ability lower than the first receiving ability. After the change, step C is executed in which the receiving means is controlled to operate in synchronization with the broadcast period of the identification information, and is controlled to stop in other broadcast periods.

In step C, after the reception of the television broadcast is stopped, the operation of the demodulating function of the identification information in the receiving means is maintained, and the demodulating function of the video information and the audio information is stopped.
Alternatively, the step C sets the tuner circuit of the receiving means to a minimum receiving sensitivity capable of receiving the identification information when an instruction to stop the reception of the television broadcast is input. In this case, the step C further supplies power to the tuner circuit in synchronization with the broadcast period of the identification information when an instruction to stop the reception of the television broadcast is input, and the power is supplied during the other broadcast periods. Stop supplying.

FIG. 2 is a block diagram illustrating a partial configuration of a television receiver according to the present invention. FIG. 2 is a circuit diagram showing an internal configuration of a clock synchronization circuit in FIG. 1. FIG. 2 is a circuit diagram showing an internal configuration of a tuner circuit in FIG. 1. The flowchart which shows operation | movement of CPU in FIG. The signal timing chart in the standby mode of the television receiver of FIG. The signal timing chart at the time of emergency broadcast detection of the television receiver of FIG. The block diagram which shows the structure of a part of conventional television receiver. TMCC TS packet data format for digital terrestrial television broadcasting.

Explanation of symbols

1 tuner circuit 2 OFDM demodulator circuit 3 CPU
4 Interface 5 Operation section

Claims (8)

Receiving means for receiving a television broadcast;
A reception setting means for selecting one stage of reception ability from a plurality of stages of reception ability and setting the reception means;
Detecting means for detecting identification information of an emergency broadcast in a periodic broadcast period included in a reception signal of a television broadcast received by the receiving means set at a reception capability at an arbitrary stage by the reception setting means;
When an instruction to stop reception is input during reception of a television broadcast by the receiving means set to the receiving capability of the first stage, the receiving capability of the receiving means is lower than the first receiving capability. Setting instruction means for instructing the reception setting means to set the reception capability of 2;
After the reception of the television broadcast is stopped, the receiving means set to the second reception capability is controlled to be in an operation state in synchronization with the broadcast period of the identification information, and is controlled to be in an operation stop state during the other broadcast periods. Reception control means;
A television receiver comprising:   The reception control means maintains the operation of the demodulation function of the identification information in the reception means and stops the demodulation function of video information and audio information after the reception of the television broadcast is stopped. The television receiver according to 1.   The reception control means sets a tuner circuit of the reception means to a minimum reception sensitivity capable of receiving identification information when a command to stop reception of a television broadcast is input. The television receiver according to 1.   The reception control means further includes power control means for controlling power supplied to the tuner circuit, and when a command to stop reception of a television broadcast is input, the tuner is synchronized with a broadcast period of identification information. 4. The television receiver according to claim 3, wherein power is supplied to the circuit, and the power supply is stopped during other broadcasting periods. Step A for setting a receiving means for receiving a television broadcast by selecting one stage of receiving ability from a plurality of stages of receiving ability;
A step B of detecting emergency broadcast identification information of a periodic broadcast period included in a reception signal of a television broadcast received by the receiving means set to a reception capability at an arbitrary stage by the step A;
When an instruction to stop reception is input during reception of a television broadcast by the receiving means set to the receiving capability of the first stage, the receiving capability of the receiving means is lower than the first receiving capability. Step C for controlling the receiving means to the operating state in synchronization with the broadcast period of the identification information and controlling to the operation stopped state for the other broadcasting periods,
TV broadcast reception method to perform.   6. The step C is characterized in that after reception of a television broadcast is stopped, the operation of the demodulation function of the identification information in the reception means is maintained, and the demodulation function of the video information and audio information is stopped. The receiving method of the television broadcast as described in 2.   6. The step C is characterized in that, when a command to stop reception of a television broadcast is input, the tuner circuit of the receiving means is set to a minimum receiving sensitivity capable of receiving identification information. The receiving method of the television broadcast as described in 2.   In step C, when an instruction to stop reception of a television broadcast is input, power is supplied to the tuner circuit in synchronization with a broadcast period of identification information, and power supply is stopped during other broadcast periods. The method for receiving a television broadcast according to claim 7.

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