JP2009117854A - Phase change memory element, phase change channel transistor and memory cell array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower a voltage required for phase transition from an amorphous phase to a crystal phase in a phase change memory element. <P>SOLUTION: The phase change memory element (1) includes a first electrode (6), a second electrode (8), and a memory layer (14) provided between the first electrode (6) and the second electrode (8). The memory layer (14) includes at least a first layer (10) constituted of a phase change material stable in an amorphous phase and a crystal phase at room temperature, and a second layer (12) constituted of a resistant material. The resistance value of the second layer (12) is made smaller than a resistance value when the first layer (10) is of the amorphous phase, and is made larger than a resistance value when the first layer (10) is of the crystal phase. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a phase change memory element and a phase change channel transistor using a phase change material that is stable in a crystalline phase and an amorphous phase at room temperature, and a memory cell array composed of these elements or transistors.

  For example, chalcogenide-based materials have characteristics that are stable in a crystalline phase and an amorphous phase at room temperature, and the specific resistance differs by 2 to 4 digits in each phase. Therefore, information is written by stabilizing a thin film of such a material in either a crystalline phase or an amorphous phase, and information is read by determining whether the thin film is a crystalline phase or an amorphous phase from measurement of resistance values. In addition, a non-volatile memory is realized.

  In such a memory, when writing information, that is, 1, 0, it is necessary to change the phase change material thin film from the crystalline phase to the amorphous phase or from the amorphous phase to the crystalline layer. In a chalcogenide-based material, normally, when the material is heated to 630 ° C. or higher and rapidly cooled, it is solidified as an amorphous phase, and when the material is heated to 200 ° C. or higher and gradually cooled, the crystal phase is stabilized. The heating of the phase change material thin film is performed using Joule heat generated by passing an electric current through the thin film. When the phase change material thin film transitions to the amorphous phase, the resistance value of the thin film is two to four orders of magnitude greater than the resistance value when transitioned to the crystalline phase. Therefore, by detecting the amount of current flowing by applying a read voltage to the phase change material thin film, it is possible to read out the written information, that is, whether the thin film is stable in the amorphous phase or the crystalline phase.

  Recently, in such a phase change material thin film, it has been found that the amount of current can be controlled by applying a bias voltage perpendicular to the direction of current flow. A phase change channel transistor having a function has been proposed (see Patent Document 1). In this phase change channel transistor, the channel portion is made of a phase change material to provide a memory function, and the current flowing through the channel portion is switched on and off by the gate voltage, thereby controlling the timing of writing and reading information. Can be controlled. Therefore, when a RAM is configured using this phase change channel transistor, the selection transistor and the memory portion can be realized by a single transistor, and an ultra-high density storage element can be provided. Incidentally, in a conventional DRAM, a memory cell including a selection transistor and a capacitor constitutes a single memory cell, and the area of the memory cell increases due to the necessity of incorporating the capacitor on a semiconductor substrate, thereby hindering miniaturization. Has been. As a result, there is a limit to increasing the density of memory cells.

JP-A-2005-93619

  In any of the phase change memory element and the phase change channel transistor, it is necessary to cause a phase transition in the phase change material layer in order to write information. For the phase transition, it is necessary to generate Joule heat by energizing the phase change material thin film. However, when a phase transition is performed from an amorphous phase to a crystalline phase, since the resistance value in the amorphous phase is high and current does not flow easily, it is necessary to apply a considerably high voltage in order to heat the material to the temperature required for the phase transition. . For this reason, the write voltage of the memory element is increased. Furthermore, when the material transitions from the amorphous phase to the crystalline phase, since the resistance value in the crystalline phase is low, an excessive current flows through the material at the above voltage, and the element may be destroyed.

  In order to prevent such inconvenience, it is necessary to lower the resistance value when the phase change material is amorphous, and to lower the applied voltage for phase transition from the amorphous phase to the crystalline phase. At present, it is desirable to reduce the difference in resistance between the amorphous phase and the crystalline phase, which have a difference of 2 to 4 digits, to about 1 digit. However, no phase change material satisfying such requirements has been obtained.

  The present invention has been made for the purpose of solving the above-described problems, and it is possible to reduce the applied voltage necessary for the phase transition from the amorphous phase to the crystalline phase without changing the phase change material itself. It is an object of the present invention to provide a phase change memory element and a phase change channel transistor having a novel structure, and a memory cell array using these elements.

  In order to solve the above problems, a memory element according to a first aspect of the present invention includes a first electrode, a second electrode, and a memory layer provided between the first and second electrodes, The memory layer includes at least a first layer composed of a phase change material that is stable in an amorphous phase and a crystalline phase at room temperature, and a second layer composed of a resistive material, The resistance value is smaller than the resistance value when the first layer is an amorphous phase, larger than the resistance value when the first layer is a crystal phase, and further, the first and second A layer is provided adjacent in parallel between the first and second electrodes.

  A phase change channel transistor according to a second invention includes a first electrode, a second electrode, a memory layer provided between the first and second electrodes, and an insulating film provided on the memory layer. The memory layer includes at least a first layer composed of a phase change material that is stable in an amorphous phase and a crystalline phase at room temperature, and a second layer composed of a resistive material. The resistance value of the second layer is smaller than the resistance value when the first layer is an amorphous phase and is larger than the resistance value when the first layer is a crystal phase.

  The first and second layers may be stacked vertically between the first and second electrodes, or may be provided so as to be adjacent in parallel between the first and second electrodes. good. Further, the third electrode may be formed on the semiconductor substrate, and the first and second electrodes and the memory layer may be formed on the insulating film provided on the semiconductor substrate so as to cover the third electrode. . Alternatively, the first and second electrodes and the memory layer are formed on the first insulating film formed on the semiconductor substrate, and the third electrode is formed on the second insulating film provided on the memory layer. Anyway.

  In order to make this phase change channel transistor function as a switching element, when a voltage is applied between the first and second electrodes, the first voltage that cuts off the current flowing through the memory layer and the second voltage that does not cut off the current. May be selectively applied to the third electrode.

  According to a third aspect of the present invention, there is provided a memory cell array in which a plurality of memory cells each including a MOS transistor and a memory portion including a phase change material layer that is stable in an amorphous phase and a crystalline phase at room temperature are arranged on the same substrate. The memory section is constituted by the phase change memory element according to the first invention.

  A memory cell array according to a fourth invention is configured by arranging a plurality of phase change channel transistors according to the second invention on the same semiconductor substrate.

  In the phase change memory element according to the first invention and the phase change channel transistor according to the second invention, the memory layer is formed by stacking the phase change material layer and the resistance layer in a direction perpendicular to the direction between the first and second electrodes When the voltage is applied between the first and second electrodes, the combined resistance of the memory layer is determined when the phase change material layer is an amorphous phase. When the phase change material layer is a crystalline phase, the resistance value of the phase change material layer is almost the same. Therefore, if the resistance value of the resistance layer is set to be smaller than the resistance value when the phase change material layer is an amorphous phase, the combined resistance is lowered and a large current flows through the resistance layer. As a result, the resistance layer easily generates heat, and the heat generation heats the phase change material layer, which is an amorphous phase, and causes phase transition.

  As described above, the memory layer has a laminated structure of the phase change material layer and the resistance layer, thereby reducing the combined resistance value of the entire memory layer, and thereby the phase from the amorphous phase to the crystal phase of the phase change material layer. The transition can be realized with a low applied voltage, and a practical phase change memory element or phase change channel transistor can be obtained.

  In addition, by arranging a plurality of such phase change memory elements or phase change channel transistors on the same substrate to constitute a memory cell array, a memory cell array that can be driven at a lower voltage can be obtained. In particular, in the case of a memory cell array composed of phase change channel transistors, a switching transistor and a memory unit, which conventionally had to be formed separately, can be realized by a single transistor, and accordingly, one memory on the substrate. The area required by the cell is greatly reduced, thereby making it possible to realize an ultra-high density memory cell array.

[First Embodiment]
FIGS. 1A and 1B are partially cutaway cross-sectional views showing the structure of the stacked phase change memory element 1 according to the first embodiment of the present invention. FIG. 4A shows a case where the phase change material layer is an amorphous phase, and FIG. 4B shows a case where the phase change material layer is a crystalline phase. In FIGS. 1A and 1B, 2 is a Si semiconductor substrate, 4 is an insulating layer made of SiO ₂ or the like, 6 and 8 are first and second electrode layers made of Al, Au or the like, Reference numeral 10 denotes a layer of a phase change material thin film (hereinafter referred to as a phase change material layer) made of a material used for a general phase change memory such as chalcogenide, and 12 denotes a resistance layer made of C, W, or the like. Phase change material layer 10 and resistance layer 12 form memory portion 14 of phase change memory element 1. Reference numeral 13 denotes a protective layer covering the memory unit 14 and is made of, for example, SiO ₂ .

Chalcogenide is a GeSbTe-based or AgInSbTe-based material containing at least Sb and Te, and is stable in an amorphous phase and a crystalline phase at room temperature. In one example, when the material takes an amorphous phase, the specific resistance ρ is about 1 Ωm, whereas when the material takes a crystalline phase, it is about 10 ⁻⁴ Ωm. Therefore, the difference in resistance value between the case where the layer 10 is an amorphous phase and the case where it is a crystalline phase is 10 ⁴ times, that is, a difference of 4 digits. Since the layer 10 is formed by a plasma deposition method or the like, the resistance value is often different from the resistance value determined by the specific resistance and shape of the material due to the difference in the plasma process.

The resistance layer 12 is configured to have a resistance value that is higher than the resistance value when the phase change material layer 10 takes a crystalline phase and smaller than the resistance value when an amorphous phase is taken. Examples of a material for realizing such a resistance layer 12 include C, W, Mo, TiN, and TiW. When the phase change material layer 10 is a chalcogenide having the specific resistance ρ as described above, the specific resistance of the resistive layer 12 can be set to about 10 ⁻² to 10 ⁻¹ Ωm. The resistance layer 12 is formed by, for example, plasma vapor deposition of the above-described resistance material on the phase change material layer 10.

  FIG. 2 shows an example of voltage-current characteristics of the phase change material layer 10 and the resistance layer 12. FIG. 2A shows voltage-current characteristics when the phase change material layer 10 has a crystal phase and its resistance value is R1, and B shows the phase change material layer 10 has an amorphous phase and its resistance value is R2. And C represents the voltage-current characteristic of the resistance material layer 12 having the resistance value R3. The resistance value R3 of the resistance layer 12 is selected so that R1 <R3 <R2.

  In FIG. 1A, since the phase change material layer 10 is in an amorphous state, its resistance value R2 is larger than the resistance value R3 of the resistance layer 12, for example, 10 times. Therefore, the combined resistance of the memory unit 14 is approximately the resistance value R3 of the resistance layer 12, and when a voltage is applied between the first and second electrodes, the current is mainly the resistance layer 12 as shown by the dotted line a in the figure. Flows through. As a result, the resistance layer 12 generates Joule heat and heats the phase change material layer 10. This heating indirectly heats the phase change material layer 10 and causes a phase transition from the amorphous phase to the crystalline phase.

  As shown in FIG. 2, when the same voltage Va is applied to an amorphous single layer (in the case of a straight line B) and a multilayer of an amorphous layer and a resistance layer (in the case of a straight line C), the flowing current I is greatly different. Since the heat generated by Joule heat is determined by the consumed power, that is, I × V, the voltage V can be reduced correspondingly if the current I is large when the same amount of heat is obtained. Therefore, in a memory layer having a structure in which a resistance layer and a phase change material layer are stacked, the phase change material layer can be heated to cause phase transition with a lower applied voltage.

  On the other hand, as shown in FIG. 1B, in the state in which the phase change material layer 10 has transitioned to the crystalline phase, the resistance value is reduced to, for example, about three orders of magnitude from that in the amorphous phase. As a result, the combined resistance of the memory unit 14 is substantially the resistance R1, and the current flows through the phase change material layer 10 as indicated by the dotted line b in the figure. Therefore, when the phase transition is performed from the crystalline phase to the amorphous phase, there is almost no need to consider the influence of the resistance layer 12.

  Hereinafter, the reason why the voltage applied for the phase transition from the amorphous phase to the crystal phase is reduced by the presence of the resistance layer 12 will be described in detail.

The amount of Joule heat generated is determined by the electric power P applied to the resistor. Here, the power P is
P = IV = V ² / R
As shown. In order to obtain a constant power P when the phase change material layer 10 is a crystalline phase with a small resistance value and when it is an amorphous phase with a large resistance value,
P = V1 ² / R1 = V2 ² / R2
Voltage V1 (applied voltage to the crystal phase) and voltage V2 (applied voltage to the amorphous phase) are required. Therefore, the voltage V2 applied to the amorphous phase is
V2 = (R2 / R1) ^1/2 · V1
Thus, the voltage V2 must be (R2 / R1) ^1/2 times the voltage V1. At present, since R2 / R1 = 10 ² to 10 ⁴ , the voltage V2 needs to be 10 to 100 times the voltage V1.

On the other hand, when the memory unit 14 has a laminated structure of the phase change material layer 10 and the resistance layer 12, the combined resistance of the memory unit 14 in which the phase change material layer 10 is in an amorphous state is approximately the resistance value of the resistance layer 12. Since R3, the voltage V3 for obtaining the power P is
V3 = (R3 / R1) ^1/2 · V1
If R3 / R1 is 5 or less, the voltage V3 may be about 2.2 times the voltage V1. As a result, what conventionally required an applied voltage of 5 V or more for transition from the amorphous phase to the crystalline phase can be made phase transition at a voltage of 5 V or less.

  3A and 3B show another example of the stacked phase change memory element according to this embodiment. In the drawings shown below, the same reference numerals as those in FIG. 1 indicate the same or similar components. The phase change memory element 1a shown in FIG. 3A has a structure in which a resistance layer 16 is first formed between first and second electrodes 6 and 8, and then a phase change material layer 10a is formed. The phase change memory element 1b shown in FIG. 3B is the same as the element shown in FIG. 3, except that the second resistance layer 18 is further provided on the phase change material layer 10a, and the phase change material layer is composed of two resistance layers 16 and 18. It is characterized by a structure sandwiching 10a. This further facilitates control of the resistance value of the memory unit. Since the resistance layer 18 is provided on the phase change material layer 10a as in the phase change memory element having the structure shown in FIG. 1, the phase change material liquefied to make the phase change material layer 10a amorphous is scattered. Can be prevented. Note that an insulating layer may be provided in place of the resistance layer 18 in the structure of FIG.

[Second Embodiment]
FIG. 4 is a perspective view showing a structure of a parallel type phase change memory device according to the second embodiment of the present invention. The element 1c of the present embodiment has a structure in which a phase change material layer 10b and a resistance layer 12b are provided adjacent to each other in parallel between the first and second electrode layers 6 and 8 on the insulating layer 4. Although not shown, a protective film may be provided on the phase change material layer 10b and the resistance layer 12b. The electrical characteristics of the phase change material layer 10b and the resistance layer 12b are the same as those in the stacked phase change memory element according to the first embodiment. Therefore, also in the memory element having this structure, when the phase change material layer 10b is in an amorphous phase, a current flows between the first and second electrode layers 6 and 8 mainly through the resistance layer 12b, and the phase change material Layer 10b is indirectly heated by the temperature rise of the resistive layer. Therefore, as in the case of the memory element according to the first embodiment, the applied voltage when the phase change material layer 10b is rewritten from the amorphous phase to the crystalline phase can be kept low. When the phase change material layer 10b undergoes a phase transition from the crystalline phase to the amorphous phase, the current flows mainly through the phase change material layer 10b, so there is no influence due to the presence of the resistance layer 12b.

[Third Embodiment]
FIGS. 5A and 5B are partially cutaway sectional views showing the structure of a memory cell array (PRAM) according to the third embodiment of the present invention. In this figure, only one memory cell of the PRAM is shown, but actually, a plurality of memory cells are formed on the same substrate to constitute a high storage capacity integrated circuit. The wiring structure in such a memory cell array is well known and will not be described here.

In FIG. 5A, 20 is a Si semiconductor substrate, 22 is a SiO ₂ layer for element isolation, 24 and 26 are, for example, n + diffusion layers, 28 is a gate insulating film, and 30 is a gate electrode. The n + diffusion layer 24 is connected to the bit line 36 through a contact 34 formed in a through hole provided in the interlayer insulating film 32. On the other diffusion layer 26, the stacked memory section according to the first embodiment or the parallel memory section 38 according to the second embodiment is formed. In the illustrated example, the memory section 38 has a laminated structure of a phase change material layer 38a and a resistance layer 38b, and the diffusion layers 26 and 40 constitute first and second electrodes. Thereby, the memory element of the first embodiment is configured. The other end of the memory unit 38 is connected to the source line 42 through the n + diffusion layer 40.

  The diffusion layers 24 and 26 and the gate electrode 30 constitute a MOS transistor, and the energization state in the channel region 44 immediately below the gate of the Si semiconductor substrate 20 is controlled to be turned on and off by the voltage applied to the gate electrode 30. That is, when the memory unit 38 is selectively driven, the voltage of the gate electrode 30 is controlled to set the channel region 44 to a conductive state, and power is supplied to the memory unit. On the contrary, when this memory portion is not selected, an off voltage is applied to the gate electrode 30.

  Therefore, if the gate voltage of the MOS transistor is controlled to make the channel region 44 conductive, a write (voltage for phase transition) or read voltage is applied to the memory unit 38 via the bit line 36, and conversely the channel If the region 44 is made non-conductive, no write or read voltage is applied. The gate electrode 30 is connected to a word line (not shown).

  FIG. 5B is a diagram showing a structure of a memory cell array according to another example of the third embodiment. This memory cell array is characterized in that a memory portion having a vertical electrode structure is formed in place of the memory portion of FIG. The memory unit 39 has a structure in which a phase change material layer 39a and a resistance layer 39b are formed adjacent to each other in parallel on the n + layer 26. The n + layer 26 is used as one electrode and the source line 42a is used as the other electrode. . In this memory cell array, information can be written to and read from the memory unit 39 in the same manner as the memory cell array shown in FIG.

  In the memory cell array of FIGS. 5A and 5B, in the memory unit 38 or 39, the phase change material layer changes from the amorphous phase to the crystalline phase as described in the description of the first and second embodiments. The voltage required for phase transition is greatly reduced compared to the case where no resistance layer is provided. As a result, a memory cell array with low driving power can be realized.

[Fourth Embodiment]
6 to 8 are partially cutaway cross-sectional views of first to fourth examples of a phase change channel transistor according to a fourth embodiment of the present invention. 6 to 8, reference numeral 50 denotes a semiconductor substrate, 52 denotes a gate electrode, 54 denotes an insulating film such as SiO ₂ , 56 denotes a source electrode, and 58 denotes a drain electrode. The first embodiment shown in FIG. 6 has a configuration in which a phase change material layer 60 is formed on a gate electrode 52 via an insulating film 54 and a resistance layer 62 is further formed thereon. The second embodiment shown in FIG. 7 has a configuration in which a resistance layer 62a is formed on a gate electrode 52 via an insulating film 54, and a layer change material layer 60a is formed thereon. In the third embodiment shown in FIG. 8A, the gate electrode is not formed on the semiconductor substrate 50, but the gate electrode 52a is formed on the phase change material layer 60a via the insulating film 64. In the fourth embodiment shown in FIG. 8B, the phase change has a structure in which the phase change material layer 60b and the resistance layer 62b are arranged adjacent to each other in parallel between the first and second electrode layers 56 and 58. A channel transistor is shown. In this phase change channel transistor, an insulating film 64a is formed on the phase change material layer 60a and the resistance layer 62b, and a gate electrode 52a is provided thereon.

  In each of the phase change channel transistors shown in FIGS. 6 to 8, the phase change material layer 60 or 60a is made to be an amorphous phase or a crystalline phase so that the transistor functions as a memory. The control of writing and reading in this case is the same as that of the phase change memory element in the first embodiment. Furthermore, the phase change material layer is phase-shifted from the amorphous phase to the crystal phase by forming the memory portion between the source and drain electrodes 56 and 58 by a laminated structure or a parallel structure of the phase change material layer and at least one resistance layer. The voltage required for the case is reduced. Therefore, the material and resistance value of the phase change material layer and the resistance layer are selected and set in the same manner as in the case of the phase change memory element in the first embodiment.

  The phase change channel transistor of this embodiment further has a switching function as a transistor in addition to the memory function. FIG. 9 schematically shows the relationship between the gate voltage and the source / drain currents of the phase change channel transistors shown in FIGS. The gate voltage is a voltage between the gate electrode 52 or 52a and the source electrode 56 or the drain electrode 58 shown in FIGS. A curve F in FIG. 9 shows a relationship between a gate voltage and a source / drain current (channel current) when the phase change material layer 60 or 60a is in a crystalline phase state, and a curve H shows the relationship between the phase change material layer 60 or 60a. The relationship between the gate voltage and the source / drain current when the amorphous phase is taken is shown.

  As shown in the figure, in the channel constituted by the phase change material layer 60 or 60a, when the gate voltage is lower than a certain value Vt, the layer 60 or 60a is in an amorphous phase in the channel region regardless of the gate voltage. A substantially constant current I1 (in the case of the amorphous phase) or I2 (in the case of the crystal phase) determined depending on whether it is in the crystalline phase or not flows when the gate voltage exceeds the voltage Vt. Therefore, by controlling the voltage applied to the gate electrode 52 or 52a, the elements shown in FIGS. 6 to 8 can be operated as switching elements.

  Note that the switching function of such a phase change material is described in detail in Patent Document 1 described above.

[Fifth Embodiment]
FIG. 10 is a partially cutaway sectional view showing the structure of the memory cell array using the phase change channel transistor according to the fourth embodiment, and shows two memory cells. In the figure, reference numeral 80 denotes a Si semiconductor substrate, 82 denotes an insulating film such as SiO ₂ , and phase change channel transistors 83 a and 83 b having the structure shown in FIG. 8 are formed on the insulating film 82. Phase change channel transistors 83a and 83b constitute a resistance layer 84 made of a resistance material, a phase change material layer 86 made of a phase change material, a gate insulating film 88, a gate electrode 90, and source and drain electrodes, respectively. First and second electrodes 92 and 94 are provided.

  Further, the gate electrode 90 is connected to a word line (not shown), the first electrode 92 is connected to a bit line 96, and the second electrode 94 is connected to a source line (not shown). Reference numeral 98 denotes an interlayer insulating film. The resistance layer 84 and the phase change material layer 86 constitute a memory unit that records information whether the phase change material layer 86 is an amorphous layer or a crystalline phase. A switching voltage for switching on and off the transistors 83a and 83b is applied to the gate electrode 90 via the word line. A write / read voltage to the memory unit is applied between the bit line 96 and the source line. Therefore, by selecting and driving the bit line and the word line, an arbitrary transistor on the memory array is selected, and information is written, read or erased.

  In the memory array of FIG. 10, the memory section is configured by a laminated structure or a parallel structure of the resistance layer 84 and the phase change material layer 86. Therefore, as described for the phase change memory elements of the first and second embodiments, This has the great advantage that the voltage required for phase transition of the phase change material layer 86 from the amorphous state to the crystalline state is reduced. Further, since the transistors constituting the memory portion have a switching function, there is no need to provide a selection transistor for addressing an arbitrary memory cell. As a result, the area of one memory cell is greatly reduced as compared with the conventional memory cell array that requires both the selection transistor and the memory portion. As a result, memory cells can be formed on the same substrate with an extremely high density.

In all the embodiments described above, as the phase change material, in addition to GeSbTe, GaSb, InSb, InSe, SbTe, GeTe, InSbTe, GaSeTe, SnSbTe, InSbGe, AgInSbTe, GeSnSbTe, GeSbSeTe, TeSb, etc. are used. Is possible. Moreover, in such a material, what changed the composition ratio variously can also be used. Examples of the material for the resistance layer include C, W, Mo, TiN, and TiW. As the insulating layer material, SiO ₂ , Si ₃ N ₄ , ZnS or the like can be used.

1 is a cross-sectional view of a phase change memory element according to a first embodiment of the present invention. FIG. 4 is a diagram showing voltage-current characteristics in the phase change memory element shown in FIG. 1. FIG. 4 is a diagram showing another embodiment of the phase change memory element shown in FIG. 1. FIG. 6 is a perspective view of a phase change memory element according to a second embodiment of the present invention. Sectional drawing of the memory cell array concerning the 3rd Embodiment of this invention. Sectional drawing of the phase change channel transistor which concerns on the 4th Embodiment of this invention. The figure which shows one Example of the phase change channel transistor shown in FIG. FIG. 7 is a diagram showing another embodiment of the phase change channel transistor shown in FIG. 6. FIG. 9 is a diagram for explaining a switching function of the phase change channel transistor shown in FIGS. FIG. 9 is a diagram showing a memory cell array according to a fifth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase change memory element 2, 20 Si semiconductor substrate 4 Insulating film 6 1st electrode 8 2nd electrode 10 Phase change material layer 12 Resistance layer 14 Memory part 16 2nd resistance layer 50 Si semiconductor substrate 52, 52a Gate electrode 54 Insulating film 56 Source electrode 58 Drain electrode 60, 60a Phase change material layer 62, 62a Resistance layer

Claims (17)

A first electrode;
A second electrode;
A memory layer provided between the first and second electrodes,
The memory layer includes at least a first layer composed of a phase change material that is stable in an amorphous phase and a crystalline phase at room temperature, and a second layer composed of a resistive material, The resistance value is set to be smaller than the resistance value when the first layer is an amorphous phase and larger than the resistance value when the first layer is a crystalline phase, and further, the first and second A phase change memory element, wherein the layer is provided adjacent to each other in parallel between the first and second electrodes.   2. The phase change memory element according to claim 1, wherein the resistance material constituting the second layer includes at least one of C, W, Mo, TiN, and TiW. 3. element.   2. The phase change memory device according to claim 1, wherein the memory layer is covered with a protective film. A first electrode;
A second electrode;
A memory layer provided between the first and second electrodes,
The memory layer includes at least a first layer composed of a phase change material that is stable in an amorphous phase and a crystalline phase at room temperature, and a second layer composed of a resistive material, The resistance value is set smaller than the resistance value when the first layer is an amorphous phase and larger than the resistance value when the first layer is a crystalline phase, and the first and second layers Are stacked in a direction perpendicular to the direction between the first and second electrodes, and the first and second electrodes and the memory layer are provided on an insulating film formed on a semiconductor substrate. A phase change memory element.   5. The phase change memory element according to claim 4, wherein the first layer of the memory layer is formed on the insulating film between the first and second electrodes, and the second layer is the first layer. A phase change memory device, wherein the phase change memory device is stacked on the first layer.   5. The phase change memory element according to claim 4, wherein the second layer of the memory layer is formed on the insulating film between the first and second electrodes, and the first layer is the second layer. A phase change memory device, wherein the phase change memory device is stacked on the layer.   5. The phase change memory element according to claim 4, wherein the memory layer further includes a third layer made of a resistive material or an insulating material on the first layer. . A first electrode;
A second electrode;
A memory layer provided between the first and second electrodes;
A third electrode provided on the memory layer via an insulating film,
The memory layer includes at least a first layer composed of a phase change material that is stable in an amorphous phase and a crystalline phase at room temperature, and a second layer composed of a resistive material, A phase change channel transistor having a resistance value smaller than a resistance value when the first layer is in an amorphous phase and larger than a resistance value when the first layer is in a crystalline phase.   9. The phase change channel transistor according to claim 8, wherein the first and second layers have a structure in which the first and second layers are stacked in a direction perpendicular to the direction between the first and second electrodes. Change channel transistor.   9. The phase change channel transistor according to claim 8, wherein the first and second layers are provided adjacent to each other in parallel between the first and second electrodes. Transistor.   11. The phase change channel transistor according to claim 8, wherein the first layer is made of a chalcogenide-based material.   11. The phase change channel transistor according to claim 8, wherein the resistance material constituting the second layer includes at least one of C, W, Mo, TiN, and TiW. Feature phase change channel transistor.   11. The phase change channel transistor according to claim 8, wherein the third electrode is formed on a semiconductor substrate, and the first electrode, the second electrode, and the memory layer are the third electrode. A phase change channel transistor, wherein the phase change channel transistor is formed on an insulating film provided on the semiconductor substrate.   11. The phase change channel transistor according to claim 8, wherein the first and second electrodes and the memory layer are formed on a first insulating film formed on a semiconductor substrate, and 3. The phase change channel transistor according to claim 1, wherein the third electrode is formed on a second insulating film provided on the memory layer.   11. The phase change channel transistor according to claim 8, wherein the third electrode is provided between the first and second electrodes in order to cause the phase change channel transistor to function as a switching element. A phase change channel transistor, wherein a first voltage that blocks current flowing through the memory layer and a second voltage that does not block when a voltage is applied to the memory layer are selectively applied. In a memory cell array in which a plurality of memory cells, each composed of one MOS transistor and a memory portion including a phase change material layer that is stable in an amorphous phase and a crystalline phase at room temperature, are arranged on the same substrate.
A memory cell array comprising the phase change memory device according to claim 1.   11. A memory cell array comprising a plurality of phase change channel transistors according to claim 8 arranged on the same substrate.

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