JP2009117031A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase speed or reduce power consumption of a semiconductor device including CAM. <P>SOLUTION: For example, the semiconductor device includes a dummy memory block MBD and a dummy submatch determining circuit SMDD, in addition to a regular memory block MB and a regular submatch determining circuit SMD. The MBD and SMDD, which have the same configurations as the MB and SMD, provide a fixed operation according to "match" or "mismatch" at all times in searching operation by fixing predetermined signals. A dummy main match determining circuit MMDD determines the match/mismatch state, and a determining timing in the regular main match determining circuit MMD is set based on the match/mismatch state. The MMD (MMDD) makes determination, based on whether the voltage of the main match line MML (MMLD) which has been rapidly charged is discharged or not via SMD (SMDD). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and in particular, in a semiconductor device including a content addressable memory cell (CAM cell) that compares information stored in a storage node and input information, information encoded in the device is displayed. The present invention relates to a technique effective when applied to a semiconductor device having a CAM array for storing or comparing.

  With the explosive spread of the Internet, the table size required for routers and switches in the network is rapidly increasing, and it is a problem to increase the speed of table search. As a means for solving this problem in terms of hardware, attention has been paid to ternary content addressable memory (TCAM).

  For example, Patent Document 1 discloses a configuration of a TCAM cell that uses two dynamic storage cells to store three values of '0' / '1' / 'X' (don't care). Yes. As a result, the cell occupation area can be reduced to increase the capacity, and the power consumption and speed of the search operation can be reduced.

  Further, for example, Non-Patent Document 1 describes an entry or search key encoding method and a memory array configuration for realizing a CAM that solves a shortage of capacity and an increase in power consumption in the TCAM. In the present technology, an encoding method called “One-hot-spot block code” is used.

  Here, in TCAM, “entry” is usually used as a word corresponding to a word widely used in DRAM and SRAM. Since an entry is a word indicating information stored in each word, in the present specification, stored information is referred to as an entry and comparison information is referred to as a search key in accordance with the convention.

JP 2003-272386 A

"IEE Eee, 2004 Symposium on VLSI Circuits, Digest of Technical Papers", June 2004, p. 382-385

  Prior to the present application, the inventors of the present application examined speeding up of the CAM using the One-hot-spot block code. Prior to the present application, the inventors of the present application related to the CAM using the One-hot-spot block code and the non-known “Japanese Patent Application No. 2003-429505” (hereinafter referred to as Reference Document 1) and non- A known "Japanese Patent Application No. 2004-169314" (hereinafter referred to as Reference Document 2) has been filed. The inventor has examined the cycle time required for the search operation of the memory array, including these techniques, and found the following two problems.

  The first problem is that, in the communication field where CAM is mainly applied, the line speed has increased by 1000 times in 10 years, whereas the performance improvement of semiconductor devices has been slow. The memory array that is the heart of the memory array is predicted to have a small degree of reduction in the search operation cycle time. Some CAM vendors have published a method on the web, etc. that improves the number of searches per unit time by applying several masks to one search key and performing a search operation with different search tables. ing. However, in order to perform packet transfer processing while maintaining the line speed, a plurality of CAMs are required, which may increase the mounting cost. In order to suppress the mounting cost, it is desirable to perform parallel processing in which search keys sequentially input to the CAM are searched at different phases.

  In order to realize such processing, in FIG. 11 of Patent Document 1 described above, the same search table is stored in a ternary content addressable memory cell array (TCAM cell array) divided into two, A so-called interleaving method in which a search key is alternately input to perform a search operation is shown. As a detailed memory array configuration, in FIG. 12 of Patent Document 1, a sense amplifier is shared between TCAM cell arrays, and a pair of bit lines connected to each sense amplifier exists in the same TCAM cell array. A bit line configuration is shown. The two dynamic memory cells described above are connected to the bit line pair.

  However, in the folded bit line configuration, information of the logical value “00” or the logical value “11” cannot be accurately read / written from / to the storage nodes of the two dynamic storage cells. In the case of a dynamic cell, the rewrite (refresh) operation cannot be performed correctly. In order to prevent malfunction, it is desirable to have a sense amplifier arrangement with a so-called open bit line configuration between TCAM cell arrays. Further, in Patent Document 1, the search line driving circuit is configured to generate a complementary signal to the search line pair, so that an arbitrary bit of the search key is masked and the corresponding bit is forcibly regarded as a match. The search operation cannot be performed. Therefore, it is desirable to replace the search line driving circuit with a new configuration.

  The second problem is that the search operation cycle time is limited by the match line charging time. In order to explain this problem, the memory array configurations shown in Non-Patent Document 1 and Reference Document 1 are shown. FIG. 2 is a circuit block diagram showing a CAM memory array configuration studied as a premise of the present invention. FIG. 3 is a circuit diagram showing a detailed configuration of each circuit block in FIG.

  The memory array shown in FIG. 2 has a hierarchical structure in which match lines are composed of main match lines MMLm (m = 0, 1,...) And sub-match lines SMLmj (m = 0, 1,..., J = 0, 1,...). Form. The memory cells DMC are arranged at the intersections of the plurality of word lines WLm (m = 0, 1,...) And the plurality of bit lines BLnx (n = 0, 1,..., X = 0, 1, 2, 3), respectively. Is done. Each of the plurality of word lines is driven by a word driver group WDB, and the plurality of bit lines are driven by a read / write circuit group RWB.

  The bit lines BLnx (n = 0, 1,..., X = 0, 1, 2, 3) have a plurality of corresponding search lines SLnx (n = 0, 1,..., X = 0, 1, 2, 3). ) Are arranged in parallel. Each of the plurality of search lines is driven by a search driver group SDB. A plurality of corresponding main match lines MMLm (m = 0, 1,...) Are arranged in parallel to the word lines WLm (m = 0, 1,...).

  Further, a plurality of submatch lines SMLmj (m = 0, 1,..., J = 0, 1,...) Are arranged in parallel to the corresponding main match lines MMLm (m = 0, 1,. The sub-match determination circuits SMDmj (m = 0, 1,..., J = 0, 1,...) Are connected to each other. For example, like the submatch line SML00, four memory cells DMCi (i = 0, 1, 2, 3) are connected to the submatch line. A group of these four memory cells DMCi (i = 0, 1, 2, 3) is referred to as a memory block MBmj (m = 0, 1,..., J = 0, 1,. ).

  Each memory cell DMC includes three NMOS transistors T311, T312 and T313 and a capacitor C as shown in FIG. The submatch determination circuit SMD includes an NMOS transistor T321 for precharging the corresponding submatch line SML and an NMOS transistor T322 for discriminating a minute signal generated on the submatch line SML.

  Further, the main match determination circuit group MMDB in FIG. 2 is composed of a plurality of main match determination circuits MMDm (m = 0, 1,...) As shown in FIG. 3, and drives the corresponding main match lines MML. PMOS transistor T331 and a sense amplifier SA for classifying the comparison result in the entry on the corresponding main match line, and outputs a hit signal (here, HIT0) having a voltage corresponding to the comparison result.

  In such a configuration, when performing a search operation, for example, the data (N00) stored in the memory cell DMC0 in FIG. 3 is compared with the data input to the search line SL00, and the match / mismatch is determined. Accordingly, charge holding or charge discharging of prematched submatch line SML00 is determined. Along with this, ON / OFF of the NMOS transistor T322 in the submatch determination circuit SMD00 is also determined.

  Here, in order to read the information of the submatch line SML00 by the main match determination circuit MMD00, the main match line MML00 holding the ground voltage VSS in advance is gradually charged by the PMOS transistor T331, and the presence / absence of discharge by the NMOS transistor T322 is checked. Operation is performed. At this time, since the current value to be charged is set to a value smaller than the on-current of the NMOS transistor T322, the main match line MML00 at the time of mismatch (when the NMOS transistor T322 is ON) is logically connected to the sense amplifier SA. The voltage can be kept lower than the threshold value.

  However, in such a method of gradually charging the main match line MML00, there is a possibility that the activation timing of the sense amplifier is delayed. In other words, since the driving capability of the NMOS transistor is generally higher than that of the PMOS transistor, in order to advance the start timing of the sense amplifier, the main match line charged to a high voltage is driven by the NMOS transistor in the match determination circuit. However, a signal corresponding to the match / mismatch can be generated earlier.

  Therefore, in view of such problems and the like, it is an object of the present invention to realize an increase in the speed of a semiconductor device including a CAM or a reduction in power consumption.

  Reference Document 2 shows an interface circuit system in CAM using the One-hot-spot block code described in Reference Document 1 and Non-Patent Document 1. Specifically, a format of an input / output signal and a coding / decoding circuit configuration for compressing and storing a plurality of pieces of information according to a data area or storing them with a mask are shown. In the CAM according to this document, a combination of a minimum value and a difference is handled when inputting / outputting an IP address or the like. An input / output signal of such a format is called quaternary information.

  When inputting / outputting other information, a combination of data and mask is handled. An input / output signal of such a format is called ternary information. By using the technique of this document, the externally attached CAM controller can easily monitor the storage status of the entry, and the convenience of the CAM using the one-hot-spot block code is increased.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to the present invention includes a plurality of banks, and further includes a plurality of CAM arrays in each bank. Here, a sense amplifier, a read circuit, a write circuit, and a search line drive circuit are arranged in a shared state between a plurality of CAM arrays in each bank. Note that the connection relationship between the bit lines and the sense amplifiers in the plurality of CAM arrays is a so-called open bit line configuration in which bit lines from both CAM arrays are connected to the sense amplifiers one by one. The memory cells in the CAM array can be dynamic memory cells, for example.

  With such a configuration, it is possible to correctly perform operations such as reading / writing and refreshing with respect to the memory cell. Furthermore, high-speed search processing can be realized by performing an interleave operation using a plurality of banks.

  In this case, control clocks having different phases may be distributed to a plurality of banks, and entry and search key processing (read operation, write operation, search operation) may be performed at different phases. Furthermore, the same search table can be registered in a plurality of banks, search keys that are successively input can be sequentially input to the plurality of banks, and a search operation can be performed in synchronization with control clocks of different phases.

  The semiconductor device according to the present invention includes a dummy circuit that generates a determination timing of the search result during a search operation using the CAM array. This dummy circuit includes, for example, a dummy memory cell, a dummy word line, a dummy match line, and the like having a configuration similar to that of a memory cell, a word line, a match line, and the like included in a normal CAM array. Perform an action fixed to match or not match. Then, the dummy circuit monitors the voltage level of the dummy match line that fluctuates depending on whether it matches or does not match, and activates the match line determination circuit (sense amplifier) in the regular CAM array at the optimum timing. This optimization of timing makes it possible to increase the speed or reduce the power consumption.

  Furthermore, when determining the match line and the dummy match line, as described in the above-mentioned problem, a method for detecting whether the voltage rises according to the presence or absence of the discharge path while gradually charging the match line Instead, it is preferable to use a method for detecting whether or not the voltage of the match line that has been rapidly charged falls according to the presence or absence of the discharge path. As a result, the search operation can be speeded up. Further, the voltage level of the match line is preferably set to the voltage level at the time of mismatch in the default state. As a result, power consumption in actual use can be reduced.

  The effects obtained by typical inventions among the inventions disclosed in this application will be briefly described, so that the semiconductor device can be increased in speed or reduced in power consumption.

In the semiconductor device of Embodiment 1 of this invention, it is a block diagram which shows the basic structural example of the principal part block of CAM contained in it. It is a circuit block diagram showing a memory array configuration of a CAM studied as a premise of the present invention. FIG. 3 is a circuit diagram showing a detailed configuration of each circuit block in FIG. 2. FIG. 2 is a circuit block diagram showing an example of a configuration of banks BK1 and BK2 in FIG. FIG. 5 is a circuit diagram showing an example of the configuration of the read / write search circuit RWSCT00 in FIG. 4 as an example. FIG. 7 is a waveform diagram showing an example of an operation when searching for two search keys D1 and D2 in the basic mode in the CAM of FIG. FIG. 6 is a waveform diagram showing an example of an operation when searching four search keys D1, D2, D3, and D4 in the interleave mode in the CAM of FIG. 1; In the semiconductor device of Embodiment 2 of this invention, it is a block diagram which shows the basic structural example of the principal part block of CAM contained in it. FIG. 9 is a waveform diagram showing an example of an operation in the case where two search keys having a width of 2 k bits wider than the bus width of the data bus DQ are searched in the basic mode in the CAM of FIG. 8. FIG. 9 is a waveform diagram showing an example of operation when searching for four search keys having a width of 2 k bits in the interleave mode in the CAM of FIG. 8. In the semiconductor device of Embodiment 3 by this invention, it is a circuit block diagram which shows the memory array structural example different from FIG. 2 of CAM contained in it. FIG. 12 is a circuit diagram illustrating a detailed configuration example of a dummy / submatch determination circuit, a dummy / main match determination circuit, and a main match determination circuit in FIG. 11; FIG. 13 is a waveform diagram showing an example of a search operation when a matching entry is detected in the subarray of FIG. FIG. 13 is a waveform diagram showing an example of a search operation when a mismatched entry is detected in the subarray of FIG. It is explanatory drawing which shows the structural example of a router typically. FIG. 16 is an explanatory diagram schematically illustrating a configuration example of a packet to be transferred by the router in FIG. 15.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor). .

  Note that, in the embodiment, a MOS (Metal Oxide Semiconductor) transistor is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor). In the drawing, a P-channel MOS transistor (PMOS transistor) is distinguished from an N-channel MOS transistor (NMOS transistor) by adding an arrow symbol to the gate. Although the connection of the substrate potential of the MOS transistor is not particularly specified in the drawing, the connection method is not particularly limited as long as the MOS transistor can operate normally.

(Embodiment 1)
First, the overall configuration of the CAM will be described.

  FIG. 1 is a block diagram showing a basic configuration example of a main block of a CAM included in the semiconductor device according to the first embodiment of the present invention. This configuration includes a command decoder CDEC, a CAM control circuit CAMCTL1, a data input / output circuit DIO, various register groups REGBK, an encoding circuit group ENCBK, a decoding circuit group DECBK, banked memory arrays BK1 and BK2, and a RAM control circuit RAMCTL. Have In the figure, for simplicity, attention is paid to a path through which data in a search operation is transmitted and received, and a refresh counter, a row decoder, and the like, which are circuit blocks related to addresses, are omitted.

  The command decoder CDEC receives and encodes the command signal CMD [j: 1], and outputs a signal for selecting a register, which will be described later, to various register groups REGBK via the command bus CBS. Alternatively, the read enable signal RDE, the write enable signal WTE, and the search enable signal SCE are output to a control circuit block in the chip such as a CAM control circuit CAMCTL1 described later.

  The CAM control circuit CAMCTL1 receives a master clock MCLK and a multi-bank enable signal MBKE generated by a controller (or a control circuit called a network processor or a search engine) connected to the CAM according to the present invention, In response to the read enable signal RDE, write enable signal WTE, and search enable signal SCE, the bank control clocks BCLK1 and BCLK2, the data clock DCLK, and the content address clock ACLK are generated.

  The data input / output circuit DIO is arranged between the data bus DQ [k: 1] and the internal data bus DBS [k: 1], and includes control signals for defining address signals, data, and various chip settings. Give and receive. In particular, when data is transferred, data is transferred in synchronization with the data clock DCLK. The following description will be continued assuming that the bus width k is an even number.

  Each of the various register groups REGBK is composed of a plurality of bits corresponding to the number of signal lines of the data bus DQ (here, k). In the figure, four register groups are shown as registers for transmitting and receiving signals via the internal data bus DBS.

  The first input mask / difference register groups INMD1 to INMDs store mask information and differences corresponding to input entry and search key data areas. The second output mask / difference register groups OUTMD1 to OUTMDs store mask information and differences corresponding to the data area of the entry to be read.

  The third data area identification register groups DFI1 to DFIs store identification information for distinguishing the information format processed by the CAM for each bit. The fourth match address registers MA1 to MAs are inserted between a match address MABS, which will be described later, and the internal data bus DBS, and store a match address (details will be described later) generated during the search operation. Note that when there are a plurality of matching entries, the address signal corresponding to the entry at the highest level (for example, the row with the lowest corresponding row address) is output in order. Note that the register group described above is composed of a plurality of registers having the same configuration, and a desired register is selected by the command signal group and the address signal described above.

  The encoding circuit group ENCBK includes k-bit ternary information-One-hot-spot block encoding circuit group TOBENC and quaternary information-One-hot according to the number of signal lines (in this case, k) of the data bus DQ. -Spot block coding circuit group QOBENC, and one of the coding blocks for each coding block according to the value of the data area identification register groups DFI1 to DFIs input via the data area identification bus DFIBS The circuit is activated.

  For example, when encoding is performed every 2 bits, the configuration of the encoding circuit group ENCBK is set every 2 bits depending on whether the information corresponding to the encoded block is ternary or quaternary. Information (here, difference and mask) obtained from the above-described input mask / difference register groups INMD1 to INMDs via the input mask / difference bus INMDBS and information inputted via the internal data bus DBS (here: (Minimum value and data) is received, and the entry or search key is encoded into a one-hot-spot block and output to an encoded information bus ENCBS composed of 2k signal lines.

  On the other hand, the decoding circuit group DECBK is a multi-bit one-hot-spot block code-three-value information decoding circuit group OBTDEC and one-hot-spot block corresponding to the number of signal lines (here, k) of the data bus DQ. One of the coded blocks is decoded for each coding block according to the values of the data area identification register groups DFI1 to DFIs input through the data area identification bus DFIBS. The circuit is activated.

  For example, when encoding is performed every 2 bits, the configuration of the decoding circuit group DECBK is set every 2 bits depending on whether the information corresponding to the encoded block is ternary or quaternary. Then, the entry read through the encoded information bus ENCBS composed of 2k signal lines is decoded, and the mask and difference are output through the output mask / difference bus OUTMDBS and the output mask / difference register groups OUTMD1 to OUTMDs described above. The data and the minimum value are output to the data input / output circuit DIO via the internal data bus DBS.

  Details of these various register groups REGBK, encoding circuit group ENCBK, and decoding circuit group DECBK are described in Reference Document 2.

  The banks BK1 and BK2 have subarrays SARYU and SARYL, a read / write search circuit group RWSBK, a memory control circuit MC, and a priority encoder PE, respectively, into which the banked memory array is further divided. The subarrays SARYU and SARYL have a configuration in which the search driver group SDB and the read / write circuit group RWB are omitted from the configuration shown in FIG. For example, when entries and search keys are encoded every 2 bits, k / 2 memory blocks are provided on one word line so that k-bit entries can be stored according to the bus width of the data bus DQ. It is connected. Although details will be described later, the read / write search circuit group RWSBK is shared by the subarrays SARYU and SARYL.

  The memory control circuit MC receives the read enable signal RDE, the write enable signal WTE, and the search enable signal SCE, respectively. When any of these signals is activated according to the operation, the bank control clock MC A plurality of internal control signals (details will be described later) are generated in synchronization with BCLK1 and BCLK2.

  In the search operation, the priority encoder PE uses the output signals of the main match determination circuit group MMDB in the subarrays SARYU and SARYL in the banks BK1 and BK2 (that is, the hit signal HIT0 shown in FIG. 3) as the match signal buses HBSU and HBSL. An address (hereinafter referred to as a match address) signal corresponding to the entry that matches the search key is generated. This address signal is input to the RAM control circuit RAMCTL and the match address register groups MA0 to MAs via the match address bus MABS.

  The RAM control circuit RAMCTL changes the match address from the content address signal group CADD [r: 1] to DRAM (dynamic random access memory) or SRAM (static random access) according to the content address clock ACLK.・ Output to memory. Here, r is an integer determined according to the memory array configuration of the CAM according to the present embodiment.

  Note that the components forming the CAM according to the present embodiment are not limited to the circuit blocks and signals illustrated in FIG. 1 but include various element blocks and signals. For example, a phase locked loop PLL or delay locked loop DLL for clock phase adjustment, a test circuit, a controller for controlling cascaded chips, and an external content memory (for example, SRAM or DRAM) are controlled. The RAM clock, the RAM control signal group, etc. are omitted in FIG. 1 for simplicity.

  Next, the configuration and operation of the memory array will be described.

  FIG. 4 is a circuit block diagram showing an example of the configuration of banks BK1 and BK2 in FIG. The subscript “n” of the symbol shown below is one of 0, 1,..., (K / 2) −1 (“k” is an even number). The subscript “x” is any one of 0, 1, 2, and 3.

  The encoded data line ENCLnx is a component of the 2k encoded information buses ENCBS described above. The read / write search circuit group RWSBK has 2k read / write search circuits RWSCTnx. The encoded information bus ENCBS is connected to the search line SLnx via the corresponding RWSCTnx. Each search line SLnx is shared by the subarrays SARYU and SARYL, and is connected to the corresponding memory cell in both subarrays. In addition, the bit line BLnxU in the subarray SARYU corresponding to the search line SLnx and the bit line BLnxL in the subarray SARYL are connected to the corresponding read / write search circuit RWSCTnx.

  FIG. 5 is a circuit diagram showing an example of the configuration of the read / write search circuit RWSCT00 in FIG. 4 as an example. The read / write search circuit according to this embodiment includes a sense amplifier SA, an equalize circuit EQ, a read circuit RCKT, a write circuit WCKT, and a search line drive circuit SCKT.

  The sense amplifier SA has a known circuit configuration in which two PMOS transistors P500 and P501 and two NMOS transistors N500 and N501 are cross-coupled as widely used in DRAMs. During standby, the common source line CSP which is at the reference voltage VREF (here, the intermediate voltage between the power supply voltage VDD and the ground voltage VSS) together with the bit lines BL00U and BL00L is set to the power supply voltage VDD and the common source line CSN is set to the ground voltage VSS. Each is activated by driving to amplify a minute voltage signal generated in the bit line pair.

  The equalize circuit EQ has a known circuit configuration including three NMOS transistors N510, N511, and N512, as widely used in DRAMs. The bit line equalize signal BLEQ to which each gate is connected is set to the boosted voltage VPP during standby (where the boosted voltage VPP is higher than the power supply voltage VDD by the threshold voltage VTN of the NMOS transistor or higher than that). By driving the transistors N511 and N512, the reference voltage VREF is supplied to the bit line pair, and the transistor N510 is turned on to short-circuit the bit line pair.

  With the above configuration of the sense amplifier SA and the equalize circuit EQ, it is possible to perform entry read / write and rewrite (refresh) operations by the same operation as a known open bit line DRAM.

  The read circuit RCKT includes PMOS transistors P520 and P521 and NMOS transistors N520, N521, N522, and N523. One of the sources or drains of the transistors N520 and N521 is connected to the bit lines BL00U and BL00L, respectively, and the other is connected to each other. This common node is called IN50. Further, the gate electrodes of the transistors N520 and N521 are connected to the read activation signals RDL and RDU, respectively. The transistors N522 and N523 are connected in series between the encoded data line ENCL00 and the ground voltage VSS terminal, and the transistor P520 is inserted so as to form a current path between the power supply voltage VDD terminal and the encoded data line ENCL00.

  The transistor P521 is inserted so as to form a current path between the power supply voltage VDD terminal and the common node IN50. Further, the gate electrodes of the transistors P520 and N522 are connected to the common node IN50, and the gate electrodes of the transistors P521 and N523 are connected to the read activation signal RD. With the above connection, the transistors P520, N522, and N523 form a driver circuit that drives the encoded data line ENCL00. Note that these read circuits (and a write circuit and search line driving circuit described later) have a circuit configuration in which the bit line pairs BL00U / BL00L both have the same load capacitance.

  In such a circuit configuration, since all of the read start signals RDL, RDU, and RD are held at the ground voltage VSS during standby, the transistors N520, N521, and N523 are in a cut-off state and are common to the bit line pair. Node IN50 is disconnected. Further, the transistor P521 is turned on and the common node IN50 is driven to the power supply voltage VDD, whereby the transistor P520 is cut off and the driver circuit is in a high impedance state.

  On the other hand, when reading an entry on the sub-array SARYU side, the minute signal read to the bit line pair is amplified by the sense amplifier SA, and then the read activation signal RDL is held at the ground voltage VSS and the ground voltage VSS is obtained. By driving the read activation signals RD and RDU to the boosted voltage VPP, the transistor N521 is turned on to short-circuit the bit line BL00L and the common node IN50. In addition, by activating the driver circuit, a voltage signal having a polarity opposite to that of the bit line BL00L is output to the encoded data line ENCL00.

  On the other hand, when reading an entry on the sub-array SARYL side, driving the signals RD and RDL to the boosted voltage VPP causes the transistor N520 to conduct and short-circuit the bit line BL00U and the common node IN50. Further, by activating the driver circuit, a voltage signal having a polarity opposite to that of the bit line BL00U is output to the encoded data line ENCL00. With such a configuration and operation, the load capacity balance of the bit line pair in the read operation can be maintained, and a read signal having the same polarity as that of the entry can be read at a high speed onto an encoded data line having a large load capacity.

  The write circuit WCKT includes NMOS transistors N530 and N531. One of the sources or drains of the transistors N530 and N531 is connected to the bit lines BL00U and BL00L, respectively, and the other is connected to the encoded data line ENCL00. In addition, the gates of the transistors N530 and N531 are connected to the write activation signals WTU and WTL, respectively.

  When writing an entry to the sub-array SARYU side in such a circuit configuration, after a minute signal read to the bit line pair is amplified by the sense amplifier SA, the write activation signal WTL is held at the ground voltage VSS and the ground voltage VSS is held. By driving the write activation signal WTU to the boosted voltage VPP, the transistor N530 is turned on, and the bit line BL00U and the encoded data line ENCL00 are short-circuited.

  On the other hand, when writing an entry on the subarray SARYL side, the transistor N531 is made conductive by driving the signal WTL to the boost voltage VPP to connect the bit line BL00L and the encoded data line ENCL00. With such a configuration and operation, the balance of the load capacity of the bit line pair in the read operation can be maintained, and a write operation similar to that of a DRAM having an open bit line configuration can be performed.

  The search line drive circuit SCKT includes PMOS transistors P540 and P541, and NMOS transistors N540, N541, and N542. The PMOS transistors P540 and P541 and the NMOS transistors N540 and N541 form a so-called clocked inverter type driver circuit configuration. The gate electrodes of the transistors P540 and N541 are connected to the search activation signals SCEB and SCET, respectively, the gate electrodes of the transistors P541 and N540 are connected to the encoded data line ENCL00, and the output node is connected to the search line SL00. The NMOS transistor N542 is inserted so as to form a current path between the search line SL00 and the ground voltage VSS terminal, and the gate electrode is connected to the search activation signal SCEB.

  In such a circuit configuration, the search line SL00 during standby is held at the ground voltage VSS when the transistor N542 is turned on because the search activation signal SCEB is held at the power supply voltage VDD. When the search operation starts, the search activation signal SCET that has been at the ground voltage VSS is driven to the power supply electrode VDD, and the search activation signal SCEB that has been at the power supply electrode VDD is driven to the ground voltage VSS, so that the transistor N542 is cut off. At the same time, the driver circuit is activated. Then, when a signal having a polarity opposite to that of the encoded search key is input to the encoded data line ENCL00 that has been set to the power supply voltage VDD during standby, the search line SL00 is driven to a voltage corresponding to the search key.

  With such a configuration and operation, the search line drive time in the search operation can be shortened, and the cycle of the memory array can be improved. Further, since the bit line and the search line share the encoded information bus, the number of bus wirings can be reduced, and the chip area can be suppressed.

  Next, a basic mode search operation using the CAM of FIG. 1 will be described.

  FIG. 6 is a waveform diagram showing an example of the operation when the two search keys D1 and D2 are searched in the basic mode in the CAM of FIG. The feature of this mode is that one search table is registered across two banks BK1 and BK2, and a search operation is performed.

  First, in the first cycle, the search command S1 is input via the command signal group CMD in synchronization with the master clock MCLK, and the search enable signal SCE is activated. In response to this, the CAM control circuit CAMCTL1 generates the data clock DCLK obtained by dividing the master clock MCKL, so that the search key D1 is synchronized with the rising edge so that the search key D1 is the data input / output circuit DIO and the encoding circuit. Input to the encoded information bus ENCBS via the group ENCBK.

  At the same time, the CAM control circuit CAMCTL1 generates pulse signals on the bank control clocks BCLK1 and BCLK2, respectively. In response to these bank control clocks and the search enable signal SCE, the memory control circuits MC of the banks BK1 and BK2 search the search enable signals SCET (1), SCEB (1), SCET (2), SCEB (2). Are activated, the search key D1 is input to the memory array. That is, the search lines SL00 (1) and SL00 (2) are driven to voltages according to the corresponding bits of the search key D1 by the search line drive circuit SCKT shown in FIG. 5, and the search operation is performed in each bank. . The numbers in parentheses correspond to the subscripts of the banks BK1 and BK2.

  In the next second cycle, the search command S2 is input subsequently to the first cycle, and the search enable signal SCE is held in the active state. Further, in synchronization with the falling edge of the data clock DCLK, the search key D2 is input to the encoded information bus ENCBS via the encoding circuit group ENCBK. Further, the CAM control circuit CAMCTL1 generates short pulse signals again in the bank control clocks BCLK1 and BCLK2 in response to the search enable signal SCE, whereby the search key D2 is input to the banks BK1 and BK2, respectively. That is, a second search operation is performed.

  In the figure, it is assumed that the banks BK1 and BK2 perform a search operation at the cycle time tARY, and match addresses A1 and A2 corresponding to the results are output after 4 cycles from the input of the search keys D1 and D2. is doing. Therefore, in the fifth cycle, the address clock ACLK obtained by dividing the master clock MCKL is generated in the CAM control circuit CAMCTL1, and the match address A1 is output from the RAM control circuit RAMCTL in synchronization with the rising edge. Further, in the sixth cycle, the match address A2 is output from the RAM control circuit RAMCTL in synchronization with the falling edge of the address clock ACLK. With the above operation, a large-scale table search can be realized with one CAM.

  Next, the search operation in the interleave mode using the CAM of FIG. 1 will be described.

  FIG. 7 is a waveform diagram showing an example of the operation when the four search keys D1, D2, D3, and D4 are searched in the interleave mode in the CAM of FIG. The feature of this operation is that the same search table is registered in the banks BK1 and BK2, and the search operation is performed by alternately inputting different search keys.

  First, in the first cycle, the multi-bank enable signal MBKE is raised to set the search operation to the interleave mode. At the same time, the search command S1 is input via the command signal group CMD in synchronization with the master clock MCLK, and the search enable signal SCE is activated. In response to these signals, the CAM control circuit CAMCTL1 generates a data clock DCLK obtained by dividing the master clock MCKL. In synchronization with this rising edge, the search key D1 is input to the encoded information bus ENCBS via the data input / output circuit DIO and the encoding circuit group ENCBK.

  The CAM control circuit CAMCTL1 further generates a bank control clock BCLK1. In response to the bank control clock and the search enable signal SCE, the memory control circuit MC of the bank BK1 activates the search enable signals SCET (1) and SCEB (1), respectively, so that the search key D1 is stored in the memory array. Entered. That is, the search line drive circuit SCKT shown in FIG. 5 drives the search line SL00 (1) to a voltage corresponding to the corresponding bit of the search key D1, and the search operation is performed in the bank BK1.

  Next, a search command S2 is input in synchronization with the falling edge of the master clock MCLK, and the search key D2 is input to the data input / output circuit DIO and the encoding circuit group in synchronization with the falling edge of the data clock DCLK. The signal is input to the encoded information bus ENCBS via ENCBK. Further, a pulse signal corresponding to the search enable signal SCE is generated in the bank control clock BCLK2 in the CAM control circuit CAMCTL1, and the search enable signal SCET (2 in response to the search enable signal SCE in the memory control circuit MC in the bank BK2. ) And SCEB (2) are activated, whereby the search key D2 is input to the bank BK2. That is, the search line SL00 (2) is driven to a voltage corresponding to the bit corresponding to the search key D2 by the search line driving circuit SCKT shown in FIG. 5, and the search operation is performed in the bank BK2.

  In the subsequent second cycle, as in the first cycle, the search keys D3 and D4 are alternately input to the banks BK1 and BK2, and a search operation is performed. In FIG. 6, as in FIG. 6, it is assumed that the match address is output after 4 cycles from the input of the search key. Therefore, the match addresses A1, A2, A3 and A4 are respectively synchronized with the rising and falling edges of the address clock ACLK generated by the CAM control circuit CAMCTL1 in the same cycle as the master clock MCLK after the fifth cycle. Output from the RAM control circuit RAMCTL.

  With the above operation, it is possible to realize a CAM that uses the banks BK1 and BK2 whose search operation cycle time is tARY to receive a search key and perform a search process at twice the speed of the operation of FIG. However, in order to realize this operation, the same search table is registered in two banks, so the memory capacity is halved. However, as shown in the above-mentioned Non-Patent Document 1, a general-purpose DRAM cell-based memory cell excellent in one-hot-spot block coding method and high integration capable of compressing and storing entries In the CAM in combination with the CAM, the memory capacity is doubled as compared with the conventional ternary CAM, so that there is little possibility of causing a memory shortage.

  In the search operation in the interleave mode, there is a problem that power consumption increases because two banks are activated simultaneously. However, since the entries can be compressed and stored by using the one-hot-spot block coding method, the memory area activated in one bank can be made narrower than the conventional ternary CAM. It is possible to reduce power consumption. Therefore, the present invention is particularly suitable when applied to a CAM using a memory array based on the one-hot-spot block coding method, and thereby, interleaved operation of a plurality of banks from the viewpoint of large capacity and low power consumption. As a result, it is possible to realize a high-speed CAM corresponding to the trend of improving the line speed of the network.

  Although the search operation has been described above, the read enable signal RDE and the write enable signal WTE are generated by inputting the read command and the write command from the command signal group CMD in the read operation and the write operation. Further, it can be easily understood that the bank control clocks BCLK1 and BCLK2 are generated from the CAM control circuit CAMCTL1 to activate the banks BK1 and BK2. In addition, it can be easily understood that the refresh operation can be performed in the other bank while the search operation is performed in one bank in the interleave mode. In this case, it is possible to alleviate the penalty of a decrease in search speed due to the refresh operation.

  As described above, typical effects obtained by using the CAM of the first embodiment are summarized as follows.

  First, the first effect of the configuration of the CAM of FIGS. 1, 4, and 5 is that the entry is correctly read / written and rewritten (refreshed) by using a so-called open bit line configuration sensing method in the same bank. The point is that it becomes possible. The second effect is that the bit line and the search line are connected to the common encoded data line via the read / write search circuit, so that the number of encoded information bus lines can be reduced and the chip area is suppressed. The point is that it becomes possible.

  The third effect is that the search operation mode can be switched according to the application by using the multi-bank enable signal MBKE and two banks as in the operations of FIGS. That is, in the basic mode, a large-capacity CAM can be realized by registering a large-scale search table across two banks. On the other hand, in the interleave mode, the same entry is registered in two banks, and different search keys are alternately input, so that the search key is received and searched in a cycle time shorter than the bank search operation cycle time. A high-speed CAM can be realized. In addition, while performing a search operation in one bank, it is possible to perform a refresh operation in the other bank.

  Note that the number of banks is not limited to two, and it can be easily understood that various operations can be performed by synchronizing more banks with clocks of different phases. In this case, it is possible to realize a high-speed CAM that receives a search key at a higher frequency and performs a search process.

(Embodiment 2)
In the second embodiment, another configuration example and an operation example of the CAM described in the first embodiment will be described.

  FIG. 8 is a block diagram showing an example of a basic configuration of a main part block of a CAM included in the semiconductor device according to the second embodiment of the present invention. The feature of this configuration is that the banked memory array has a hierarchical structure, and a memory array configuration having two main banks composed of a plurality of banks is used to search wider than the bus width of the data bus DQ. The key search operation is performed. In the following, the configuration of FIG. 8 will be described with a focus on differences from the configuration shown in FIG.

  The CAM control circuit CAMCTL8 receives a master clock MCLK and a multi-bank enable signal MBKE generated by a controller (or a control circuit called a network processor or a search engine) connected to the CAM according to the present invention. In response to the read enable signal RDE, the write enable signal WTE, and the search enable signal SCE, the bank control clocks BCLKA1, BCLKB1, BCLKA2, BCLKB2, the data clock DCLK, and the content address clock ACLK are generated. Also, global IO control clocks GCLKWS and GCLKR and a multi-bank enable signal GMBKEN are generated.

  The demultiplexer WSDMUX receives the entry and search key encoded by the encoding circuit group ENCBK via the encoded information bus ENCBS, and receives two signals according to the global IO control clock GCLKWS and the multi-bank enable signal GMBKEN. It is distributed appropriately to the global IO (GIOA, GIOB) and transferred to the main bank described later. On the other hand, the multiplexer RMUX appropriately receives the entry read from the main bank from the two global IOs (GIOA, GIOB) according to the global IO control clock GCLKR and the multi-bank enable signal GMBKEN, and encodes the information bus. The data is output to the decoding circuit group DECBK via ENCBS.

  Each of the main banks MBK1 and MBK2 includes banks BKA and BKB and a main priority encoder MPE. The banks BKA and BKB have the same configuration as the banks BK1 and BK2 shown in FIG. The bank BKA in the main bank MBK1 exchanges information with the global IO (GIOA) in synchronization with the bank control signal BCLKA1. The bank BKB in the main bank MBK1 exchanges information with the global IO (GIOB) in synchronization with the bank control signal BCLKB1. The bank BKA in the main bank MBK2 exchanges information with the global IO (GIOA) in synchronization with the bank control signal BCLKA2. The bank BKB in the main bank MBK2 exchanges information with the global IO (GIOB) in synchronization with the bank control signal BCLKB2.

  The main banks MBK1 and MBK2 configured by these banks perform operations in accordance with the read enable signal RDE, the write enable signal WTE, and the search enable signal SCE. The main priority encoder MPE generates a match address on the match address bus MABS according to the output of the priority encoder PE in the banks BKA and BKB received via the sub match address buses SMABSA and SMABSB. To do.

  Next, the basic mode search operation using the CAM of FIG. 8 will be described.

  FIG. 9 is a waveform diagram showing an example of operation in the case where two search keys having a width of 2 k bits wider than the bus width of the data bus DQ are searched in the basic mode in the CAM of FIG.

  First, in the first cycle, the search command S1A is input via the command signal group CMD in synchronization with the master clock MCLK, and the search enable signal SCE is activated. At the same time, in synchronization with the rising edge of the data clock DCLK having the same cycle as the master clock MCLK, the first half bit D1A of the first search key is encoded via the data input / output circuit DIO and the encoding circuit group ENCBK. Input to ENCBS.

  In addition, when the multi-bank enable signal GMBKEN is inactive and the global IO control clock GCLKWS having the same cycle as the master clock MCLK rises, the search key is transferred from the demultiplexer WSDMUX to the global IO (GIOA). Further, in the CAM control circuit CAMCTL8, pulse signals corresponding to the search enable signal SCE are generated in the bank control clocks BCLKA1 and BCLKA2, respectively, and in the memory control circuit MC in the bank BKA in the main banks MBK1 and MBK2, the search enable signal is generated. A search key is activated when search enable signals SCET (A1) and SCET (A2) are activated in response to signal SCE (for simplicity, search enable signals SCEB (A1) and SCEB (A2) are omitted). Are input to the banks BKA in the main banks MBK1 and MBK2, respectively.

  That is, the search lines SL00 (A1) and SL00 (A2) are driven by the search line driving circuit SCKT shown in FIG. 5 to voltages corresponding to the corresponding bits of the search keys, respectively, and are stored in the main banks MBK1 and MBK2. Search operations are simultaneously performed in the bank BKA. The alphanumeric characters in parentheses correspond to the main bank and bank subscripts, and indicate the position of the bank. For example, SCET (A1) means a search enable signal in the bank BKA in the main bank MBK1.

  Next, the search command S1B is input in synchronization with the falling edge of the master clock MCLK, and the latter half bit D1B of the first search key is set in the data input / output circuit in synchronization with the falling edge of the data clock DCLK. The signal is input to the encoded information bus ENCBS via the DIO and the encoding circuit group ENCBK. Further, when the multi-bank enable signal GMBKEN is inactive and the global IO control clock GCLKWS having the same cycle as the master clock MCLK falls, the search key is transferred from the demultiplexer WSDMUX to the global IO (GIOB). .

  Further, in the CAM control circuit CAMCTL8, pulse signals corresponding to the search enable signal SCE are generated in the bank control clocks BCLKB1 and BCLKB2, respectively, and in the search and enable in the memory control circuit MC in the bank BKB in the main banks MBK1 and MBK2. A search key is activated when search enable signals SCET (B1) and SCET (B2) corresponding to signal SCE are activated (for simplicity, search enable signals SCEB (B1) and SCEB (B2) are omitted). Are input to the banks BKB in the main banks MBK1 and MBK2, respectively.

  That is, the search lines SL00 (B1) and SL00 (B2) are driven by the search line driving circuit SCKT shown in FIG. 5 to voltages corresponding to the corresponding bits of the search keys, respectively, and are stored in the main banks MBK1 and MBK2. Search operations are performed in the banks BKB.

  In the subsequent second cycle, as in the first cycle, the second search key is divided and input into the first half bit D2A and the second half bit D2B, and the search operation is performed in the main banks MBK1 and MBK2, respectively. In this figure, as in FIG. 6, it is assumed that the match address is output after 4 cycles from the input of the search key, and the address clock ACLK obtained by multiplying the master clock MCLK after the 5th cycle. Match addresses A1 and A2 are output from the RAM control circuit RAMCTL in synchronization with the rising and falling edges of the RAM. With the above configuration and operation, a search operation for a search key having a wide bit width can be performed in the same six cycles as the operation shown in FIG.

  Next, an interleave mode search operation using the CAM of FIG. 8 will be described.

  FIG. 10 is a waveform diagram showing an example of operation when searching for four search keys having a width of 2 k bits in the interleave mode in the CAM of FIG. The feature of this operation is that the cycle time of the master clock MCLK is set to be shorter than the search operation cycle time tARY of the memory array (here, tARY / 2), and the search key is received at high speed to perform the search process. There is.

  First, in the first cycle, the multi-bank enable signal MBKE is activated, the search operation is set to the interleave mode, and a pulse signal having the same cycle as the master clock MCLK is used as the data clock by using the CAM control circuit CAMCTL8. DCLK and global IO control clock GCLKWS are generated. Further, the multi bank enable signal GMBKEN rises in response to the multi bank enable signal MBKE.

  Further, the search command S1A is input via the command signal group CMD in synchronization with the master clock MCLK, and the search enable signal SCE is activated. At the same time, in synchronization with the rising edge of the data clock DCLK, the first half bit D1A of the first search key is input to the encoded information bus ENCBS via the data input / output circuit DIO and the encoding circuit group ENCBK, and the multi-bank When the enable signal GMBKEN is active and the global IO control clock GCLKWS rises, the search key is transferred from the encoding circuit group ENCBK to the global IO (GIOA) via the demultiplexer WSDMUX.

  Further, in the CAM control circuit CAMCTL8, a pulse signal corresponding to the search enable signal SCE and the multi-bank enable signal MBKE is generated in the bank control clock BCLKA1, and the search is performed in the memory control circuit MC in the bank BKA in the main bank MBK1. When the search enable signal SCET (A1) is activated in response to the enable signal SCE (for the sake of simplicity, the search enable signal SCEB (A1) is omitted), the search key is the bank BKA in the main bank MBK1. Is input. That is, search line SL00 (A1) is driven to a voltage corresponding to the corresponding bit of the search key by search line drive circuit SCKT shown in FIG. 5, and a search operation is performed in bank BKA in main bank MBK1. .

  Next, the search command S1B is input in synchronization with the falling edge of the master clock MCLK, and the latter half bit D1B of the first search key is set in the data input / output circuit in synchronization with the falling edge of the data clock DCLK. When the global IO control clock GCLKWS having the same cycle as the master clock MCLK falls while being input to the encoded information bus ENCBS via the DIO and the encoding circuit group ENCBK and the multi-bank enable signal GMBKEN is active, The search key is transferred from the demultiplexer WSDMUX to the global IO (GIOB).

  Further, in the CAM control circuit CAMCTL8, a pulse signal corresponding to the search enable signal SCE is generated in the bank control clock BCLKB1, and further in the memory control circuit MC in the bank BKB in the main bank MBK1, in response to the search enable signal SCE. When the search enable signal SCET (B1) is activated (for the sake of simplicity, the search enable signal SCEB (B1) is omitted), a search key is input to the bank BKB in the main bank MBK1. That is, the search line SL00 (B1) is driven to a voltage corresponding to the corresponding bit of the search key, and the search operation is performed in the bank BKB in the main bank MBK1.

  In the subsequent second cycle, as in the first cycle, the second search key is divided and input into the first half bit D2A and the second half bit D2B. As the bank control clocks BCLKA2 and BCLKB2 sequentially rise, A search operation is performed in the banks BKA and BKB in the bank MBK2.

  By performing the above operation from the third cycle to the fourth cycle, the third and fourth search keys are searched in the main banks MBK1 and MBK2, respectively. In the figure, it is assumed that the time from the input of the search key to the output of the match address is the same as in FIG. As described above, since the frequency of the master clock MCLK is double the bank search operation frequency, the CAM control circuit CAMCTL8 divides the master clock MCLK after 8 cycles equivalent to the operation time shown in FIG. Match addresses A1, A2, A3, and A4 are output from the RAM control circuit RAMCTL in synchronization with each edge of the address clock ACLK generated by the rotation.

  With the above configuration and operation, it is possible to perform a search operation by receiving a search key having a wide bit width in a cycle time shorter than the search operation cycle time tARY of the memory array. Further, even when the global IO is wired over a wide area of the chip, the load capacity increases, and it becomes difficult to shorten the operation cycle time of the global IO. The search operation can be performed by transferring the entry to the bank at high speed.

  The number of banks is not limited to two, and it can be easily understood that various operations can be performed by synchronizing more banks with clocks of different phases, as in the first embodiment. In this case, it is possible to realize a high-speed CAM that receives a search key at a higher frequency and performs a search process. FIG. 8 shows a configuration in which information encoded using two global IOs is distributed in the chip. However, the number of global IOs is not limited to this. If the operation cycle time of the global IO is shorter than the cycle time required for the search key receiving operation, one global IO can be used, and the chip area can be suppressed.

(Embodiment 3)
In the third embodiment, another example of the configuration and operation of the subarray used in the CAM described in the first and second embodiments will be described. FIG. 11 is a circuit block diagram showing a memory array configuration example different from FIG. 2 of the CAM included in the semiconductor device according to the third embodiment of the present invention. Hereinafter, the description will be made by paying attention to the difference from the memory array configuration of FIG.

  The memory array configuration shown in FIG. 11 is characterized in that dummy memory blocks MBD0, MBD1,... Having the same configuration are arranged on the dummy word line WLD in addition to the normal memory blocks shown in FIGS. Thus, the sense amplifier activation timing is generated. In the dummy memory blocks MBD0, MBD1,..., Dummy dummy match signals SMLD0, SMLD1,... And dummy main match lines MMLD are inserted with corresponding dummy submatch determination circuits SMDD0, SMDD1,. .

  Further, each of the memory cells DMC0, DMC1, DMC2, and DMC3 in the dummy memory blocks MBD0, MBD1,... Is connected to the dummy word line WLD, and the gate electrodes of the transistors T312 and T313 in each memory cell are connected to the ground voltage. Fixed to VSS. The dummy main match determination circuit MMDD generates a pulse signal corresponding to the voltage change of the dummy main match line MMLD in the sense amplifier enable signals SAEB and SAET. The main match determination circuit group MMDB11 corresponding to the regular memory blocks MB00, MB01,... Is controlled by the sense amplifier enable signals SAEB, SAET.

  FIG. 12 is a circuit diagram showing a detailed configuration example of the dummy / submatch determination circuit, dummy / main match determination circuit, and main match determination circuit in FIG. The dummy submatch determination circuits SMDD0, SMDD1,... Have the same transistors as the submatch determination circuits SMD00, SMD01,..., And in the dummy submatch determination circuits SMDD1,. The gate electrode is separated from the dummy submatch line and grounded. The transistor T201 is conductive because the gate electrode is fixed at the boosted voltage VPP, and the dummy submatch lines SMLD0, SMLD1,... Are always driven to the precharge voltage VPC.

  Here, although the precharge voltage VPC is lower than the array voltage VDL, it is set to a voltage level at which the transistor T202 is sufficiently conducted. Therefore, the transistor T202 in the dummy submatch determination circuit SMDD0 is turned on, and the other transistors T202 in the dummy submatch determination circuit are cut off. That is, an entry in which only one memory block (in this case, dummy memory block MBD0) is in a mismatch state is assumed, and a corresponding signal is generated on the dummy main match line MMLD. The array voltage VDL is set to a voltage lower than the power supply voltage VDD described in the first embodiment.

  The dummy main match determination circuit MMDD includes a PMOS transistor T211, inverter circuits IV21, IV22, IV23, a NAND circuit ND21, and a delay circuit DLY. The transistor T211 is set so that the gate size thereof is larger than that of the transistor T202 in the submatch determination circuit, and the dummy T211 is set in accordance with the search enable signal (search enable signal line) SEB connected to the gate electrode. The main match line MMLD is charged at high speed.

  The inverter circuit IV21 outputs a signal corresponding to the voltage change of the dummy main match line MMLD connected to the input terminal to the node IN20. The inverter circuits IV22 and IV23, the NAND circuit ND21, and the delay circuit DLY are connected to realize a circuit configuration that generates a one-shot pulse in response to a voltage change of the node IN20. The delay circuit DLY has, for example, a configuration in which an even number of inverter circuits are cascade-connected. The delay circuit DLY is inverted by the inverter circuit IV22 and then delayed and input to one input terminal of the NAND circuit ND21. The node IN20 is directly connected to the other input terminal of the NAND circuit ND21, and a sense amplifier enable signal SAEB is generated from the output terminal of the NAND circuit ND21. Further, the sense amplifier enable signal SAEB is inverted by the inverter circuit IV23 to generate the sense amplifier enable signal SAET.

  The main match determination circuit MMD110 is one of a plurality of main match determination circuits constituting the main match determination circuit group MMDB11 of FIG. 11, and includes PMOS transistors T221 and T222, a clocked inverter circuit CIV21, and a latch circuit LA. Composed. The transistor T221 is set to have the same gate size as that of the transistor T211 in the dummy main match determination circuit MMDD, and charges the main match line MML0 at high speed according to the search enable signal SEB connected to the gate electrode.

  The clocked inverter circuit CIV21 corresponds to the sense amplifier SA shown in FIG. 3, and is activated by the sense amplifier enable signals SAET and SAEB, and sends a signal corresponding to the voltage of the main match line MML0 to the hit signal node. Output to HIT0. Transistor T222 has a source electrode and a drain electrode connected to array voltage VDL terminal and hit signal node HIT0, respectively. The gate electrode is connected to the sense amplifier enable signal SAET, and drives the hit signal node HIT0 to the array voltage VDL during standby. The voltage change of the hit signal node HIT0 is held by the latch circuit LA.

  In the memory array having such a configuration, the search operation is performed as follows.

  First, the search operation when the search key matches the entry will be described with reference to FIG. Here, to simplify the description, it is assumed that the memory array shown in FIG. 11 has a configuration having two memory blocks per word line. Further, an entry corresponding to a range of 1 to 3 (decimal number) is stored in the memory block on the noticed word line WL0, and a comparison with a search key corresponding to 3 (decimal number) is performed. Assume that

  Accordingly, in FIG. 11, the storage node N00 in the memory block MB00 and the storage nodes N11 to N13 in the memory block MB01 are connected to the ground voltage VSS and the memory block according to the entry “0001 1110” block-coded every 2 bits. N01 to N03 in MB00 and storage node N10 in memory block MB01 are held at power supply voltage VDD. Further, it is assumed that all storage nodes in the memory block on the dummy word line WLD are at the ground voltage VSS.

  First, in the standby state, by driving the precharge activation signal line PC to the boosted voltage VPP, the transistor T201 in the submatch determination circuit is in a conductive state, so that the submatch lines SML00 and SML01 are driven to the precharge voltage VPC, respectively. The Here, as described above, the precharge voltage VPC is at a voltage level at which the transistor T202 in the submatch determination circuit is sufficiently conductive, so that the main match line MML0 is driven to the ground voltage VSS.

  The transistor T201 in the dummy / submatch determination circuit is in a conductive state because the boosted voltage VPP is input to the gate electrode, and the dummy / submatch lines SMLD0 and SMLD1 are always driven to the precharge voltage VPC. For this reason, since the transistor T202 in the dummy submatch determination circuit SMDD0 is conductive, the dummy main match line MMLD is driven to the ground voltage VSS.

  When the search operation starts, the precharge activation signal line PC having the boosted voltage VPP is driven to the ground voltage VSS to stop the pre-match line precharge, and then the search line having the ground voltage VSS is searched. In response to this, the array voltage VDL is driven. In the figure, in response to the encoded search key “0001 1000”, the search lines SL03 and SL10 having the ground voltage VSS are held while the search lines SL00 to SL02 and SL11 to SL13 are held at the ground voltage VSS, respectively. An example of driving each to the array voltage VDL is shown.

  Here, in the memory cell DMC3 in the memory block MB00 and the memory cell DMC0 in the memory block MB01, the transistors T312 and T313 are both turned on, so that the submatch lines SML00 and SML01 having the precharge voltage VPC are discharged, respectively. . Accordingly, transistor T202 in submatch determination circuits SMD00 and SMD01 is cut off. In this state, when the search enable signal line SEB having the array voltage VDL is driven to the ground voltage VSS, the dummy main match determination circuit MMDD and the transistor T211 in the main match determination circuit MMD110 become conductive, so that the ground voltage VSS Dummy main match line MMLD and main match line MML0 are charged at high speed toward array voltage VDL.

  Thereafter, the search enable signal SEB, which is the ground voltage VSS, is driven to the array voltage VDL at a timing when the dummy main match line MMLD and the main match line MML0 are charged to a voltage sufficiently higher than the reference voltage VREF. The transistor T211 is cut off and charging is stopped. Next, since the transistor T202 in the dummy submatch determination circuit SMDD0 is turned on, the voltage of the dummy main match line MMLD decreases toward the ground voltage VSS.

  Here, the dummy main match determination circuit MMDD detects the timing when the voltage of the dummy main match line MMLD falls below the reference voltage VREF, and based on this timing, the clocked inverter in the main match determination circuit MMD110 The circuit CIV21 (sense amplifier SA) is activated and the activation time width is determined.

  That is, the dummy main match determination circuit MMDD in FIG. 12 generates a pulse signal corresponding to the voltage change of the dummy main match line MMLD at the node IN20 via the inverter circuit IV21, and further via the NAND circuit ND21. The sense amplifier enable signal SAEB at the array voltage VDL is driven to the ground voltage VSS, and the sense amplifier enable signal SAET at the ground voltage VSS is driven to the array voltage VDL. As a result, the transistor T222 in the main match determination circuit MMD110 is cut off, and the clocked inverter CIV21 is activated. Here, since the main match line MML0 is held at a high voltage, the hit signal node HIT0 having the array voltage VDL is discharged to the ground voltage VSS.

  Thereafter, the dummy main match determination circuit MMDD uses the one-shot pulse generation circuit to change the sense amplifier enable signal SAEB at the ground voltage VSS to the array voltage VDL and the sense amplifier at the array voltage VDL. Each of the enable signals SAET is driven to the ground voltage VSS, and the clocked inverter CIV21 is inactivated. Further, when the transistor T222 is turned on, the hit signal node HIT is driven to the array voltage VDL. Further, by driving the precharge activation signal line PC at the ground voltage VSS to the boosted voltage VPP, the submatch lines SML00 and SML01 are driven to the precharge voltage VPC, and the main match line MML0 is driven to the ground voltage VSS. Return to standby again.

  Next, the search operation when the search key and the entry do not match will be described with reference to FIG. Here, as in FIG. 13, an entry (“0001 1110”) corresponding to a range of 1 to 3 (decimal number) is stored in the memory block on the word line WL0, and 0 (decimal). Assume that a comparison is made with the corresponding search key. Note that the precharge operation and the drive timing of each signal are the same as those described with reference to FIG.

  When the search operation starts, in response to the encoded search key “0001 0001”, the search lines SL00, SL03, SL11, SL13, which are at the ground voltage VSS, with the search lines SL01-SL03, SL11-SL13 held at the ground voltage VSS, respectively. SL10 is driven to the array voltage VDL. Here, in the memory cell DMC0 in the memory block MB01, the transistors T312 and T313 are both turned on, so that the submatch line SML01 at the precharge voltage VPC is discharged.

  However, the transistors that are turned on in the memory block MB00 are the transistor T312 in the memory cell DMC0 and the transistor T313 in the memory cells DMC1 to DMC3. Therefore, in any memory cell, the sub-match line SML00 is connected to the ground electrode. A current path is not formed. That is, submatch line SML00 is maintained at precharge voltage VPC, and transistor T202 in submatch determination circuit SMD00 is maintained in a conductive state.

  Accordingly, since the charge injected from the transistor T211 with the activation of the search enable signal line SEB is discharged from the main match line MML0 through the transistor T202 in the same manner as the dummy main match line MMLD, the dummy main match line MMLD is discharged. The voltage of the main match line MML0 is suppressed to a level lower than the logic threshold value VREF of the sense amplifier. Therefore, even if the clocked inverter CIV21 in the main match determination circuit MMD110 is activated by the above-described sense amplifier enable signals SAET and SAEB, the hit signal node HIT0 is held at the array voltage VDL.

  With the configuration and operation described above, the memory array shown in FIGS. 11 and 12 obtains the following three effects. First, the gate size of the PMOS transistor T211 in the main match determination circuit MMD110 is set to be larger than the NMOS transistor T202 in the submatch determination circuit, and the main match line is first driven to a high voltage. Then, by discharging the transistor T202, a voltage signal corresponding to the comparison result between the search key and the entry can be generated at high speed on the main match line.

  Second, dummy memory blocks MBD0, MBD1,..., Dummy submatch determination circuits SMDD0, SMDD1,..., And dummy main match determination circuit MMDD are arranged, and an entry when one memory block does not match is entered. By generating a corresponding signal on the dummy main match line MMLD, it is possible to generate the sense amplifier enable signals SAET and SAEB at the timing corresponding to the operation that takes the longest time for signal generation among the mismatched entries. Thus, by optimizing the start timing of the sense amplifier enable signal, it is possible to suppress an increase in power consumption due to the start timing being too early and a decrease in operating speed due to the start timing being too late. .

  Third, by setting the output of the clocked inverter CIV21 to the mismatch signal level by default, it is possible to greatly suppress power consumption in the search operation. That is, there are usually very few matching entries in the search table, and only the clocked inverter CIV21 corresponding to the few matching entries performs the operation of inverting the output. Therefore, power consumption in actual use is limited to the clocked inverter CIV21 corresponding to the matching entry and the latch circuit LA corresponding thereto.

  FIG. 12 shows a configuration in which the dummy / submatch determination circuit SMDD0 closest to the dummy / mainmatch determination circuit MMDD is used as the dummy / submatch determination circuit for discharging the dummy / mainmatch line MMLD. However, the arrangement of the dummy / submatch determination circuit for discharging the dummy main match line MMLD is not limited to this, and various arrangements are possible. In general, the signal propagation time depends on the distance from the transmission unit (or drive circuit; here, the dummy submatch determination circuit) to the reception unit (here, the dummy main match determination circuit MMDD). The start timing of the sense amplifier enable signals SAET and SAEB is determined by making the dummy submatch determination circuit located at the farthest end of the main match determination circuit MMDD as a dummy submatch determination circuit for discharging the dummy main match line MMLD. Accuracy can be increased.

  The invention made by the inventor has been specifically described based on the embodiment of the invention. Finally, a configuration example of the network router NR to which the CAM according to the invention is applied will be described with reference to FIG. In the figure, for simplicity of explanation, a router manager group RMB, a crossbar switch group CBSWB, and packet processor units PPU0 to PPUy are shown as main blocks.

  The router manager group RMB is composed of a plurality of central processing units (CPUs), and performs setting and control of the entire network router. The crossbar switch group CBSWB connects desired packet processor units according to the transfer path of the packet to be processed. The packet processor units PPU0 to PPUy are blocks that exchange packets with the corresponding networks IPN0 to IPNy, respectively.

  Reference numeral 130 schematically represents a packet PCT processed by the network router. The packet PCT is roughly divided into two areas. One 140 is a header area HDR, and the other 131 is a payload area PYLD. The header area HDR 140 further includes a plurality of (here, three) areas 141, 142, and 143 as shown in FIG.

  The area 141 is a second layer header L2HDR, and includes a source MAC address (Source address Media Access Control), a destination MAC address (Destination address Media Access Control), and the like. The area 142 is a third-layer header L3HDR, and includes a source IP address (Source IP address), a destination IP address (Destination IP address), and the like. The area 143 is a fourth-layer header L4HDR, and includes a protocol, that is, a source port (Destination port) representing a higher-level application, a destination port, and the like.

  The payload area PYLD has information designated by the sender, such as the body of an e-mail or a text file. The arrow 132 shown in the figure is the packet PCT transfer path, and the arrow 133 is the header area transfer path. Hereinafter, the detailed configuration of the packet processor units PPU0 to PPUy will be described while paying attention to these paths.

  Each of the packet processor units PPU0 to PPUy uses a network interface NIF, a packet forwarding processor PFP, a search engine SE, a content addressable memory CAM according to this embodiment, a DRAM, and the like. It consists of a content memory CM and a central processing unit PPUP for packet processor units.

  The network interface NIF and the packet forwarding processor PFP are connected by a system bus SBS. The packet forwarding processor PFP and the search engine SE are connected by an internal bus IBS. The search engine SE and the content addressable memory CAM are connected by a data bus DQ, a master clock MCLK, and a multi-bank enable signal MBKE. The search engine SE and the content memory CM are connected by a content data bus CBS. It is connected. The content addressable memory CAM and the content memory CM are connected by a content address bus CADD.

  For example, the router NR transmits and receives packet PCTs via the network interface NIF between the Internet network IPN0 and the packet processing unit PPU0. The packet forwarding processor PFP decodes the content of the received packet and transfers the header area HDR to the search engine SE while holding the payload area PYLD. The search engine SE extracts desired information from the header area using the central processing unit PPUP for packet processing units connected via the packet processing bus PPBS, and uses the content addressable memory CAM as a search key. Forward to.

  As described in the first and second embodiments, the content addressable memory CAM receives a search key in synchronization with the master clock MCLK and searches in a mode corresponding to the multi-bank enable signal MBKE. Perform the action. The content addressable memory CAM stores a large number of entries composed of information in the same format as the search key, and generates an address corresponding to the matched entry by the search operation. When this address is input to the content memory CM via the content address bus CADD, information on the corresponding entry is read from the content memory CM, and the packet forwarding processor PFP is read via the search engine SE. Forwarded to

  The information read here is, for example, transfer control information including optimum route information to the destination. The packet forwarding processor PFP rewrites the contents of the header area HDR based on this transfer control information, and reconstructs the packet PCT together with the above-described payload area PYLD. Then, the packet PCT is transferred from the crossbar switch group CBSWB to the network connected to the network router as the next relay point through the packet processing unit designated.

  In such a router NR configuration, the search key is generated using the search engine SE and the central processing unit PPUP for the packet processor unit. On the other hand, an entry stored in the content addressable memory CAM is generated and registered while the information ETR set by the administrator of the router NR is analyzed by the router manager group RMB or the central processing unit PPUP for the packet processor unit. .

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the CAM according to the present invention can be applied not only to an off-chip, that is, a single device, but also to a CAM block mounted on a system LSI called a so-called system-on-chip (SoC). The same effect as the embodiment can be obtained. Further, the memory cell may have a configuration other than that based on the DRAM cell of FIG. For example, since the manufacturing process of the CAM is simplified by using the SRAM cell, the chip unit price can be suppressed.

  As another example, a memory cell such as a flash memory, a ferroelectric RAM (ferroelectric random access memory), or an MRAM (magnetoressive random access memory) can be applied. In this case, since both have a nonvolatile memory cell structure, the search operation can be resumed in a short time even if a power interruption accident occurs.

  3 and 12 show the memory cell configuration in which NMOS transistors are connected in series in the order of T312 and T313 between the submatch line and the ground electrode, but the same search operation is possible even if the order is reversed. It is. Further, FIGS. 1 and 8 show the configuration including the encoding circuit group and the decoding circuit group corresponding to the ternary information and the quaternary information, but the configuration of the peripheral circuit is not limited to this, and the One-hot- Various modifications are possible in the case of a CAM that processes a spot block-encoded entry and a search key. For example, as shown in FIG. 8 of Reference 1, the same effect can be obtained even with a circuit configuration including a compression circuit and an expansion circuit inside the chip.

  In this embodiment, the CAM configuration in which the search key and the entry are encoded every 2 bits and searched and stored is shown by taking the memory block shown in FIGS. 2 and 3 as an example. However, the CAM configuration is not limited to this, and the number of encoded bits may be 3 bits or more as shown in FIG. For example, when coding every 3 bits, the memory block is composed of eight memory cells as shown in FIG. 12 of Reference 1, and the coding information bus, global IO, etc. are coded accordingly. The bus width for transmitting information is expanded. With such a configuration, the amount of information per entry is improved, and a CAM having a large capacity can be realized effectively.

  The CAM configuration that realizes the interleave operation described in the first and second embodiments can also be applied to a ternary CAM. That is, the configuration of the ternary CAM cell is the same as the combination of the two memory cells shown in FIGS. 2 and 3 of the present specification as shown in FIG. By performing accurate read / write and refresh operations using the configuration shown in FIGS. 4 and 5, a highly reliable and high-speed ternary CAM can be realized.

  The semiconductor device of the present invention can perform a search without delay by receiving a search key in a cycle faster than the search operation cycle of the memory array by interleaving a plurality of banked memory arrays. It is suitable for network router technology that searches tables without limiting the line speed that is rapidly increasing.

T201, T202, T211, T311, T312, T313, T321, T322, T331, N500, N501, N510, N511, N512, N520, N521, N522, N523, N530, N531, N540, N541, N543 NMOS transistors T211, T221 , T222, P500, P501, P520, P521, P540, P541 PMOS transistor C capacitor DMC0, DMC1, DMC2, DMC3 memory cell MMLm (m = 0, 1,...) Main match line MMLD dummy main match line SMLmj (m = 0, 1,..., J = 0, 1,...) Submatch line SMLDj (j = 0, 1,...) Dummy submatch line WLm (m = 0, 1,...) Word line WLD Dummy word line BLnx n = 0, 1,..., x = 0, 1,..., bit line SLnx (n = 0, 1,..., x = 0, 1,...) search line PC precharge activation signal line SEB search enable signal line Nnx (N = 0, 1,..., X = 0, 1,...) Storage node MBmj (m = 0, 1,..., J = 0, 1,...) Memory block MBDj (m = 0, 1,..., J = 0, 1,...) Dummy memory block SMDmj (m = 0, 1,..., J = 0, 1,...) Submatch determination circuit SMDDj (m = 0, 1,..., J = 0, 1,...) Dummy submatch determination circuit WDB Word driver group MMDB, MMDB11 Main match determination circuit group SDB Search line drive circuit group RWB Read / write circuit group RWSBK Read / write search circuit group SARYU, SARYL Subarray MMD0, MMD110 Main Check circuit MMDD dummy main match determination circuit RWSBKnx (n = 0, 1,..., X = 0, 1,...) Read / write search circuit SA sense amplifier EQ equalize circuit RCKT read circuit WCKT write circuit SCKT search line drive circuit VDD Power supply voltage VSS Ground voltage VDL Array voltage VPC Precharge voltage CSP, CSN Common source line BLEQ Bit line equalize signal RDU, RDL, RD Read start signal WTU, WTL Write start signal SCET, SCEB Search start signal IV21, IV22, IV23 Inverter circuit CIV21 Clocked inverter circuit LA latch circuit ND NAND circuit DLY delay circuit HIT0 hit signal node CADD content address bus DQ data bus DBS Data bus DIO Data input / output circuit BK1, BK2, BKA, BKB Bank MC Memory control circuit MBK1, MBK2 Main bank CAMCTL1, CAMCTL8 CAM control circuit TOBENC, QOBENC Encoding circuit group ENCBK Encoding circuit group OBTDEC, OBQDEC Decoding circuit group DECBK decoding circuit group MPE main priority encoder PE priority encoder RAMCTL RAM control circuit CDEC command decoder WSDMUX demultiplexer RMUX multiplexer REGBK Various registers INMD1-INMDs Input mask / difference registers OUTMD1-OUTMDs Output mask / difference registers DFI1 ~ DFIs Data area identification register group MA1 ~ MAs Match-a Less register CMD External command signal group MCLK Master clock MBKE, GMBKEN Multi bank enable signal INMDBS Input mask / difference bus OUTMDBS Output mask / difference bus HBSU, HBSL Hit signal bus MABS Match address bus SMABSA, SMABSB Sub Match address bus DFIBS Data area identification bus ENCBS Encoded information bus GIOA, GIOB Global IO
ENCLnx (n = 0, 1,..., X = 0, 1,...) Encoded data line RDE Read enable signal WTE Write enable signal SCE Search enable signal ACLK Content address clock DCLK Data clock BCLK1, BCLK2 , BCLKA1, BCLKA2, BCLKB1, BCLKB2 Bank control clock GCLKWS, GCLKR Global IO control clock 130 Packet 131 Payload area 140 Header area 141 Second layer header area 142 Third layer header area 143 Fourth layer header area NR Network router NIF network・ Interface PFP packet forwarding processor SE search engine CAM content ・ Addressable memory CM content Memory PPU Packet processing unit Central processing unit for PPUP packet processing unit RMB Routing manager group CBSWB Crossbar switch group CBS Content bus PPBS Packet processing bus IPNx (x = 0, 1, ..., y) Network SBS system bus IBS internal bus ETR Information set by router NR administrator

Claims (2)

Multiple bit lines,
A plurality of search lines provided corresponding to the plurality of bit lines, respectively, and arranged in parallel with the plurality of bit lines;
A plurality of word lines intersecting the plurality of bit lines;
A plurality of memory cells disposed at intersections of the plurality of bit lines and the plurality of word lines;
A plurality of main match lines provided corresponding to the plurality of word lines, respectively, and arranged in parallel with the plurality of word lines;
A plurality of main match lines are provided corresponding to each of the plurality of main match lines, arranged in parallel with the plurality of main match lines, each connected to a predetermined number of memory cells in the plurality of memory cells. Submatch lines,
A plurality of submatch determination circuits respectively connected between the plurality of submatch lines and any main match line corresponding to the plurality of submatch lines;
A plurality of main match determination circuits each connected to the plurality of main match lines, each including a sense amplifier;
A semiconductor device that compares information input through the plurality of search lines with information held in the plurality of memory cells and amplifies the comparison result by a sense amplifier in the plurality of main match determination circuits Because
In the search operation, the plurality of main match determination circuits first charge the plurality of main match lines to a voltage higher than a logical threshold value of the plurality of sense amplifiers, and after stopping the charging, the plurality of main match lines Activating the plurality of sense amplifiers when a line charge is discharged by a part or all of the plurality of submatch determination circuits to become a voltage lower than a logical threshold value of the plurality of sense amplifiers. A featured semiconductor device. The semiconductor device according to claim 1, further comprising:
A dummy main match line arranged in parallel with the plurality of word lines;
A plurality of dummy sub-match lines provided corresponding to the dummy main match lines, and arranged in parallel with the dummy main match lines;
A plurality of dummy submatch determination circuits respectively connected between the plurality of dummy submatch lines and the dummy main match line;
A dummy main match determination circuit connected to the dummy main match line,
The plurality of dummy submatch determination circuits are configured to simulate the plurality of submatch determination circuits,
The dummy main match determination circuit has a sense amplifier having the same configuration as the plurality of main match determination circuits,
The dummy main match determination circuit and the plurality of main match determination circuits are connected by a sense amplifier enable signal line,
The dummy main match determination circuit charges the dummy main match line to a voltage higher than a logical threshold value of the sense amplifier at the same timing and driving capability as the plurality of main match determination circuits during a search operation, After the charging is stopped, the charge on the dummy main match line is discharged by a predetermined dummy sub-match determination circuit in the plurality of dummy sub-match determination circuits to a voltage lower than the logical threshold value of the sense amplifier. A semiconductor device characterized by generating a start signal for the sense amplifier at this stage.

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