JP2009116460A - Information processing apparatus and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing apparatus that secures high reliability, as much as possible, while reducing the frequency of execution of the operation checks on an expanded memory, and to provide electronic equipment equipped with the processing apparatus. <P>SOLUTION: If it is not detected that a cover member to be opened so as to attach and detach the expanded memory is opened, while the information processor is turned off (No, in step S1), an operation check on only a standard memory is made in start-up of the processor (step S3); and if it is detected that the member is opened while the processor is turned off (Yes, in step S1), it is so constituted that the operation checks on the standard memory and the expanded memory are made at the start-up of the processor (step S11). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus that is mounted on an electronic device such as a copying machine, a printer device, a facsimile device, a scanner device, or a multifunction device thereof, and controls the electronic device, and is particularly executed when the information processing device is started up. This is related to the operation check of standard memory and additional memory.

2. Description of the Related Art Conventionally, electronic devices such as copiers, printer devices, facsimile devices, scanner devices, and multi-function devices of these types are used as control devices for controlling the electronic devices, such as CPU (arithmetic unit), ROM, RAM (memory), etc. Is mounted. In the information processing apparatus, the CPU controls the operation of the electronic device by developing and executing various electronic programs stored in the ROM on the RAM.
Generally, in the information processing apparatus, a memory operation check (hereinafter referred to as “memory check”) is executed when the information processing apparatus is activated. For example, in Patent Document 1, when the information processing apparatus is started, a memory check is performed only for the minimum necessary storage area necessary for starting the operating system, and other storage areas are stored in the storage area. It is disclosed to check each time when using the device. According to such a memory check method, since only the minimum necessary memory check is executed at the time of startup, the time required for startup can be shortened.
JP 2000-293391 A

By the way, in the information processing apparatus, the processing speed may be improved by adding an additional memory as an option separately from the standard memory provided in the information processing apparatus. In this case, when the information processing apparatus is started, not only a memory check for the standard memory but also a memory check for the additional memory is required.
However, if the memory check is always performed for both the standard memory and the additional memory at the time of starting up the information processing apparatus, there arises a problem that the time required for starting up becomes long.
Further, for example, using the technique disclosed in Patent Document 1, a memory check is executed only for a part of the storage areas of the standard memory and the additional memory at the time of startup, and other storage areas are It may be possible to check each time the storage area is used. However, in this case, the memory check for the storage area of each of the standard memory and the additional memory that is not the target of the memory check when the information processing apparatus is started up is performed during the normal operation of the information processing apparatus. There arises a problem that the processing speed decreases due to the load.
Note that many of the abnormalities that occur in the additional memory occur when the additional memory is attached or detached. For example, static damage when the user attaches / detaches the additional memory and poor mounting of the additional memory are typical causes.
Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information processing apparatus capable of ensuring as high reliability as possible while reducing the frequency of execution of the operation check of the additional memory. The object is to provide an electronic apparatus equipped with the same.

To achieve the above object, the present invention provides a standard memory having a data storage area, a memory mounting portion to which an additional memory is mounted, and a cover member that is opened when the additional memory is mounted to the memory mounting portion. , Which is applied to an information processing apparatus using only the standard memory, or an arithmetic device that executes various processes using the standard memory and the additional memory. Cover opening detection means for detecting that the cover member has been opened while the power is turned off, and the cover member while the information processing apparatus is turned off by the cover opening detection means. When the information processing device is not detected to be opened, an operation check of only the standard memory is performed when the information processing apparatus is activated, and the cover open detection means performs the information processing. If it is detected that the cover member is opened while the power of the device is turned off, the operation check of the standard memory and the additional memory is executed when the information processing apparatus is started. Is done.
According to the present invention, the operation check of the additional memory at the time of starting the information processing apparatus can be performed when the cover member is opened and the additional memory is attached or detached when the information processing apparatus is powered off. This is executed when the possibility is high, that is, when there is a relatively high possibility that an abnormality has occurred in the additional memory. As a result, it is possible to ensure as high reliability as possible while reducing the execution frequency of the operation check of the additional memory and reducing the average time required to start up the information processing apparatus.

Further, the additional memory may become abnormal due to deterioration over time. Therefore, the number of unchecked times when the operation check of the additional memory by the memory check means is not executed at the time of starting the information processing apparatus, or the unchecked time when the operation check of the additional memory is not executed is performed. When the counted number of unchecked times or the unchecked time reaches a predetermined value or more set in advance, it is desirable to execute an operation check of the additional memory. As a result, the operation check of the additional memory is periodically performed, so that it is possible to detect the occurrence of an abnormality due to deterioration over time.
By the way, the present invention may be understood as an invention of an electronic device including the information processing apparatus. In an electronic device provided with the information processing apparatus, it is possible to ensure as high reliability as possible while shortening the average time required to start the electronic device.

  According to the present invention, the operation check of the additional memory at the time of starting the information processing apparatus can be performed when the cover member is opened and the additional memory is attached or detached when the information processing apparatus is powered off. This is executed when there is a high probability that an abnormality has occurred in the additional memory, and it is relatively high. It is possible to ensure the highest possible reliability while shortening the time. In addition, it is conceivable that the reliability can be further improved by periodically checking the operation of the additional memory.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that the present invention can be understood. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.
FIG. 1 is a schematic diagram showing a schematic configuration of a control device X according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining an example of a procedure of a memory check process executed by the control device X. is there.
A control device X (an example of an information processing device) according to an embodiment of the present invention is mounted on an electronic device such as a copying machine, a printer device, a facsimile device, a scanner device, or a multifunction device thereof, and the operation of the electronic device is controlled. It is something to control. The present invention may be understood as an invention of an electronic device including the control device X.
As shown in FIG. 1, the control device X includes a CPU 1 (an example of an arithmetic device) that executes various arithmetic processes, a ROM 2 in which data such as various electronic programs are stored in advance, and the CPU 1 A standard memory 3 having a storage area used when it is executed, and a memory to which the additional memory 4 having a storage area used when the electronic program is executed by the CPU 1 as well as the standard memory 3 is mounted. Slot 5 (an example of a memory mounting portion), a cover member 6 that is opened when the additional memory 4 is mounted in the memory slot 5, and a cover monitor that monitors the opening and closing of the cover member 6 when the operation of the control device X is stopped A circuit 7 (an example of a cover open detection unit) is schematically provided.

The CPU 1 has a nonvolatile built-in memory 1a having a small capacity storage area where various parameters can be read and written. Specifically, the built-in memory 1a stores information such as a check flag F and an unchecked number N used in a memory check process (see the flowchart of FIG. 2) described later.
The check flag F serves as an index for the CPU 1 to determine whether the operation check of the additional memory 4 is necessary, and when the check flag F is raised (F = 1). This indicates that an operation check is necessary, and when the check flag F is not raised (F = 0), it indicates that no operation check is necessary.
The unchecked number N indicates the number of times that the operation check of the additional memory 4 has not been executed when the control device X is started up, and is reset when the operation check of the additional memory 4 is executed (N = 0). (S12 in the flowchart of FIG. 2). When the unchecked number N reaches a predetermined value or more, the check flag F is set (S6 in the flowchart of FIG. 2).

The standard memory 3 is a RAM such as a DRAM or SRAM capable of reading and writing data, and is a memory provided as a standard in the control device X. The CPU 1 develops and executes the electronic program stored in the ROM 2 in a storage area in the standard memory 3. Specifically, the CPU 1 uses the standard memory 3 for executing an operating system (OS) stored in at least the ROM 2.
The extension memory 4 is a RAM such as a DRAM or SRAM capable of reading and writing data, similar to the standard memory 3, and is attachable to and detachable from the memory slot 5. The CPU 1 uses the additional memory 4 in addition to the standard memory 3 when executing an electronic program other than the operating system. That is, the CPU 1 executes various processes using only the standard memory 3 or using the standard memory 3 and the additional memory 4.
As described above, in the configuration in which the additional memory 4 can be expanded, the CPU 1 can execute processing using the storage areas of both the standard memory 3 and the additional memory 4, thereby improving the processing speed. Is possible.
The cover member 6 is provided in a casing (not shown) of the control device X or a casing (not shown) of an electronic device in which the control device X is mounted. When the memory slot 5 is attached to or detached from the memory slot 5, it is opened by the user. As described above, when the cover member 6 is opened and the expansion memory 4 is attached / detached, there is a possibility that abnormalities such as electrostatic breakdown or poor mounting may occur in the expansion memory 4.

The cover monitoring circuit 7 monitors the opening and closing of the cover member 6 and includes, for example, an opening / closing switch 71, a capacitor 72, a resistor 73, a transistor 74, and the like.
Specifically, as shown in FIG. 1, the open / close switch 71 and the resistor 73 are connected in series, and these are connected in parallel to the capacitor 72. The capacitor 72 has one end connected to the emitter terminal of the transistor 74 and the CPU 1 and the other end connected to the ground. On the other hand, the CPU 1 is connected to the base terminal of the transistor 74, and a power source is connected to the collector terminal.

As shown by the solid line in FIG. 1, the open / close switch 71 contacts the rib of the cover member 6 when the cover member 6 is closed, and is turned off (OFF state). As shown by the broken line in FIG. Further, the limit switch is turned on (on state) when the cover member 6 is opened and the contact with the rib of the cover member 6 is released.
That is, the open / close switch 71 cuts off the connection between the capacitor 72 and the resistor 73 when the cover member 6 is closed, and connects the capacitor 72 and the resistor 73 when the cover member 6 is opened. To do.

The capacitor 72 is an electronic component having an electrostatic capacity, such as an electric double layer capacitor (also referred to as a super capacitor), for example, and accumulates and discharges charges. The capacitor 72 discharges the accumulated electric charge when connected to the resistor 73.
Accordingly, the capacitor 72 is in a charged state if the cover member 6 is closed and not connected to the resistor 73, but is discharged when the cover member 6 is opened and connected to the resistor 73. It will be. That is, in the cover monitoring circuit 7, when the capacitor 72 is charged, the cover X is turned off when the control device X is turned off depending on whether the charged state of the capacitor 72 is maintained. It is possible to detect whether the member 6 has been opened.
The detection result by the cover monitoring circuit 7 is input from the capacitor 72 to the CPU 1 as a cover open signal. Here, the cover open signal indicates, for example, that the cover member 6 is opened when “L”, and indicates that the cover member 6 is not opened when “H”.
As a result, the CPU 1 can determine whether the cover member 6 has been opened or not when the control device X is powered off in response to the cover open signal. Note that if the cover member 6 is opened and the open / close switch 71 is turned on while the control device X is powered off, current flows from the capacitor 72 to the CPU 1 as well. There is concern about the occurrence of up. For this reason, it is desirable to provide a diode or the like at the input terminal of the CPU 1 so as to provide latch-up protection. Of course, other known methods may be used as the latch-up protection method of the CPU 1. For example, when the control device X is turned off, an open collector is provided in front of the input terminal for the cover open signal to the CPU 1 so that no current flows to the CPU 1 even if the open / close switch 71 is closed. It is conceivable to provide a transistor (or FET, etc.).

The transistor 74 switches the presence / absence of power supply to the capacitor 72, that is, the presence / absence of charging, in accordance with a charge execution signal (“L” or “H”) output from the CPU 1.
In the control device X, while the power source of the control device X is ON, the transistor 74 is turned ON by supplying an “L” signal as the charge execution signal from the CPU 1, and power is supplied to the capacitor 72. Then, the capacitor 72 is charged. When the power source of the control device X is turned off, the CPU 1 outputs an “H” signal as the charge execution signal, and the transistor 74 is turned off. At this time, even if the power of the control device X is turned off and the power supply from the transistor 74 is cut off, the capacitor 72 holds the accumulated charge (charged state). As described above, the capacitor 72 is discharged when the cover member 6 is opened and the open / close switch 71 is closed and connected to the resistor 73.

Hereinafter, an example of the procedure of the memory check process executed by the CPU 1 according to the memory check program stored in the ROM will be described with reference to the flowchart of FIG. In the figure, S1, S2,... Represent processing procedure (step) numbers.
The memory check process is executed by the CPU 1 when, for example, the electronic device in which the control device X is mounted is turned on. In the memory check process, the CPU 1 executes the process using the built-in memory 1a provided inside.
In the memory check process executed by the control device X according to the embodiment of the present invention, as will be described below, the operation check of the additional memory 4 is performed when the cover member 6 is opened or for a predetermined period. It is executed only when the possibility that an abnormality has occurred in the additional memory 4 is relatively high, such as progress.

(Step S1)
First, in step S1, the CPU 1 determines whether or not the cover member 6 is opened when the control device X is powered off in response to the cover opening signal from the cover monitoring circuit 7. to decide.
For example, when the cover open signal is “L”, the CPU 1 determines that the cover member 6 is opened when the power of the control device X is turned off (Yes side of S1). In this case, it is determined that the operation check of the additional memory 4 is necessary, and the process proceeds to step S11. The processing after step S11 will be described later.
On the other hand, when it is determined that the cover member 6 is not opened when the cover open signal is “H” and the control device X is powered off (No side of S1), It is determined that the operation check of the additional memory 4 is not necessary, and the process proceeds to step S2. First, the processing of steps S2 to S7 executed subsequently in this case will be described.

(Step S2)
In step 2, the CPU 1 determines whether or not the check flag F stored in the built-in memory 1a is set (F = 1). Here, the check flag F is used to determine whether or not the operation check of the additional memory 4 needs to be executed. The check flag F is set in step S6 to be described later and reset in step S13 to be described later (F = 0). It is what is done.
Here, if it is determined that the check flag F is set (Yes side of S2), it is determined that an operation check of the additional memory 4 is necessary, and the processing is performed in the same manner as in step S1. The process proceeds to S11.
On the other hand, if it is determined that the check flag F is not set (No side of S2), it is determined that the operation check of the additional memory 4 is not necessary, and the process proceeds to step S3.

(Step S3)
In step S3, the CPU 1 performs an operation check on only the standard memory 3. Note that the operation check of the standard memory 3 by the CPU 1 may be performed by a well-known check process such as a read / write test.
At this time, the operation check target is, for example, the entire storage area of the standard memory 3. As in the prior art (see Patent Document 1), the operation check may be executed only for the minimum storage area required for executing the operating system in the standard memory 3 here.
Thus, when the control device X is turned off, the cover member 6 is not opened (No side of S1), and the check flag F is not set (S2). No), the operation check of only the standard memory 3 is executed on the assumption that the operation check of the additional memory 4 is unnecessary. Therefore, the execution frequency of the operation check of the additional memory 4 is reduced, and the average time required for starting the control device X can be shortened. As a result, the average time required for starting the electronic device on which the control device X is mounted. Can be shortened. Further, it is desirable that the operation check of the additional memory 4 is not executed even during the normal operation of the control device X. Thereby, it is possible to prevent a decrease in processing speed during normal operation.

(Steps S4 to S7)
In step S4, the CPU 1 increments the unchecked number N, which indicates the number of times the operation check of the additional memory 4 has not been executed, when the control device X is started up (N = N + 1). The initial value of the unchecked number N is 0. Here, the CPU 1 when counting the unchecked number N corresponds to a counter means.
Thereafter, in step S5, the CPU 1 determines whether or not the unchecked number N counted up in step S4 is less than a predetermined number set in advance. Here, it is assumed that the predetermined number of times is 10.
If it is determined that the unchecked number N is less than 10 (Yes in S5), the process proceeds to step S6, and it is determined that the unchecked number N has reached 10 or more. If so (NO side of S5), the process proceeds to step S7.

(Steps S6 and S7)
In step S6, the CPU 1 sets the check flag F indicating that the number of unchecked times N has reached 10 and the operation check of the additional memory 4 needs to be executed (F = 1). As a result, when the control device X is activated next time, it is determined in step S2 that the check flag F is set, and the process proceeds to later-described step S11. As described above, in the memory check process, when the number of unchecked times N in which the operation check of the additional memory 4 has not been executed when the control device X is started reaches a predetermined value or more, the check is performed. The flag F is set and the operation check of the additional memory 4 is executed. It should be noted that the operation check of the additional memory 4 may be executed not when the control device X is started next but when it is determined in step S5 that the unchecked number N has reached 10. It doesn't matter.
In step S 7, the CPU 1 outputs an “L” signal as the charge execution signal, whereby the transistor 74 is turned on and charging of the capacitor 72 is started. As a result, the cover open signal input to the CPU 1 becomes “H”, and when the power to the control device X is turned off, the cover member 6 can be detected to be opened. . Thereafter, the memory check process is terminated.

(Steps S11-13)
On the other hand, as described above, after activation of the control device X, when it is determined in step S1 that the cover member 6 is opened when the power of the control device X is turned off (Yes side of S1) Alternatively, if it is determined in step S2 that the check flag F is set (Yes side of S2), it is necessary to perform an operation check of the additional memory 4, and the process proceeds to step S11. To do.
In step S11, the CPU 1 checks the operation of both the standard memory 3 and the additional memory 4. That is, in the memory check process, the operation check of the additional memory 4 is executed only when the possibility that an abnormality has occurred in the additional memory 4 is relatively high. At this time, the object of the operation check is, for example, the entire storage area of the standard memory 3 and the additional memory 4.
When the operation check of the standard memory 3 and the additional memory 4 in step S11 ends normally, in the subsequent step S12, the unchecked number N is reset by the CPU 1 (N = 0).
Thereafter, in step S13, the CPU 1 resets the check flag F (F = 0), and then shifts the processing to step S7.

As described above, in the memory check process executed by the control device X, the cover monitoring circuit 7 detects that the cover member 6 is opened while the control device X is powered off. If not, the operation check of only the standard memory 3 is performed when the control device X is started, and the cover member 6 is opened while the power of the control device X is turned off by the cover monitoring circuit 7. If it is detected that the control device X has been activated, an operation check of the standard memory 3 and the additional memory 4 is executed. Here, the CPU 1 when executing the memory check process corresponds to the memory check means.
Even if the expansion memory 4 is not attached or detached, an abnormality may occur in the expansion memory 4 due to deterioration over time. In the memory check process, the operation check of the expansion memory 4 is performed when the control device X is started. When the unchecked number N indicating the number of times of the unchecked execution has reached a predetermined value (here, 10 times) or more and the check flag F is set, It is controlled to perform an operation check. Here, the CPU 1 when executing such processing corresponds to a periodic memory check means. As described above, by periodically checking the operation of the additional memory 4, it is possible to detect the occurrence of an abnormality due to deterioration over time.
Instead of the unchecked count N, an unchecked time during which the operation check of the additional memory 4 has not been executed is counted, and when the unchecked time reaches a predetermined value or more, Executing an operation check of the additional memory 4 can be considered as another embodiment. The CPU 1 when executing such processing also corresponds to regular memory check means.
As described above, the control device X does not always execute the operation check of the additional memory 4 when the control device X is activated, and reduces the frequency of execution of the operation check of the additional memory 4 to reduce the control control X. The average time required for starting the apparatus X is shortened. On the other hand, when the possibility that an abnormality has occurred in the additional memory 4 is relatively high, an operation check of the additional memory 4 is executed to ensure as high reliability as possible.

The schematic diagram which shows schematic structure of the control apparatus which concerns on embodiment of this invention. The flowchart for demonstrating an example of the procedure of the memory check process performed with the control apparatus which concerns on embodiment of this invention.

Explanation of symbols

1: CPU (an example of an arithmetic unit)
2: ROM
3: Standard memory 4: Additional memory 5: Memory slot (memory mounting part)
6: Cover member 7: Cover monitoring circuit (an example of cover open detection means)
71: Open / close switch 72: Capacitor 73: Resistor 74: Transistors S1, S2...: Processing procedure (step) number X: Control device

Claims (3)

A standard memory having a data storage area, a memory mounting portion to which an additional memory is mounted, a cover member that is opened when the additional memory is mounted to the memory mounting portion, and using only the standard memory, or An information processing apparatus comprising a standard memory and an arithmetic device that executes various processes using the additional memory,
Cover opening detection means for detecting that the cover member is opened while the information processing apparatus is powered off;
If it is not detected by the cover open detection means that the cover member has been opened while the information processing apparatus is powered off, an operation check of only the standard memory is performed when the information processing apparatus is activated. When the information processing apparatus detects that the cover member has been opened while the information processing apparatus is powered off, the standard memory and the expansion are executed when the information processing apparatus is activated. A memory check means for performing a memory operation check;
An information processing apparatus comprising: Counter means for counting the number of unchecked times when the operation check of the additional memory is not executed by the memory check means at the time of starting the information processing apparatus, or the unchecked time when the operation check of the additional memory is not executed; ,
Periodic memory check means for performing an operation check of the additional memory when the unchecked count or unchecked time counted by the counter means reaches a predetermined value or more,
The information processing apparatus according to claim 1, further comprising:   An electronic apparatus comprising the information processing apparatus according to claim 1.

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