JP2009116410A - Electric property estimation program, electric property estimation device and electric property estimation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To estimate an electric property of a semiconductor package with high accuracy as considering cost. <P>SOLUTION: This electric property estimation device acquires information related to a configuration of a PKG (semiconductor package), specifies substrate cost and assembly cost from the acquired information related to the configuration of the PKG, and calculates cost of the PKG. The electric property estimation device acquires wire length information of the PKG from design information, specifies an electromagnetic field analysis simulation result according to the wire length information as an electric property value of a wire portion of the PKG, similarly acquires interposer wiring length information of the PKG from the design information, specifies an electromagnetic field analysis simulation result according to the interposer wiring length information as an electric property value of an interposer portion of the PKG, and outputs them together with a cost calculation result. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electrical property estimation program, an electrical property estimation method, and an electrical property estimation device that estimate electrical properties of a semiconductor package.

  In recent years, with the development of LSI manufacturing technology, it has become possible to increase the operating frequency of LSI chips. With the improvement of microfabrication technology, various types of semiconductor packages (hereinafter referred to as “PKG”) on which LSI chips capable of high-speed operation are mounted are provided. In such a PKG, electrical noise such as SSO (simultaneous output switching) noise and crosstalk noise generated in the PKG has a greater influence on LSI chip operation than in the past. Therefore, in order to design a PKG that achieves proper operation, it is necessary to accurately grasp the electrical noise as described above.

  In order to accurately grasp the electrical noise generated inside the PKG, the electrical characteristics of the PKG must be estimated. In particular, when collaborative design is performed in consideration of both the type of LSI chip, the configuration of the LSI chip, and the PKG, a technique for accurately estimating the electrical characteristics of the entire PKG is required. Conventionally, in order to estimate the electrical characteristics of a PKG, a method of referring to the electrical characteristics of the PKG that is most similar to the PKG to be estimated from an existing PKG electrical characteristics database such as IBIS data, or the structure of the PKG is applied to a simple calculation formula. Thus, a method for calculating the electrical characteristics of PKG has been used.

  Furthermore, in recent years, in order to extract the electrical characteristics of PKG equipped with high-speed multi-pins such as FCBGA (Flip Chip Ball Grid Array), the PKG model is divided, and the electrical characteristics model of each part is created and synthesized. Analyze the electrical characteristics of the PKG as a whole (for example, see Patent Document 1 below), divide the power pattern (plane) of the PKG board into meshes, and create the electrical parameters of the power pattern from the RLGC formula of the parallel plate model In other words, there is disclosed an analysis method for analyzing electrical characteristics (for example, see Patent Document 2 below).

Japanese Patent Laid-Open No. 2007-4602 JP 2006-253187 A

  However, in the case of a method of referring to similar electrical characteristics in the existing PKG electrical characteristics database as in the prior art, the extraction conditions for the information stored in the electrical characteristics database are not clear, and the database is prepared as a database. Since there are few types of PKG, there is a problem that the estimation accuracy is low.

  Moreover, when using a simple calculation formula, it cannot respond to various PKGs having different structures. Therefore, in the case of a PKG having a complicated structure due to multifunctionalization, there is a problem that estimation becomes difficult.

  Furthermore, the techniques disclosed in Patent Documents 1 and 2 are both methods for generating an electrical characteristic model after completing the layout design of PKG. Therefore, there has been a problem that it is not possible to feed back to the PKG design of the electrical noise calculated from the estimation result of the electrical characteristics corresponding to the contents of the PKG from the initial design stage.

  In addition, although cost adjustment is an important factor in recent PKG manufacturing, none of the above-described conventional techniques has a function of referring to information on cost from the contents of PKG design. Therefore, there is a problem that the PKG design considering the cost cannot be performed.

  In order to solve the above-described problems caused by the prior art, the present invention provides an electrical property estimation program, an electrical property estimation device, and an electrical property estimation method capable of estimating various electrical properties of PKG with high accuracy while considering cost. The purpose is to provide.

  In order to solve the above-described problems and achieve the object, the electrical characteristic estimation program, the electrical characteristic estimation device, and the electrical characteristic estimation method are configured to estimate the electrical characteristics of the semiconductor package from the design information of the semiconductor package on which the LSI chip is mounted. Electrical property estimation processing for performing acquisition of information related to the configuration of the semiconductor package, specifying a substrate cost and assembly cost from the acquired information related to the configuration of the semiconductor package, and calculating the cost of the semiconductor package Then, wire length information for connecting the LSI chip to the semiconductor package is acquired from the design information, and an electromagnetic field analysis simulation result corresponding to the acquired wire length information is specified as an electrical characteristic value of the wire portion of the semiconductor package The interposer distribution of the semiconductor package The length information is acquired from the design information, the electromagnetic field analysis simulation result corresponding to the acquired interposer wiring length information is specified as the electrical characteristic value of the interposer portion of the semiconductor package, and the semiconductor calculated by the cost calculation It is a requirement to output the cost of the package, the electrical characteristic value of the identified wire part, and the electrical characteristic value of the interposer part.

  According to the electrical characteristic estimation program, the electrical characteristic estimation apparatus, and the electrical characteristic estimation method, the electrical characteristics obtained by independently estimating the wire part and the interposer part of the semiconductor package are output, and the cost of the semiconductor package is also included. Can be output.

  The electrical property estimation program, the electrical property estimation device, and the electrical property estimation method described above correspond to the operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as the electrical property value of the wire portion. A resistance value may be calculated and this resistance value may be output.

  According to the electrical property estimation program, electrical property estimation device, and electrical property estimation method, when the induction coefficient and the capacitance are specified as the electrical property value of the wire portion by the electromagnetic field analysis simulation, the frequency depends on the frequency of the wire portion. The resistance value can be estimated.

  The electrical property estimation program, the electrical property estimation device, and the electrical property estimation method described above may be in accordance with an operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as electrical property values of the interposer portion. It is also possible to calculate a resistance value and output the resistance value.

  According to the electrical characteristic estimation program, the electrical characteristic estimation device, and the electrical characteristic estimation method, when the induction coefficient and the capacitance are specified as the electrical characteristic value of the interposer part by electromagnetic field analysis simulation, the frequency of the interposer part is determined. It is possible to estimate the resistance value according to the above.

  In addition, the above-described electrical property estimation program, electrical property estimation device, and electrical property estimation method are a library in which electromagnetic field analysis simulation results for each change in wire length are stored in advance, and an electromagnetic field analysis simulation for each change in interposer wiring length. The electrical characteristic value of the wire part and the electrical characteristic value of the interposer part may be specified with reference to a library storing results.

  According to the electrical characteristic estimation program, the electrical characteristic estimation apparatus, and the electrical characteristic estimation method, the electromagnetic field analysis simulation is performed when the estimation process is executed in order to refer to the electromagnetic field analysis simulation result stored in the library when specifying the electrical characteristics. The electrical characteristics can be immediately identified without any problems.

  In addition, the electrical property estimation program, the electrical property estimation device, and the electrical property estimation method may include at least one of the output cost of the semiconductor package, the electrical property value of the wire portion, and the electrical property value of the interposer portion. When a value change instruction is received, design information corresponding to the received change instruction may be created and the design information may be output.

  According to the electrical characteristic estimation program, the electrical characteristic estimation apparatus, and the electrical characteristic estimation method, it is possible to feed back the estimation result of the electrical characteristics and cost regarding a certain PKG to the design of the PKG.

  According to this electrical property estimation program, electrical property estimation device, and electrical property estimation method, it is possible to estimate the electrical properties of various PKGs with high accuracy while considering the cost.

  Exemplary embodiments of an electrical property estimation program, an electrical property estimation device, and an electrical property estimation method will be described below in detail with reference to the accompanying drawings.

(Outline of electrical property estimation process)
An outline of the electrical property estimation process according to the present embodiment will be described. FIG. 1 is an explanatory diagram showing an outline of the electrical characteristic estimation processing according to the present embodiment. In the electrical characteristic estimation process according to the present embodiment, the PKG is divided into parts of a wire part and an interposer part, and the electrical characteristic value of each part is estimated independently. At this time, the cost of the PKG to be estimated is calculated in conjunction.

  Specifically, as in the electrical property estimation process 100 of FIG. 1, first, the PKG is designed by the semiconductor package (PKG) design tool 110. The semiconductor package (PKG) design tool 110 uses, for example, a three-dimensional CAD for PKG design. This 3D CAD is used to design a PKG according to the application.

  The electrical property estimation tool 120 estimates the electrical property value of the PKG using the design information of the PKG designed by the semiconductor package (PKG) design tool 110 as input information 111. Specifically, the PKG design information is information such as the type of candidate PKG, the number of pins, the external size, the wire length of each PKG, and each wiring length. Note that if it is desired to design a PKG that falls within a predetermined cost, cost setting information may be set as the input information 111.

  By the electrical property estimation process by the electrical property estimation tool 120, the electrical property estimated value for each PKG and the PKG cost are output as the output information 121. Further, when cost setting information is set as the input information 111, the electrical characteristic estimated value may be output limited to the PKG in the cost range set by the cost setting information.

  The output information 121 output by the electrical characteristic estimation tool 120 is fed back to the semiconductor package (PKG) design tool 110. The designer refers to the output information 121 fed back to the semiconductor package (PKG) design tool 110 and adjusts the design of the PKG. The design information of the PKG after the design adjustment is input again to the electrical property estimation tool 110 and an estimation process is performed. By repeating this process, the semiconductor package (PKG) design tool 110 can design the PKG desired by the designer. When the PKG design is determined by the semiconductor package (PKG) design tool 110, the PKG is manufactured according to the PKG design information determined by the PKG manufacturing apparatus 130.

  As described above, in the electrical property estimation process 100 of the present embodiment, the electrical property and cost of the PKG can be estimated at the time of designing the PKG. Hereinafter, as an implementation example of the electrical property estimation tool 120, a case where an electrical property estimation device is provided will be specifically described.

(Hardware configuration of electrical characteristic estimation device)
Next, the hardware configuration of the electrical characteristic estimation apparatus according to this embodiment will be described. FIG. 2 is an explanatory diagram showing a hardware configuration of the electrical characteristic estimation apparatus according to the present embodiment.

  In FIG. 2, an electrical characteristic estimation device 200 is composed of a computer main body 210, an input device 220, and an output device 230, and a network 240 such as a LAN, WAN, or Internet via a router or modem (not shown). Can be connected to.

  The computer main body 210 has a CPU, a memory, and an interface. The CPU governs overall control of the electrical characteristic estimation apparatus 200. The memory is composed of ROM, RAM, HD, optical disk 211, and flash memory. The memory is used as a work area for the CPU.

  The memory stores various programs such as a basic input / output program and an electrical characteristic estimation program, and is loaded according to a command from the CPU. Data read / write of the HD and the optical disk 211 is controlled by a disk drive. The optical disk 211 and the flash memory are detachable from the computer main body 210. The interface controls input from the input device 220, output to the output device 230, and transmission / reception with respect to the network 240.

  The input device 220 includes a keyboard 221, a mouse 222, a scanner 223, and the like. The keyboard 221 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Further, it may be a touch panel type. The mouse 222 performs cursor movement, range selection, window movement, size change, and the like. The scanner 223 optically reads an image. The read image is captured as image data and stored in a memory in the computer main body 210. Note that the scanner 223 may have an OCR function.

  Examples of the output device 230 include a display 231, a speaker 232, and a printer 233. The display 231 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. The printer 233 prints image data and document data. The speaker 232 outputs sounds such as sound effects and reading sounds.

(Functional configuration of electrical characteristic estimation device)
Next, a functional configuration of the electrical characteristic estimation apparatus will be described. FIG. 3 is a block diagram illustrating a functional configuration of the electrical characteristic estimation apparatus. 3, the electrical characteristic estimation apparatus 200 includes a configuration information acquisition unit 301, a cost calculation unit 302, a wire length information acquisition unit 303, an interposer wiring length information acquisition unit 304, a specification unit 305, and an output unit 306. And. In addition, an electromagnetic field analysis simulator 320 that performs electromagnetic field analysis simulation is connected to the electrical characteristic estimation apparatus 200.

  The configuration information acquisition unit 301 acquires information regarding the configuration of the PKG. The information regarding the configuration of the PKG is information indicating what kind of LSI chip is used to design the PKG, such as the type of candidate PKG and the number of pins. The configuration information acquisition unit 301 may accept input of information relating to the configuration of the PKG from the PKG designer, or may have a function of appropriately extracting from the design information of the PKG.

  The cost calculation unit 302 specifies the board cost and the assembly cost from the information related to the configuration of the PKG acquired by the configuration information acquisition unit 301, and calculates the cost of the PKG. The expression of the cost value calculated by the cost calculation unit 302 is not limited, and may be an absolute value such as an actual unit price or a relative value based on a reference value or a conventional value.

  The wire length information acquisition unit 303 acquires wire length information for connecting the LSI chip to the PKG from the design information 310. Further, the interposer wiring length information acquisition unit 304 acquires PKG interposer wiring length information from the design information 310.

  The identifying unit 305 identifies the electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquiring unit 303 as the electrical characteristic value of the wire portion of the PKG. The identifying unit 305 identifies the electromagnetic field analysis simulation result corresponding to the interposer wiring length information acquired by the interposer wiring length information acquiring unit 304 as the electrical characteristic value of the interposer portion of the PKG.

  Further, when the specifying unit 305 specifies the induction coefficient and the capacitance as the electric characteristic value of the wire portion of the PKG, the specifying unit 305 calculates a resistance value according to the operating frequency of the PKG, and calculates the induction coefficient as the electric characteristic value of the interposer portion. And the capacitance are determined, a resistance value corresponding to the operating frequency of the semiconductor package is calculated.

  In the electromagnetic field analysis simulation of the wire length information or the interposer wiring length information by the specifying unit 305, the electric characteristics may be specified for each electric characteristic estimation process by the electromagnetic field analysis simulator 320, but the electromagnetic field analysis simulator 320 in advance. A library that stores electromagnetic field analysis simulation results for each change in wire length and electromagnetic field analysis simulation results for each change in interposer wiring length is prepared. The electrical property value of the poser portion may be specified.

  The output unit 306 outputs the PKG cost calculated by the cost calculation unit 302, the electrical characteristic value of the wire portion specified by the specifying unit 305, and the electrical characteristic value of the interposer portion. The output here is not limited to the output from the output device 230 but also includes a process of storing information on the cost and each electrical characteristic value in a recording unit such as the optical disk 211. Note that, when the resistance value is calculated by the specifying unit 305, the output unit 306 also outputs the resistance value.

  In addition to the functions 301 to 306 described above, the electrical property estimation apparatus 200 includes at least the cost of the PKG output by the output unit 306, the electrical property value of the wire portion, and the electrical property value of the interposer portion. You may provide the reception part which receives the change instruction | indication of one value, and the preparation part which produces the design information according to the change instruction received by this reception part (all are not shown). When such a configuration is added, the output unit 306 outputs the design information when the design information is created by the creation unit.

  Each of the functions 301 to 306 described above is executed by causing the CPU to execute an electrical characteristic estimation program related to the functions 301 to 306 stored in the storage unit of the electrical characteristic estimation apparatus 200 or by using an input / output I / F. It is possible to realize the electrical characteristic estimation process by controlling.

(Electrical characteristics estimation process)
Next, the procedure of the electrical property estimation process by the electrical property estimation apparatus 200 will be described. FIG. 4 is a flowchart showing a procedure of electrical characteristic estimation processing by the electrical characteristic estimation apparatus. In the flowchart of FIG. 4, first, it is determined whether or not the configuration information acquisition unit 301 has acquired information regarding the configuration of the PKG (step S401). Here, the process waits until the information related to the PKG configuration is acquired (step S401: No loop). When the information is acquired (step S401: Yes), the cost calculation unit 302 calculates the PKG cost from the acquired information related to the PKG configuration ( Step S402).

  When the cost calculation ends, it is determined whether or not the wire length information acquisition unit 303 has acquired the wire length information from the design information (step S403). In this case as well, the process waits until the wire length information is acquired (step S403: No loop). If acquired (step S403: Yes), the specifying unit 305 specifies the electrical characteristics of the wire portion (step S404).

  Similarly, it is determined whether the interposer wiring length information acquisition unit 304 has acquired interposer wiring length information from the design information (step S405). Also here, the process waits until the interposer wiring length information is acquired (step S405: No loop). If acquired (step S405: Yes), the specifying unit 305 specifies the electrical characteristics of the interposer part (step S406).

  Finally, the PKG cost calculated by the cost calculation unit 302 and the electrical characteristics of the PKG wire portion and interposer portion specified by the specifying unit 305 are output (step S407), and the series of processing ends. When the PKG design is corrected from the output result, the above-described processing of steps S401 to S407 is performed again using the information related to the configuration of the modified PKG and the design information.

  As described above, the electrical characteristic estimation apparatus 200 can output the electrical characteristics estimated independently for the wire portion and the interposer portion of the PKG, and can also output the cost of the PKG. Since the PKG is divided into parts and the respective electric characteristics are estimated, it is possible to estimate the electric characteristics with high accuracy regardless of the type of the PKG regardless of whether the structure is complicated or simple.

  In addition, the electrical characteristic estimation apparatus 200 can feed back the estimation result of the electrical characteristics to the PKG design, and can perform the PKG design in consideration of the cost at the time of feedback.

  Next, specific examples of the estimation processing of the electrical characteristics of each part (wire portion and interposer portion) in the specifying unit 305 and the cost calculation processing in the cost calculation unit 302 as described above will be individually described below.

(Estimation of electrical characteristics according to wire length)
First, the estimation of the wire portion, that is, the estimation of the electrical characteristics according to the wire length will be described. FIG. 5 is an explanatory diagram showing an example of a three-dimensional wire model. FIG. 5 shows a wiring example of wires connecting the LSI chip and the substrate portion of the PKG. In order to cope with the higher functionality of LSIs and the increase in the number of pins in recent years, the configuration of PKGs has been increased in number, and wires are often wired in multiple stages. Therefore, as shown in FIG. 5, it is necessary to obtain the wire length from the three-dimensional wire model in consideration of the chip thickness, the lifting height, and the CAD wire length.

  FIG. 6A is an explanatory diagram illustrating an example of an approximate expression for specifying the electrical characteristics, and FIG. 6B is a chart illustrating an example of calculating electrical characteristics according to the wire length. When the CAD wire length is obtained by the three-dimensional wire model as shown in FIG. 5, the capacitance (capacitance) and the inductance (inductive coefficient) are specified as shown in a chart 620 of FIG. 6-2. These electrical characteristic values can be obtained from the approximate expression 610 as shown in FIG.

  The approximate expression in FIG. 6A is obtained in advance from the calculation result obtained by the electromagnetic field analysis simulator. FIG. 6A shows an example of inductance, but the capacitance can be similarly obtained from the calculation result by the electromagnetic field analysis simulator. Furthermore, a resistance value corresponding to the operating frequency of the LSI chip can also be calculated from the inductance and capacitance obtained from the approximate expression.

  In the process of estimating the electrical characteristics including these three-dimensional wire models, the three-dimensional wire model obtained by the semiconductor package (PKG) design tool 110 may be used, or the specifying unit 305 or the electromagnetic field analysis simulator 320 may be used. 3D wire model corresponding tool may be mounted to obtain the wire length, and then the electrical characteristics may be specified.

(Estimation of electrical characteristics according to interposer wiring length)
Next, the estimation of the interposer portion, that is, the estimation of the electrical characteristics according to the interposer wiring length will be described. FIG. 7 is an explanatory diagram showing an example of a two-dimensional model of interposer wiring. Since the interposer wirings (line 1 to line 5) interact with each other like the interposer model 700 of FIG. 7, the electrical characteristics are calculated for each arrangement point (line x) and the minimum wiring interval W. There is a need. Here, the minimum wiring interval W is set to a parameter with a wiring interval from 1 to 5 times the minimum wiring interval W, with the interposer wiring width being the minimum wiring interval W.

  FIGS. 8-1 to 8-5 are tables illustrating examples of electrical characteristics according to the minimum wiring interval. 8-1 is the minimum wiring interval W × 1, FIG. 8-2 is the minimum wiring interval W × 2, FIG. 8-3 is the minimum wiring interval W × 3, FIG. 8-4 is the minimum wiring interval W × 4, FIG. -5 represents the electrical characteristics (self-inductance Lm, capacitance Cm) at each arrangement point (line x) when the minimum wiring interval W × 5. In this manner, since the electrical characteristics can be specified for each wiring interval, the interposer wiring interval and the wiring structure can be optimized.

  In the process of estimating the electrical characteristics in consideration of the two-dimensional model of the interposer wiring, the two-dimensional model of the interposer wiring obtained by the semiconductor package (PKG) design tool 110 may be used, or the specifying unit 305 Alternatively, the electromagnetic field analysis simulator 320 may be equipped with a corresponding tool for a two-dimensional model of interposer wiring to obtain mutual components, and then the electrical characteristics may be specified.

(Calculation of PKG cost)
Next, calculation of the PKG cost will be described. FIG. 9 is a chart showing an example of calculating the PKG cost. As shown in the chart 900 of FIG. 9, the cost calculation unit 302 calculates cost data for each variation of the configuration of each PKG. Each cost data shown in the chart 900 is a value calculated individually from data of each substrate cost corresponding to the type of PKG and each assembly cost. The chart 900 shows the cost in a quantitative manner with a PKG cost of size 10 mm ² , 2 layers, design rule A as the standard “1.0”, but a specific unit price (such as XX yen) is shown. It may be displayed.

(Electrical characteristics estimation example)
Next, an example of estimating the electrical characteristics of a certain PKG using each estimate and cost calculation described above will be described. FIG. 10 is a flowchart illustrating an example of electrical characteristic estimation. FIG. 11 is an explanatory diagram showing an example of the estimation target PKG. The procedure for estimating the electrical characteristics of the PKG 1100 shown in FIG. 11 will be described below using the flowchart of FIG.

  In the flowchart of FIG. 10, it is determined whether or not information on the estimation target PKG has been input (step S <b> 1001). Here, the PKG 1100 in FIG. 11 is the estimation target PKG. Information on the PKG to be estimated includes, for example, information on the configuration of the PKG type (BGA 400 pin, etc.), the PKG external shape (** mm), the number of layers (* layer, etc.) in the case of a multilayer structure, and PKG design information. An LSI chip + PKG outline drawing is created, and information on the wire length and interposer wiring length of the part whose electrical characteristics are to be estimated is obtained using a major function or the like. Specifically, information that wire length = ** mm and interposer wiring length = ** mm is acquired.

  Wait until the information of the target PKG is input (step S1001: No loop), and when the information of the PKG is input (step S1001: Yes), the electrical property estimation process of the wire portion of the target PKG (step S1002), Interposer section electrical characteristic estimation processing (step S1003) is performed. Note that the processes of steps S1002 and S1003 are in no particular order.

  Next, it is determined whether a cost range has been input (step S1004). If the cost range has been input (step S1004: Yes), the PKG wire LCR value and interposer LCR value that fall within the input cost range are output (step S1005), and a series of processing ends. To do.

  On the other hand, if the cost range is not input in step S1004 (step S1004: No), the cost is calculated from the information of the PKG (step S1006). Then, the PKG wire LRC value, interposer LCR value, and cost are output (step S1007), and a series of processing ends.

  FIG. 12 is an explanatory diagram illustrating an output example of the electrical characteristic estimation result. In FIG. 12, a window 1200 is displayed on the display as an output example of the electrical characteristic estimation apparatus 200. When the electrical characteristic estimation as described in the flowchart of FIG. 11 is performed, the LKG value 1220 of the PKG is estimated according to the design information (CAD wire length, lifting height) 1210 of the PKG as in the window 1200. Is output. At this time, a cost calculation value 1230 corresponding to the design information of the PKG is also output to the same window 1200 in order to compare the costs.

  Further, as described above, the estimation result of the electric characteristic value by the electric characteristic estimating apparatus 200 can be applied to the process of estimating electric noise such as crosstalk and SSO noise. Since the electrical characteristics according to the configuration of the PKG can be estimated, it is possible to estimate the noise including the sensitivity fluctuation for each PKG. These noise estimation results can be fed back to PKG design constraints. Accordingly, it is possible to select a PKG having an optimum configuration corresponding to a desired cost band from the initial stage of PKG design.

  As described above, according to the present embodiment, it is possible to estimate high-quality electrical characteristic values at the initial stage of PKG design. In addition, since it is possible to compare and examine electrical characteristic values for different configurations such as the type and outer shape of the PKG, it is possible to design an optimal PKG suitable for the application. Furthermore, since the cost of the PKG can be output in conjunction with the estimation result of the electrical characteristic value, development with an awareness of the cost of the PKG can be performed from the initial design stage. Thus, by using the electrical property estimation process according to the present embodiment, various electrical properties of PKG can be estimated with high accuracy while considering the cost.

  The electrical characteristic estimation method described in the present embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. This program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. Further, this program may be a transmission medium that can be distributed via a network such as the Internet.

  In addition, the electrical characteristic estimation apparatus 200 described in the present embodiment is a PLD (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured specific integrated circuit (ASIC) (hereinafter simply referred to as “ASIC”) or a PLD (such as an FPGA). It can also be realized by Programmable Logic Device). Specifically, for example, the function (301 to 306) of the above-described electrical characteristic estimation apparatus 200 is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD, thereby providing the electrical characteristic estimation apparatus 200. Can be manufactured.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) An electrical characteristic estimation program for causing a computer to execute an estimation process of electrical characteristics of a semiconductor package from design information of a semiconductor package on which an LSI chip is mounted,
A configuration information acquisition step for acquiring information on the configuration of the semiconductor package;
A cost calculation step of calculating a cost of the semiconductor package by specifying a substrate cost and an assembly cost from information on the configuration of the semiconductor package acquired by the configuration information acquisition step;
Wire length information acquisition step for acquiring wire length information for connecting the LSI chip to the semiconductor package from the design information;
A first specifying step of specifying an electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquiring step as an electrical characteristic value of the wire portion of the semiconductor package;
An interposer wiring length information acquisition step for acquiring interposer wiring length information of the semiconductor package from the design information;
A second specifying step of specifying an electromagnetic field analysis simulation result corresponding to the interposer wiring length information acquired by the interposer wiring length information acquiring step as an electrical characteristic value of the interposer portion of the semiconductor package;
The cost of the semiconductor package calculated by the cost calculating step, the electric characteristic value of the wire portion specified by the first specifying step, and the electric characteristic value of the interposer portion specified by the second specifying step And an output process for outputting
Is executed by the computer.

(Supplementary Note 2) A resistance value calculation step of calculating a resistance value according to the operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as the electrical characteristic values of the wire portion in the first specification step. To the computer,
The electrical characteristic estimation program according to appendix 1, wherein the output step outputs the resistance value when the resistance value is calculated by the resistance value calculation step.

(Supplementary Note 3) When an induction coefficient and a capacitance are specified as electrical characteristic values of the interposer portion in the second specifying step, a resistance value calculation for calculating a resistance value according to the operating frequency of the semiconductor package Causing the computer to execute a process;
The electrical characteristic estimation program according to appendix 1, wherein the output step outputs the resistance value when the resistance value is calculated by the resistance value calculation step.

(Supplementary Note 4) A first resistor that calculates a resistance value according to an operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as electrical characteristic values of the wire portion by the first specifying step. A value calculation process;
A second resistance value calculating step of calculating a resistance value according to an operating frequency of the semiconductor package when the induction coefficient and the capacitance are specified as the electrical characteristic values of the interposer portion by the second specifying step. And causing the computer to execute
The electrical characteristic estimation program according to appendix 1, wherein the output step outputs the resistance value when the resistance value is calculated by the first resistance value calculating step and the second resistance value calculating step. .

(Supplementary Note 5) The first identification step is to identify an electrical characteristic value of the wire portion by referring to a library in which electromagnetic field analysis simulation results for each change in wire length are stored in advance.
The second specification step is characterized in that an electrical characteristic value of the interposer portion is specified by referring to a library in which electromagnetic field analysis simulation results for each change in interposer wiring length are stored in advance. The electrical characteristic estimation program as described in any one of.

(Additional remark 6) The reception process which receives the change instruction | indication of at least 1 value of the cost of the said semiconductor package output by the said output process, the electrical property value of the said wire part, and the electrical property value of the said interposer part, ,
A creation step for creating design information corresponding to the change instruction received in the reception step;
When design information is created by the creation process, a design information output process for outputting the design information;
The electrical characteristic estimation program according to any one of appendices 1 to 5, wherein the computer is executed.

(Appendix 7) An electrical characteristic estimation device that performs estimation processing of electrical characteristics of a semiconductor package from design information of a semiconductor package on which an LSI chip is mounted,
Configuration information acquisition means for acquiring information on the configuration of the semiconductor package;
A cost calculation means for specifying a substrate cost and an assembly cost from information on the configuration of the semiconductor package acquired by the configuration information acquisition means, and calculating the cost of the semiconductor package;
Wire length information acquisition means for acquiring wire length information for connecting the LSI chip to the semiconductor package from the design information;
Interposer wiring length information acquisition means for acquiring interposer wiring length information of the semiconductor package from the design information;
The electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquisition unit is specified as the electrical characteristic value of the wire portion of the semiconductor package, and the interposer wiring length acquired by the interposer wiring length information acquisition unit Identifying means for identifying an electromagnetic field analysis simulation result according to information as an electrical characteristic value of an interposer portion of the semiconductor package;
Output means for outputting the cost of the semiconductor package calculated by the cost calculating means, the electrical characteristic value of the wire portion specified by the specifying means, and the electrical characteristic value of the interposer portion;
An electrical characteristic estimation device comprising:

(Supplementary Note 8) The specifying unit includes a resistance value calculating unit that calculates a resistance value according to an operating frequency of the semiconductor package, when an induction coefficient and a capacitance are specified as an electrical characteristic value of the wire portion.
The electrical characteristic estimation apparatus according to appendix 7, wherein the output means outputs the resistance value when the resistance value is calculated by the resistance value calculation means.

(Supplementary Note 9) The specifying unit includes a resistance value calculating unit that calculates a resistance value according to an operating frequency of the semiconductor package, when an induction coefficient and a capacitance are specified as an electrical characteristic value of the interposer portion.
The electrical characteristic estimation apparatus according to appendix 7, wherein the output means outputs the resistance value when the resistance value is calculated by the resistance value calculation means.

(Supplementary Note 10) When the specifying unit specifies the induction coefficient and the capacitance as the electric characteristic value of the wire part, the specifying unit calculates a resistance value according to the operating frequency of the semiconductor package, and the electric characteristic of the interposer part When the induction coefficient and the capacitance are specified as values, a resistance value calculating means for calculating a resistance value according to the operating frequency of the semiconductor package is provided.
The electrical characteristic estimation apparatus according to appendix 7, wherein the output means outputs the resistance value calculated by the resistance value calculation means.

(Supplementary Note 11) The specifying unit refers to a library in which electromagnetic field analysis simulation results for each change in wire length and electromagnetic field analysis simulation results for each change in interposer wiring length are stored in advance. The electrical property estimation device according to any one of appendices 7 to 10, wherein a property value and an electrical property value of the interposer portion are specified.

(Appendix 12) Accepting means for accepting an instruction to change at least one of the cost of the semiconductor package output by the output means, the electrical characteristic value of the wire portion, and the electrical characteristic value of the interposer portion;
Creating means for creating design information according to the change instruction received by the receiving means,
The electrical characteristic estimation apparatus according to any one of appendices 7 to 11, wherein the output means outputs the design information when the creation information is created by the creation means.

(Supplementary note 13) An electrical characteristic estimation method for performing estimation processing of electrical characteristics of a semiconductor package from design information of a semiconductor package on which an LSI chip is mounted,
A configuration information acquisition step of acquiring information on the configuration of the semiconductor package;
A cost calculation step of identifying a substrate cost and an assembly cost from information on the configuration of the semiconductor package acquired by the configuration information acquisition step, and calculating a cost of the semiconductor package;
Wire length information acquisition step for acquiring wire length information for connecting the LSI chip to the semiconductor package from the design information;
A first specifying step of specifying an electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquiring step as an electrical characteristic value of the wire portion of the semiconductor package;
An interposer wiring length information acquisition step for acquiring interposer wiring length information of the semiconductor package from the design information;
A second specifying step of specifying an electromagnetic field analysis simulation result corresponding to the interposer wiring length information acquired by the interposer wiring length information acquiring step as an electrical characteristic value of the interposer portion of the semiconductor package;
The cost of the semiconductor package calculated by the cost calculating step, the electric characteristic value of the wire portion specified by the first specifying step, and the electric characteristic value of the interposer portion specified by the second specifying step An output process for outputting
A method for estimating electrical characteristics, comprising:

(Supplementary Note 14) A resistance value calculating step of calculating a resistance value according to an operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as the electric characteristic value of the wire portion in the first specifying step. Including
14. The electrical characteristic estimation method according to appendix 13, wherein the output step outputs the resistance value when the resistance value is calculated by the resistance value calculation step.

(Supplementary Note 15) When an induction coefficient and a capacitance are specified as electrical characteristic values of the interposer portion in the second specifying step, a resistance value calculation that calculates a resistance value according to the operating frequency of the semiconductor package Including steps,
14. The electrical characteristic estimation method according to appendix 13, wherein the output step outputs the resistance value when the resistance value is calculated by the resistance value calculation step.

(Supplementary Note 16) A first resistor that calculates a resistance value according to an operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as electrical characteristic values of the wire portion by the first specifying step. A value calculation process;
A second resistance value calculating step of calculating a resistance value according to the operating frequency of the semiconductor package when the induction coefficient and the capacitance are specified as the electrical characteristic values of the interposer portion by the second specifying step. And including
14. The electrical characteristic estimation method according to appendix 13, wherein the output step outputs the resistance value when the resistance value is calculated by the first resistance value calculating step and the second resistance value calculating step. .

(Supplementary Note 17) The first specifying step specifies an electrical characteristic value of the wire portion by referring to a library in which electromagnetic field analysis simulation results for each change in wire length are stored in advance,
The second specifying step specifies the electrical characteristic value of the interposer portion with reference to a library in which electromagnetic field analysis simulation results for each change of the interposer wiring length are stored in advance. The electrical property estimation method according to any one of the above.

(Supplementary Note 18) A reception step of receiving an instruction to change at least one of the cost of the semiconductor package output by the output step, the electrical property value of the wire portion, and the electrical property value of the interposer portion;
A creation step of creating design information according to the change instruction received by the reception step;
When design information is created by the creation step, a design information output step for outputting the design information;
The electrical property estimation method according to any one of supplementary notes 13 to 17, characterized by including:

It is explanatory drawing which shows the outline | summary of the electrical property estimation process concerning this Embodiment. It is explanatory drawing which shows the hardware constitutions of the electrical property estimation apparatus concerning this Embodiment. It is a block diagram which shows the functional structure of an electrical property estimation apparatus. It is a flowchart which shows the procedure of the electrical property estimation process by an electrical property estimation apparatus. It is explanatory drawing which shows an example of a three-dimensional wire model. It is explanatory drawing which shows an example of the approximate expression for specifying an electrical property. It is a graph which shows the example of calculation of the electrical property according to wire length. It is explanatory drawing which shows an example of the two-dimensional model of interposer wiring. It is a graph which shows an example of the electrical property according to the minimum wiring space | interval (1 time). It is a graph which shows an example of the electrical property according to the minimum wiring space | interval (2 times). It is a graph which shows an example of the electrical property according to the minimum wiring space | interval (3 times). It is a graph which shows an example of the electrical property according to the minimum wiring space | interval (4 times). It is a graph which shows an example of the electrical property according to the minimum wiring space | interval (5 times). It is a chart which shows the example of calculation of PKG cost. It is a flowchart which shows an example of electrical property estimation. It is explanatory drawing which shows an example of estimation object PKG. It is explanatory drawing which shows the example of an output of an electrical property estimation result.

Explanation of symbols

DESCRIPTION OF SYMBOLS 110 Semiconductor package (PKG) design tool 120 Electrical characteristic estimation tool 130 PKG manufacturing apparatus 200 Electrical characteristic estimation apparatus 210 Computer main body 220 Input apparatus 230 Output apparatus 240 Network

Claims (8)

An electrical characteristic estimation program for causing a computer to execute an estimation process of electrical characteristics of the semiconductor package from design information of the semiconductor package on which the LSI chip is mounted,
A configuration information acquisition step for acquiring information on the configuration of the semiconductor package;
A cost calculation step of calculating a cost of the semiconductor package by specifying a substrate cost and an assembly cost from information on the configuration of the semiconductor package acquired by the configuration information acquisition step;
Wire length information acquisition step for acquiring wire length information for connecting the LSI chip to the semiconductor package from the design information;
A first specifying step of specifying an electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquiring step as an electrical characteristic value of the wire portion of the semiconductor package;
An interposer wiring length information acquisition step for acquiring interposer wiring length information of the semiconductor package from the design information;
A second specifying step of specifying an electromagnetic field analysis simulation result corresponding to the interposer wiring length information acquired by the interposer wiring length information acquiring step as an electrical characteristic value of the interposer portion of the semiconductor package;
The cost of the semiconductor package calculated by the cost calculating step, the electric characteristic value of the wire portion specified by the first specifying step, and the electric characteristic value of the interposer portion specified by the second specifying step And an output process for outputting
Is executed by the computer. When the induction coefficient and the capacitance are specified as the electrical characteristic value of the wire portion by the first specifying step, the resistance value calculating step for causing the computer to calculate a resistance value corresponding to the operating frequency of the semiconductor package is performed. Let it run
The electrical characteristic estimation program according to claim 1, wherein the output step outputs the resistance value when the resistance value is calculated by the resistance value calculation step. A resistance value calculating step of calculating a resistance value according to an operating frequency of the semiconductor package when an induction coefficient and a capacitance are specified as electrical characteristic values of the interposer portion by the second specifying step; To run
The electrical characteristic estimation program according to claim 1, wherein the output step outputs the resistance value when the resistance value is calculated by the resistance value calculation step. In the first specifying step, the electric characteristic value of the wire portion is specified by referring to a library in which electromagnetic field analysis simulation results for each change in wire length are stored in advance.
The second specifying step is characterized in that an electrical characteristic value of the interposer portion is specified by referring to a library in which electromagnetic field analysis simulation results for each change in interposer wiring length are stored in advance. The electrical property estimation program according to any one of 3 above. An electrical characteristic estimation device that performs estimation processing of electrical characteristics of a semiconductor package from design information of a semiconductor package on which an LSI chip is mounted,
Configuration information acquisition means for acquiring information on the configuration of the semiconductor package;
A cost calculation means for specifying a substrate cost and an assembly cost from information on the configuration of the semiconductor package acquired by the configuration information acquisition means, and calculating the cost of the semiconductor package;
Wire length information acquisition means for acquiring wire length information for connecting the LSI chip to the semiconductor package from the design information;
Interposer wiring length information acquisition means for acquiring interposer wiring length information of the semiconductor package from the design information;
The electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquisition unit is specified as the electrical characteristic value of the wire portion of the semiconductor package, and the interposer wiring length acquired by the interposer wiring length information acquisition unit Identifying means for identifying an electromagnetic field analysis simulation result according to information as an electrical characteristic value of an interposer portion of the semiconductor package;
Output means for outputting the cost of the semiconductor package calculated by the cost calculating means, the electrical characteristic value of the wire portion specified by the specifying means, and the electrical characteristic value of the interposer portion;
An electrical characteristic estimation device comprising: The specifying means includes a resistance value calculating means for calculating a resistance value according to an operating frequency of the semiconductor package, when an induction coefficient and a capacitance are specified as an electrical characteristic value of the wire portion,
6. The electrical characteristic estimation apparatus according to claim 5, wherein the output means outputs the resistance value when the resistance value is calculated by the resistance value calculation means. The specifying unit includes a resistance value calculating unit that calculates a resistance value according to an operating frequency of the semiconductor package, when an induction coefficient and a capacitance are specified as an electrical characteristic value of the interposer portion.
6. The electrical characteristic estimation apparatus according to claim 5, wherein the output means outputs the resistance value when the resistance value is calculated by the resistance value calculation means. An electrical property estimation method for performing estimation processing of electrical characteristics of a semiconductor package from design information of a semiconductor package on which an LSI chip is mounted,
A configuration information acquisition step of acquiring information on the configuration of the semiconductor package;
A cost calculation step of identifying a substrate cost and an assembly cost from information on the configuration of the semiconductor package acquired by the configuration information acquisition step, and calculating a cost of the semiconductor package;
Wire length information acquisition step for acquiring wire length information for connecting the LSI chip to the semiconductor package from the design information;
A first specifying step of specifying an electromagnetic field analysis simulation result corresponding to the wire length information acquired by the wire length information acquiring step as an electrical characteristic value of the wire portion of the semiconductor package;
An interposer wiring length information acquisition step for acquiring interposer wiring length information of the semiconductor package from the design information;
A second specifying step of specifying an electromagnetic field analysis simulation result corresponding to the interposer wiring length information acquired by the interposer wiring length information acquiring step as an electrical characteristic value of the interposer portion of the semiconductor package;
The cost of the semiconductor package calculated by the cost calculating step, the electric characteristic value of the wire portion specified by the first specifying step, and the electric characteristic value of the interposer portion specified by the second specifying step An output process for outputting
A method for estimating electrical characteristics, comprising:

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