JP2009115992A - Method for manufacturing flattening structure and method for manufacturing display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase exposure accuracy of a resist layer as much as possible, while increasing durability of a flattening structure against ashing. <P>SOLUTION: The method includes steps of layering a barrier layer 16 on the surface of a flattening film 15 formed on a substrate 11, forming a resist layer 20 on the surface of the barrier layer 16, forming a mask by exposing the resist layer 20 to form an aperture, etching the flattening film 15 through the aperture of the mask, and removing the mask from the etched flattening film 15 by ashing, wherein the barrier layer 16 comprises an underlayer anti-reflection film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a planarization structure included in, for example, a semiconductor device and a method for manufacturing a display device.

  For example, in an electronic apparatus such as a liquid crystal display device, a large number of elements such as TFTs (thin film transistors) which are semiconductor devices are formed. In order to improve the reliability of the electronic device, it is necessary to form the elements and wirings formed on the substrate with high accuracy. For example, in a semiconductor device, a wiring or electrode pattern is formed in an uneven shape on an insulating substrate, and a flattening film, which is an insulating film, is formed to cover and flatten the unevenness. Thus, a planarization structure is formed on the substrate. The planarizing film is generally composed of SOG (Spin on Glass), a polymer film, or the like.

  On the planarizing film of the semiconductor device, an opening pattern such as a contact hole is formed by photolithography, and then a new thin film pattern such as a wiring is stacked. In order to form such a thin film pattern on the flattening film with high accuracy, it is necessary to maintain the flatness of the surface of the flattening film.

However, if the photoresist formed on the planarizing film is removed by ashing in the step of forming the contact hole or the like, the surface of the film shrinks as a result of, for example, promoting SOG SiO ₂ to be densified. There is a risk of cracking. In addition, since the polymer film has low resistance to oxygen plasma, it is inevitable that the surface of the planarization film is eroded by ashing.

  Therefore, in general, an insulating film for further planarization is formed on the surface of the planarization film by CVD. However, in such a conventional manufacturing method, since the planarization film is formed twice, the number of steps is increased.

  On the other hand, for example, as disclosed in Patent Document 1, it is known to provide a barrier layer made of inorganic SOG on the surface of the planarization film.

FIG. 8 is a cross-sectional view showing a conventional planarization structure. As shown in FIG. 8, a semiconductor layer 112 formed in an island shape and a gate insulating film 113 covering the semiconductor layer 112 are formed on the surface of the insulating substrate 111. On the gate insulating film 113, a gate electrode 114 is formed in a region overlapping with the semiconductor layer 112, and a planarizing film 115 made of SOG is formed so as to cover the gate electrode 114. A barrier layer 116 made of inorganic SOG is formed on the surface of the planarizing film 115. Then, the resist layer 120 is formed on the barrier layer 116, and the resist layer 120 is irradiated with the exposure light 121 to form a mask having a predetermined shape. Subsequently, after the planarization film 115 and the barrier layer 116 are etched, the resist layer 120 is removed by ashing.
JP 2005-150268 A

  However, actually, even when the barrier layer made of inorganic SOG is provided as described above, the resistance to oxygen plasma at the time of ashing is still low, for example, much lower than a film formed by CVD. Therefore, there is a problem that the ashing processing conditions are limited.

  Further, when the resist layer on the barrier layer is exposed, the exposure light is reflected on the lower surface side of the resist layer, and a standing wave due to multiple interference is generated in the resist layer. As a result, since the exposure accuracy of the resist layer is lowered, there is also a problem that the shape accuracy of the opening pattern formed in the planarization film is lowered.

  The present invention has been made in view of such various points, and an object of the present invention is to increase the exposure accuracy of the resist layer as much as possible while increasing the resistance to the ashing of the flattened structure.

  In order to achieve the above object, in the present invention, a barrier layer composed of a lower antireflection film is laminated on the surface of the planarization film.

  Specifically, a method for manufacturing a planarization structure according to the present invention is a method for manufacturing a planarization structure including a planarization film formed on a substrate and planarizing unevenness on the substrate. A step of laminating a barrier layer on the surface of the flattening film formed in the step, a step of forming a resist layer on the surface of the barrier layer, and exposing the resist layer to form an opening in the resist layer. A step of forming a mask, a step of etching the barrier layer and the planarizing film through the opening of the mask, and a step of removing the mask from the etched barrier layer by ashing, The barrier layer is composed of a lower antireflection film.

  The planarizing film may be made of SOG.

  The planarization film may be composed of a polymer film.

  Prior to the formation of the resist layer, it is preferable that the planarizing film and the barrier layer be simultaneously fired and fully cured.

  In the method for manufacturing a display device according to the present invention, the step of forming the first substrate, the step of forming the second substrate, and the first substrate and the second substrate are bonded together via the display medium layer. The first substrate is formed on the substrate so as to cover the semiconductor layer, and the unevenness on the substrate is flattened. The step of forming the first substrate includes a step of laminating a barrier layer on the surface of the planarization film formed on the substrate, and a resist on the surface of the barrier layer. Forming a layer; exposing the resist layer to form an opening in the resist layer; forming a mask; and forming the barrier layer and the planarizing film through the opening in the mask. Etching process and etched burrs Includes removing by ashing the mask from the layer, the barrier layer is composed of a lower layer antireflection film.

  The planarizing film may be made of SOG.

  The planarization film may be composed of a polymer film.

  Prior to the formation of the resist layer, it is preferable that the planarizing film and the barrier layer be simultaneously fired and fully cured.

-Action-
Next, the operation of the present invention will be described.

  In the case of manufacturing a display device including the planarization structure, a first substrate and a second substrate are formed in advance, and then the first substrate and the second substrate are bonded together via a display medium layer.

  In the step of forming the first substrate, first, a planarizing film is formed on the substrate, and a barrier layer is laminated on the surface of the planarizing film. This barrier layer is composed of a lower antireflection film (BARC: Bottom AntiReflective Coating).

  Next, a resist layer is formed on the surface of the barrier layer. Thereafter, the resist layer is exposed and an opening is formed in the resist layer to form a mask. Next, the barrier layer and the planarizing film are etched through the opening of the mask. Thereby, the planarizing film is patterned. Thereafter, the mask is removed from the etched barrier layer by ashing.

  At that time, since a barrier layer made of a lower antireflection film is formed on the surface of the planarizing film, the resistance of the barrier layer to oxygen plasma is enhanced. Therefore, the resistance against ashing of the planarization structure can be improved without forming a new planarization film by CVD.

  In addition, since the barrier layer is composed of a lower antireflection film, when the resist layer is exposed, exposure light is absorbed by the lower antireflection film on the lower surface side of the resist layer, and exposure within the resist layer is performed. Generation of standing waves due to multiple interference of light is prevented. As a result, since the exposure accuracy of the resist layer is increased, the etching accuracy of the planarization film is also increased. Thus, the planarization structure and the display device having the planarization structure are formed with high accuracy, and the reliability of the entire device is improved.

  According to the present invention, the resistance against ashing of the planarization structure can be enhanced by laminating the barrier layer made of the lower antireflection film on the surface of the planarization film. Furthermore, the exposure accuracy of the resist layer can be increased, and the etching accuracy of the planarization film can be increased. In addition, since the flatness can be maintained without forming a new flattening film separately by CVD, the number of steps can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

Embodiment 1 of the Invention
1 to 7 show Embodiment 1 of the present invention.

  FIG. 1 is a cross-sectional view showing the resist layer 20 and the barrier layer 16 to be exposed. FIG. 2 is a cross-sectional view showing the semiconductor layer 12 and the gate electrode 14 formed on the substrate 11. FIG. 3 is a cross-sectional view showing the planarization film 15 covering the gate electrode 14. FIG. 4 is a cross-sectional view showing the barrier layer 16 formed on the surface of the planarizing film 15. FIG. 5 is a cross-sectional view showing the planarizing film 15 and the mask in which the contact holes 23 are formed. FIG. 6 is a cross-sectional view showing the TFT 30 having the planarization structure 10. FIG. 7 is a cross-sectional view showing a schematic structure of the liquid crystal display device 1.

  First, the configuration of the liquid crystal display device 1 of Embodiment 1 will be described with reference to FIG.

  The liquid crystal display device 1 is provided between a TFT substrate 51 which is a first substrate, a counter substrate 52 which is a second substrate disposed to face the TFT substrate 51, and the TFT substrate 51 and the counter substrate 52. And a liquid crystal layer 53 which is a display medium layer. The planarization structure of the first embodiment is formed on the TFT substrate 51.

  Although not shown, the counter substrate 52 is formed with a color filter, a common electrode made of ITO or the like, a black matrix, and the like. The counter substrate 52 is provided with an alignment film on the surface on the liquid crystal layer 53 side, and a polarizing plate is laminated on the surface opposite to the liquid crystal layer 53. Further, the liquid crystal layer 53 is sealed with a sealing material 54 interposed between the TFT substrate 51 and the counter substrate 52.

  On the other hand, the TFT substrate 51 is configured as a so-called active matrix substrate. Although not shown, the TFT substrate 51 has a plurality of pixels, which are display unit regions, arranged in a matrix. The TFT substrate 51 is provided with a TFT formed in each pixel and a TFT constituting a drive circuit as a driver. The TFT substrate 51 is provided with an alignment film on the surface on the liquid crystal layer 53 side, and a polarizing plate is laminated on the surface opposite to the liquid crystal layer 53. Thus, the liquid crystal display device 1 is configured to perform desired display by driving the liquid crystal layer 53 for each pixel.

  As shown in FIG. 6, the planarization structure 10 according to the first exemplary embodiment includes a planarization film 15 that is formed on a substrate 11 and planarizes unevenness on the substrate 11. Further, the TFT 30 which is a semiconductor device in the first embodiment includes the planarization structure 10. The TFT 30 according to the first embodiment is formed on the TFT substrate 51 constituting the liquid crystal display device 1 as described above.

  The substrate 11 is an insulating substrate, and is constituted by, for example, a glass substrate 11. As shown in FIG. 6, the semiconductor layer 12 is formed in an island shape on the surface of the glass substrate 11. The semiconductor layer 12 is composed of a silicon film and forms an active region of the TFT 30. A gate insulating film 13 is formed on the glass substrate 11 so as to cover the semiconductor layer 12.

  A gate electrode 14 is formed on the gate insulating film 13 so as to overlap a part of the semiconductor layer 12. The region of the semiconductor layer 12 that overlaps the gate electrode 14 is a channel region (not shown). Although not shown, a source region and a drain region are formed in regions on both the left and right sides of the channel region in the semiconductor layer 12.

  Further, a planarizing film 15 is formed on the gate insulating film 13 so as to cover the gate electrode 14 and the semiconductor layer 12. The planarizing film 15 is made of SOG (Spin on Glass). The planarizing film 15 may be made of a polymer film. In the planarizing film 15 and the gate insulating film 13, contact holes 23 penetrating the planarizing film 15 and the gate insulating film 13 are formed at positions above the source region and the drain region of the semiconductor layer 12, respectively.

  An electrode portion 24 made of a metal material is formed in the contact hole 23 and on the surface of the planarizing film 15 around the opening. That is, the electrode portion 24 that conducts to the source region constitutes a source electrode, while the electrode portion 24 that conducts to the drain region constitutes a drain electrode. Thus, the TFT 30 is configured, for example, as a top gate type, and has the planarization structure 10 in which the surface of the planarization film 15 is planarized.

-Manufacturing method-
Next, a method for manufacturing the liquid crystal display device 1 will be described together with a method for manufacturing the planarization structure 10.

  In the case of manufacturing the liquid crystal display device 1, a step of forming the TFT substrate 51, a step of forming the counter substrate 52, and a step of bonding the TFT substrate 51 and the counter substrate 52 through the liquid crystal layer 53 are performed. Do.

  In the step of forming the counter substrate 52, although not shown, the color filter, the common electrode, the black matrix, and the like are formed on the glass substrate. On the other hand, in the process of forming the TFT substrate 51, each process described below is performed.

  First, as shown in FIG. 2, a semiconductor layer 12 is formed by patterning a silicon film formed on a glass substrate 11 with a thickness of about 50 nm into an island shape by photolithography. Next, the gate insulating film 13 is formed on the glass substrate 11 and the semiconductor layer 12 to a thickness of about 60 nm by CVD or the like. Thereafter, the gate electrode 14 is formed by photolithography so that a part thereof overlaps the semiconductor layer 12.

Next, as shown in FIG. 3, a planarizing film 15 as an interlayer insulating film is formed so as to cover the gate electrode 14 and the gate insulating film 13. The planarizing film 15 is formed to a thickness of about 800 to 1000 nm so that the lower step can be planarized. That is, as the planarizing film 15, a liquid material in which silica (SiO ₂ ) is dissolved in a solvent is spin-coated on the gate insulating film 13, and then pre-baked at a temperature of about 150 ° C. to volatilize the solvent.

  Subsequently, as shown in FIG. 4, a barrier layer 16 is laminated on the surface of the planarizing film 15. The barrier layer 16 is composed of a lower antireflection coating (BARC), that is, the BARC 16 made of an organic film or the like is applied to the surface of the pre-baked planarizing film 15 with a thickness of 100 nm. Then, in order to volatilize the solvent contained in BARC16, it prebakes at the temperature of about 100 degreeC. Thereafter, the SOG 15 that is the planarizing film 15 and the BARC 16 that is the barrier layer 16 are heated at about 350 ° C. for 1 hour, and are simultaneously fired to be fully cured.

  Next, as shown in FIG. 1, a resist layer 20 is formed on the surface of the barrier layer 16. Next, the resist layer 20 is irradiated with exposure light 21 to expose the resist layer 20, thereby forming an opening 22 and a mask as shown in FIG. At this time, the exposure light 21 reaching the lower surface side of the resist layer 20 is absorbed by the barrier layer 16 made of BARC, and reflection thereof is prevented.

Thereafter, as shown in FIG. 5, the barrier layer 16, the planarization film 15, and the gate insulating film 13 are etched through the opening 22 of the mask. As the etching, dry etching using CF ₄ gas is performed. Thus, contact holes 23 are formed in the semiconductor layer 12 at positions above the source region and the drain region, respectively.

  Next, the resist layer 20 as a mask is removed from the etched barrier layer 16 by an ashing process and an organic chemical solution. Ashing is performed by irradiating oxygen plasma. Subsequently, the barrier layer 16 from which the resist layer 20 has been removed is removed from the surface of the planarizing film 15 by dry etching.

  Thereafter, as shown in FIG. 6, a metal film is formed on the surface of the planarizing film 15 from which the resist layer 20 and the barrier layer 16 have been removed and inside the contact hole 23, and the metal film is patterned by photolithography. As a result, the electrode portion 24 that is electrically connected to the source region or the drain region of the semiconductor layer 12 is formed.

  As described above, the TFT 30 having the planarization structure 10 and the liquid crystal display device 1 including the TFT 30 are manufactured.

-Effect of Embodiment 1-
Therefore, according to the first embodiment, the barrier layer 16 composed of the lower antireflection film (BARC) is laminated on the surface of the planarizing film 15, so that the resistance of the barrier layer 16 to oxygen plasma is increased. Can do. That is, it is possible to increase the resistance of the planarization structure 10 to ashing. As a result, since the flatness of the planarizing film 15 can be maintained well, a thin film pattern such as the electrode portion 24 formed on the surface can be formed with high accuracy. In addition, it is not necessary to separately form a new flattening film by CVD or the like for the purpose of maintaining flatness, so that the number of steps can be reduced while maintaining flatness.

  Further, since the barrier layer 16 is composed of the BARC, when the resist layer 20 is exposed, the exposure light 21 is absorbed by the barrier layer 16 on the lower surface side of the resist layer 20, and the exposure light 21 is multiplexed in the resist layer 20. Generation of standing waves due to interference can be prevented. Therefore, as a result of improving the exposure accuracy of the resist layer 20, the etching accuracy of the planarizing film 15 can also be improved. Thus, the planarization structure 10 and the liquid crystal display device 1 having the same can be formed with high accuracy while reducing the cost, and the reliability of the entire device can be improved.

<< Other Embodiments >>
In the first embodiment, the example of the planarization structure and the display device in which the barrier layer 16 is removed from the surface of the planarization film 15 has been described. However, the present invention is not limited to this, and the barrier layer is formed on the surface of the planarization film 15. 16 may be left without being removed. That is, in this case, the electrode portion 24 is formed on the surface of the barrier layer 16. From the viewpoint of reducing the number of steps, it is preferable to leave the planarization film 15.

  In the first embodiment, the planarization structure 10 included in the TFT 30 has been described. However, the present invention is not limited to this, and planarization in other elements including a planarization film that covers the uneven shape and planarizes. The same applies to the structure.

  In the first embodiment, the liquid crystal display device 1 has been described as an example. However, the present invention is not limited to this, and the same applies to other display devices having the above planarization structure such as an organic EL display device. Applicable to.

  As described above, the present invention is useful for a method for manufacturing a flattened structure and a method for manufacturing a display device. In particular, the exposure accuracy of the resist layer is made as high as possible while increasing resistance to ashing of the flattened structure. It is suitable for the case where it increases.

FIG. 1 is a cross-sectional view showing a resist layer and a barrier layer to be exposed. FIG. 2 is a cross-sectional view showing a semiconductor layer and a gate electrode formed on the substrate. FIG. 3 is a cross-sectional view showing a planarization film covering the gate electrode. FIG. 4 is a cross-sectional view showing the barrier layer formed on the surface of the planarizing film. FIG. 5 is a cross-sectional view showing a planarizing film and a mask in which contact holes are formed. FIG. 6 is a cross-sectional view showing a TFT having a planarization structure according to the first embodiment. FIG. 7 is a cross-sectional view showing a schematic structure of the liquid crystal display device. FIG. 8 is a cross-sectional view showing a conventional planarization structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Flattening structure 11 Glass substrate (board | substrate)
12 Semiconductor layer 13 Gate insulating film 14 Gate electrode 15 Planarizing film, SOG
16 Barrier layer, BARC
20 resist layer 21 exposure light 22 opening 23 contact hole 24 electrode 30 TFT
51 TFT substrate (first substrate)
52 Counter substrate (second substrate)
53 Liquid crystal layer (display medium layer)
54 Sealing material

Claims (8)

A method of manufacturing a planarization structure including a planarization film formed on a substrate and planarizing unevenness on the substrate,
Laminating a barrier layer on the surface of the planarization film formed on the substrate;
Forming a resist layer on the surface of the barrier layer;
Forming a mask by exposing the resist layer to form an opening in the resist layer; and
Etching the barrier layer and the planarizing film through the opening of the mask;
Removing the mask from the etched barrier layer by ashing,
The method for producing a flattened structure, wherein the barrier layer is composed of a lower antireflection film. In the manufacturing method of the planarization structure described in Claim 1,
The method for manufacturing a planarization structure, wherein the planarization film is made of SOG. In the manufacturing method of the planarization structure described in Claim 1,
The method for producing a flattened structure, wherein the flattened film is composed of a polymer film. In the manufacturing method of the planarization structure described in Claim 1,
Before the formation of the resist layer, the planarization film and the barrier layer are simultaneously fired to be fully cured. A method for manufacturing a display device, comprising: a step of forming a first substrate; a step of forming a second substrate; and a step of bonding the first substrate and the second substrate through a display medium layer,
The first substrate includes a semiconductor layer formed on the substrate, and a planarization film that is formed on the substrate so as to cover the semiconductor layer and planarizes unevenness on the substrate,
The step of forming the first substrate includes a step of laminating a barrier layer on the surface of the planarizing film formed on the substrate, a step of forming a resist layer on the surface of the barrier layer, and the resist layer Are exposed to form an opening in the resist layer, a step of forming a mask, a step of etching the barrier layer and the planarizing film through the opening of the mask, and the etched barrier Removing the mask from the layer by ashing,
The method for manufacturing a display device, wherein the barrier layer is formed of a lower antireflection film. In the manufacturing method of the display device according to claim 5,
The method for manufacturing a display device, wherein the planarizing film is made of SOG. In the manufacturing method of the display device according to claim 5,
The method for manufacturing a display device, wherein the planarizing film is made of a polymer film. In the manufacturing method of the display device according to claim 5,
A method of manufacturing a display device, wherein the planarizing film and the barrier layer are simultaneously fired and fully cured before forming the resist layer.

Images