JP2009111533A - Solid-state imaging device, electronic information apparatus, test device, and test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To match linearity of a photoelectric conversion characteristic among a plurality of pixels shared by one pixel circuit, and to reproduce a clear image without having color collapse by improving the linearity of the photoelectric conversion characteristic, in a solid-state imaging device. <P>SOLUTION: The solid-state imaging device includes: signal line drive transistors Ct connected between a power step-up line supplying a power step-up level obtained by stepping up a power voltage and respective vertical signal lines, and driving the vertical signal lines; and a step-up control circuit 110 controlling gate voltages of the signal line drive transistors Ct to make a step-up level of an FD part in transferring signal charge from pixels in an even row coincide with that in reading the signal charge from pixels in an odd row. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, an electronic information device, a test device, and a test method, and in particular, a solid-state imaging device such as a CMOS image sensor used in an electronic imaging device such as a video camera, a digital camera, and a mobile phone camera, The present invention also relates to an electronic information device using such a solid-state imaging device, and a test apparatus and a test method for testing the solid-state imaging device.

  In general, a CMOS image sensor includes a plurality of pixels arranged two-dimensionally, and a vertical signal line arranged for each pixel column for reading out signal charges from each pixel of each pixel column, and a charge storage unit The signal charges from the pixels accumulated in the (floating diffusion portion) are amplified and read out to the vertical signal line.

  In such a conventional image sensor, the potential between the vertical signal line in the pixel region and the floating diffusion portion (hereinafter also referred to as the FD portion) is used to boost the potential of the FD portion, and the photoelectric conversion characteristics are increased. Attempts have been made to improve image quality by expanding linearity (see Patent Document 1).

  When the image quality of the created CMOS image sensor was evaluated for the CMOS image sensor having such a circuit configuration, a slightly dark picture with a collapsed color was observed.

  FIG. 8 shows the results of measuring the photoelectric conversion characteristics of each pixel for such a CMOS image sensor.

  Here, in the CMOS image sensor, a pixel circuit forming a pixel shares two pixels.

  Specifically, a first pixel column in which red pixels and green pixels are alternately arranged in the column direction, and a second pixel column in which green pixels and blue pixels are alternately arranged in the column direction are: Alternatingly arranged in the row direction. Here, the red pixel (R pixel) in the first pixel column is adjacent to the green pixel (Gr pixel) in the second pixel column, and the green pixel (Gb pixel) in the first pixel column is the second pixel column. Adjacent to the blue pixel (B pixel). Further, in this CMOS image sensor, the pixel circuit forming the pixel has a circuit configuration in which two pixels are shared, and in the first pixel column, the adjacent even-numbered R pixel and odd-numbered Gb pixel are one pixel circuit. In the second pixel column, adjacent even-numbered Gr pixels and odd-numbered B pixels are shared by the pixel circuits.

  In FIG. 8, the shutter speed or illuminance corresponding to the signal charge amount generated in the pixel is taken in the horizontal axis direction, and the pixel signal (pixel output) output from the pixel is taken in the vertical axis. It is shown.

  The graph L0 shows the characteristics of even-numbered Gr pixels or R pixels (hereinafter referred to as Gr / R pixels), and the graph L1 represents odd-numbered B pixels or Gb pixels (hereinafter referred to as Gb / B pixels). The characteristics are shown.

  As can be seen from the graphs L0 and L1, the inflection point X0 of the Gr / R pixel (even number row) occurs when the photoelectric conversion amount in the pixel is smaller than the inflection point X1 of the Gb / B pixel (odd number row). Due to such a deviation in the linearity of the photoelectric conversion characteristics, the displayed image becomes a dark image with a collapsed color.

  Hereinafter, the conventional CMOS image sensor will be described in more detail.

  FIG. 9 shows a two-pixel shared pixel circuit constituting the CMOS image sensor.

  Here, the pixel circuit sharing two pixels includes two photodiodes PD0 and PD1 that convert light into electrons, two transfer transistors Tt0 and Tt1 that transfer signal charges generated by the photodiodes to the FD section, An amplification transistor SFt for amplifying the signal charge transferred to the FD section and generating a corresponding signal voltage on the vertical signal line Vsig, and resetting the FD section, that is, the gate of the amplification transistor SFt to a reset voltage VR 1 And two reset transistors Rt.

  The gate of the transfer transistor Tt0 is connected to the signal line of the transfer signal (Tx0 signal), and the gate of the transfer transistor Tt1 is connected to the signal line of the transfer signal (Tx1 signal). The reset transistor Rt is connected between a voltage line for supplying a reset voltage VR and the FD unit, and a reset signal VRESET is applied to the gate of the reset transistor Rt. The vertical signal line Vsig is provided for each pixel column. One end of the amplification transistor SFt of the pixel circuit in each pixel column is connected to the corresponding vertical signal line Vsig, and the other end supplies a pixel drain voltage. Connected to the transistor St.

  In the CMOS image sensor having such a configuration, the coupling capacitor C0 between the Tx0 signal signal line of the even-numbered Gr / R pixel and the FD portion, the signal line of the Tx1 signal of the odd-numbered Gb / B pixel, and the FD Comparing the coupling capacitance C1 with the part, it has been found that the coupling capacitance C1 is extremely larger than the coupling capacitance C0.

  Hereinafter, a pixel signal reading operation will be described with reference to a timing chart shown in FIG.

FIG. 10 shows the relationship between the transfer gate control signal (Tx0 signal, Tx1 signal) and the FD level V _FD when the signal charge is read from the Gr / R pixel (even number row) (FIG. 10A). This is shown in comparison with the signal charge readout from the B pixel (odd row) (FIG. (B)).

  The φr signal becomes L level, the transistor St connected to one end of the amplification transistor SFt is turned on, and the potential of the FD portion is supplied to the gate of the amplification transistor SFt. Then, the gate potential is amplified by the amplification transistor SFt, and the power supply level is supplied to the drain thereof.

  In this state, that is, in the tA period, the reset voltage VR is amplified by the amplification transistor SFt by the reset operation and supplied to the vertical signal line Vsig. In this tA period, the FD level (the potential level of the FD portion) is boosted to the Vsig boost by the capacitor C2 between the vertical signal line Vsig and the FD portion.

At this time, when reading out the signal charges accumulated in the photodiodes PD0 in the even-numbered rows, the transfer gate signal Tx0 is set to the H level (tB period), and the signal charges are read out to the FD portion. In this case, because capacitance C0 between the signal line and the FD portion of the Tx0 signal is small, a small (boosted level of the FD portion) Tx boost level by C0 capacitance, boost level _{V FD} of the FD section, the odd row access It becomes lower than the boosted level of the FD section at that time (FIG. 10A).

Next, when reading the charges accumulated in the photodiodes PD1 in the odd rows, the transfer gate signal Tx1 is set to the H level (period tB), and the signal charges are read to the FD. In this case, the larger the capacitance C1 between the signal line and the FD portion of the Tx1 signal is large (step-up level of the FD portion) Tx boost level by capacitor C1, boosting the level _{V FD} of the FD section, the even-numbered row access It becomes higher than the boost level V _FD of the FD section at that time (FIG. 10B).

  FIG. 11 shows the potential distribution in the path from the photodiode PD to the FD part. FIG. 11A shows the Gr / R pixels (even rows) before reading (tA period) and before reading (tB (Period) shows the change of the potential distribution, and FIG. 11B shows the change of the potential distribution before reading (tA period) and before reading (tB period) for the Gb / B pixel (odd row). Show.

  As shown in FIG. 11A, in the Gr / R pixel (even-numbered row) P0 having a small Tx capacitance C0 that is the gate capacitance of the transfer transistor Tt0, the FD generated by the coupling by the capacitance C0 when the Tx0 signal line is boosted. The boosting of the potential of the part is small, and distributed charge Dc is generated. That is, a part of the signal charge generated by the photoelectric conversion remains as the distributed charge Dc in the photodiode PD. When such distributed charge Dc remains, an afterimage is generated on the display screen, and the image quality is greatly deteriorated. Further, since the signal charge is not accumulated in the FD portion to a level proportional to the illuminance, that is, there is no linearity of the photoelectric conversion characteristic, and a dark image is displayed at the bright time (high illuminance).

On the other hand, as shown in FIG. 11B, in the Gb / B pixel (odd row) P1 having a large Tx capacitance C1 which is the gate capacitance of the transfer transistor Tt1, it is generated by coupling by the capacitance C1 when the Tx1 signal line is boosted. The potential of the FD portion to be boosted is large and no distributed charge (afterimage) is generated. Therefore, in the Gb / B pixel (odd row) P1, no afterimage is generated, the linearity of the photoelectric characteristics is ensured, and a clear image quality without color collapse is reproduced.
JP 2007-124344 A

  As described above, in the conventional CMOS image sensor, the problem that the displayed image becomes a dark image with a collapsed color is that the capacitance (Tx) between the gate of the transfer transistor and the FD portion in the even and odd rows. (Capacity between FDs) is different, and this is a problem caused by the small capacity. Therefore, it is first to attempt to match the capacitance values by means of layout.

  However, in the pixel layout, the aperture ratio that greatly affects the sensitivity is improved (the window area with respect to the pixel area, that is, the light capturing area is increased), and the aperture position common to each pixel effective for crosstalk and shading is shared. Give priority to conversion.

  Therefore, at present, it is difficult to match the Tx-FD capacitances in each row depending on the pixel layout.

  As a result, as shown in the prior art, the boost level of the FD section is increased, distribution charges are prevented, afterimage generation is suppressed and the linearity of the photoelectric characteristics is improved, and a clear image without color collapse is reproduced. There is a need to.

  The present invention has been made in order to solve the above-described conventional problems, and can control the potential level of the FD portion when the signal charge is transferred from the pixel to the FD portion, so that it can be shared by one pixel circuit. Solid-state imaging device capable of matching linearity of photoelectric conversion characteristics among a plurality of pixels, electronic information equipment using the solid-state imaging device, and test apparatus and test method for testing the solid-state imaging device The purpose is to obtain.

  A solid-state imaging device according to the present invention includes a plurality of pixels arranged two-dimensionally and a vertical signal line arranged for each pixel column and for reading out signal charges from each pixel of each pixel column. A transfer transistor corresponding to each pixel, wherein the pixel circuit forming the pixel shares a plurality of pixels arranged in the pixel column direction and transfers the signal charge from each pixel to a charge storage unit. And a potential level of the charge storage portion when driving a transfer transistor corresponding to each pixel row includes a coupling capacitance between the gate of the transfer transistor and the charge storage portion, and A boosting control circuit that controls the boosted potential of the vertical signal line so as to be the same level between the pixel rows by the coupling capacity between the vertical signal line and the charge storage unit is provided. the above Target is achieved.

  According to the present invention, in the solid-state imaging device, the pixel circuit is an N pixel sharing circuit that shares N pixels (N is a natural number), and the pixel circuit photoelectrically converts incident light. A conversion element; one charge storage unit that stores the signal charge obtained by the photoelectric conversion; N transfer transistors that transfer the signal charge from the photoelectric conversion elements to the charge storage unit; It is preferable to have one amplification transistor that is connected to the vertical signal line, has a gate connected to the charge storage unit, and amplifies the potential of the charge storage unit and reads it out to the vertical signal line.

  According to the present invention, in the solid-state imaging device, the boost control circuit is connected to a boosted voltage obtained by boosting a power supply voltage, and transfers a signal line drive transistor that drives the vertical signal line to the charge storage unit. A gate voltage control circuit that controls the gate voltage of the signal line driving transistor according to which pixel row in the pixel circuit corresponds to the selected pixel row. preferable.

  According to the present invention, in the solid-state imaging device, the pixel circuit is a two-pixel sharing circuit that shares two pixels arranged in a column direction, and the boost control circuit receives signal charges from pixels in even rows. When transferring the signal charge so that the potential of the charge storage unit when transferring to the signal charge and the potential of the charge storage unit when transferring the signal charge from the odd-numbered pixels to the signal charge storage unit are equal to each other In addition, it is preferable to control the boost level of the vertical signal line.

  The present invention provides the solid-state imaging device, wherein the boost control circuit includes a row determination unit that determines whether the selected pixel row is an even row or an odd row based on a row address, It is preferable that the gate voltage of the signal line driving transistor is controlled based on the determination result.

  According to the present invention, in the solid-state imaging device, the boost control circuit selects a gate voltage of the signal line driving transistor to be set when the even row is selected and the odd row by an external signal. And determining the gate voltage of the signal line driving transistor to be set, and having a setting circuit for storing the determined gate voltage, based on the determination result, the gate voltage of the signal line driving transistor, The gate voltage determined by the setting circuit is preferably controlled.

  In the solid-state imaging device according to the present invention, the pixel circuit is a four-pixel sharing circuit that shares the first to fourth pixels arranged in a column direction, and the boost control circuit includes the first to fourth pixels. The step-up level of the vertical signal line is controlled when transferring the signal charge so that the potential of the charge storage unit when the signal charge is transferred from the pixel to the charge storage unit becomes the same potential. Is preferred.

  In the solid-state imaging device according to the aspect of the invention, the boost control circuit may be configured such that the selected pixel row corresponds to any one of the first to fourth pixels shared by the pixel circuit based on a row address. It is preferable to have a row determination unit that determines whether the signal line is in the range, and to control the gate voltage of the signal line driving transistor based on the determination result.

  According to the present invention, in the solid-state imaging device, the boost setting circuit should be set when a pixel row corresponding to each of the first to fourth pixels is selected by an external signal. A setting circuit for determining the gate voltage of each of the signal line and storing the determined gate voltage, and based on the determination result, the gate voltage of the signal line driving transistor is set to the gate voltage set by the setting circuit. It is preferable to control.

  An electronic information device according to the present invention is an electronic information device including an imaging unit, and the imaging unit includes the solid-state imaging device, thereby achieving the object.

  A test apparatus according to the present invention is a test apparatus for testing the solid-state imaging device, and sets the boost level of the charge storage unit when the transfer transistor is driven for each pixel in the pixel circuit of the solid-state imaging device. A determination unit configured to detect and determine a relative difference in the boost level of the charge storage unit between the pixels in the pixel circuit, the determination unit in the pixel circuit based on the determination result For each pixel, a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven is output to the boost control circuit of the solid-state imaging device, thereby achieving the above object. .

  According to the present invention, in the test apparatus, the pixel circuit of the solid-state imaging device is a two-pixel sharing circuit that shares two pixels, and the determination unit drives the transfer transistors corresponding to pixels in even rows. A boost level difference between the boost level of the charge storage unit and the boost level of the charge storage unit when the transfer transistors corresponding to the pixels in the odd-numbered rows are driven is determined, and each pixel in the pixel circuit is determined based on the determination result. For each pixel, it is preferable to output a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven to the boost control circuit of the solid-state imaging device.

  According to the present invention, in the test apparatus, the pixel circuit of the solid-state imaging device is a four-pixel sharing circuit that shares four pixels, and the determination unit drives a transfer transistor corresponding to each pixel of the four-pixel sharing circuit. And determining a relative difference in the boost level of the charge storage unit corresponding to the four pixels based on the boost level of the charge storage unit at the time, and based on the determination result, for each pixel in the pixel circuit In addition, it is preferable that a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven is output to the boost control circuit of the solid-state imaging device.

  A test method according to the present invention is a test method for testing the solid-state imaging device, wherein the boost level of the charge storage unit when the transfer transistor is driven for each pixel in the pixel circuit of the solid-state imaging device. A determination step of detecting and determining a relative difference in the boost level of the charge storage unit between the pixels in the pixel circuit, and the transfer for each pixel in the pixel circuit based on the determination result An output step of outputting a signal indicating the potential level of the vertical signal line to be set when the transistor is driven to the boost control circuit of the solid-state imaging device, thereby achieving the above object.

  According to the present invention, in the test method, the pixel circuit of the solid-state imaging device is a two-pixel sharing circuit that shares two pixels, and in the determination step, the transfer transistor corresponding to pixels in even rows is driven. A boost level difference between the boost level of the charge storage unit and the boost level of the charge storage unit when driving the transfer transistors corresponding to the pixels in the odd-numbered rows is determined, and in the output step, based on the determination result, For each pixel in the pixel circuit, it is preferable to output a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven to the boost control circuit of the solid-state imaging device.

  According to the present invention, in the test method, the pixel circuit of the solid-state imaging device is a four-pixel sharing circuit that shares four pixels. In the determination step, a transfer transistor corresponding to each pixel of the four-pixel sharing circuit is driven. And determining a relative difference in the boost level of the charge storage unit corresponding to the four pixels based on the boost level of the charge storage unit at the time, and in the output step, based on the determination result, the pixel It is preferable that a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven is output to the boost control circuit of the solid-state imaging device for each pixel in the circuit.

  Hereinafter, the operation of the present invention will be described.

  According to the solid-state imaging device according to the present invention, the potential level of the vertical signal line is controlled for each pixel row so that the potential level of the FD portion increases when the signal charge is transferred to the FD portion. The linearity of photoelectric conversion characteristics can be matched between a plurality of pixels shared by a circuit.

  Specifically, the linearity of the photoelectric conversion characteristics can be expanded by changing the Vsig boost level in the odd and even rows and boosting and matching the FD level at the time of reading the pixel data. This makes it possible to display a clear image with no color collapse at the bright time (high brightness).

  As a result, by improving the linearity of the photoelectric conversion characteristics, a clear image without color collapse can be reproduced.

  Moreover, in an electronic information device using such a solid-state imaging device as an imaging unit, a clear image without color collapse is recorded on a recording medium, displayed on a display screen, printed out, and further transmitted. You can do it.

  In addition, according to the test apparatus or test method of the present invention, the solid-state imaging device is tested before the LSI test to measure variations in photoelectric conversion characteristics among a plurality of pixels shared by one pixel circuit. Then, based on the measurement result, the potential level of the vertical signal line at the time of transfer to the FD portion of the signal pixel is changed so that the photoelectric conversion characteristics match among a plurality of pixels shared by the pixel circuit Therefore, the solid-state imaging device can be adjusted to one that can reproduce a clear image without color crushing by improving the linearity of photoelectric conversion characteristics.

  As described above, according to the present invention, it is possible to control the potential level of the FD unit when the signal charge is transferred from the pixel to the FD unit, and thereby, among a plurality of pixels shared by one pixel circuit. In addition, it is possible to obtain a solid-state imaging device capable of matching the linearity of photoelectric conversion characteristics, an electronic information device using the solid-state imaging device, and a test device and a test method for testing the solid-state imaging device.

  Hereinafter, embodiments of the present invention will be described.

(Embodiment 1)
FIG. 1 is a block diagram illustrating a solid-state imaging device according to Embodiment 1 of the present invention.

  A solid-state imaging device 100 according to the first embodiment illustrated in FIG. 1 is arranged for each pixel column and a plurality of pixels P arranged two-dimensionally in the pixel region 101, and reads out signal charges from each pixel in each pixel column. Vertical signal lines Vsig0 to Vsign.

  Here, the pixel circuit forming the pixel has the same circuit configuration as that of the two-pixel sharing described with reference to FIG. 9 will be briefly described below. Also in the first embodiment, the pixel circuit sharing two pixels includes two photodiodes PD0 and PD1 that convert light into electrons, and signal charges generated by the photodiodes. Transfer transistors Tt0 and Tt1 for transferring the signal charges to the FD section, an amplification transistor SFt for amplifying the signal charge transferred to the FD section and generating a corresponding signal voltage on the vertical signal line Vsig, and the FD section That is, it has one reset transistor Rt that resets the gate of the amplification transistor SFt to the reset voltage VR. Other configurations in the pixel circuit are the same as those in the conventional CMOS image sensor shown in FIG.

  The solid-state imaging device 100 also includes a vertical shift register 103 that selects a pixel row in the pixel column, a selection circuit 104 that selects each of the vertical signal lines Vsig0 to Vn, and a pixel signal of the selected vertical signal line. The output circuit 105 amplifies and outputs, and the row address decoder 102 which decodes the row address signal Sh and supplies it to the vertical shift register 103.

  Furthermore, the solid-state imaging device 100 according to the first embodiment includes a power supply boosting line that supplies a power supply boosting level obtained by boosting a power supply voltage, and a Vsig signal control transistor Ct connected between the vertical signal lines, and the control transistor. A boost control circuit 110 that controls the gate voltage of Ct so that the boost level of the FD portion is the same when the signal charge is transferred from the even-numbered row pixels and when the signal charge is read from the odd-numbered row pixels; is doing.

  FIG. 2A is a diagram showing a specific circuit configuration of the boost control circuit 110.

  The boost control circuit 110 includes a resistor 115 and a load transistor Lt connected in series between a power boosting line 111a that supplies a power boosting level obtained by boosting a power supply voltage and a ground line. Here, the resistor 115 has 16 connection nodes N1 to N16 provided at regular intervals between both ends thereof, and the highest voltage is generated at the node N16. A voltage obtained by sequentially subtracting a certain voltage drop from a voltage generated at the node N16 is generated at each of N15 to N1.

  Further, the boost control circuit 110 controls a plurality of setting transistors T0F to T01 connected between the gate of the Vsig signal control transistor Ct and the nodes N16 to N1, and on / off control of the setting transistors T0F to T01. The row control circuit 112 to be performed, and when the row control circuit 112 selects an odd-numbered row or an even-numbered row based on address information from the row address decoder 102, which of the setting transistors is to be turned on from the outside And a setting circuit 113 for setting based on the setting signal.

  Here, the power boosting line 111a may be the same as the power boosting line 111b to which the Vsig signal control transistor is connected.

  As described above, the solid-state imaging device 100 according to the first embodiment realizes a circuit configuration in which the FD boost level by the vertical signal line Vsig is changed between selection of an even-numbered row and selection of an odd-numbered row. Therefore, the even-numbered pixel row is selected so that the potential level of the FD portion is equal in the transfer period in which the signal charge is transferred from each pixel, when the even-numbered row is selected and when the odd-numbered row is selected. When the selection transistor that is turned on when the odd pixel row is selected and the selection transistor that is turned on when the odd-numbered pixel row is selected are set by the setting circuit 113, the two transistors shared by one pixel circuit are shared. The linearity of photoelectric characteristics can be matched.

  Next, the function and effect will be described with reference to FIGS.

  FIG. 3A is a diagram illustrating a test process and a characteristic correction process performed before the LSI test, and FIG. 3B is a diagram illustrating an operation flow of the device whose characteristics are corrected, that is, a solid-state imaging device. .

  First, the test process and characteristic correction process of the solid-state imaging device 100 according to the first embodiment are performed using the test device 120 shown in FIGS. 1 and 2B.

  The test apparatus 120 includes a drive unit 121 that drives the solid-state imaging device, a determination unit 122 that determines characteristics of the solid-state imaging device, and a test control unit 123 that controls the drive unit and the determination unit during a test. .

  For example, in the solid-state imaging device 100, as shown in FIG. 8, both the Gr / R pixels (even rows) and the Gb / B pixels (odd rows) have high illuminance (in FIG. In this state, the test apparatus 120 supplies a control signal so that the imaging operation is performed. For example, the control signal Vcont is a signal that operates the vertical shift register 103, and the control signal Hcont is a control signal that operates the selection circuit 104. At this time, the setting circuit 113 of the boost control circuit 110 is set to a default setting.

  When the solid-state imaging device 100 operates in accordance with a control signal from the test device 120, the vertical shift register 103 reads signal charges generated in each pixel as signal voltages for each pixel row to the corresponding vertical signal lines Vsig0 to Vsign. . When the selection circuit 104 selects the vertical signal line, the pixel signal Ps from each pixel is output to the output circuit 105. The output circuit 105 amplifies the input signal voltage and outputs it to the test apparatus 120 as pixel data Dout.

  Then, in the test apparatus 120, based on the output signal (pixel output) Dout supplied from the output circuit 105 of the solid-state imaging apparatus 100 and the illuminance irradiated on the solid-state imaging apparatus 100, Gr / R pixels (even numbers) Row) and Gb / B pixels (odd row) are examined for photoelectric conversion characteristics (step S1). Such inspection is performed for each production lot or wafer.

  Next, the test apparatus 120 recognizes a difference in photoelectric conversion characteristics between the Gr / R pixels (even rows) and the Gb / B pixels (odd rows) (step S2). Specifically, based on the difference ΔDout between the pixel output from the Gr / R pixel (even row) at the illuminance Sm and the pixel output from the Gb / B pixel (odd row), the Gr / R pixel (even row) ) And the Tx boost level of the Gb / B pixel (odd row) are detected. Here, when the gate signal Tx of the transfer transistor is set to the high level, the Tx boost level is determined by the coupling capacitance between the gate and the FD portion and the coupling capacitance between the FD portion and the vertical signal line. This is the level at which the potential of the part is boosted.

  Specifically, as shown in FIG. 4B, in the Gr / R pixels in even rows, the Tx boost level Vc0 is small because the Tx-FD capacitance C0 is small. In this case, the Vsig boost level Vsig0 by the Vsig signal is increased, and the FD level is increased by the subsequent Tx boost. On the other hand, as shown in FIG. 4A, in the Gb / B pixels in the odd-numbered rows, the Tx boost level Vc1 becomes large because the Tx-FD capacitance C1 is large. In this case, the Vsig boost level Vsig1 based on the Vsig signal is made smaller than the Vsig boost level Vsig0 of the even-numbered row, and the FD level is increased by the subsequent Tx boost.

  Further, the Vsig level can be changed by controlling the gate level of the drive transistor of the vertical signal line Vsig as shown in Step S3 below.

  That is, the test apparatus 120 sets the Tx boost level when the signal charge is transferred from the Gr / R pixels in the even-numbered rows with poor photoelectric conversion characteristics to the FD portion based on the difference in photoelectric conversion characteristics, and is an odd number with good photoelectric conversion characteristics. The boost level of the vertical signal line Vsig at the time of transfer of the signal charge is obtained to match the Tx boost level when the signal charge is transferred from the Gb / B pixel in the row to the FD portion. Then, a setting signal is output to the setting circuit 113, and the register value in the row control circuit 112 is changed so that the boosted level of the vertical signal line Vsig becomes the above-described level when the signal charge is transferred (step S3). ). The setting circuit 113 holds the setting based on the setting signal, and after setting, the solid-state imaging device operates in the setting state held in the setting circuit 113.

  In this way, by setting the Tx boost level when selecting even and odd rows to the same level Lco, the distribution charge (afterimage) is suppressed, that is, the bending point X0 of the photoelectric conversion characteristics of the Gr / B pixel is increased, and Increase the linearity of photoelectric conversion characteristics. Note that the Tx boost level when selecting even and odd rows may be increased and set to the same level. FIG. 5 shows a state in which the photoelectric conversion characteristics of the Gr / R pixels (even number rows) and the photoelectric conversion characteristics of the Gb / B pixels (odd number rows) coincide with each other.

  Thereafter, the test apparatus 120 operates the solid-state imaging device in the same manner as in step S1, and confirms the improvement in photoelectric conversion characteristics (step S4).

  Next, an actual operation of the solid-state imaging device whose characteristics are corrected as described above will be described.

  In actual operation, in the solid-state imaging device 100, reading of the signal charge from the pixel is performed by a control signal from a control circuit (not shown) arranged around the pixel region, not the test device.

  That is, when the row address signal Sh is input to the row address decoder 102, the row address signal is decoded by the decoder 102 and input to the vertical shift register 103. Then, the vertical shift register 103 sequentially sets the transfer gate signals Tx0 to Txn to the H level at a predetermined timing according to the address information. Then, the signal voltage corresponding to the signal charge is read from the pixels in each pixel row to the corresponding vertical signal lines Vsig0 to Vsign. The signal voltage read out from each pixel in one pixel row to the corresponding vertical signal line is sequentially output via the selection circuit 104 until the signal voltage is read out from the next pixel row. Is output.

  In a state where such signal charges are being read, the row address decoder determines whether the pixel row selected by the vertical register is an odd row or an even row (step S11).

  In the row control circuit 112 in the booster circuit 110, the setting circuit sets the row address according to the determination result determined by the row address decoder, that is, depending on whether the row address specifies an even row or an odd row. Register setting values are assigned to even and odd rows. That is, when the register value “0E” H is set for the even-numbered row and the register value “OC” H is set for the odd-numbered row by the setting circuit, the row address indicates the even-numbered row. The register value “0E” H is output, and when the row address indicates an odd-numbered row, the register value “OC” H is output (step S12).

  Thereby, in the boost control circuit 110, the transistor T0E is turned on when the signal charge is transferred from the Gr / R pixel (even row), and the transistor T0C is turned on when the signal charge is transferred from the Gb / B pixel (odd row). The potential of the vertical signal line Vsig is higher when the signal charge is transferred from the Gr / R pixel (even row) than when the signal charge is transferred from the Gb / B pixel (odd row). The voltage is boosted to the boost level (step S13). As a result, the Tx boost level boosted by the coupling capacitor C2 between the vertical signal line Vsig and the FD portion, that is, the boost level during charge transfer in the FD portion is the same as that when the Gr / R pixel (even row) is selected. The Gb / B pixels (odd rows) are almost the same when selected (step S14).

  Hereinafter, a method for setting a register value in step S3 will be specifically described.

  For example, when the register value is 0CH, the VFD level is 3.09V, and when the register value is 0EH, the VFD level is 3.34V.

  However, these VFD level values are extracted from the digital output values output from the column AD (selection circuit) 104 shown in FIG. 1 in the test process shown in FIG.

  Next, when the Tx signal is at the H level, the Tx boost level at which the potential of the FD portion is boosted is extracted from the output of the column AD, that is, the signal voltage from the output circuit, for odd and even rows. For example, if the Tx boost level of the odd-numbered row is 0.28V and the Tx boost level of the even-numbered row is 0.50V, the Tx boost level difference between the odd-numbered row and the even-numbered row is 0.22V.

  Therefore, at the time of reading a signal, the boost level of the FD portion is increased, the boost level of the FD portion is matched between the even-numbered row and the odd-numbered row, and charge distribution (afterimage) is eliminated. Improvements can be made.

  For example, at the Vsig level control register setting value 0EH, the boosting level of the odd-numbered FD section is 3.34V + 0.28V = 3.62V, and at the Vsig level control register setting value 0CH, the boosting level of the even-numbered FD section. The level is 3.09V + 0.50V = 3.59V, and they are almost the same.

  As described above, according to the solid-state imaging device according to the first embodiment, the potential level of the vertical signal line is controlled for each pixel row so that the potential level of the FD portion increases when the signal charge is transferred to the FD portion. The linearity of photoelectric conversion characteristics can be matched between a plurality of pixels shared by one pixel circuit. As a result, by improving the linearity of the photoelectric conversion characteristics, a clear image without color collapse can be reproduced.

In the first embodiment, the solid-state imaging device is shown in which the pixel circuit shares two pixels. However, the solid-state imaging device of the present invention is not limited to the one in which the pixel circuit shares two pixels. In principle, the present invention can be applied to a solid-state imaging device in which pixel circuits share N (N is a natural number). Hereinafter, a solid-state imaging device in which pixel circuits share four pixels will be described as a second embodiment.
(Embodiment 2)
6 and 7 are diagrams for explaining a solid-state imaging device according to Embodiment 2 of the present invention. FIG. 6 shows a pixel circuit sharing four pixels constituting the solid-state imaging device.

  The pixel circuit sharing four pixels shown in FIG. 6 includes four photodiodes PD1 to PD4 that convert light into electrons, and four transfer transistors Tt0 to Tt4 that transfer signal charges generated by the photodiodes to the FD section. The amplification transistor SFt that amplifies the signal charge transferred to the FD section and generates a signal voltage corresponding to the signal charge on the vertical signal line Vsig, and the gate of the FD section, that is, the amplification transistor SFt is reset to the reset voltage VR. One reset transistor Rt is provided.

  Other configurations of the solid-state imaging device of the second embodiment are the same as those in the solid-state imaging device 100 of the first embodiment described above.

  In the second embodiment, in the solid-state imaging device in which the test and the photoelectric conversion characteristic correction described in the first embodiment are not performed, the illuminance (or shutter speed) at which the linearity of the photoelectric conversion characteristic is impaired is a pixel circuit. Are different values among the pixels shared. That is, four pixels constituting the pixel circuit, that is, the first Gr / R pixel (even row), the first Gb / B pixel (odd row), the second Gr / R pixel (even row), the second The Gb / B pixels (odd rows) have different photoelectric conversion characteristics as indicated by graphs L0 to L3 in FIG.

  As described above, in a solid-state imaging device in which the pixel circuit is shared by four pixels, in a test before the LSI test, for example, the photoelectric conversion characteristic of the pixel having the best characteristics in the pixel circuit sharing the four pixels is changed to the other pixel. The setting circuit of the boost control circuit is set so that the photoelectric conversion characteristics match.

  In this case, the first Gr / R pixel (even row), the first Gb / B pixel (odd row), the second Gr / R pixel (even row), and the second Gb / B pixel (odd row) In this order, the coupling capacitances C00, C01, C02, C03 (C00 <C01 <C02 <C03) between the transfer gate and the FD portion are increased, so that when the charges are transferred from these pixels, the vertical signal line By setting the potential of Vsig as follows, the photoelectric conversion characteristics of these pixels can be made uniform.

  That is, the first Gr / R pixel (even row), the first Gb / B pixel (odd row), the second Gr / R pixel (even row), and the second Gb / B pixel (odd row). If the potential levels of the vertical signal lines during charge transfer from each pixel are V0, V1, V2, and V3, the potential level V0 is the inflection point X0 of the photoelectric conversion characteristics of the first Gr / R pixel (even number row). Is set to coincide with the inflection point X3 of the second Gb / B pixel (odd row) photoelectric conversion characteristic. The potential level V1 is set so that the inflection point X1 of the photoelectric conversion characteristic of the first Gb / B pixel (odd row) coincides with the inflection point X3 of the second Gb / B pixel (odd row) photoelectric conversion characteristic. To do. Further, the potential level V2 is such that the inflection point X2 of the photoelectric conversion characteristic of the first Gr / R pixel (even number row) coincides with the inflection point X3 of the second Gb / B pixel (odd number row) photoelectric conversion characteristic. Set.

  In other words, in the setting circuit, the register level is set so that the potential levels V0 to V3 of the vertical signal lines at the time of charge transfer from each pixel match the photoelectric conversion characteristics of each pixel in the pixel circuit sharing four pixels as described above. A set value is determined.

In the second embodiment having such a configuration, in the pixel circuit sharing four pixels, as in the first embodiment, each pixel row is set so that the potential level of the FD portion increases when the signal charge is transferred to the FD portion. In addition, since the potential level of the vertical signal line is controlled, the linearity of the photoelectric conversion characteristics can be matched between a plurality of pixels shared by one pixel circuit. As a result, it is possible to reproduce a clear image without color crushing by improving the linearity of the photoelectric conversion characteristics.
(Embodiment 3)
Although not particularly described in the first and second embodiments, a digital camera such as a digital video camera or a digital still camera using at least one of the solid-state imaging devices of the first and second embodiments as an imaging unit, An electronic information device having an image input device such as an image input camera, a scanner, a facsimile, a camera-equipped mobile phone device, and the like will be described. The electronic information device of the present invention performs data recording after performing predetermined signal processing for recording high-quality image data obtained by using at least one of the solid-state imaging devices of the first and second embodiments of the present invention as an imaging unit. A memory unit such as a recording medium, a display unit such as a liquid crystal display device that displays the image data on a display screen such as a liquid crystal display screen after performing predetermined signal processing for display, and the image data for communication At least one of communication means such as a transmission / reception device that performs communication processing after the signal processing and image output means for printing (printing) and outputting (printing out) the image data.

  In an electronic information device using such a solid-state imaging device as an imaging unit, a clear image without color collapse is recorded on a recording medium, displayed on a display screen, printed out, and further transmitted. can do.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device, an electronic information device using the solid-state imaging device, and a test device and a test method for testing the solid-state imaging device. By controlling the potential level of the vertical signal line so that the level increases, the linearity of the photoelectric conversion characteristics can be made to coincide between a plurality of pixels shared by one pixel circuit, thereby preventing color collapse. A clear image can be reproduced.

FIG. 1 is a block diagram illustrating a solid-state imaging device according to Embodiment 1 of the present invention. FIG. 2 is a diagram illustrating a specific circuit configuration (FIG. (A)) of the boost control circuit 110 in the solid-state imaging device of the first embodiment and a configuration of a test device (FIG. (B)) of the solid-state imaging device. is there. FIG. 3 is a diagram for explaining the operation of the first embodiment, and FIG. 3A is a diagram for explaining a test process and a characteristic correction process performed before the LSI test for the solid-state imaging device. FIG. 3B is a diagram for explaining the operation of the device whose characteristics are corrected, that is, the solid-state imaging device. FIG. 4 is a diagram showing a potential distribution in a path from the photodiode PD to the FD portion. The potential distribution during charge transfer in the Gb / B pixel (odd row) (FIG. 4A), and the Gr / R pixel. The potential distribution (figure (b)) at the time of charge transfer in (even numbered rows) is shown. FIG. 5 shows a state in which the photoelectric conversion characteristics of the Gr / R pixels (even rows) and the photoelectric conversion characteristics of the Gb / B pixels (odd rows) match in the solid-state imaging device of the first embodiment. FIG. FIG. 6 is a diagram for explaining a solid-state imaging device according to Embodiment 2 of the present invention, and shows a pixel circuit sharing four pixels constituting the solid-state imaging device. FIG. 7 is a diagram showing the photoelectric conversion characteristics of the solid-state imaging device of the second embodiment before and after correction (FIG. (A)) and after correction (FIG. (B)). FIG. 8 is a diagram showing the results of measuring the photoelectric conversion characteristics of each pixel for a conventional CMOS image sensor. FIG. 9 is a diagram showing a two-pixel shared pixel circuit constituting a conventional CMOS image sensor. FIG. 10 shows the relationship between the transfer gate control signal (Tx0 signal, Tx1 signal) and the FD level in a conventional CMOS image sensor when signal charges are read from Gr / R pixels (even rows) (FIG. 10A). ) And a time of reading out signal charges from Gb / B pixels (odd rows) (FIG. 5B). FIG. 11 is a diagram illustrating a potential distribution in a path from the photodiode PD to the FD portion. FIG. 11A illustrates a Gr / R pixel (even number row) before reading (tA period) and before reading ( FIG. 11B shows the change in the potential distribution before reading (tA period) and before reading (tB period) for the Gb / B pixel (odd row). Is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Solid-state imaging device 102 Row address decoder 103 Vertical shift register 104 Selection circuit 105 Output circuit 110 Boost control circuit 111a, 111b Power supply boost level line 112 Row control circuit 113 Setting circuit 120 Test device C0-C3, C00-C03 Coupling capacity Rt Reset transistor SFt Amplifying transistor Tt0 to Tt3 Transfer transistor Tx0 to Tx3 Transfer gate signal

Claims (16)

A solid-state imaging device comprising a plurality of pixels arranged two-dimensionally and a vertical signal line arranged for each pixel column and for reading signal charges from each pixel of each pixel column,
The pixel circuit that forms the pixel shares a plurality of pixels arranged in the pixel column direction, and transfers the signal charge from each pixel to the charge storage unit. The pixel circuit has a transfer transistor corresponding to each pixel. The circuit configuration
The potential level of the charge storage unit when the transfer transistor corresponding to each pixel row is driven is determined by the coupling capacitance between the gate of the transfer transistor and the charge storage unit, the vertical signal line, and the charge storage unit. A solid-state imaging device including a boosting control circuit that controls a boosted potential of the vertical signal line so that the pixel rows have the same level by a coupling capacitor. The pixel circuit is an N pixel sharing circuit that shares N (N is a natural number) pixels,
The pixel circuit includes N photoelectric conversion elements that photoelectrically convert incident light, one charge storage unit that stores signal charges obtained by the photoelectric conversion, and the signal charges from the photoelectric conversion elements. N transfer transistors to be transferred to the storage unit, a source side is connected to the vertical signal line, a gate is connected to the charge storage unit, a potential of the charge storage unit is amplified and read out to the vertical signal line The solid-state imaging device according to claim 1, further comprising an amplification transistor.   The boost control circuit is connected to a boosted voltage obtained by boosting a power supply voltage, and a signal line driving transistor for driving the vertical signal line and a signal line driving transistor for transferring the signal charge to the charge storage unit. The solid-state imaging device according to claim 2, further comprising: a gate voltage control circuit that controls a gate voltage according to which pixel row in the pixel circuit corresponds to the selected pixel row. The pixel circuit is a two-pixel sharing circuit that shares two pixels arranged in a column direction,
The boost control circuit is configured to transfer the signal charge from the even-numbered pixels to the charge storage unit and the potential of the charge storage unit to transfer the signal charges from the odd-numbered pixels to the signal charge storage unit. 3. The solid-state imaging device according to claim 2, wherein when the signal charge is transferred, the boost level of the vertical signal line is controlled so that the potential of the charge storage unit becomes equal.   The boost control circuit includes a row determination unit that determines whether a selected pixel row is an even row or an odd row based on a row address, and the signal line driving transistor based on the determination result The solid-state imaging device according to claim 4, wherein the gate voltage is controlled. The boost control circuit includes:
The gate voltage of the signal line drive transistor to be set when the even-numbered row is selected by an external signal and the gate voltage of the signal line drive transistor to be set when the odd-numbered row is selected. A setting circuit for determining and storing the determined gate voltage;
The solid-state imaging device according to claim 5, wherein the gate voltage of the signal line driving transistor is controlled to the gate voltage determined by the setting circuit based on the determination result. The pixel circuit is a four-pixel sharing circuit that shares first to fourth pixels arranged in a column direction,
The boost control circuit, when transferring the signal charge so that the potential of the charge storage unit when transferring the signal charge from each of the first to fourth pixels to the charge storage unit becomes the same potential, The solid-state imaging device according to claim 3, which controls a boosted level of the vertical signal line.   The boost control circuit includes a row determination unit that determines whether the selected pixel row is a pixel row corresponding to any of the first to fourth pixels shared by the pixel circuit based on a row address. The solid-state imaging device according to claim 7, further comprising: controlling a gate voltage of the signal line driving transistor based on the determination result. The boost setting circuit includes:
The gate voltage of the signal line driving transistor to be set when the pixel row corresponding to each of the first to fourth pixels is selected is determined by an external signal, and the determined gate voltage is stored. Having a setting circuit,
The solid-state imaging device according to claim 8, wherein the gate voltage of the signal line driving transistor is controlled to a gate voltage set by the setting circuit based on the determination result. An electronic information device including an imaging unit,
An electronic information device including the solid-state imaging device according to any one of claims 1 to 9. A test apparatus for testing the solid-state imaging device according to claim 1,
For each pixel in the pixel circuit of the solid-state imaging device, the boost level of the charge storage unit when the transfer transistor is driven is detected, and the boost level of the charge storage unit between the pixels in the pixel circuit is detected. A determination unit for determining a relative difference;
The determination unit outputs a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven for each pixel in the pixel circuit based on the determination result. Test equipment to output to. The pixel circuit of the solid-state imaging device is a two-pixel sharing circuit that shares two pixels,
The determination unit includes a boost level of the charge storage unit when driving a transfer transistor corresponding to a pixel in an even row, and a boost level of the charge storage unit when driving a transfer transistor corresponding to a pixel in an odd row. A signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven for each pixel in the pixel circuit based on the determination result. The test apparatus according to claim 11, wherein the test apparatus outputs the boost control circuit. The pixel circuit of the solid-state imaging device is a 4-pixel sharing circuit that shares 4 pixels,
The determination unit is configured to determine a relative boost level of the charge storage unit corresponding to the four pixels based on a boost level of the charge storage unit when the transfer transistor corresponding to each pixel of the four-pixel sharing circuit is driven. A signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven for each pixel in the pixel circuit based on the determination result. The test apparatus according to claim 11 which outputs to a circuit. A test method for testing the solid-state imaging device according to claim 1,
For each pixel in the pixel circuit of the solid-state imaging device, the boost level of the charge storage unit when the transfer transistor is driven is detected, and the boost level of the charge storage unit between the pixels in the pixel circuit is detected. A determination step for determining a relative difference;
An output step of outputting a signal indicating the potential level of the vertical signal line to be set when driving the transfer transistor to the boost control circuit of the solid-state imaging device for each pixel in the pixel circuit based on the determination result And testing methods including. The pixel circuit of the solid-state imaging device is a two-pixel sharing circuit that shares two pixels,
In the determination step, the boost level of the charge storage unit when driving the transfer transistors corresponding to the pixels in the even rows, and the boost level of the charge storage unit when driving the transfer transistors corresponding to the pixels in the odd rows The boost level difference of
In the output step, a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven for each pixel in the pixel circuit based on the determination result, the boost control circuit of the solid-state imaging device The test method according to claim 14, which is output to The pixel circuit of the solid-state imaging device is a 4-pixel sharing circuit that shares 4 pixels,
In the determination step, based on the boost level of the charge storage unit when the transfer transistor corresponding to each pixel of the 4-pixel sharing circuit is driven, the boost level of the charge storage unit corresponding to the four pixels is relatively To determine the difference
In the output step, a signal indicating the potential level of the vertical signal line to be set when the transfer transistor is driven for each pixel in the pixel circuit based on the determination result, the boost control circuit of the solid-state imaging device The test method according to claim 14, which is output to

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