JP2009111102A - Integrated light-emitting source and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a large-area light-emitting source which is improved in light extraction efficiency and is applicable to lighting. <P>SOLUTION: The integrated light-emitting source has a main support 100, a plurality of light-emitting elements 10 arrayed thereupon, and a light-extracting material 110, which is stuck tightly to the integrated light-emitting elements 10 and is formed of a transparent material at a light emission wavelength. Each of the light-emitting elements 110 has a thin-film crystal layer, a second conductivity-type electrode, and a first conductivity-type side electrode on a transparent substrate, and a fist light extraction direction is a substrate side. Both the electrodes are formed on the side opposite from the first light extraction direction, without spatially overlapping with each other. A sidewall surface of the thin-film crystal layer is retracted from an end of the substrate. An insulating layer covers predetermined parts of the thin-film crystal layer and both the electrodes. Furthermore, a light equalizing layer that improves the uniformity of emitted light is provided between the substrate and first conductivity-type semiconductor layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated type compound semiconductor light emitting device further integrated. Note that in this specification, the expression “light-emitting diode or LED” is used as a term including a general light-emitting element including a laser diode, a superluminescent diode, and the like.

  LEDs having an emission spectrum in the visible region are widely manufactured industrially and are widely used for display applications. The most common shape is that an LED having a pair of p-side electrode and n-side electrode is wrapped with a silicone-based sealing material to form a shell shape. As a white light emitting device, a white LED in which a LED emitting blue or ultraviolet light and a phosphor is combined is put into practical use. However, although such a light source is suitable for display applications, it has a small shape and a small light emitting area per device, and thus is not suitable for illumination applications.

  There is also known an example in which a plurality of semiconductor light emitting elements having different wavelengths are mounted on a single support, mounted close to each other, and surrounded by a sealing material to form a light emitting source. Semiconductor light emitting devices having different emission wavelengths of red, green, and blue can be mounted on one support to be whitened. Even in this embodiment, even if whitening is achieved, the light emitting area per device is small, so that it is not suitable for lighting applications.

  In order to increase the area, a large number of small LEDs are arranged, but there are problems in that the assembly cost of each light emitting device is increased and the in-plane uniformity of light emission intensity is poor.

For the purpose of uniform light emission over a large area or for use as a display, a light emitting device in which a plurality of LEDs are integrated on the same substrate has been proposed. For example, Japanese Patent Application Laid-Open No. 2002-324915 (Patent Document 1) describes that a plurality of light emitting units are arranged in parallel on the same substrate, and a phosphor is attached together with a binder to enlarge the light emitting device. (See paragraph [0085] of Patent Document 1). In addition, International Patent Publication No. WO2006 / 090804 (Patent Document 2) describes a silicone-based sealant suitable for a semiconductor light emitting device, and describes that the material can be used as a light extraction film ( (See paragraph 0397 of Patent Document 2). Japanese Patent Laid-Open No. 2003-115611 (Patent Document 2) discloses a light emitting device in which LEDs are integrated for the purpose of use as a surface light source or a display.
JP 2002-324915 A JP 2003-115611 A

  However, even in a conventional light emitting device in which a plurality of units are integrated, the light emitting area cannot be expanded to a size larger than that of one substrate. At present, a sapphire substrate mainly used for epitaxial growth of GaN-based materials is about 2-3 inches in size, and for example, it is deficient even in terms of the size of household main lighting. On the other hand, in a semiconductor light emitting device, improvement in luminous efficiency is always required. However, neither Patent Document 1 nor 2 describes an attempt to improve the integrated semiconductor light emitting device from the viewpoint of light extraction.

  An object of the present invention is to provide a large-area light-emitting source that is further integrated with an integrated light-emitting device and can be applied, for example, for illumination.

  The present invention relates to the following matters.

[1] A main support, a plurality of light emitting elements defined in the following (A) arranged on the main support, and attached in close contact with the light emitting device, are transparent at an emission wavelength. An integrated light source having a light extraction material made of a material.
(A):
A compound semiconductor thin film having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer on a substrate transparent to the emission wavelength A compound semiconductor light emitting device having a crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenization layer for improving uniformity of light emitted from the surface on the first light extraction direction side between the substrate and the first conductivity type semiconductor layer, and optionally, the substrate and light homogenization as an arbitrary configuration Having a buffer layer between the layers;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer.

[2] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which part of the light homogenization layer forms a receding side wall surface and an end step surface is formed between the light homogenization layer and a non-retreating side wall surface that does not recede, or (Ii) A shape in which a part of the light uniformizing layer and the buffer layer both constitute a receding side wall surface and an end step surface is formed between the buffer layer and the non-backed side wall surface that has not receded. Or (iii) a shape in which both the light homogenizing layer and the buffer layer are all receded and the exposed portion of the substrate forms an end step surface,
Having any of the following shapes;
The integrated light-emitting device according to [1], wherein the insulating film covers a surface on an end step surface from a position away from an end of the light-emitting element and a surface coinciding with a receding sidewall surface of the first conductivity type semiconductor layer. source.

[3] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which a part of the light homogenizing layer forms a receding side wall surface and an end step surface is formed between the light homogenizing layer and a non-retreating side wall surface that is not receded, or (Ii) A shape in which a part of the light uniformizing layer and the buffer layer constitutes a receding side wall surface, and an end step surface is formed between the buffer layer and the non-backed side wall surface that has not receded. Or (iii) the light homogenizing layer and the buffer layer are all retreated, and the portion where the substrate is exposed has any shape of an end step surface;
The integrated light source according to [1], wherein the insulating film covers at least a part of the receding side wall surfaces of the light homogenizing layer and the buffer layer, but is not formed on the end step surface. .

[4] The light emitting element includes:
The light uniformizing layer according to any one of [1] to [3], wherein the light uniformizing layer is a layer provided between the substrate and the first conductivity type cladding layer as a part of the thin film crystal layer. Integrated light source.

[5] A main support, a plurality of light emitting elements defined in the following (B) arranged on the main support, and attached in close contact with the light emitting device, are transparent at an emission wavelength. An integrated light source having a light extraction material made of a material.
(B):
A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenizing layer between the buffer layer and the first conductivity type semiconductor layer for improving uniformity of light emitted from the surface on the first light extraction direction side;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. And having an insulating layer formed at a position away from the light emitting element end, or (ii) the light uniform When the buffer layer and the buffer layer both form a receding side wall surface and have no end step surface, the buffer layer is not formed at least on the first light extraction direction side portion of the buffer layer. Having an insulating layer covering the receding sidewall surface from the middle or from the middle of the light homogenizing layer;
The compound semiconductor light-emitting element further comprising a support body to which the first conductivity-type side electrode and the second conductivity-type side electrode are connected to support the light-emitting element.

[6] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(Ii) The light homogenizing layer and the buffer layer both form a receding side wall surface and have no end step surface,
[5] The insulating layer which covers the receding side wall surface from the middle of the buffer layer or from the middle of the light homogenization layer without being formed at least in the first light extraction direction side portion of the buffer layer [5] An integrated light source as described in 1. above.

[7] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I): A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. It is a shape that forms an end step surface with the non-retreating side wall surface that is not, and at least an insulating layer formed from a position away from the light emitting element end,
The integrated light emission according to [5], wherein the insulating film covers at least a part of the receding side wall surfaces of the light homogenizing layer and the buffer layer, but is not formed on the end step surface. source.

[8] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I): A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer It is a shape that forms an end step surface between the non-retreated non-retreated side wall surface, and at least an insulating layer formed from a position away from the light emitting element end,
The integrated light emission according to [5], wherein the insulating film covers a surface on the end step surface from a position away from the end of the light emitting element, and a surface coinciding with a side wall receding surface of the first conductivity type semiconductor layer. source.

[9] A main support, a plurality of light emitting elements defined in the following (C) arranged on the main support, and attached in close contact with the light emitting device, are transparent at an emission wavelength. An integrated light source having a light extraction material made of a material.
(C):
On the substrate transparent to the emission wavelength, the first conductive type semiconductor layer including the buffer layer, the first conductive type cladding layer, the active layer structure, and the second conductive type semiconductor layer including the second conductive type cladding layer are provided. A compound semiconductor light emitting device having a compound semiconductor thin film crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer.

[10] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which a part of the buffer layer forms a receding side wall surface, and an end step surface is formed between the buffer layer and a non-backed side wall surface that is not receded, or (ii) A shape in which the buffer layer is all receded and the exposed portion of the substrate forms an end step surface,
Having any of the following shapes;
The integrated light-emitting device according to [9], wherein the insulating film covers a surface on the end step surface from a position away from the light-emitting element end and a surface coinciding with the receding side wall surface of the first conductivity type semiconductor layer. source.

[11] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which part of the buffer layer forms a receding side wall surface and an end step surface is formed between the buffer layer and the non-backed side wall surface that is not receded, or (ii) All of the buffer layers recede, and the exposed portion of the substrate has any shape that forms an end step surface;
The integrated light source according to [9], wherein the insulating film covers at least a part of the receding sidewall surface of the buffer layer but is not formed on the end step surface.

[12] A main support, a plurality of light emitting elements defined in the following (D) arranged on the main support, and attached in close contact with the light emitting device, are transparent at an emission wavelength. An integrated light source having a light extraction material made of a material.
(D):
A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
The first conductivity type side electrode and the second conductivity type side electrode are connected and have a support for supporting the light emitting element;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) When a part of the buffer layer constitutes a receding side wall surface and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that has not receded, At least an insulating layer formed from a position away from the end of the light emitting element, or (ii) when the buffer layer forms a receding side wall surface and does not have an end step surface, the buffer A compound semiconductor light emitting device comprising: an insulating layer which covers the receding side wall surface from the middle of the buffer layer without being formed at least in a first light extraction direction side portion of the layer.

[13] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(Ii) The buffer layers together form a receding side wall surface and there is no end step surface,
The integrated light source according to [12], further including an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed at least in the first light extraction direction side portion of the buffer layer.

[14] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
The integrated light source according to [12], wherein the insulating film covers at least a part of the receding sidewall surface of the buffer layer but is not formed on the end step surface.

[15] The light emitting element includes:
For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
The integrated light emission according to [12], wherein the insulating film covers a surface on the end step surface from a position away from the light emitting element end, and a surface coinciding with the side wall receding surface of the first conductive type semiconductor layer. source.

[16] The light extraction material is attached in the following form: (i) The form attached to the surface of the light emitting element on the first light extraction direction side;
(Ii) a form covering the whole of the light emitting element;
(Iii) A form in which the space between the light emitting elements is filled;
(Iv) a form covering a plurality of light emitting elements; and (v) a form covering all the light emitting elements;
The integrated light source according to any one of the above [1] to [15], which is attached to the light emitting element so as to satisfy at least one of the above.

  [17] The integrated light source according to any one of [1] to [16], wherein the light extraction material contains a silicon-containing compound.

  [18] The integrated light source according to [17], wherein the silicon-containing compound is a condensation-type silicone material.

[19] The condensation-type silicone material has the following conditions (1) to (3):
(1) The silicon content is 20% by weight or more;
(2) In a solid Si-nuclear magnetic resonance (NMR) spectrum, it has at least one peak derived from Si in the following (a) and / or (b);
(A) The peak top position is in the region of chemical shift −40 ppm or more and 0 ppm or less with respect to the silicone rubber, and the peak half width is 0.3 ppm or more and 3.0 ppm or less. (B) The peak top position. In the region where the chemical shift is −80 ppm or more and less than −40 ppm based on the silicone rubber, and the peak half-value width is 0.3 ppm or more and 5.0 ppm or less (3) Silanol content is 0.01% by weight or more, Up to 10% by weight;
The integrated light source according to [18], wherein at least one of the above is satisfied.

[20] The light emitting device defined by (A) in [1] above, the light emitting device defined by (B) in [5] above, the light emitting device defined by (C) in [9] above, and the above [12] producing a plurality of light-emitting elements selected from the group consisting of the light-emitting elements defined in (D);
Arranging the plurality of light emitting elements on a main support;
A step of closely attaching a light extraction material made of a material transparent to the light emission wavelength of the light emitting element to the plurality of light emitting elements arranged on the main support; and
A method for manufacturing an integrated light source comprising:

[21] The step of attaching the light extraction material includes:
(I) a form attached to a surface on the first light extraction direction side of the light emitting element;
(Ii) a form covering the whole of the light emitting element;
(Iii) A form in which the space between the light emitting elements is filled;
(Iv) a form covering a plurality of light emitting elements; and (v) a form covering all the light emitting elements;
The method for producing an integrated light source according to [20], further comprising attaching the light extraction material to the light emitting element so as to satisfy at least one of the above.

[22] The step of attaching the light extraction material includes:
Attaching a liquid silicone material to the light emitting element;
Curing the adhered silicone material;
The manufacturing method of the integrated light source as described in said [20] or [21] containing.

  According to the present invention, the light emitting element has a structure suitable for light emission as a large area surface light source, and can provide a large area light emission source suitable for use for illumination. Furthermore, by attaching a light extraction material to the light emitting element, light extraction efficiency can be improved, and a light emission source more suitable for illumination can be provided. Depending on the form of attaching the light extraction material, the uniformity as a surface light source in the light emitting device can be further improved.

  In this specification, the expression “stacked” or “overlapping” refers to the state in which objects are in direct contact with each other, as long as they do not depart from the spirit of the present invention. It may also refer to a spatially overlapping state when projected. In addition, the expression “above (below)” is not limited to the state in which the objects are in direct contact and one is placed above (below) the other, so long as it does not depart from the spirit of the present invention. Even if they are not in contact with each other, they may be used in a state where one is arranged above (below) the other. Furthermore, the expression “after (before, before)” means that even if an event occurs immediately after (before) another event, a third event is Even if it occurs after sandwiching (front), it is used for both. In addition to the expression “when the object is in direct contact”, the expression “in contact with” means that “the object and the object are not in direct contact” as long as they conform to the gist of the present invention. Even if it is in indirect contact via the third member ”,“ the part in which the object is in direct contact with the part in indirect contact through the third member is mixed In some cases, it means “if you are doing”.

  Furthermore, in the present invention, “thin film crystal growth” means so-called MOCVD (Metal Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), Plasma Assist MBE, PLD (Pulsed Laser Deposition), PED (PED) In addition to the formation of a thin film layer, an amorphous layer, a microcrystal, a polycrystal, a single crystal, or a laminated structure thereof in a crystal growth apparatus such as a VPE (Vapor Phase Epitaxy) or LPE (Liquid Phase Epitaxy) method, a subsequent thin film The term “thin film crystal growth” includes the heat treatment of the layer, the carrier activation treatment by plasma treatment, and the like. In the present invention, the “thin film crystal layer” refers to a film formed by “thin film crystal growth”.

  In the present invention, the light-emitting element (compound semiconductor light-emitting element) can extract light in all directions, and the light distribution can be arbitrarily adjusted by appropriately changing the structure of the light extraction material and the insulating layer described later. can do. In the present invention, the term “first light extraction direction” is sometimes used to describe the direction in the light-emitting element, but this term simply refers to various light extraction directions regardless of the light distribution. In the sense of one direction, it is used only to specify the direction. Specifically, the “first light extraction direction” means a side opposite to the side where the first conductivity type side electrode and the second conductivity type side electrode of the light emitting element are provided.

  In addition, the “integrated light source” of the present invention is obtained by integrating a plurality of light emitting elements, but may be simply referred to as “light source”. The “main support” is used to support all of the light emitting elements constituting the light emitting source.

<< 1. Overall structure of the present invention >>
The integrated light source of the present invention includes a main support, a plurality of light emitting elements arranged on the main support, and a light extraction material attached in close contact with the light emitting elements. The light emitting device includes a compound semiconductor thin film crystal layer (hereinafter referred to as a first conductive type semiconductor layer including a first conductive type cladding layer, an active layer structure, and a second conductive type semiconductor layer including a second conductive type cladding layer in this order). And may be simply referred to as a thin film crystal layer), a second conductivity type side electrode, and a first conductivity type side electrode. Further, the second conductivity type side electrode and the first conductivity type side electrode do not have a spatial overlap with each other and are formed on the side opposite to the first light extraction direction. The light emitting element is flip-chip mounted on the main support using the second conductivity type side electrode and the first conductivity type side electrode.

  The number of light emitting elements arranged on the main support is not particularly limited, and the number can be appropriately set according to the size of one main support provided. For example, the number of light emitting elements may be two, or more than 500 light emitting elements may be arranged. The number of preferable light emitting elements in the integrated light source is 25 to 10,000, and it is also preferable to arrange the light emitting elements two-dimensionally. Furthermore, it is also preferable that the main support is configured three-dimensionally and a light emitting element is mounted on the main support to form a three-dimensional light source.

  In the integrated light source, the light emitting elements are preferably arranged close to each other. The degree of proximity is determined by the mechanical accuracy of a bonding apparatus capable of flip chip bonding, and adjacent light emitting elements are arranged at intervals of 100 μm or less, more preferably at intervals of 25 μm or less, most preferably at intervals of 10 μm or less. Is done. However, in reality, there may be irregularities at the edges of each light-emitting element during scribing or braking of the light-emitting element, and due to the mechanical accuracy of the bonding device, etc., the light-emitting elements should be extremely close to each other. Is not realistic. Therefore, practically, adjacent light emitting elements are arranged at intervals of 1 μm or more, more preferably at intervals of 2 μm or more, and most preferably at intervals of 5 μm or more. When the insulation between the light emitting elements is maintained, the light emitting elements may contact each other.

  The light emitting element used in the present invention is a light emitting element having a structure as described later. In addition, the light emitting device can include a buffer layer, a light uniformizing layer, an insulating layer, a wiring, and other necessary components as necessary.

Further, the main support used in the integrated light source of the present invention is not particularly limited as long as it can support a large number of light emitting elements, but when wiring, electrodes, etc. are formed on the main support. A base having at least a surface formed of an insulating material is preferable. Specific examples include AlN, SiC, diamond, BN, CuW, Al ₂ O ₃ , Si, and glass. When the light-emitting element is mounted on the main support in a state of being mounted on an insulating growth substrate, submount, or support, and the main support is not required to have insulation, a substrate formed of a metal material is used. It is good also as a support body. As the main support formed of a metal material, simple metals such as Al and Cu are preferable from the viewpoint of heat dissipation, and composite materials such as stainless steel and composite materials such as Cu and Fe plated with Ni are also available. preferable.

  In the integrated light source of the present invention, the light extraction material is attached in direct contact with the light emitting device.

  The light extraction material is mainly used for the purpose of increasing the extraction efficiency of light emitted from the integrated light source toward the air. Further, depending on the mode of attachment, the light emitted from one light emitting element included in one integrated light source is also used for the purpose of optically coupling with another light emitting element. Furthermore, since the light extraction material is excellent in adhesiveness, it usually has an effect of increasing the heat dissipation efficiency and reducing the temperature rise of the light emitting element.

As an example of the mode of attachment of the light extraction material,
(I) a form attached to the surface of the light emitting element on the first light extraction direction side;
(Ii) a form covering the entire light emitting element;
(Iii) A form in which the space between the light emitting elements is filled;
(Iv) a form in which a plurality of light emitting elements are continuously covered; and (v) a form in which all the light emitting elements are continuously covered;
Can be mentioned. In particular, in the case of (ii) to (v), it is preferable to fill the voids present in the light emitting element and / or cover the side surfaces of the light emitting unit. In the present invention, the light extraction material is preferably attached to the light emitting element so as to satisfy at least one of the forms (i) to (v).

  These forms (i) to (v) will be described with reference to the drawings.

  FIGS. 7-1 and 7-2 show examples of the form (i). A plurality (three in the figure) of light emitting elements 10 are integrated on the main support 100. As the light emitting element 10, a type A light emitting element to be described later is shown in this drawing. The light extraction material 110 is attached to the surface of the light emitting element on the first light extraction direction side (the surface of the substrate for growing a thin film crystal layer in the type A light emitting element). In the form (i), the light extraction material 110 may be attached in a discontinuous shape such as an island shape and a stripe shape as shown in FIG. 7-1 or as shown in FIG. 7-2. The surface on the first light extraction direction side may be continuously covered. Thus, when the light extraction material 110 is not continuous between the light emitting elements 10, an effect is mainly seen in terms of light extraction.

  FIG. 8A shows an example of the form (ii). In this embodiment, the light extraction material 110 is attached to cover the entire light emitting element 10, but is not continuous between the light emitting elements 10. Even in this embodiment, the light extraction material 110 is not continuous between the light emitting elements 10, and therefore, the object is to improve the optical characteristics of the individual light emitting elements 10. In this embodiment, since the light extraction material 110 is attached to the surface on the first light extraction direction side, in addition to obtaining the effect (i), the side surface of the light emitting element 10 is covered, and the light emitting element 10 is covered. By filling the voids 90 existing in the film, light can be extracted from the side surface of the thin film crystal layer. The light extraction from the side surface of the thin film crystal layer contributes to the improvement of luminous efficiency, prevents heat accumulation by extracting light stagnating in the thin film crystal layer, and the main support 100 (there is another support). In this case, the heat radiation efficiency can be improved by thermal coupling with the other. As shown in FIG. 8B, even when the light extraction material is not attached to the surface on the first light extraction direction side, the effect of light uniformity can be obtained by filling the gap 90 portion. The same applies to other forms.)

  FIG. 9 shows an example of the form (iii). In this embodiment, the light extraction material 110 is in close contact with the side surface of the light emitting element 10 and fills the gap between the adjacent light emitting elements 10. When the light extraction material 110 is in close contact with the side surface of the light emitting element 10, the efficiency of light extraction from the side surface is improved, and when the light extraction material is in contact with and attached to the plurality of light emitting elements 10, The effect of optical coupling between the light emitting elements 10 can also be obtained. That is, since the space between the plurality of light emitting elements 10 is filled with the light extraction material 110, the light emitted from one light emitting element 10 is also distributed in the space between the adjacent light emitting devices 10. Light is also emitted from the space between the elements 10. Therefore, the uniformity of the intensity distribution of the light emitted from the integrated light source is improved, and the application as a surface light source becomes more advantageous.

  FIG. 10 shows an example of the form (iv) or (v). In this embodiment, since the light extraction material 110 continuously covers a plurality or all of the light emitting elements 10, the light extraction material 110 is in close contact with the first light extraction direction side surface and the side surface of the light emitting element 10, and the light emitting element 10. The gap between is filled. Therefore, light extraction from the surface on the first light extraction direction side, light extraction from the side surface, light emission from the gap between the light emitting elements 10 and optical coupling between the light emitting elements 10 can be achieved. Therefore, it is most preferable that the light extraction material 110 is provided so as to cover the form of FIG.

  In any form, the light extraction material is preferably formed to have a curved surface that protrudes outward in order to improve light extraction efficiency.

  Hereinafter, the light emitting device and the light extraction material used in the present invention will be described.

<< 2. Light emitting element >>
The plurality of light emitting elements incorporated in the integrated light source of the present invention is preferably selected from the group consisting of the following type A light emitting elements, type B light emitting elements, type C light emitting elements and type D light emitting elements. .

Type A:
A compound semiconductor thin film having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer on a substrate transparent to the emission wavelength A compound semiconductor light emitting device having a crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenization layer for improving uniformity of light emitted from the surface on the first light extraction direction side between the substrate and the first conductivity type semiconductor layer, and optionally, the substrate and light homogenization as an arbitrary configuration Having a buffer layer between the layers;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer.

Type B:
A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenizing layer between the buffer layer and the first conductivity type semiconductor layer for improving uniformity of light emitted from the surface on the first light extraction direction side;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. And having an insulating layer formed at a position away from the light emitting element end, or (ii) the light uniform And when the buffer layer and the buffer layer both form a receding side wall surface and have no end step surface, the buffer layer is not formed in at least the first light extraction direction side portion of the buffer layer. An insulating layer covering the receding side wall surface from the middle of the light uniforming layer or from the middle of the light uniformizing layer;
The compound semiconductor light-emitting element further comprising a support body to which the first conductivity-type side electrode and the second conductivity-type side electrode are connected to support the light-emitting element.

Type C:
On the substrate transparent to the emission wavelength, the first conductive type semiconductor layer including the buffer layer, the first conductive type cladding layer, the active layer structure, and the second conductive type semiconductor layer including the second conductive type cladding layer are provided. A compound semiconductor light emitting device having a compound semiconductor thin film crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer.

Type D:
A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
The first conductivity type side electrode and the second conductivity type side electrode are connected and have a support for supporting the light emitting element;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) When a part of the buffer layer constitutes a receding side wall surface and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that has not receded, At least an insulating layer formed from a position away from the end of the light emitting element, or (ii) when the buffer layer forms a receding side wall surface and does not have an end step surface, the buffer A compound semiconductor light emitting device comprising: an insulating layer which covers the receding side wall surface from the middle of the buffer layer without being formed at least in a first light extraction direction side portion of the layer.

  The advantages of using the type A, B, C and D integrated light-emitting devices are as follows. There are two types of conventional integrated light-emitting devices. The first type is a device in which light-emitting units including a pair of pn junction portions are electrically separated from each other (the device described in Patent Document 1). And the device described in claim 4 of Patent Document 2 and FIG. 10 (b)), and the second type is a device in which light emitting units including a pair of pn junction portions are electrically coupled to each other (Claim 5 of Patent Document 2, FIG. 10A, etc.). In the first type, since the emission intensity is greatly reduced at the separation groove between the light emitting units, there is a problem in the uniformity of the entire surface light source, and when one of the light emitting units deteriorates, only the vicinity thereof is affected. However, there is a problem that the emission intensity is extremely reduced. In the second type, since the n-type semiconductor layer is common to the entire light emitting device, not only does the current flow from the n-side electrode to the nearest p-side electrode, but any p-type from one n-side electrode. A current flows into the side electrode, and current injection efficiency is not high when viewed as the whole light emitting device. In addition, since all the p-side electrodes and all the n-side electrodes are electrically coupled, there is a problem in that deterioration at one place results in deterioration of the entire apparatus.

  On the other hand, the integrated light emitting devices of types A, B, C, and D do not have such a problem and have high uniformity of light emission intensity. Therefore, the integrated light emission used in the integrated light source of the present invention Particularly suitable as a device.

  The types A to D will be described in order below.

<< 2-1. Type A >>
The characteristics of the type A light emitting element are specified by the following matters.

1. A compound semiconductor thin film having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer on a substrate transparent to the emission wavelength A compound semiconductor light emitting device having a crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenization layer for improving uniformity of light emitted from the surface on the first light extraction direction side between the substrate and the first conductivity type semiconductor layer, and optionally, the substrate and light homogenization as an arbitrary configuration Having a buffer layer between the layers;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer.

2. For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which part of the light homogenization layer forms a receding side wall surface and an end step surface is formed between the light homogenization layer and a non-retreating side wall surface that does not recede, or (Ii) A shape in which a part of the light uniformizing layer and the buffer layer both constitute a receding side wall surface and an end step surface is formed between the buffer layer and the non-backed side wall surface that has not receded. Or (iii) a shape in which both the light homogenizing layer and the buffer layer are all receded and the exposed portion of the substrate forms an end step surface,
Having any of the following shapes;
2. The light emitting device as described in 1 above, wherein the insulating layer covers a surface on an end step surface from a position away from an end of the light emitting element and a surface coinciding with a receding side wall surface of the first conductivity type semiconductor layer. element.

3. For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which a part of the light homogenizing layer forms a receding side wall surface and an end step surface is formed between the light homogenizing layer and a non-retreating side wall surface that is not receded, or (Ii) A shape in which a part of the light uniformizing layer and the buffer layer constitutes a receding side wall surface, and an end step surface is formed between the buffer layer and the non-backed side wall surface that has not receded. Or (iii) the light homogenizing layer and the buffer layer are all retreated, and the portion where the substrate is exposed has any shape of an end step surface;
2. The light emitting device according to 1 above, wherein the insulating layer covers at least part of the receding side wall surfaces of the light homogenizing layer and the buffer layer, but is not formed on the end step surface. .

  4). The light uniformizing layer is a layer provided between the substrate and the first conductivity type cladding layer as a part of the thin film crystal layer. Light emitting element.

5). When the average refractive index of the substrate at the emission wavelength is expressed as n _sb , the average refractive index of the light uniformizing layer is expressed as n _oc , and the average refractive index of the first conductive semiconductor layer is expressed as n ₁ ,
n _sb <n _oc and n ₁ <n _oc
The light-emitting element according to any one of 1 to 4 above, wherein:

6). The light emitting wavelength of the light emitting element is λ (nm), the average refractive index of the substrate at the light emitting wavelength is n _sb , the average refractive index of the light uniformizing layer is no _oc , and the physical thickness of the light uniformizing layer is _toc (Nm), and the relative refractive index difference Δ _(oc−sb) between the light homogenization layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × ( _noc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
The light emitting device according to any one of 1 to 5 above, wherein t _oc is selected so as to satisfy

7). The emission wavelength of the light emitting element is λ (nm), the average refractive index at the emission wavelength of the light homogenizing layer is n _oc , the average refractive index at the emission wavelength of the first conductivity type semiconductor layer is n ₁ , and the light homogenizing layer. the physical thickness and _t oc (nm), the relative refractive index difference of the light uniformizing layer and the first conductivity type semiconductor layer delta a _{(oc-1) Δ (oc} -1) ≡ ((n oc) 2 - ( n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
7. The light emitting device according to any one of 1 to 6 above, wherein t _oc is selected so as to satisfy

8). The specific resistance ρ _oc (Ω · cm) of the entire light homogenizing layer is
0.5 ≦ ρ _oc
The light-emitting element according to any one of 1 to 7 above, wherein:

  9. 9. The light emitting device as described in any one of 1 to 8 above, wherein the light homogenizing layer has a laminated structure of a plurality of layers.

10. 10. The light emitting device according to any one of 1 to 9 above, wherein the width _{L1w of the} narrowest portion among the portions where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. .

11. The width L _{2w of the} narrowest portion among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer is 15 μm or more, Light emitting element.

12 12. The light emitting device as described in 11 above, wherein L _2w is 100 μm or more.

13. The width L _ws of the narrowest portion of the end surface portion that is not covered with the insulating layer among the substrate surface exposed by the receding of the side wall surface of the thin film crystal layer is 15 μm or more. The light emitting element in any one.

  14 Any of 1 to 13 above, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. A light emitting device according to any one of the above.

  15. Said 1-14 characterized by the said 2nd conductivity type side electrode including the layer which consists of a material containing the element chosen from the group which consists of Ni, Pt, Pd, Mo, Au, and those 2 or more types of combinations. The light emitting element in any one of.

16. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. 16. The light-emitting element according to any one of 1 to 15 above, which is a single layer.

  17. 16. The light emitting device as described in any one of 1 to 15 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  18. 18. The light-emitting element according to 17 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

19. 19. The light emitting device as described in 18 above, wherein the fluoride is selected from the group consisting of AlF _x , BaF _x , CaF _x , SrF _x and MgF _x .

20. Wherein the substrate, _sapphire, SiC, GaN, LiGaO 2, _ZnO, light-emitting device according to any one of the above 1 to 19, characterized in that it is selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO.

  21. 21. The light-emitting element according to any one of 1 to 20, wherein a surface of the substrate on the first light extraction direction side is not flat.

22. R3 is a reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the light uniformizing layer is reflected by the substrate, and the light emitting element is perpendicularly incident on the first light extraction direction side space from the substrate. When the reflectance at which the light of the emission wavelength is reflected at the interface with the space is represented by R4,
R4 <R3
The light emitting element according to any one of the above items 1 to 21, wherein a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above condition.

  23. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 23. The light emitting device according to any one of 1 to 22, wherein an element selected from the group consisting of Al is contained.

24. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The light-emitting element according to any one of 1 to 23, wherein:

  25. 25. The light-emitting element according to any one of 1 to 24 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  26. 25. The light emitting device according to any one of 1 to 24, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal layer by solder.

  According to the type A light-emitting element, a flip-chip mount that can emit blue or ultraviolet light and has high output, high efficiency, and high uniformity of brightness on the first light extraction direction side. Type semiconductor light emitting device can be provided.

  In the structure of the light emitting element of type A, since process damage in each step in the manufacturing process is eliminated, the function of the light emitting element is not impaired and the element is highly reliable.

  Hereinafter, the type A light emitting device will be described in more detail.

  FIGS. 1-1A and 1-2A show typical examples of compound semiconductor light-emitting elements of the type A form (hereinafter simply referred to as light-emitting elements). FIG. 1-1B and FIG. 1-2B are diagrams in which a part of FIG. 1-1A and FIG. 1-2A are omitted for explanation, and FIGS. 1-3A and 1-3B are structures of light-emitting elements. It is a figure which shows the shape in the middle of preparation in order to explain in detail. Hereinafter, a description will be given with reference to FIGS. 1-1A to 1-3B.

  A light emitting device of type A has a first conductivity type including a buffer layer 22, a light uniformizing layer 23, and a first conductivity type cladding layer 24 on a substrate 21, as shown in FIGS. 1-1A and 1-2A. A compound semiconductor thin film crystal layer having a semiconductor layer, a second conductivity type semiconductor layer including a second conductivity type cladding layer 26, and an active layer structure 25 sandwiched between the first and second conductivity type semiconductor layers; A conductive type side electrode 27 and a first conductive type side electrode 28 are provided.

  The second conductivity type side electrode 27 is arranged on a part of the surface of the second conductivity type clad layer 26, and the portion where the second conductivity type clad layer 26 and the second conductivity type side electrode 27 are in contact is the second current. An injection region 35 is formed. Further, the second conductivity type cladding layer, a part of the active layer structure, and a part of the first conductivity type cladding layer are removed, and the first conductivity type cladding layer 24 exposed at the removed portion is formed. The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the substrate by arranging the first conductivity type side electrode 28 in contact therewith. . The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are respectively connected to the metal layer 41 on the submount 40 via the metal solder 42.

  In this embodiment, the first conductivity type side electrode 28 and the second conductivity type side electrode 27 do not spatially overlap each other. This means that, as shown in FIGS. 1-1A and 1-2A, shadows do not overlap when the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are projected onto the substrate surface. To do.

  When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” or the like. At the same time, in this embodiment, the insulating layer is arranged at an optimum position so as not to damage the element and affect the performance or affect the yield.

  The type A light-emitting element can take different forms at two locations: (I) a stepped shape at the end of the light-emitting element 10 and (II) a shape of the insulating layer 30 at the end of the light-emitting element. (I) The step shape of the end of the light emitting element 10 is roughly divided by the etching depth when forming the inter-device isolation groove 13 (see FIGS. 1-3A and the like) for element isolation in the manufacturing process. (I) halfway through the light uniformizing layer 23, (ii) halfway through the buffer layer 22 (when the buffer layer is present, the same applies hereinafter), and (iii) up to the substrate surface (or deeper). There is a choice. Further, since the wall surface of the inter-device isolation groove 13 recedes from the element end after element isolation, in this embodiment, the surface that appears as the side wall surface when the inter-device isolation groove 13 is formed is referred to as “retreat” for the element after element isolation. It is called “side wall surface”. Further, the side wall surface that appears at the element end due to element isolation is referred to as a “non-retreat side wall surface”. A step surface is formed at the end of the light emitting element between the receding side wall surface and the non-backed side wall surface, and this is referred to as an “end step surface”.

  Corresponding to the depths (i) to (iii) of the inter-device separation groove 13, in (i), a part of the light homogenizing layer 23 has a receding side wall surface with respect to the receding side wall surface of the thin film crystal layer. The side wall of the light uniformizing layer 23 that is configured and remains (on the first light extraction direction side) is a non-retreating side wall surface, and has an end step surface at the end of the light uniformizing layer 23. Similarly, in (ii), the buffer layer 22 has an end step surface at the end. In (iii), since both the side walls of the light uniformizing layer 23 and the buffer layer 22 constitute a receding side wall surface (because it becomes a side wall surface of the inter-device separation groove 13), the portion where the substrate 21 is exposed is the end portion. The shape becomes a stepped surface.

  FIG. 1-1C and FIG. 1-2C correspond to (i). The shapes corresponding to (ii) are FIGS. 1-1D, 1-2D, and 1-2E. FIG. 1-1A (FIG. 1-1B) and FIG. 1-2A (FIG. 1-2B) correspond to (iii).

  (II) Regarding the shape of the insulating layer 30 at the end of the light emitting element, in the manufacturing process, (i) a region including the center on the groove bottom surface while leaving the insulating layer 30 formed on the side wall of the inter-device separation groove 13 (Ii) In addition to all of the insulating layer 30 formed on the bottom surface of the groove, the insulating layer 30 including part of the side wall in the groove is removed. In the light emitting device 10 manufactured as a result, there are two types: (i) a shape in which the insulating layer 30 is attached to the groove bottom surface, and (ii) a shape in which the insulating layer 30 is separated from the groove bottom surface. FIG. 1-1A (FIG. 1-1B), FIG. 1-1C, and FIG. 1-1D correspond to (i). FIGS. 1-2A (FIGS. 1-2B), 1-2C, 1-2D, and 1-2E correspond to (ii).

  The shape of the light-emitting element 10 of type A will be described separately as (II) the first aspect and (ii): the second aspect according to the shape of the insulating layer 30 at the end of the light-emitting element.

[First embodiment]
A form belonging to the first aspect is shown in FIGS. 1-1A to 1-1D. First, a typical form will be described with reference to FIG. 1-1A. Among the thin film crystal layers, at least the first conductive semiconductor layer, the active layer structure 25 and the side wall surfaces of the second conductive semiconductor layer are recessed from the end of the substrate 21. This shape appears in all forms of Type A. As shown in FIG. 1-3A, in the manufacturing process, after forming a thin film crystal layer, in order to separate each element, the thin film crystal layer is removed to a predetermined depth by a method described later. This is because the separation groove 13 is formed and the elements are separated in the separation groove. FIG. 1-1A shows an example in which the thin film crystal layer is removed until the substrate 21 is reached, which is one of the preferred forms of type A. In type A, the first conductive semiconductor layer, the active layer structure 25 and the second conductive semiconductor layer, which are portions related to essential functions such as current injection and light emission, are generally used scribes, Since the element is separated without undergoing a process of element separation such as braking, the thin film crystal layer related to the performance is not directly damaged. For this reason, performances such as tolerance and reliability are excellent particularly in large current injection.

  The side wall surface exposed when the thin film crystal layer is removed is covered with an insulating layer 30. Further, before the element division, as shown in FIG. 1-3A, the insulating layer 30 does not cover the entire groove bottom surface of the inter-device isolation groove 13, but the insulating layer 30 is formed on the substrate surface (that is, the groove bottom surface). A scribe region 14 that is not formed is formed. Since only the substrate 21 has to be scribed and braked during element separation such as scribe and braking during the manufacturing process, the thin film crystal layer is not directly damaged. In addition, since the insulating layer 30 does not peel off, reliable insulation can be maintained, and the thin film crystal layer is not damaged by the tension generated when the insulating layer 30 peels off.

In the separated light-emitting element 10 obtained as a result, as shown in part A of FIGS. 1-1A and 1-1B, the entire surface of the substrate surface exposed by retreating the side wall surface of the thin film crystal layer is covered with the insulating layer. 30 does not cover, but covers the substrate surface on the inner side from the position separated by L _ws from the end of the substrate 21. When divided from the center of the width of the scribe region 14, the distance L _ws that is not covered with the insulating layer 30 corresponds to approximately ½ of the width of the scribe region 14 in the range of manufacturing fluctuation or the like. That is, as a result of ensuring that the insulating layer 30 is not peeled off from the side surface of the thin film crystal layer by this shape, the light-emitting element 10 has an unintentional short circuit even if the solder wraps around. In addition to being prevented, the thin film crystal layer is not damaged, so that the function of the light emitting element 10 is not impaired and the element is highly reliable.

The size of L _ws may be larger than 0 in the completed light emitting element 10, but is usually 10 μm or more, preferably 15 μm or more. As a design value, if the width of the scribe region 14 is 2L _ws , 2L _ws is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _WS is usually 300 μm or less, preferably 200 μm or less.

  It is also a preferred embodiment that the inter-device separation groove 13 is formed halfway through the light uniformizing layer 23 or halfway through the buffer layer 22. As a result, in the completed light emitting device 10, at least the first conductive semiconductor layer, the active layer structure 25, and the second conductive semiconductor layer are retracted inward from the end (substrate end) of the light emitting device 10, and the receding side wall surface is formed. The end step surface 55 formed and based on the groove bottom surface is present at the end of the light emitting element 10. In FIG. 1-1A, the substrate surface itself corresponds to the step surface.

FIG. 1-1C shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the light uniformizing layer 23. As shown in part A, a part of the buffer layer 22 and the light uniformizing layer 23 exists as a non-retreating side wall surface to the light emitting element end, and the wall surface recedes from the element end from the middle of the light uniformizing layer 23. A receding side wall surface (side wall of the inter-device separation groove) is formed together with the side wall surface of the conductive semiconductor layer. Between the non-retreat side wall surface and the retreat side wall surface, an end step surface 55 based on the bottom surface of the inter-device separation groove exists. All the wall surfaces of the buffer layer 22 are exposed. On the other hand, as shown by A part in FIG. 1-1C, the part of the non-retreating side wall surface is exposed and the part of the retreating side wall surface is covered with the insulating layer 30 among the side walls of the light uniformizing layer 23. The inside of the stepped surface 55 is continuously covered with the receding side wall surface from a position away from the end (a position corresponding to L _ws in FIG. 1-1B). This corresponds to a form in which the inter-device separation groove is stopped in the middle of the light uniformizing layer 23 in FIG. 1-1A (FIG. 1-1B).

FIG. 1-1D shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the buffer layer 22. As shown in part A, the buffer layer 22 exists up to the end of the light emitting element, and the buffer layer 22 has an end step surface 55 based on the bottom surface of the inter-device separation groove, Of these, it has a non-retreat side wall surface (element end portion) and a retreat side wall surface portion (side wall of the inter-device separation groove) that enters inside from the light emitting element end. 1-1D, the non-retreated side wall surface of the side wall of the buffer layer 22 is exposed without being covered with the insulating layer 30, and the retreated side wall surface portion is covered with the insulating layer 30, The inner side of the end step surface 55 is continuously covered with the receding side wall surface from a position away from the end (a position corresponding to L _ws in FIG. 1-1B). This corresponds to a form in which the inter-device separation groove is stopped in the middle of the buffer layer 22 in FIG. 1-1A (FIG. 1-1B).

  As in these examples, even when the inter-device isolation groove is formed up to the middle of the combined layer of the light uniformizing layer 23 and the buffer layer 22, the insulating layer 30 covering the side wall extends to the end of the light emitting element. In the device having a shape that does not reach, it is guaranteed that the insulating layer 30 is not peeled off, and the exposed layer is made of a highly insulating material, so that the light emitting device of the form of FIG. Similar to 10, the device is highly reliable.

[Second embodiment]
A form belonging to the second mode is shown in FIGS. 1-2A to 1-2E. The second mode is the same as the first mode in the layer configuration and the like, and (II) the shape of the insulating layer 30 at the end of the light emitting element is different from the first mode.

  First, as shown in FIG. 1-2A, the side wall surfaces of at least the first conductive semiconductor layer, the active layer structure 25, and the second conductive semiconductor layer in the thin film crystal layer are set back from the edge of the substrate 21 to form the back side wall surface. Is configured. This shape appears in all forms of Type A. As shown in FIG. 1-3B, in the manufacturing process, after the thin film crystal layer is formed, the thin film crystal layer is removed by a method described later in order to separate the elements from each other. This is because the device is separated in the separation groove. As in the other aspects of type A, at least the first conductivity type semiconductor layer (first conductivity type cladding layer 24 in the figure) of the side wall surface exposed when the thin film crystal layer is removed, the active layer structure 25. The sidewall surfaces of the second conductivity type semiconductor layer (second conductivity type clad layer 26 in the figure) are covered with an insulating layer 30.

  In the second mode, the insulating layer 30 is not present in the portion corresponding to the bottom surface of the inter-device separation groove in the surface of the substrate 21. The insulating layer non-formed portion 15 which is not covered with the insulating layer 30 on the receding side wall surface of the thin film crystal layer is present at least on the first light extraction direction side of the side wall surface of the buffer layer 22. It may extend over the entire 22 side wall surfaces. Further, it may extend to a part or all of the side wall surface of the light uniformizing layer 23. In addition, when the inter-device separation groove is formed by etching part of the substrate 21, only the substrate portion of the wall surface of the separation groove is exposed and the buffer layer 22 may be covered.

  In this case, it is preferable that the buffer layer 22 of the insulating layer non-forming portion 15 that is not covered with the insulating layer 30 is an undoped undoped layer. Moreover, when the insulating layer non-formation part 15 extends to the light uniformization layer 23, it is preferable that it is an undoped layer which is not doped to the part. If the exposed part is a highly insulating material, there is no possibility of short circuit due to the wrapping of solder, and the element is highly reliable.

  As shown in FIG. 1-3B, this structure corresponds to the shape before element separation during the manufacturing process, and the insulating layer 30 includes a substrate surface in the groove of the inter-device separation groove 13 and a groove adjacent to the substrate surface. It is removed from the insulating layer non-forming portion 15 on the side wall surface.

  Since the insulating layer 30 is not formed on the portion in contact with the substrate 21, only the substrate 21 has to be scribed and braked when separating elements such as scribe and braking during the manufacturing process. There is no direct damage. In addition, since the insulating layer 30 does not peel off, reliable insulation can be maintained, and the thin film crystal layer is not damaged by the tension generated when the insulating layer 30 peels off.

  In the separated light-emitting element 10 obtained as a result, as shown in part A of FIGS. 1-2A and 1-2B, the insulating layer 30 is exposed on the substrate surface where the side wall surface of the thin-film crystal layer is retreated. Not covered. As a result of ensuring that the insulating layer 30 is not peeled off from the side surface of the thin film crystal layer by this shape, the light emitting element 10 can prevent an unintended short circuit even if the solder wraps around. In addition, since the thin film crystal layer is not damaged, the function of the light emitting element 10 is not impaired and the element is highly reliable.

  Also in the second mode, it is also a preferred mode that the inter-device separation groove 13 is formed halfway through the light uniformizing layer 23 or halfway through the buffer layer 22. As a result, in the completed light-emitting element 10, at least the first conductive type semiconductor layer, the active layer structure 25, and the second conductive type semiconductor layer are retracted inward from the end (substrate end) of the device, and the end portion based on the groove bottom surface A step surface exists at the end of the light emitting element 10.

  1-2C shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the light uniformizing layer 23. FIG. As shown in part A, a part of the buffer layer 22 and the light homogenizing layer 23 exists as a non-retreating side wall surface to the light emitting element end, and the wall surface retreats from the element end from the middle of the light homogenizing layer 23. A receding side wall surface (side wall of the inter-device isolation groove) is formed together with the side wall surface of the conductive semiconductor layer. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. All the wall surfaces of the buffer layer 22 are exposed. Further, the end step surface 55 of the light uniformizing layer 23 is not covered with the insulating layer 30, and the insulating layer non-formed portion 15 not covered with the insulating layer 30 is formed on the receding side wall surface. Present on the light extraction direction side. This corresponds to a form in which the inter-device separation groove is stopped in the middle of the light uniformizing layer 23 in FIG. 1-2A (FIG. 1-2B).

  FIGS. 1-2D and 1-2E show an example of a light emitting device manufactured by forming the inter-device separation groove partway in the buffer layer 22. FIG. As shown in part A, a part of the buffer layer 22 exists as a non-retreat side wall surface to the light emitting element end, and the wall surface retreats from the element end from the middle of the buffer layer 22 together with the side wall surface of the second conductivity type semiconductor layer. A receding side wall surface (side wall of the inter-device separation groove) is formed. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. The non-retreating side wall surface (side wall portion of the element end) and the end step surface 55 are not covered with the insulating layer 30, and the receding side wall surface (side wall of the device isolation groove) is covered with the insulating layer 30. The non-insulating layer non-formed portion 15 exists on the first light extraction direction side. This corresponds to a form in which the inter-device separation groove is stopped in the middle of the buffer layer 22 in FIG. 1-2A (FIGS. 1-2B). The insulating layer non-forming portion 15 may extend over the entire side wall surface of the buffer layer 22 in some cases. Further, as shown in FIG. 1-2E, the light uniformizing layer 23 may extend to a part or all of the side wall surface.

  As in these examples, even when the inter-device separation groove 13 is formed up to the middle of the combined layer of the light uniformizing layer 23 and the buffer layer 22, the insulating layer 30 that covers the side wall is provided on the light emitting element 10. In the device having a shape that does not reach the end, it is guaranteed that the insulating layer 30 is not peeled off, and the exposed layer is made of a highly insulating material. Like the light emitting element 10, the device is highly reliable.

In common with the first aspect and the second aspect, in type A, the insulating layer 30 is formed on the substrate side of the first conductivity type side electrode 28 (see FIG. 1-1B and B part in FIG. 1-2B). A part of the first light extraction direction side). That is, the insulating layer 30 is interposed between a portion between the first conductivity type side electrode 28 and the first conductivity type semiconductor layer (first conductivity type cladding layer 24 in this embodiment). As a result, the area of the first conductivity type side electrode 28 is larger than the area of the first current injection region 36. As shown in FIGS. 1-1B and 1-2B, if the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode 28 is in contact with the insulating layer 30 is L _1w , L _1w is It is preferably 7 μm or more, particularly preferably 9 μm or more. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

Furthermore, the insulating layer 30 covers a part of the sub-mount side (opposite to the first light extraction direction) of the second conductivity type side electrode 27 as shown in a portion C of FIGS. 1-1B and 1-2B. ing. That is, the area of the electrode exposed portion 37 of the second conductivity type side electrode 27 is smaller than the area of the second conductivity type side electrode 27, and the area of the second current injection region 35 is equal to the area of the second conductivity type side electrode 27. equal. As shown in FIGS. 1-1B and 1-2B, if the width of the narrowest portion of the width covered by the insulating layer 30 from the periphery of the second conductivity type side electrode 27 is L _2W , L _2W Is preferably 15 μm or more. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can. L _2w is usually 2000 μm or less, preferably 750 μm or less.

  Further, the first conductive semiconductor layer (first conductive clad layer 24 in this embodiment) and the second conductive semiconductor layer (second conductive clad layer 26 in this embodiment) on the submount side (first light The exposed portion of the surface on the opposite side of the take-out direction is usually covered with an insulating layer 30 as shown in FIG.

  Due to such a positional relationship between the insulating layer 30 and the electrodes 27 and 28, it is possible to manufacture by a process with little process damage.

  As described above, the light emitting element 10 of type A has the insulating layer 30 in which process damage, heat dissipation when flip chip mounting is performed, and insulating properties are comprehensively considered.

  Furthermore, the light emitting element 10 of type A has a light uniformizing layer 23 on the first light extraction direction side from the first conductive semiconductor layer (the first conductive clad layer 24 in this embodiment). Although the light homogenization layer 23 will be described later in detail, it has an appropriate light confinement effect, and the light emitted from the active layer structure 25 is distributed throughout the light homogenization layer without being localized. Therefore, when viewed from the surface 50a on the first light extraction direction side of the substrate 21, light is distributed also to a region corresponding to the non-light emitting portion without the active structure layer 25 for extraction of the first conductivity type side electrode 28. In addition, even if the light emission in the active structure layer 25 is uneven, the light is distributed so as to be uniform. Furthermore, since the periphery of the light homogenizing layer 23 is covered with the insulating layer 30, increasing the reflectance of the insulating layer 30 with respect to the emission wavelength increases the light confinement effect in the light homogenizing layer 23. The uniformity is further improved.

  Hereinafter, each member and structure constituting the light emitting element 10 of type A will be described in more detail.

<Board>
The material of the substrate is not particularly limited as long as it is optically approximately transparent to the emission wavelength of the light emitting element. Here, “substantially transparent” means that there is no absorption with respect to the emission wavelength, or even if there is absorption, the light output is not reduced by 50% or more due to absorption by the substrate.

The substrate is preferably an electrically insulating substrate. This is because even when a solder material or the like adheres to the periphery of the substrate when flip chip mounting is performed, current injection into the light emitting element is not affected. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light-emitting material or InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, the Si doping concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or less, more preferably 8 × 10 ¹⁷ cm ⁻ when an undoped substrate is intentionally used. ^It is desirable that it is ³ or less from the viewpoints of electrical resistance and crystallinity.

  The substrate used in the type A light emitting device is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. There can also be. Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when using a c + plane substrate of sapphire as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture a compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. In addition, the substrate is intentionally roughened in relation to the buffer layer, which will be described later, thereby introducing a threading transition that occurs at the interface between the thin film crystal layer and the substrate near the active layer of the light emitting device. It is also possible not to do so.

In the light emitting element of the type A, confine light in the later light uniformizing layer, in order to guide so as to be distributed in the layer at the same time, the substrate has a refractive index at the emission wavelength of the compound semiconductor light emitting device (n _sb ) Is relatively smaller than the average refractive index (n _oc ) of the light homogenizing layer.

  In one embodiment, the thickness of the substrate is usually about 250 to 700 μm at the initial stage of device fabrication, so that crystal growth of the light emitting device and mechanical strength in the device fabrication process are ensured. Is normal. After growing a thin film crystal layer using this, in order to make it easy to separate each element, it is appropriately thinned during the process by a polishing process, and finally the apparatus has a thickness of about 100 μm or less. desirable. Moreover, it is the thickness of 30 micrometers or more normally.

  In different embodiments, the thickness of the substrate may be different from the conventional one, and may be about 350 μm, further about 400 μm, or about 500 μm.

In addition, when the substrate is selected so as to be a relatively low refractive index layer with respect to the waveguide in order to confine and guide light in the light uniformizing layer described later, the physical thickness of the substrate is determined by the light emitting element. When the emission wavelength is λ (nm) and the average refractive index of the substrate is n _sb , it is desirable that the thickness is larger than 4λ / _nsb .

Further, it is desirable that a so-called low reflection coating layer or low reflection optical film is formed on the surface of the substrate on the first light extraction direction side. Reflection due to a difference in refractive index at the substrate-air interface can be suppressed, so that high output and high efficiency of the device can be achieved. Here, the reflectance at which the light having the emission wavelength of the light emitting element perpendicularly incident on the substrate side from the light uniformizing layer side (from the buffer layer when the buffer layer is present) is reflected by the substrate is R3, and the first reflectance from the substrate. When the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the light extraction direction side of the light is reflected at the interface with the space is represented by R4,
R4 <R3
It is preferable that a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above condition. For example, when the substrate is sapphire, it is desirable to use MgF ₂ or the like as the low reflection coating film. Relative refractive index n _s of the substrate at the emission wavelength, the refractive index of the low reflecting coating film, since it is desirable near √n _s, relative to the square root of the refractive index of the sapphire, the refractive index of MgF ₂ are close It is.

In the type A light-emitting element, it is also preferable that the surface on the first light extraction direction side of the substrate is an uneven surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Further, when the emission wavelength of the element is λ (nm), the roughness of the rough surface is the average roughness Ra (nm).
λ / 5 (nm) <Ra (nm) <10 × λ (nm)
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

<Buffer layer>
The buffer layer is mainly used for thin film crystal growth on the substrate, such as suppression of transition, mitigation of imperfection of the substrate crystal, and reduction of various mismatches between the substrate crystal and the desired thin film crystal growth layer. Formed for the purpose of crystal growth.

  The buffer layer is formed by thin-film crystal growth, and an InAlGaN-based material, an InAlBGaN-based material, an InGaN-based material, an AlGaN-based material, an AlN-based material, a GaN-based material, or the like, which is a desirable form in the present invention, is formed on a different substrate. When growing, the buffer layer is particularly important because the lattice constant matching with the substrate is not necessarily ensured. For example, when a thin film crystal growth layer is grown by metal organic vapor phase epitaxy (MOVPE method), a low temperature growth AlN layer near 600 ° C. is used as a buffer layer, or a low temperature growth GaN layer formed near 500 ° C. Can also be used. Also, AlN, GaN, AlGaN, InAlGaN, InAlBGaN, etc. grown at a high temperature of about 800 ° C. to 1000 ° C. can be used. These layers are generally thin and about 5-40 nm.

  The buffer layer is not necessarily a single layer. In order to improve the crystallinity on the GaN buffer layer grown at a low temperature, several GaN layers grown at a temperature of about 1000 ° C. without doping are used. You may make it have about μm. Actually, it is usual to have such a thick film buffer layer, and the thickness is about 0.5 to 7 μm. The buffer layer may be doped with Si or the like, or may be formed by stacking a doped layer and an undoped layer in the buffer layer.

  As a typical embodiment, a low-temperature buffer layer in which a thin film crystal is grown at a low temperature of about 350 ° C. to less than 650 ° C. in contact with a substrate, and a high-temperature buffer layer in which a thin film crystal is grown at a high temperature of about 650 ° C. to 1100 ° C. The thing of a 2 layer structure is mentioned. When the substrate is GaN, all of the buffer layer can be GaN formed at a high temperature of 900 ° C. or higher.

  For the formation of the buffer layer, lateral growth technology (ELO), which is a kind of so-called microchannel epitaxy, can also be used, thereby reducing the density of threading transitions generated between a substrate such as sapphire and an InAlGaN-based material. It can also be greatly reduced. Furthermore, even when using a processed substrate in which the surface of the substrate is processed to have irregularities, it is possible to eliminate some of the dislocations during lateral growth, and such a substrate and a buffer layer It is preferable to apply this combination to a light emitting element of type A. Further, in this case, the unevenness formed on the substrate has an effect of improving the light extraction efficiency, which is preferable.

  In the type A light emitting device, the buffer layer is integrated with a light homogenizing layer described later so as to realize light confinement in order to increase the uniformity of the light intensity on the surface on the first light extraction direction side. It doesn't matter. Further, part or all of the buffer layer may also serve as the light uniformizing layer.

  Further, although the buffer layer may become an exposed portion of the inter-device separation groove, the exposed portion is preferably an undoped portion. Thereby, the insulation failure by the solder | pewter etc. at the time of apparatus assembly can be suppressed.

<Light homogenization layer>
The light homogenizing layer of the type A light-emitting element is configured to guide light gently while leaking part of the light by temporarily confining and distributing the light emitted by the active layer structure in the layer. Is a layer that exhibits effects such as scattering of light, multiple reflection, and thin film interference, and improves the uniformity of the light emitting element on the first light extraction direction side.

  The light homogenizing layer 23 is preferably formed of a compound semiconductor layer, and as shown in FIGS. 1-1A, 1-2A and other drawings, a buffer layer is present, and the buffer layer and the first conductivity type are present. It is desirable to exist between the semiconductor layers (first conductivity type cladding layers). The film forming method is not particularly limited. However, in order to easily manufacture a light emitting element, it is desirable to manufacture the light emitting element simultaneously with other thin film crystal layers by using a thin film crystal growth technique.

In the light emitting element of type A, the refractive index of the light homogenizing layer is selected so that light is confined at least in the layer, that is, the light distribution density is increased. Therefore, the average refractive index (n _oc ) of the light uniformizing layer is larger than the average refractive index of the first conductivity type cladding layer, and in an embodiment with the substrate, it is larger than the average refractive index (n _sb ) of the substrate. In particular, it is preferable that the average refractive index (n ₁ ) of the first conductivity type semiconductor layer existing between the light homogenizing layer and the active layer structure be larger. Moreover, it is more than the average refractive index ( _nbf ) of a buffer layer, and it is preferable that it is especially larger than the average refractive index of a buffer layer. In addition, the material constituting the light homogenizing layer is particularly preferably transparent to light emitted from the quantum well layer. In the case of a light emitting device based on a group III-V nitride such as InAlGaN, it is desirable to contain In or Al to such an extent that light emitted from the active layer structure is not absorbed. It is preferable to contain.

  Further, the light homogenizing layer does not need to be a single layer, and may be composed of a plurality of layers. When composed of a plurality of layers, for example, a plurality of layers such as AlGaN, InGaN, InAlGaN, AlN, and GaN may exist, or a superlattice structure may be used. In addition, a structure such as a quantum dot may be included, and in the case of having a size approximately equal to the emission wavelength of the element, it is possible to induce light scattering. Furthermore, the light uniformizing layer is grown into a thin film crystal, the crystal growth is interrupted once, and the surface is appropriately roughened, etc., and further thin film crystal growth is performed to appropriately scatter light, multiple reflections, thin film interference, etc. It is also possible to cause

Here, the average refractive index (nav) of each layer is the product of the refractive index (nx) of each of the n types of materials constituting the layer and the physical thickness (tx) of the material. Is divided by the total thickness,
nav = (n1 × t1 + n2 × t2 +... + nn × tn) / (t1 + t2 +... + tn)

As an example of the light homogenizing layer, for example, the active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is n-GaN, and the buffer layer Is undoped GaN and the substrate is sapphire, a single layer of undoped GaN can be used as the light uniformizing layer. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

The active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is composed of n-GaN and n-AlGaN layers, and the buffer layer is When the laminated structure of undoped GaN and Si-doped GaN and the substrate is sapphire, a single layer of undoped GaN can be used as the light uniformizing layer. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

The active layer structure has _a quantum well layer having a composition of In _a Ga _1-a N, the emission wavelength is 460 nm, the first conductivity type cladding layer is composed of n-GaN and n-AlGaN layers, and the buffer layer is When undoped GaN and Si-doped GaN are laminated, and the substrate is Si-doped GaN, In _b Ga _1-b N having a composition transparent to the emission wavelength is desired in the thick undoped GaN as the light uniformizing layer A multilayer structure having a desired number of thicknesses can be used. In general, the refractive index of a semiconductor material at a wavelength transparent to the material tends to decrease as the carrier concentration increases.

In such a structure, it is desirable that the light homogenizing layer further includes materials such as In _b Ga _1-b N and In _c Al _d Ga _1-cd N, and the composition b, c, d N-GaN that is transparent at a wavelength of 460 nm and may be included in the first conductivity type semiconductor layer, undoped GaN that may be included in the buffer layer, and as a substrate Since the refractive index can be larger than that of certain sapphire, GaN, etc., it can be used as a light uniformizing layer, and they may be used as a single layer or as a plurality of laminated structures selected from them and an undoped GaN layer .

  It is also preferable that the light homogenizing layer has a superlattice / quantum well structure composed of an InGaN layer and a GaN layer in which the In composition and the thickness of the InGaN layer are set so as not to absorb the emission wavelength of the compound semiconductor light emitting device.

  It is also important that the thickness of the light homogenizing layer is selected so that it functions as a multimode optical waveguide that receives a part of the light emitted from the quantum well layer and propagates the light in the layer.

The physical thickness of the light homogenizing layer is represented by t _oc (nm), the emission wavelength of the light emitting element is λ (nm), the average refractive index of the light homogenizing layer is n _oc , and the average refractive index of the first conductivity type semiconductor layer _Is expressed as n ₁ , and the average refractive index of the substrate is expressed as n _sb , the relative refractive index difference Δ _(oc−1) between the light uniformizing layer and the first conductive type semiconductor layer is expressed as Δ _(oc−1) ≡ ((n ^{_{oc) 2 - (n 1)}} 2) / (2 × (n oc) 2)
It is defined as Further, the relative refractive index difference Δ _(oc−sb) between the light uniformizing layer and the substrate is expressed by Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × (n _oc ) ² )
It is defined as If the light uniformizing layer is regarded as a symmetrical slab waveguide sandwiched by the average refractive index of the first conductivity type semiconductor layer, the condition for the waveguide to be multimode is that the normalized frequency is π / 2 or more. (√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
It is desirable that t _oc be selected to satisfy At the same time, if the light uniformizing layer is regarded as a symmetrical slab waveguide sandwiched by the average refractive index of the substrate, the condition for the waveguide to become multimode is that the normalized frequency is π / 2 or more. (√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
It is desirable that t _oc is selected so as to satisfy.

  Specifically, for example, if the average refractive index of the light uniformizing layer is 2.50 and the average refractive index of the substrate is 1.70 at a wavelength of 460 nm, the thickness of the light uniformizing layer is about 0. If it is .13 μm or more, the above formula is satisfied. For example, if the average refractive index of the light uniformizing layer is 2.50 at the wavelength of 460 nm and the average refractive index of the first conductive semiconductor layer is 2.499, the thickness of the light uniformizing layer is as follows: If it is about 3.3 μm or more, the above formula is satisfied. As described above, the thickness of the light uniformizing layer can be appropriately selected depending on the average refractive index of the substrate, the average refractive index of the light uniformizing layer, and the average refractive index of the first conductivity type semiconductor layer when the substrate is provided. However, generally, 1 to 7 μm is preferable, and 3 to 5 μm is more preferable.

  In this way, light confinement and gentle leakage are realized, and depending on the structure, a light emitting device is realized by realizing a multimode waveguide that also exhibits effects such as light scattering, multiple reflection, and thin film interference. It becomes easy to realize uniform light emission on the surface on the first light extraction direction side.

  Note that if light is extremely confined in the light homogenization layer, the light emitting element improves the uniformity of light emission but makes it difficult to extract light. Therefore, the thickness, material, structure, configuration, and refraction of the light homogenization layer are difficult. It is preferable to appropriately select a ratio and the like so that wave guide is generated while being leaky to some extent. In particular, regarding the thickness, it is not desirable that the thickness of the light uniformizing layer is extremely increased and the optical confinement of the waveguide is excessive. For example, the upper limit is preferably 30 μm or less, and is preferably 10 μm or less. More desirably, it is most desirably 5 μm or less.

The light uniformizing layer of the type A light-emitting element may be either conductive or insulating, but insulating is preferable in terms of more reliably preventing a short circuit due to solder or the like. For example, the specific resistance ρ _oc (Ω · cm) of the entire layer is preferably 0.5 (Ω · cm) or more. More preferably, it is 1.0 (Ω · cm) or more, more preferably 1.5 (Ω · cm) or more, and most preferably 5 (Ω · cm) or more. In order to have a high specific resistance, the light uniformizing layer is preferably undoped. Further, in the case where the light uniformizing layer is composed of a plurality of layers, there is no problem as long as there is a partially doped layer between the undoped layers. In this case, the layer adjacent to the first conductivity type semiconductor layer (for example, the first conductivity type clad layer) may have the above specific resistance. In general, in a semiconductor, in a wavelength region transparent to a material, the refractive index of an undoped layer is intentionally doped and the refractive index is higher than that of a layer having a large number of carriers even in the same material. Therefore, the undoped layer is preferable from the viewpoint of optical characteristics and electrical characteristics. In particular, when the light uniformizing layer is an exposed portion at the device end, the exposed portion is preferably an undoped portion. Thereby, the insulation failure by the solder | pewter etc. at the time of apparatus assembly can be suppressed.

  In the type A light emitting device, the light homogenizing layer distributes and distributes light, whereas the buffer layer described above is intended to reduce various mismatches when crystals grow on the substrate. The function is different. However, the same layer may have two functions at the same time. In addition, when the light uniformizing layer or the buffer layer includes a plurality of layers, some layers may have two functions. Furthermore, even if the composition is the same, if the growth method and conditions are different, only one function may be provided.

  Further, in the type A light emitting device, the exposed side surface of the light uniformizing layer is covered with an insulating layer. Thereby, when the light emitting element is flip-chip mounted on a submount or the like, it is possible to prevent the occurrence of a short circuit due to soldering on the side wall of the thin film crystal layer.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
In a typical embodiment of a type A light emitting device, a first conductivity type cladding layer 24 is in contact with the light uniformizing layer 23 as shown in FIG. 1-1A. The first conductivity type clad layer 24 functions together with the second conductivity type clad layer 26 to be described later to the active layer structure 25 to be described later, efficiently injects carriers, and overflow from the active layer structure 25 also occurs. It has a function to suppress and realize light emission in the quantum well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The first conductivity type semiconductor layer includes a layer doped to the first conductivity type in addition to the above-mentioned layer having a cladding function, for the purpose of improving the function of the device or for manufacturing reasons, like a contact layer. . In a broad sense, the entire first conductivity type semiconductor layer may be considered as the first conductivity type cladding layer, and in this case, the contact layer and the like can also be regarded as a part of the first conductivity type cladding layer.

  In general, the first conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the active layer structure described later and a material larger than the average band gap of the active layer structure described later. It is desirable. Furthermore, the first conductivity type cladding layer is generally made of a material that forms a so-called type I band lineup in relation to the barrier layer in the active layer structure. Under such guidelines, the first conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure, and the like prepared for realizing a desired emission wavelength.

  For example, when C + plane sapphire is used as a substrate and a laminated structure of low-temperature grown GaN and high-temperature grown GaN is used as a buffer layer, a GaN-based material, an AlGaN-based material, an AlGaInN-based material is used as the first conductivity type cladding layer. A material, an InAlBGaN-based material, or a multilayer structure thereof can be used.

The carrier concentration of the first conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 5 × 10 ¹⁷ cm ⁻³ or more, and most preferably 1 × 10 ¹⁸ cm ⁻³ or more. The upper limit is preferably 5 × 10 ¹⁹ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ⁻³ or less, and most preferably 7 × 10 ¹⁸ cm ⁻³ or less. Here, when the first conductivity type is n-type, Si is most desirable as a dopant.

  In the example of FIG. 1-1A, the structure of the first conductivity type cladding layer shows a first conductivity type cladding layer composed of a single layer, but the first conductivity type cladding layer is composed of two or more layers. There may be. In this case, for example, a GaN-based material and an AlGaN-based material, an InAlGaN-based material, an InAlBGaN-based material, or an AlN-based material can be used. Further, the entire first conductivity type cladding layer may be a superlattice structure as a laminated structure of different materials. Furthermore, it is also possible to change the above-mentioned carrier concentration in the first conductivity type cladding layer.

  In the portion of the first conductivity type clad layer that is in contact with the first conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  A part of the first conductivity type cladding layer is etched, and the exposed side wall, the etched part, etc. of the first conductivity type cladding layer are in contact with the first conductivity type side electrode described later. A structure in which all except one current injection region is covered with an insulating layer is desirable.

  In addition to the first conductivity type cladding layer, a different layer may exist as necessary as the first conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in the connection portion with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

<Active layer structure>
An active layer structure 25 is formed on the first conductivity type cladding layer 24. The active layer structure is a layer that emits light by recombination of electrons and holes (or holes and electrons) injected from the above-described first conductivity type cladding layer and the second conductivity type cladding layer described later. A structure including a quantum well layer and including a barrier layer disposed adjacent to the quantum well layer or disposed between the quantum well layer and the cladding layer. Here, in order to realize high output and high efficiency, which are one object of the present invention, when the number of quantum well layers in the active layer structure is W and the number of barrier layers is B, B = W + 1 is preferably satisfied. That is, the relationship between the cladding layer and the entire layer of the active layer structure is formed as “first conductivity type cladding layer, active layer structure, second conductivity type cladding layer”, and the active layer structure is defined as “barrier layer, quantum well. It is desirable for high output to be formed as “layer, barrier layer” or “barrier layer, quantum well layer, barrier layer, quantum well layer, barrier layer”. FIG. 1-4 schematically shows a structure in which five quantum well layers and six barrier layers are stacked.

  Here, in the quantum well layer, the layer thickness is as thin as the de Broglie wavelength in order to express the quantum size effect and increase the light emission efficiency. For this reason, in order to achieve high output, it is desirable to provide not only a single quantum well layer but also a plurality of quantum well layers and separate them into an active layer structure. At this time, a layer that is separated while controlling the coupling between the quantum well layers is a barrier layer. In addition, it is desirable that the barrier layer exists for separation of the cladding layer and the quantum well layer. For example, when the cladding layer is made of AlGaN and the quantum well layer is made of InGaN, a form in which a barrier layer made of GaN exists between them is desirable. This is also desirable from the viewpoint of thin film crystal growth because it can be easily changed when the optimum temperature for crystal growth is different. When the clad layer is made of InAlGaN having the widest band gap and the quantum well layer is made of InAlGaN having the narrowest band gap, InAlGaN having an intermediate band gap can be used for the barrier layer. Furthermore, in general, the difference in the band gap between the cladding layer and the quantum well layer is larger than the difference in the band gap between the barrier layer and the quantum well layer, and considering the efficiency of carrier injection into the quantum well layer, The quantum well layer is preferably not directly adjacent to the cladding layer.

  It is desirable that the quantum well layer is not intentionally doped. On the other hand, it is desirable to dope the barrier layer to reduce the resistance of the entire system. In particular, the barrier layer is preferably doped with an n-type dopant, particularly Si. This is because Mg, which is a p-type dopant, easily diffuses in the device, and it is important to suppress the diffusion of Mg during high output operation. Therefore, Si is effective, and it is desirable that the barrier layer is doped with Si. However, it is preferable not to perform doping at the interface between the quantum well layer and the barrier layer.

  The active layer structure side wall of one device is preferably covered with an insulating layer 30 as shown in FIG. 1-1A. In this way, when the manufactured element is flip-chip bonded, there is an advantage that a short circuit due to solder or the like does not occur on the side wall of the active layer structure.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductivity type cladding layer 26 efficiently injects carriers into the aforementioned active layer structure 25 together with the aforementioned first conductivity type cladding layer 24 and suppresses overflow from the active layer structure. It has a function for realizing light emission in the well layer with high efficiency. In addition, it contributes to confinement of light in the vicinity of the active layer structure, and has a function for realizing light emission in the quantum well layer with high efficiency. The second conductivity type semiconductor layer includes a layer doped to the second conductivity type in addition to the above-mentioned layer having a cladding function, for the purpose of improving the function of the device or for manufacturing reasons, like a contact layer. . In a broad sense, the entire second conductivity type semiconductor layer may be considered as the second conductivity type cladding layer. In that case, the contact layer or the like can also be regarded as a part of the second conductivity type cladding layer.

  In general, the second conductivity type cladding layer is made of a material having a refractive index smaller than the average refractive index of the active layer structure described above and a material larger than the average band gap of the active layer structure described above. It is desirable. Furthermore, the second conductivity type clad layer is generally made of a material that forms a so-called type I band lineup, particularly in relation to the barrier layer in the active layer structure. Under such guidelines, the second conductivity type cladding layer material can be appropriately selected in view of the substrate, buffer layer, active layer structure and the like prepared for realizing a desired emission wavelength. For example, when C + plane sapphire is used as the substrate and GaN is used as the buffer layer, GaN-based material, AlN-based material, AlGaN-based material, AlGaInN-based material, AlGaBInN-based material, etc. are used as the second conductivity type cladding layer. Can be used. Further, a laminated structure of the above materials may be used. Also, the first conductivity type cladding layer and the second conductivity type cladding layer can be made of the same material.

The carrier concentration of the second conductivity type cladding layer is preferably 1 × 10 ¹⁷ cm ⁻³ or more as a lower limit, more preferably 4 × 10 ¹⁷ cm ⁻³ or more, and further preferably 5 × 10 ¹⁷ cm ⁻³ or more. × 10 ¹⁷ cm ⁻³ or more is most preferable. Preferably 7 × ¹⁰ 18 ^{cm -3} or less as an upper limit, more preferably 3 × ¹⁰ 18 ^{cm -3} or less, and most preferably 2 × ¹⁰ 18 ^{cm -3} or less. Here, Mg is most desirable as the dopant when the second conductivity type is p-type.

  The structure of the second conductivity type cladding layer is an example of a single layer formed in the example of FIG. 1-1A. However, the second conductivity type cladding layer is composed of two or more layers. May be. In this case, for example, a GaN-based material and an AlGaN-based material can be used. The entire second conductivity type cladding layer may be a superlattice structure composed of a laminated structure of different materials. Furthermore, it is possible to change the carrier concentration described above in the second conductivity type cladding layer.

  In general, in a GaN-based material, when the n-type dopant is Si and the p-type dopant is Mg, the crystallinity of p-type GaN, p-type AlGaN, and p-type AlInGaN is n-type GaN, n It does not reach each of type AlGaN and n-type AlInGaN. Therefore, in device fabrication, it is desirable to implement a p-type cladding layer with poor crystallinity after crystal growth of the active layer structure. From this viewpoint, the first conductivity type is n-type and the second conductivity type is p-type. Is desirable.

  In addition, it is desirable that the thickness of the p-type cladding layer with poor crystallinity (which corresponds to the second conductivity type cladding layer in the case of taking a desirable form) is somewhat thin. This is because, in a type A light emitting device that performs flip-chip bonding, the substrate side is the first light extraction direction, so there is no need to consider the light extraction from the second conductivity type side electrode described later. It is possible to form a large-area thick film electrode. For this reason, it is not necessary to expect current diffusion in the lateral direction in the second conductivity type side cladding layer as in face-up mounting, and the second conductivity type side cladding layer may be thinned to some extent. It is also advantageous from the structure. However, when it is extremely thin, the carrier injection efficiency is lowered, and therefore there is an optimum value. The thickness of the second conductivity type side cladding layer can be selected as appropriate, but is preferably 0.05 μm to 0.3 μm, and most preferably 0.1 μm to 0.2 μm.

  In the portion of the second conductivity type clad layer that is in contact with the second conductivity type side electrode, the carrier concentration can be intentionally increased to reduce the contact resistance with the electrode.

  It is desirable that the exposed side wall of the second conductivity type cladding layer be entirely covered with an insulating layer except for a second current injection region that realizes contact with the second conductivity type side electrode described later.

  Furthermore, in addition to the second conductivity type cladding layer, a different layer may exist as necessary as the second conductivity type semiconductor layer. For example, a contact layer for facilitating carrier injection may be included in a portion in contact with the electrode. Each layer may be divided into a plurality of layers having different compositions or formation conditions.

  In addition, unless it is contrary to the summary of this invention, you may form the layer which does not enter into the above-mentioned category as needed as a thin film crystal layer.

<Second conductivity type side electrode>
The second conductivity type side electrode realizes a good ohmic contact with the second conductivity type nitride compound semiconductor, and becomes a reflection mirror in a good emission wavelength band when flip-chip mounted, When flip-chip mounting is performed, good adhesion to a submount using a solder material or the like is realized. For this purpose, the material can be selected as appropriate, and the second conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  Further, when the second conductivity type is p-type and the second conductivity type side electrode side of the second conductivity type side cladding layer is GaN, Ni, Pt, Pd, A material containing either Mo or Au or two or more elements thereof is preferable. This electrode may have a multilayer structure, and at least one layer is formed of a material containing the above element, and preferably each layer is made of a material containing the above element and having different constituent components (type and / or ratio). The electrode constituent material is preferably a single metal or an alloy.

  In a particularly preferred embodiment, the first layer on the p-side cladding layer side of the second conductivity type side electrode is Ni, and the surface of the second conductivity type side electrode opposite to the p-side cladding layer side is Au. This is because Ni has a large work function absolute value, which is convenient for p-type materials, and Au is preferable as the outermost surface material in consideration of resistance to process damage described later, mounting convenience, and the like.

  The second conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the second conductivity type carrier can be injected. For example, when the second conductivity type side contact layer is provided, the second conductivity type side electrode is in contact with it. Formed.

<First conductivity type side electrode>
The first-conductivity-type-side electrode achieves good ohmic contact with the first-conductivity-type nitride compound semiconductor, and when flip-chip mounted, it becomes a reflection mirror in a good emission wavelength band, When chip mounting is performed, good adhesion to a submount using a solder material or the like is realized. For this purpose, a material can be appropriately selected. The first conductivity type side electrode may be a single layer or a plurality of layers. In general, in order to achieve a plurality of purposes required for an electrode, a plurality of layer structures are usually employed.

  If the first conductivity type is n-type, the n-side electrode is preferably made of Ti, Al, Ag, Mo, or a material containing two or more elements thereof. This electrode may have a multilayer structure, and at least one layer is formed of a material containing the above element, and preferably each layer is made of a material containing the above element and having different constituent components (type and / or ratio). The electrode constituent material is preferably a single metal or an alloy. These are because the absolute value of the work function of these metals is small. Further, Al is usually exposed on the side opposite to the first light extraction direction of the n-side electrode.

  In the type A light emitting device, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially separated. It is desirable that there is no overlap. This is because when the light emitting element is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while ensuring a sufficient area to ensure sufficient adhesion with the submount or the like. It is important to ensure a sufficient interval to prevent an unintended short circuit due to a solder material or the like.

  Here, the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode is in contact with the insulating layer is preferably 15 μm or more. This is because a margin is required in the process of forming the first conductivity type side electrode, which is preferably formed by a photolithography process and a lift-off method.

  The first conductivity type side electrode may be in contact with any layer of the thin film crystal layer as long as the first conductivity type carrier can be injected. For example, when the first conductivity type side contact layer is provided, the first conductivity type side electrode is in contact with it. Formed.

<Insulating layer>
When the flip-chip mounting is performed, the insulating layer 30 has a mounting solder, a conductive paste material or the like “between the second conductive type side electrode and the first conductive type side electrode” or “a thin film such as an active layer structure”. This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer”. The structure and shape are as described above.

The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation. For example, single layer oxides, nitrides, fluorides and the like are preferable. Specifically, SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF It is preferably selected from _{x 1} , CaF _x , SrF _x , MgF _{x and the} like. These can secure insulating properties stably over a long period of time.

  On the other hand, the insulating layer 30 can be a multilayer film of an insulator. This is because since the dielectric multilayer film is used, an optical function can be expressed with respect to light generated in the light emitting element by appropriately adjusting the refractive index of the dielectric in the insulating layer.

Further, considering the stability of the material and the range of refractive index, it is desirable that the dielectric film contains fluoride, and specifically, AlF _x , BaF _x , CaF _x , SrF _x , MgF It is desirable that any of _x is included.

<Submount>
The submount 40 has a metal layer and has both functions of current injection and heat dissipation to the flip chip mounted device. The base material of the submount is preferably one of metal, AlN, SiC, diamond, BN, and CuW. These materials are desirable because they are excellent in heat dissipation and can effectively suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as submount base materials. When the submount base material is selected from metals, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, when covered with a dielectric such as, _SiN x was formed by various CVD methods, SiO ₂ or the like is desirable.

  The light emitting element is bonded to the metal layer on the submount by various solder materials and paste materials. In order to sufficiently secure heat dissipation for high output operation and high efficiency light emission of the element, it is particularly desirable to join with metal solder. Examples of the metal solder include In, InAg, PbSn, SnAg, AuSn, AuGe, and AuSi. These solders are stable and can be appropriately selected in light of the operating temperature environment.

  It is also possible to mount a plurality of type A light emitting elements on one submount. By freely changing the metal wiring on the submount, the light emitting elements on one submount can be connected in parallel. Alternatively, they can be connected in series, or they can be mixed.

  [Method for Manufacturing Type A Light-Emitting Element]

  Next, a method for manufacturing a type A light emitting device will be described. A manufacturing method of a representative form will be described.

<Embodiment 1 of Manufacturing Method>
In Embodiment 1 of the manufacturing method, a method for manufacturing the light-emitting element shown in FIGS. 1-1C and 1-1D will be described mainly using the light-emitting element shown in FIG. 1-1A. As shown in FIG. 1-5, first, a substrate 21 is prepared, and a buffer layer 22, a light homogenizing layer 23, a first conductivity type cladding layer 24, an active layer structure 25, and a second conductivity type cladding layer 26 are formed on its surface. Films are sequentially formed by thin film crystal growth. The MOCVD method is preferably used for forming these thin film crystal layers. However, the MBE method, the PLD method, the PED method, the VPE method, the LPE method, and the like can also be used to form the entire thin film crystal layer or a part of the thin film crystal layer. These layer configurations can be appropriately changed according to the purpose of the element. Further, after the formation of the thin film crystal layer, various kinds of treatments may be performed. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  In order to realize the shapes shown in FIGS. 1-1A, 1-1B, and 1-3A in the present invention after the thin film crystal layer growth, as shown in FIG. It is preferable to form the electrode 27. That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. When the p-type electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface when the second conductivity type is p-type as a desirable form, this is compared with GaN-based materials. This is because the hole concentration in the p-GaN clad layer with a low effective activation rate is lowered by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. Therefore, after the thin film crystal growth, the formation of the second conductivity type side electrode may be performed in other process steps (for example, a first etching step, a second etching step, or an insulating layer forming step, which will be described later, the exposed portion of the second conductivity type side electrode). It is desirable to carry out prior to the forming step, the first current injection region forming step, the first conductivity type side electrode forming step, and the like.

  Further, in the case where the second conductivity type is p-type in the type A light emitting element, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a representative example. In the case where the surface is a relatively stable metal such as Au, the possibility of process damage is low even after the subsequent process. Also from this point of view, in the manufacture of the type A light emitting device, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  Similarly, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer can be reduced.

  Various film formation techniques such as sputtering, vacuum deposition, and plating can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique or a metal A place-selective vapor deposition using a mask or the like can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 1-6, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, since the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask as will be described in detail in the second etching step described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, the process damage received by the second conductivity type side electrode is reduced.

  Next, as shown in FIGS. 1-7, an inter-device separation groove 13 is formed by a second etching step. In the type A light-emitting element, the inter-device separation groove needs to be formed by dividing at least the first conductivity type cladding layer. In this embodiment, the inter-device separation groove 13 reaches the substrate 21. Formed as follows. In this case, in order to separate the device, the GaN-based material on the sapphire substrate is peeled off even when diamond scribing is performed from the side where the thin film crystal layer is formed in the process of scribing, breaking, etc. It is possible to suppress. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to form an inter-device separation groove by etching up to a part of a sapphire substrate (the same applies to other substrates such as GaN).

  On the other hand, a mode in which the inter-device separation groove does not reach the substrate is also a preferable mode. For example, if the inter-device separation groove is formed up to the middle of the combined layer of the light uniformizing layer and the buffer layer, an insulating layer can be formed on the side wall of the first conductivity type cladding layer, Insulation can be maintained against wraparound (see FIGS. 1-1C and 1-1D for the form after the light-emitting element is completed). In this case, the bottom surface of the groove is formed in the middle of the combined layer of the light uniformizing layer and the buffer layer, and this becomes an end step surface at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Since the bottom surface of the groove is subjected to processing such as scribing at the time of element separation, the end step surface after element separation is often not high in terms of planarity as a surface and parallelism with the layer direction. Moreover, it is preferable that the layer exposed from the side wall without being covered with the insulating layer has high insulating properties.

  In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. In general, the sum of the layers etched by the first etching step is usually about 0.5 μm. However, in the second etching step, all of the first conductivity type cladding layer 24, the light uniformizing layer 23 and the buffer are formed. Since it is necessary to etch at least a part of the layer 22, in some cases, it may be 3 to 7 μm, and in some cases, it may be in the range of 3 to 10 μm, or even 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that requires etching of the system material, a relatively thick SiN _x film is required. For example, when a 10 μm GaN-based material is etched in the second dry etching step, a SiN _x mask exceeding 2 μm is required. However, at the SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the inter-device separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first and second etching steps, while it can be easily etched for patterning etching (preferably wet etching). In addition, a patterning shape, particularly one having good linearity in the side wall portion is required. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in controllability of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, when a mask such as SrF ₂ is exposed to plasma such as chlorine during dry etching of a semiconductor layer, the etching rate at the time of subsequent mask layer removal is lower than before exposure to plasma such as chlorine. Have a tendency to For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _1-16, SiN x, SiO ₂ or the like mask 51, Even if it does not exist in the entire lower part of the metal fluoride mask layer 52, it is sufficient if it is formed on a material that is at least sensitive to acids.

  By such a second etching step, an inter-device separation groove 13 is formed as shown in FIGS. 1-7.

Note that the first etching step and the second etching step may be performed either first or later. In order to simplify the process, it is also preferable to perform the first etching step first and then perform the second etching step without removing the etching mask at that time. As shown in FIG. 1-16, first, a first etching mask 51 is formed of an acid-resistant material such as SiN _x and SiO ₂ (preferably SiN _x ), and etching is performed so that the first conductivity type cladding layer 24 appears. The second etching mask 52 made of a metal fluoride layer is formed without removing the mask 51. And after implementing a 2nd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the device manufacturing process and further for securing the scribe region.

  The “recessed side wall surface” defined in the description of Type A is a side wall surface that appears as a side wall in the second etching step, that is, the formation of an inter-device separation groove, and is not a wall surface that appears only in the first etching.

  After the second etching step, an insulating layer 30 is formed as shown in FIGS. 1-8. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

Next, as shown in FIG. 1-9A, a predetermined portion of the insulating layer 30 is removed, and the second conductive type side electrode exposed portion 37 from which the insulating layer is removed on the second conductive type side electrode 27, the first conductive type. A first current injection region 36 from which the insulating layer has been removed is formed on the mold cladding layer, and a scribe region 14 from which the insulating layer has been removed is formed in the inter-device isolation trench 13. The removal of the insulating layer 30 on the second conductivity type side electrode 27 is performed so that the peripheral portion of the second conductivity type side electrode is covered with the insulating layer. That is, the surface area of the exposed portion of the second conductivity type side electrode is smaller than the area of the second current injection region. Here, in order to prevent the occurrence of an unintended short circuit due to a margin of the element manufacturing process, particularly a photolithography process, or a solder material, a part of the second conductivity type side electrode covered with an insulating layer The width (L _2w ) of the narrowest portion is preferably 15 μm or more as described above. More desirably, it is 100 μm or more. By covering most of the area of the second conductivity type side electrode with the insulating layer, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode due to the metal solder material.

For the removal of the insulating layer, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer is a single layer of SiN _x , dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

As already described, the width of the scribe region 14 can be set so as to obtain a predetermined L _ws .

  Further, the second conductivity type side electrode exposed portion 37, the first current injection region 36, and the scribe region 14 may be formed separately, but are usually formed by etching at the same time. Even when the inter-device separation groove is formed up to the middle of the combined layer of the light uniformizing layer and the buffer layer, when the insulating layer is deposited by the above process, it is deposited not on the substrate surface but on the groove bottom surface. However, the same process can be adopted.

Next, as shown in FIGS. 1-10, the first conductivity type side electrode 28 is formed. In this embodiment, the first conductivity type side electrode is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode and the second conductivity type side electrode are spatially overlapped. The feature is not to. This is because when the element is flip-chip mounted with solder or the like, the second conductivity type side electrode and the first conductivity type side electrode are secured while securing a sufficient area to ensure sufficient adhesion with the submount or the like. It is important to ensure a sufficient interval to prevent an unintended short circuit due to a solder material or the like. Among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer, the width (L _1w ) of the narrowest portion is set to be in the above-described range. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from any one of Ti, Al, Ag, and Mo. Further, Al is usually exposed in the direction facing the first light extraction direction of the n-side electrode.

  Various film formation techniques such as sputtering, vacuum evaporation, plating, etc. can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique, a metal mask, or the like was used. Site selective vapor deposition or the like can be used as appropriate.

  In this example, the first conductivity type side electrode is formed so as to be in contact with a part of the first conductivity type cladding layer. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact with the first conductivity type side electrode. Can do.

  In the manufacturing method of the present invention, the first conductivity type side electrode is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is formed with Al on the surface of the electrode material in a preferred embodiment. In this case, if the n-side electrode is formed before the formation of the insulating layer like the second conductivity type side electrode, the surface of the n-side electrode, that is, the Al metal, has a history of the etching process of the insulating layer. Become. As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching an insulating layer, but Al has low resistance to various etchants including hydrofluoric acid, and such a process is effectively performed. Then, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in this embodiment, the formation of the first conductivity type side electrode after the formation of the insulating layer and after the removal of the unnecessary portion scheduled for the insulating layer is effective in reducing damage to the electrode.

  After the structure of FIG. 1-10 is formed in this manner, the inter-device separation grooves are used to damage the substrate by diamond scribe to separate each compound semiconductor light emitting element one by one. A part of the substrate material is ablated by laser scribing.

  In addition, the inter-device separation groove may be formed up to the middle of the combined layer of the light uniformizing layer and the buffer layer. In this case as well, the inter-device separation groove is used for the substrate. Abrasion by diamond scribe and ablation of a part of the substrate material by laser scribe are performed.

  In this embodiment, since there is no thin film crystal layer that affects the performance in the inter-device isolation groove during the element isolation step, process damage is not introduced into the thin film crystal layer. In addition, since there is no insulating layer in the scribe region, there is no possibility that the insulating layer is peeled off during scribing.

  After the scribe is completed, the compound semiconductor light-emitting element is divided into one device at a time in the braking process, and is preferably mounted on the submount with a solder material or the like.

  As described above, the light-emitting element shown in FIG. 1-1A is completed. Similarly, the light emitting device shown in FIGS. 1-1C and 1-1D can also be manufactured.

  In this manufacturing method, as described, formation of a thin film crystal layer, formation of a second conductivity type side electrode, etching process (first etching process and second etching process), formation of an insulating layer, removal of the insulating layer (second conductivity) The formation of the mold side electrode exposed portion, the formation of the first current injection region, the formation of the scribe region) and the formation of the first conductivity type side electrode are preferably performed in this order. A light-emitting element can be obtained in which the thin film crystal layer directly under the side electrode is not damaged and the first conductivity type side electrode is not damaged. The device shape reflects the process flow. That is, this light emitting element has a structure in which the second conductivity type side electrode, the insulating layer, and the first conductivity type side electrode are laminated in this order. In other words, the second conductivity type side electrode is in contact with the second conductivity type clad layer (or other second conductivity type thin film crystal layer) without an insulating layer interposed, There is a portion covered with an insulating layer, and an insulating layer is interposed between the first conductivity type side electrode and the first conductivity type side cladding layer (or other first conductivity type thin film crystal layer) around the electrode. There is a part that is.

<Embodiment 2 of Manufacturing Method>
In Embodiment 2 of the manufacturing method, a method for manufacturing the light-emitting element shown in FIGS. 1-2C, 1-2D, and 1-2E will be described mainly using the light-emitting element shown in FIG. 1-2A. In the second embodiment, the process up to the formation of the insulating layer 30 in the first embodiment is the same (FIGS. 1-5 to 1-8). Thereafter, in the first embodiment, only the region including the central part of the inter-device separation groove on the substrate surface (groove bottom surface) is removed. However, in the second embodiment, as shown in FIG. Then, all of the insulating layer 30 on the substrate 21 (that is, the bottom surface of the groove) is removed, and the insulating layer on the substrate side (that is, the bottom surface side of the groove) of the insulating layer formed on the side wall in the groove is removed. The formation portion 15 is used. As a forming method, the following process is possible. First, a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device separation trench 13 is formed by photolithography, and then wet etching is performed using an etchant that can etch the insulating layer. Removal of the insulating layer on the substrate surface in the groove proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer covering the substrate side of the trench side wall is removed with a wet etchant. As shown in FIG. 1-9B, the insulating layer exists on the side wall on the substrate side. A shape that does not occur is obtained.

  The side wall exposed by removing the insulating layer is at least a portion of the side wall of the buffer layer on the substrate side. In some embodiments, the entire side wall of the buffer layer 22 may be exposed. You may expose at least one part of a side wall. When part of the side wall of the light homogenizing layer 23 is exposed, the side wall of the buffer layer is exposed in FIG. 1-2A, and the insulating layer ratio forming portion in FIG. It reaches to the side wall. The exposed side wall where the insulating layer is not present is preferably the side wall of the undoped layer. This is because, when flip chip mounting is performed, an unintended electrical short circuit does not occur even if solder for bonding with the submount adheres to the side wall. Such a removed shape of the insulating layer is a desirable shape because an unintended defect such as peeling of the insulating layer does not occur accompanying the removal of the substrate, particularly during the manufacturing process of the light emitting element. In addition, when the inter-device separation groove is formed by etching up to a part of the substrate, only the substrate portion of the wall surface of the groove is exposed and the buffer layer may be covered with an insulating layer.

  As in the first embodiment, the second conductivity type side electrode exposed portion 37, the first current injection region 36, and the insulating layer non-formed portion 15 may be formed separately, but are usually formed simultaneously by etching. .

  Thereafter, the light-emitting element shown in FIG. 1-2A can be completed by a process similar to that of Embodiment 1.

  In the second embodiment of the manufacturing method, similarly to the first embodiment, a mode in which the inter-device separation groove does not reach the substrate is also a preferable mode. For example, if the inter-device separation groove is formed up to the middle of the combined layer of the light uniformizing layer and the buffer layer, an insulating layer can be formed on the side wall of the first conductivity type cladding layer, It is possible to maintain insulation against the wraparound (forms after the light emitting element is completed are FIGS. 1-2C, 1-2D, and 1-2E). In this case, the bottom surface of the groove is formed in the middle of the combined layer of the light uniformizing layer and the buffer layer, and this becomes an end step surface at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Moreover, it is preferable that the layer exposed from the side wall without being covered with the insulating layer has high insulating properties. When the insulating layer 30 is deposited, the same process can be adopted although the insulating layer 30 is deposited not on the substrate surface but on the groove bottom surface. Otherwise, the light emitting device shown in FIGS. 1-2C, 1-2D, and 1-2E can be manufactured in the same manner as in the second embodiment. The difference in shape between FIGS. 1-2D and 1-2E is controlled by adjusting the side etching time and the like.

  The light-emitting element manufactured by the process of Embodiment 2 (and its deformation process) is also a device in which the insulating layer covering the side wall has a shape that does not reach the end of the light-emitting element, and the insulating layer does not peel off By configuring the exposed layer with a highly insulating material, the device can be as reliable as the light emitting element in the form of FIG. 1-1A.

<< 2-2. Type B >>
The characteristics of the type B light emitting element are specified by the following matters.

1. A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenizing layer between the buffer layer and the first conductivity type semiconductor layer for improving uniformity of light emitted from the surface on the first light extraction direction side;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. And having an insulating layer formed at a position away from the light emitting element end, or (ii) the light uniform When the buffer layer and the buffer layer both form a receding side wall surface and have no end step surface, the buffer layer is not formed at least on the first light extraction direction side portion of the buffer layer. Having an insulating layer covering the receding sidewall surface from the middle or from the middle of the light homogenizing layer;
The compound semiconductor light-emitting element further comprising a support body to which the first conductivity-type side electrode and the second conductivity-type side electrode are connected to support the light-emitting element.

2. For the receding sidewall surface of the thin film crystal layer,
(Ii) The light homogenizing layer and the buffer layer both form a receding side wall surface and have no end step surface,
The insulating layer covering the receding side wall surface from the middle of the buffer layer or from the middle of the light homogenizing layer without being formed at least in the first light extraction direction side portion of the buffer layer. 2. The light emitting device according to 1 above.

3. For the receding sidewall surface of the thin film crystal layer,
(I): A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. It is a shape that forms an end step surface with the non-retreating side wall surface that is not, and at least an insulating layer formed from a position away from the light emitting element end,
2. The light emitting device according to claim 1, wherein the insulating layer covers at least a part of the receding side wall surfaces of the light homogenizing layer and the buffer layer, but is not formed on the end step surface. element.

4). For the receding sidewall surface of the thin film crystal layer,
(I): A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer It is a shape that forms an end step surface between the non-retreated non-retreated side wall surface, and at least an insulating layer formed from a position away from the light emitting element end,
2. The light emitting device according to 1 above, wherein the insulating layer covers a surface on an end step surface from a position away from an end of the light emitting element and a surface coinciding with a side wall receding surface of the first conductivity type semiconductor layer. element.

  5). 5. The light emitting device according to 4 above, wherein a layer constituting a portion of the buffer layer whose side wall surface is not covered with the insulating layer is an undoped type.

  6). The light homogenization layer is a layer provided between the substrate and the first conductivity type cladding layer as a part of the thin film crystal layer. Light emitting element.

7). When the average refractive index of the light homogenizing layer is represented by no _oc , the average refractive index of the first conductive semiconductor layer is represented by n ₁ , and the average refractive index of the buffer layer is represented by n _bf ,
n ₁ <n _oc and n _bf ≦ n _oc
The light-emitting element according to any one of 1 to 6 above, wherein:

8). The emission wavelength of the light emitting element is λ (nm), the average refractive index at the emission wavelength of the light homogenizing layer is n _oc , the average refractive index at the emission wavelength of the first conductivity type semiconductor layer is n ₁ , and the light homogenizing layer. the physical thickness and _t oc (nm), the relative refractive index difference of the light uniformizing layer and the first conductivity type semiconductor layer delta a _{(oc-1) Δ (oc} -1) ≡ ((n oc) 2 - ( n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_8. The light-emitting element according to any one of 1 to 7 above, wherein t _oc is selected so as to satisfy

9. further,
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ 2 × π
_9. The light-emitting element according to 8 above, wherein t _oc is selected so as to satisfy

10. The specific resistance ρ _oc (Ω · cm) of the entire light homogenizing layer is
0.5 ≦ ρ _oc
The light-emitting element according to any one of 1 to 9 above, wherein:

  11. 11. The light emitting device as described in any one of 1 to 10 above, wherein the light uniformizing layer has a laminated structure of a plurality of layers.

12 12. The light-emitting element according to any one of 1 to 11 above, wherein the width _{L1w of the} narrowest portion among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. .

13. 13. The width L _{2w of the} narrowest part among the widths of the part where the second conductivity type side electrode is covered with the insulating layer is 15 μm or more. Light emitting element.

14 _14. The light emitting device as described in 13 above, wherein the L _2w is 100 μm or more.

  15. Any one of the above 1 to 14, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. A light emitting device according to any one of the above.

  16. Said 1-15 characterized by the said 2nd conductivity type side electrode including the layer which consists of a material containing the element chosen from the group which consists of Ni, Pt, Pd, Mo, Au, and those 2 or more types of combinations. The light emitting element in any one of.

17. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The light emitting device as described in any one of 1 to 16 above, wherein the light emitting device is a single layer.

  18. 18. The light emitting device as described in any one of 1 to 17 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  19. 19. The light-emitting element according to 18 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

20. 20. The light emitting device as described in 19 above, wherein the fluoride is selected from the group consisting of AlF _x , BaF _x , CaF _x , SrF _x and MgF _x .

21. 1 to 20 above, wherein the thin film crystal layer is formed on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ and MgO. The light emitting element in any one.

  22. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and The light emitting device according to any one of 1 to 21, wherein an element selected from the group consisting of Al is contained.

23. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
23. The light-emitting element according to any one of 1 to 22 above, wherein

  24. 24. The light emitting device according to any one of 1 to 23, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  25. 25. The light emitting device according to any one of 1 to 24, wherein the first conductivity type side electrode and the second conductivity type side electrode are bonded to a support having a metal layer by solder.

  26. 26. The above-mentioned 25, wherein the first conductive type side electrode and the second conductive type side electrode and the metal layer of the support are joined by only metal solder or metal solder and metal bumps. Light emitting element.

27. 27. The light emitting device as described in 25 or 26 above, wherein the base material of the support is selected from the group consisting of AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN and CuW.

  28. 28. The light-emitting element according to any one of the items 25 to 27, wherein a metal layer is not formed at a separation portion between the devices of the support.

  29. 3. The light emitting device according to 2 above, wherein a surface of the substrate on the first light extraction direction side is not flat.

  30. 4. The light-emitting element according to 3 above, wherein a surface of the buffer layer on the first light extraction direction side is not flat.

31. The reflectance of the light having the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is R3, and the light emission of the light emitting element is perpendicularly incident on the first light extraction direction side space from the substrate. When the reflectance at which the wavelength of light is reflected at the interface with the space is represented by R4,
R4 <R3
3. The light emitting device according to 2, wherein a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above.

32. The reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the light uniformizing layer is reflected by the buffer layer is R3, and the light is perpendicularly incident on the first light extraction direction side space from the buffer layer. When the reflectance at which the light of the emission wavelength of the light emitting element is reflected at the interface with the space is represented by R4,
R4 <R3
4. The light-emitting element according to 3 above, wherein a low-reflection optical film is provided on the first light extraction direction side of the buffer layer so as to satisfy the above.

  According to the type B light emitting element, a flip chip mount that is capable of emitting blue or ultraviolet light and has high output, high efficiency, and high brightness uniformity on the first light extraction direction side. Type semiconductor light emitting device can be provided.

  In the structure of the type B light-emitting element, process damage in each step in the manufacturing process is eliminated, so that the function of the light-emitting element is not impaired and the element is highly reliable.

  Hereinafter, the type B light emitting device will be described in more detail.

  FIG. 2-1A, FIG. 2-2A, and FIG. 2-3A show typical examples of type B compound semiconductor light-emitting elements (hereinafter simply referred to as light-emitting elements). FIGS. 2-1B and 2-3B are diagrams in which a part of FIGS. 2-1A and 2-3A is omitted for the sake of explanation. FIGS. 2-4A and 2-4B are diagrams showing shapes in the course of fabrication in order to explain the structure of the light-emitting element in detail. Hereinafter, a description will be given with reference to FIGS. 2-1A to 2-4B.

  As shown in FIGS. 2-1A, 2-2A, and 2-3A, the type B light emitting device includes a buffer layer 22, a light uniformizing layer 23, and a first conductivity type cladding layer 24 on a substrate 21. Compound semiconductor thin film crystal layer having one conductive semiconductor layer, a second conductive semiconductor layer including a second conductive clad layer 26, and an active layer structure 25 sandwiched between the first and second conductive semiconductor layers , The second conductivity type side electrode 27, and the first conductivity type side electrode 28.

  The second conductivity type side electrode 27 is arranged on a part of the surface of the second conductivity type clad layer 26, and the portion where the second conductivity type clad layer 26 and the second conductivity type side electrode 27 are in contact is the second current. An injection region 35 is formed. Further, the second conductivity type cladding layer 26, a part of the active layer structure 25, and a part of the first conductivity type cladding layer 24 are removed, and the first conductivity type cladding exposed at the removed portion. By arranging the first conductivity type side electrode 28 in contact with the layer 24, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the buffer layer 22. It is configured. The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are connected to a metal layer 41 on the support 40 via a metal solder 42, respectively.

  In the type B light emitting device, the first conductivity type side electrode 28 and the second conductivity type side electrode 27 do not overlap each other spatially. As shown in FIGS. 2-1A, 2-2A, and 2-3A, this is because the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are placed on the first light extraction direction side surface 50b. Means that shadows do not overlap when projected.

  When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” or the like. At the same time, in the type B light-emitting element 10, the insulating layer is disposed at an optimal position so as not to damage the element and affect the performance or affect the yield.

  The type B light emitting element 10 can take different forms at two locations: (I) a stepped shape at the end of the light emitting element 10 and (II) a shape of the insulating layer 30 at the end of the light emitting element. (I) The step shape at the end of the light emitting element 10 is roughly divided according to the etching depth when forming the inter-device isolation groove 13 (see FIG. 2-4A, etc.) for element isolation in the manufacturing process. There are three options: (i) halfway through the light homogenizing layer 23, (ii) halfway through the buffer layer 22, and (iii) up to (or deeper than) the substrate surface for thin film crystal layer growth. Further, since the wall surface of the inter-device isolation groove 13 recedes from the element end after element isolation, in Type B, the surface that appears as the side wall surface when forming the inter-device isolation groove 13 is referred to as “retreat” for the element after element isolation. It is called “side wall surface”. Further, the side wall surface that appears at the element end due to element isolation is referred to as a “non-retreat side wall surface”. A stepped surface is formed at the end of the light emitting element 10 between the receding side wall surface and the non-backed side wall surface, and this is referred to as an “end stepped surface”.

  Corresponding to the depths (i) to (iii) of the inter-device separation groove 13, in (i), a part of the light homogenizing layer 23 has a receding side wall surface with respect to the receding side wall surface of the thin film crystal layer. The side wall of the light uniformizing layer 23 that is configured and remains (on the first light extraction direction side) is a non-retreating side wall surface, and has an end step surface at the end of the light uniformizing layer 23. Similarly, in (ii), the buffer layer 22 has an end step surface at the end. In (iii), since both side walls of the light uniformizing layer 23 and the buffer layer 22 constitute receding side wall surfaces (because they become side wall surfaces of the inter-device isolation trenches 13), there is no type B in which no substrate exists after the device is completed. In the light emitting element, there is no end step surface. Even in the case of (iii), the wall surface of the inter-device separation groove 13 is receded from the element end surface when separated without forming the inter-device separation groove 13. This is referred to as the “retreat side wall surface”.

  FIG. 2-2A and FIG. 2-3A (FIG. 2-3B) correspond to (i). The shapes corresponding to (ii) are FIGS. 2-2B, 2-2C, and 2-3C. FIG. 2-1A (FIG. 2-1B) corresponds to (iii).

  (II) Regarding the shape of the insulating layer 30 at the end of the light emitting element, in the manufacturing process, (i) a region including the center on the groove bottom surface while leaving the insulating layer 30 formed on the side wall of the inter-device separation groove 13 (Ii) In addition to all of the insulating layer 30 formed on the bottom surface of the groove, the insulating layer 30 including part of the side wall in the groove is removed. In the light emitting device 10 manufactured as a result, there are two types: (i) a shape in which the insulating layer 30 is attached to the groove bottom surface, and (ii) a shape in which the insulating layer 30 is separated from the groove bottom surface. FIG. 2-3A (FIG. 2-3B) and FIG. 2-3C correspond to (i). FIG. 2-1A (FIG. 2-1B), FIG. 2-2A (FIG. 2-2B), and FIG. 2-2C correspond to (ii).

  In the light emitting element of type A, since the substrate for growing the thin film crystal layer is removed during the manufacturing process, it is not preferable that the insulating layer 30 is attached to the substrate when the substrate is removed. Therefore, in combination with the above, (I) the stepped shape of the end of the light emitting element 10 is (iii) a shape in which neither the light uniformizing layer 23 nor the buffer layer 22 has a step, and (II) the end of the light emitting element As for the shape of the insulating layer 30 of the part, the combination that becomes (i) the shape in which the insulating layer 30 is attached to the bottom surface of the groove is not included in the type B.

  The shape of the type B light emitting element is (II) the shape of the insulating layer 30 at the end of the light emitting element, the first mode: (ii) the shape in which the insulating layer 30 is separated from the groove bottom surface, the second mode: (i The description will be made separately in the order of the shape of the insulating layer 30 attached to the bottom surface of the groove.

  However, in common with the type B light emitting element, the insulating layer 30 does not reach the end of the buffer layer 22 in the first light extraction direction.

[First embodiment]
The forms belonging to the first mode are shown in FIGS. 2-1A to 2-2C. First, a typical form will be described with reference to FIG. As shown in FIG. 2A, the type B light-emitting element does not have a substrate in the first light extraction direction. The insulating layer 30 includes at least a first conductivity type semiconductor layer (first conductivity type cladding layer 24 in the figure), an active layer structure 25, and a second conductivity type among the side wall surfaces exposed when the thin film crystal layer is removed. The side wall surface of the semiconductor layer (the second conductivity type cladding layer 26 in the figure) is covered. In addition, there is an insulating layer non-formation portion 15 that is not covered with the insulating layer 30 at least on the first light extraction direction side of the side wall surface of the buffer layer 22. It may be all over. Further, it may extend to a part or all of the side wall surface of the light homogenizing layer 23. Thus, in the type B light emitting device, the insulating layer 30 does not exist at the device end of the buffer layer 22 on the first light extraction direction side. This is the same even when the buffer layer 22 or the light uniformizing layer 23 has an end step surface in other embodiments.

  The buffer layer 22 of the insulating layer non-forming portion 15 that is not covered with the insulating layer 30 is preferably an undoped undoped layer. Moreover, when the insulating layer non-formation part 15 extends to the light uniformization layer 23, it is preferable that it is an undoped layer which is not doped to the part. If the exposed part is a highly insulating material, there is no possibility of short circuit due to the wrapping of solder, and the element is highly reliable.

  This structure passes through the shape shown in FIG. 2-4A before element separation during the manufacturing process. In the middle of the manufacturing process, the insulating layer 30 is removed from the substrate surface (groove bottom surface) in the groove of the inter-device separation groove 13 and the insulating layer non-forming portion 15 on the groove side wall surface adjacent to the substrate surface (groove bottom surface). Yes. In the type B light emitting device, the substrate 21 is peeled off during the manufacturing process. At this time, since the insulating layer 30 is not in contact with the substrate 21, the insulating layer 30 is not peeled when the substrate is peeled off. Therefore, in addition to ensuring reliable insulation, the thin film crystal layer is not damaged by the tension generated when the insulating layer 30 is peeled off.

  In the separated light-emitting element 10 obtained as a result, as shown in part A of FIG. 2A, the insulating layer not covered with the insulating layer 30 on the first light extraction direction side of the wall surface of the buffer layer 22 A non-formed portion 15 is present. That is, as a result of this shape being ensured that the insulating layer 30 is not peeled off on the side surface of the thin film crystal layer, the light-emitting element 10 has an unintentional short circuit even if the solder wraps around. In addition to being prevented, the thin film crystal layer is not damaged, so that the function of the light emitting element 10 is not impaired and the element is highly reliable.

Furthermore, the insulating layer 30 is in contact with a part of the substrate side (first light extraction direction side) of the first conductivity type side electrode 28 as shown in a portion B of FIG. 2-1B. That is, the insulating layer 30 is interposed between a portion between the first conductivity type side electrode 28 and the first conductivity type semiconductor layer (first conductivity type cladding layer 24 in this embodiment). As a result, the area of the first conductivity type side electrode 28 is larger than the area of the first current injection region 36. As shown in FIG. 2-1B, when the width of the narrowest portion among the widths of the portion where the first conductivity type side electrode 28 is in contact with the insulating layer 30 is L _1w , L _1w is preferably 7 μm or more, Particularly, 9 μm or more is preferable. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

Furthermore, the insulating layer 30 covers a part of the second conductivity type side electrode 27 on the support 40 side (the side opposite to the first light extraction direction), as shown in part C of FIG. 2-1B. That is, the area of the electrode exposed portion 37 of the second conductivity type side electrode 27 is smaller than the area of the second conductivity type side electrode 27, and the area of the second current injection region 35 is equal to the area of the second conductivity type side electrode 27. equal. As shown in FIG. 2-3B, when the width of the narrowest portion of the width covered by the insulating layer 30 from the periphery of the second conductivity type side electrode 27 is L _2W , L _2W is 15 μm or more. It is preferable. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can. L _2w is usually 2000 μm or less, preferably 750 μm or less.

  Further, the first conductive semiconductor layer (first conductive clad layer 24 in this embodiment) and the second conductive semiconductor layer (second conductive clad layer 26 in this embodiment) on the support 40 side (first The exposed portion of the surface on the opposite side of the light extraction direction is also usually covered with an insulating layer 30 as shown in the figure to prevent short circuits.

  Due to such a positional relationship between the insulating layer 30 and the electrodes 27 and 28, it is possible to manufacture by a process with little process damage.

  Furthermore, the type B light emitting element has a light uniformizing layer 23 on the first light extraction direction side from the first conductive semiconductor layer (in this embodiment, the first conductive clad layer 24). Although the light homogenization layer 23 will be described later in detail, it has an appropriate light confinement effect, and the light emitted from the active layer structure 25 is distributed throughout the light homogenization layer without being localized. Therefore, when viewed from the surface 50b on the first light extraction direction side, the light is distributed also in the region corresponding to the non-light emitting portion where the active structure layer 25 is not present for the extraction of the first conductivity type side electrode 28, and Even if the light emission in the active structure layer is uneven, the light is distributed so as to be uniform. Furthermore, since the periphery of the light homogenizing layer 23 is covered with the insulating layer 30, increasing the reflectance of the insulating layer 30 with respect to the emission wavelength increases the light confinement effect in the light homogenizing layer 23. The uniformity is further improved.

[First aspect 2]
Other forms belonging to the first mode will be described with reference to FIGS. 2-2A to 2-2C. 2A differs from the light emitting device of FIG. 2A in that (I) the step shape of the end of the light emitting device 10 is (iii) which of the light uniformizing layer 23 and the buffer layer 22 is different. 2A to 2-2C, the light emitting element shown in FIGS. 2-2A to 2-2C has (i) an end step surface 55 based on an inter-device separation groove at the end of the light uniformizing layer 23. Or (ii) a shape having an end step surface 55 based on the inter-device separation groove at the end of the buffer layer 22.

  This shape is manufactured by forming the inter-device separation groove halfway through the light uniformizing layer 23 or halfway through the buffer layer 22, and as a result, in the completed light emitting element 10, at least the first conductive semiconductor layer, The active layer structure 25 and the second conductivity type semiconductor layer recede inward from the end of the light emitting element 10 to form a receding side wall surface, and the end step surface 55 is between the element end wall surface (non-receding side wall surface). Existing.

  FIG. 2-2A shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the light uniformizing layer 23. As shown in part A, a part of the buffer layer 22 and the light homogenizing layer 23 exists as a non-retreating side wall surface up to the light emitting element end, and the wall surface recedes from the element end from the middle of the light homogenizing layer 23. A receding side wall surface (side wall of the inter-device separation groove) is formed together with the side wall surface of the two-conductivity type semiconductor layer. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. All the wall surfaces of the buffer layer 22 are exposed. Further, the end step surface 55 of the light uniformizing layer 23 is not covered with the insulating layer 30, and the insulating layer non-formed portion 15 not covered with the insulating layer 30 is formed on the receding side wall surface. Present on the light extraction direction side.

  FIG. 2-2B shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the buffer layer 22. As shown in part A, a part of the buffer layer 22 exists as a non-retreat side wall surface to the light emitting element end, and the wall surface retreats from the element end from the middle of the buffer layer 22 together with the side wall surface of the second conductivity type semiconductor layer. A receding side wall surface (side wall of the inter-device separation groove) is formed. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. The non-retreating side wall surface (side wall portion at the element end) is not covered with the insulating layer 30, and the end step surface 55 is not covered with the insulating layer 30. On the side wall of the groove, an insulating layer non-formed portion 15 that is not covered with the insulating layer 30 exists on the first light extraction direction side. In this example, the insulating layer non-forming portion 15 exists only in the buffer layer 22, and the light uniformizing layer 23 is covered with the insulating layer 30. FIG. 2-2C is also an example of a light emitting device manufactured by forming the inter-device separation groove partway through the buffer layer 22. As shown in this figure, the insulating layer non-formed portion 15 extends from the buffer layer 22 to the light uniformizing layer 23, and all the side walls of the buffer layer 22 are exposed.

  As in these examples, even when the inter-device separation groove 13 is formed up to the middle of the combined layer of the light homogenizing layer 13 and the buffer layer 22, the insulating layer 30 that covers the side wall is provided on the light emitting element 10. In the device having a shape that does not reach the end, it is guaranteed that the insulating layer 30 is not peeled off, and the exposed layer is made of a highly insulating material. Like the light emitting element 10, the device is highly reliable.

[Second embodiment]
In the second aspect, (II) the shape of the insulating layer 30 at the end of the light emitting element is (i) the shape in which the insulating layer 30 is attached to the bottom surface of the groove. In the light emitting device of FIG. 2-3A, the device separation groove 13 is formed partway through the light uniformizing layer 23 and the insulating layer 30 is formed in the device separation groove 13 before the device separation, as shown in FIG. Rather than covering the entire groove bottom surface, a scribe region 14 in which the insulating layer 30 is not formed is formed on the groove bottom surface. Therefore, the buffer layer 22 and the light uniformizing layer 23 may be braked during element separation such as scribe and braking during the manufacturing process, and the layer related to device performance, that is, the first conductive layer, of the thin film crystal layer. The semiconductor layer, the active layer structure 25 and the second conductive semiconductor layer are not directly damaged. Further, since the insulating layer 30 is divided from the scribe region 14 without the insulating layer 30 at the bottom of the groove, the insulating layer 30 does not peel off, so that in addition to maintaining reliable insulation, the tensile force generated when the insulating layer 30 peels off, The thin film crystal layer is not damaged.

As a result, in the separated light emitting device, as shown in part A of FIGS. 2-3A and 2-3B, the entire surface of the end step surface (groove bottom surface) 55 formed in the light uniformizing layer 23 is obtained. Is not covered by the insulating layer 30 but covers the substrate surface on the inner side from the position separated by L _ws from the element end. When divided from the center of the width of the scribe region 14, the distance L _ws that is not covered with the insulating layer 30 corresponds to approximately ½ of the width of the scribe region 14 in the range of manufacturing fluctuation or the like. That is, this shape ensures that the insulating layer 30 is not peeled off from the side surface of the thin film crystal layer. As a result, the light-emitting element prevents an unintended short circuit even if the solder wraps around. In addition, since the thin film crystal layer is not damaged, the function of the light emitting element is not impaired and the element is highly reliable.

L _ws may be larger than 0 in the completed light emitting device, but is usually 10 μm or more, preferably 15 μm or more. As a design value, if the width of the scribe region 14 is 2L _ws , 2L _ws is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _WS is usually 300 μm or less, preferably 200 μm or less.

  In the light emitting device shown in FIG. 2-3C, the inter-device separation groove is formed partway through the buffer layer 22 as shown in FIG. 2-4C, and the insulating layer 30 formed on the bottom surface of the groove includes the groove center region. It is a form manufactured by being removed in the scribe region 14.

  Also in the light-emitting element of the second embodiment, the exposed layer is made of a highly insulating material, so that the device is as reliable as the light-emitting element 10 in the form of FIG. Further, the shape of the other parts of the second aspect is the same as that of the first aspect.

  Below, each member and structure which comprise a light emitting element are demonstrated in detail.

<Board>
In the type B light emitting device, no substrate remains on the completed light emitting device. As the substrate, a substrate on which a semiconductor layer can be grown is selected, and a substrate that can be finally removed is used. The substrate need not be transparent, but when the substrate is peeled off by laser debonding, which will be described later, in the manufacturing process, it is preferable to transmit laser light having a specific wavelength. Further, it is preferably an electrically insulating substrate. This is because, in the manufacturing process, when the substrate is similarly peeled by the laser debonding method, it is difficult to adopt such a substrate peeling method due to absorption by free electrons or the like in the conductive substrate.

All of the substrate materials described above for Type A can be used for Type B light-emitting elements. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light-emitting material or InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, the Si doping concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or less, more preferably 8 × 10 ¹⁷ cm ⁻ when an undoped substrate is intentionally used. ^It is desirable that it is ³ or less from the viewpoints of electrical resistance and crystallinity. When chemical etching is premised when removing the substrate, ZnO that can be easily removed with hydrochloric acid or the like is preferable.

  In addition, as described in the type A, an off-substrate can be used, a point that the substrate may be subjected to chemical etching or heat treatment in advance, and a point that the substrate may be intentionally uneven. And so on.

  In one embodiment, the thickness of the substrate is usually about 250 to 700 μm at the initial stage of device fabrication, and it is necessary to ensure the mechanical strength in the semiconductor crystal growth and device fabrication process. It is normal. After the necessary semiconductor layer is grown using the substrate, the substrate is removed by, for example, polishing, etching, laser debonding, or the like. In particular, when the film is peeled off by an optical method such as laser debonding, it is desirable to use a double-sided polished substrate during the growth of a thin film crystal. This is because if a single-side polished substrate is used for a laser irradiated from a surface on which no thin film crystal is grown, it will be incident from a rough surface, and an unnecessarily large laser output is required during laser debonding. It is.

<Buffer layer>
With respect to the buffer layer, all of the matters described for type A also apply to the type B light-emitting element. Since no substrate remains in the type B light emitting device, preferable matters will be further described.

  In the completed light-emitting element, as already described, at least the vicinity of the first light extraction direction (the substrate side when forming the buffer layer) on the side wall surface of the buffer layer is not covered with the insulating layer.

Furthermore, in order to confine light in a light homogenization layer, which will be described later, and to guide the light, the refractive index of the buffer layer at the emission wavelength of the light emitting element is equal to or less than the average refractive index of the light homogenization layer, preferably the light homogenization layer Less than the average refractive index. Physical thickness of the buffer, the emission wavelength of the light emitting element lambda (nm), when representing the average refractive index of the buffer n _bf, it is desirable that thicker than 4λ / n _bf.

Further, since the substrate is removed during the manufacturing process, the buffer layer becomes a surface on the first light extraction direction side. As described above, as one method of peeling the substrate, a method of peeling the substrate by optically decomposing a part of the buffer layer using light that is transparent to the substrate and absorbs the buffer layer Is mentioned. When such a method is adopted, a material suitable for the method is selected. For example, when the substrate is sapphire and the buffer layer is GaN, an excimer laser having an oscillation wavelength of 248 nm is irradiated from the substrate side on which no thin film crystal is grown, and the buffer layer GaN is made of metal Ga and nitrogen. It is also possible to carry out laser debonding in which the substrate is peeled off as a result.
In the type B light emitting element, since the substrate does not exist in the first light extraction direction, a so-called low reflection coating layer or low reflection optical film may be formed on the surface of the buffer layer on the first light extraction direction side. desirable. Reflection due to a difference in refractive index at the buffer layer-air interface can be suppressed, and higher output and higher element efficiency can be achieved. Here, the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the light homogenizing layer described later is reflected by the buffer layer is R3, and the space on the first light extraction direction side from the buffer layer When the reflectance at which the light having the emission wavelength of the light-emitting element perpendicularly incident on the light is reflected at the interface with the space is represented by R4,
R4 <R3
It is desirable that a low reflection optical film be provided on the first light extraction direction side of the buffer layer so as to satisfy the above. For example, when the buffer layer is GaN, it is desirable to use Al ₂ O ₃ or the like as the low reflection coating film. This is because it is desirable that the refractive index of the low-reflection coating film is close to √n _bf with respect to the refractive index n _bf of the buffer layer at the light emission wavelength of the device, so that Al ₂ O with respect to the square root of the refractive index of GaN. _{This is because} the refractive index of ₃ is close.

It is also preferable that the surface of the buffer layer on the first light extraction direction side is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Here, when the light emission wavelength of the device is λ (nm), the roughness of the buffer layer is such that the average roughness Ra (nm) is λ / 5 (nm) <Ra (nm) <10 × λ (nm).
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

  In this form, at least a portion of the buffer layer is exposed at the device edge. Therefore, at least the exposed portion is preferably an undoped portion, since insulation failure due to solder or the like during device assembly can be suppressed.

<Light homogenization layer>
The light uniformizing layer in the type B light emitting element can adopt the same configuration as that used in the type A light emitting element.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
The first conductive type semiconductor layer and the first conductive type clad layer in the type B light emitting device can adopt the same configuration as that used in the type A light emitting device.

<Active layer structure>
The active layer structure in the type B light emitting device can adopt the same configuration as that used in the type A light emitting device.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductive type semiconductor layer and the second conductive type cladding layer in the type B light emitting element can adopt the same configuration as that used in the type A light emitting element.

<Second conductivity type side electrode>
The second conductivity type side electrode in the type B light emitting element can adopt the same configuration as that used in the type A light emitting element.

<First conductivity type side electrode>
The first conductive type side electrode in the type B light emitting element can adopt the same configuration as that used in the type A light emitting element.

<Insulating layer>
The insulating layer in the type B light emitting element can adopt the same configuration as that used in the type A light emitting element.

<Support>
In the type B light emitting device, since the substrate is not present in the completed device, the function required for the support is somewhat different from the submount described in the type A.

Although it is essential that the support 40 can serve as a support for the thin film crystal layer when the substrate is peeled off, the support 40 can also have functions of current introduction and heat dissipation after device completion. Highly desirable. From this viewpoint, the base material of the support is preferably selected from the group consisting of metal, AlN, SiC, diamond, BN, and CuW. These materials are preferable in that they are excellent in heat dissipation and can efficiently suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as a support. In addition, when a portion of the thin film crystal layer is decomposed into metal Ga and nitrogen by laser irradiation when removing the substrate, which will be described later, it is desirable to perform wet etching when removing the metal Ga. The body is preferably made of a material that is not etched. When the base material of the support is selected from metal, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, when covered with a dielectric such as, _SiN x was formed by various CVD methods, SiO ₂ or the like is desirable.

  From the viewpoint that the support further has a function of current introduction and heat dissipation after completion of the element, it is desirable that the support has an electrode wiring for current introduction on the base material, and the element is arranged on the electrode wiring. It is desirable that the mounting portion has an adhesive layer for joining the element and the support appropriately. Here, although it is possible to use a paste containing Ag, a metal bump, or the like as the adhesive layer, it is very desirable from the viewpoint of heat dissipation that it is made of metal solder. The metal solder can realize a flip chip mount that is overwhelmingly excellent in heat dissipation compared with a paste material containing Ag, a metal bump, and the like. Here, examples of the metal solder include In, InAg, InSn, SnAg, PbSn, AuSn, AuGe, and AuSi. In particular, a high melting point solder such as AuSn, AuSi, or AuGe is more desirable. This is because when a large current is injected to operate the light emitting element at an ultrahigh output, the temperature in the vicinity of the element rises to about 200 ° C. The melting point of the solder material is higher than the element temperature during driving. The metal solder which has is more preferable. In some cases, it is also desirable to use bumps in order to cancel out the level difference of the elements at the time of flip chip mounting, and further to join the metal solder material while filling the periphery thereof.

Further, since the device is usually separated by dividing the support as will be described later, in the completed light emitting device, it is preferable that an isolation region where no metal wiring exists is present around the support 40. As shown in FIG. 2-5, the width of the region where no metal wiring exists is L _WSPT2 (in FIG. 2-5, the left side is _represented by L _{WSPT2 (left)} and the right side is represented by L _{WSPT2 (right))} . , L _WSPT2 may be larger than 0 in the completed device, but the preferred range varies depending on what method is used in the separation step as described below.

When separating by scribing, it is usually 10 μm or more, preferably 15 μm or more. Therefore, it is preferable that 2L _WSPT2 is 30 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 300 μm or less, preferably 200 μm or less.

Further, when separating by dicing, L _WSPT2 is usually 100 μm or more, preferably 500 μm or more. Therefore, it is preferable that 2L _WSPT2 is 1000 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 2000 μm or less, preferably 1500 μm or less.

  An embodiment in which the support is not divided is also possible. For example, a plurality of light emitting elements can be mounted on one support. By freely changing the metal wiring on the support, each light emitting element on one support can be connected in parallel, connected in series, or mixed.

[Method for Manufacturing Type B Light-Emitting Element]
Next, a method for manufacturing a type B light emitting device will be described.

<The manufacturing method of the light emitting element of a 1st aspect>
In one example of the manufacturing method, as shown in FIG. 2-7, first, a substrate 21 is prepared, and a buffer layer 22, a light uniformizing layer 23, a first conductivity type cladding layer 24, an active layer structure 25, The two-conductivity-type cladding layer 26 is sequentially formed by thin film crystal growth. The MOCVD method is preferably used. However, the MBE method, the PLD method, and the like can also be used for forming all thin film crystal layers or some thin film crystal layers. These layer configurations can be appropriately changed according to the purpose of the element. Further, after the formation of the thin film crystal layer, various kinds of treatments may be performed. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  In order to realize the shape shown in FIGS. 2-1A to 2-2C after the thin film crystal layer growth, it is preferable to form the second conductivity type side electrode 27 as shown in FIG. 2-7. . That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. In the case where the second conductivity type is p-type as a preferred embodiment, if the p-side electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface, This is because the hole concentration in the p-GaN cladding layer having a relatively low activation rate is reduced by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. For this reason, in the present invention, after the thin film crystal growth, the formation of the second conductivity type side electrode is performed in another process step (for example, the first etching step, the second etching step, or the insulating layer forming step described later, the second conductivity type side). It is desirable that the electrode exposed portion forming step, the first current injection region forming step, the first conductivity type side electrode forming step, etc.) be performed prior to this.

  In the present invention, when the second conductivity type is p-type, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a representative example. Is a relatively stable metal such as Au, it is unlikely to be damaged by the process even after the subsequent process. Also from this viewpoint, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  In Type B, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer is reduced similarly. Can do.

  Various film formation techniques such as sputtering, vacuum deposition, and plating can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique or a metal A place-selective vapor deposition using a mask or the like can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 2-8, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, since the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask as will be described in detail in the second etching step described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, the process damage received by the second conductivity type side electrode is reduced.

  Next, as shown in FIGS. 2-9, an inter-device separation groove 13 is formed by a second etching process. In Type B, the inter-device separation groove 13 needs to be formed by dividing at least the first conductivity type clad layer 24. In this embodiment, the inter-device separation groove 13 reaches the substrate 21. Formed. In this case, the GaN-based material on the sapphire substrate is peeled off even when diamond scribe is performed from the side on which the thin film crystal layer is formed in steps such as scribing and breaking in order to separate the elements. It is possible to suppress. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to form an inter-device separation groove by etching up to a part of a sapphire substrate (the same applies to other substrates such as GaN).

  On the other hand, a mode in which the inter-device separation groove does not reach the substrate is also a preferable mode. For example, if the inter-device separation groove is formed up to the middle of the combined layer of the light uniformizing layer and the buffer layer, an insulating layer can be formed on the side wall of the first conductivity type cladding layer, Insulation can be maintained against wraparound (see FIGS. 2-2A to 2-2C for the form after the light emitting element is completed). In this case, the bottom surface of the groove is formed in the middle of the combined layer of the light uniformizing layer and the buffer layer, and this becomes an end step surface at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Since the bottom surface of the groove is subjected to processing such as scribing at the time of element separation, the end step surface after element separation is often not high in terms of planarity as a surface and parallelism with the layer direction. Moreover, it is preferable that the layer exposed from the side wall without being covered with the insulating layer has high insulating properties.

  In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. In general, the sum of the layers etched by the first etching step is usually about 0.5 μm. However, in the second etching step, all of the first conductivity type cladding layer 24, the light uniformizing layer 23 and the buffer are formed. Since it is necessary to etch at least a part of the layer 22, in some cases, it may be 3 to 7 μm, and in some cases, it may be in the range of 3 to 10 μm, or even 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that requires etching of the system material, a relatively thick SiN _x film is required. For example, when a 10 μm GaN-based material is etched in the second dry etching step, a SiN _x mask exceeding 2 μm is required. However, at the SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the inter-device separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first and second etching steps, while it can be easily etched for patterning etching (preferably wet etching). In addition, a patterning shape, particularly one having good linearity in the side wall portion is required. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in controllability of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, when a mask such as SrF ₂ is exposed to plasma such as chlorine during dry etching of a semiconductor layer, the etching rate at the time of subsequent mask layer removal is lower than before exposure to plasma such as chlorine. Have a tendency to For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _2-19, SiN x, SiO ₂ or the like mask 51, Even if it does not exist in the entire lower part of the metal fluoride mask layer 52, it should be formed on a material that is at least sensitive to acids.

  By such a second etching step, an inter-device separation groove 13 is formed as shown in FIG. 2-9.

Note that the first etching step and the second etching step may be performed either first or later. In order to simplify the process, it is also preferable to perform the first etching step first and then perform the second etching step without removing the etching mask at that time. As shown in FIG. 2-19, first, a first etching mask 51 is formed of an acid-resistant material (preferably SiN _x ) such as SiN _x and SiO ₂ , and etching is performed so that the first conductivity type cladding layer 24 appears. The second etching mask 52 made of a metal fluoride layer is formed without removing the mask 51. And after implementing a 2nd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the device manufacturing process and further for securing the scribe region.

  The “recessed side wall surface” defined in the description of Type B is a side wall surface that appears as a side wall in the second etching step, that is, the formation of the inter-device separation groove, and is not a wall surface that appears only in the first etching.

  After the second etching step, an insulating layer 30 is formed as shown in FIG. 2-10. The insulating layer can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

  Next, as shown in FIG. 2-11, a predetermined portion of the insulating layer 30 is removed, and the second conductive type side electrode exposed portion 37 from which the insulating layer is removed on the second conductive type side electrode 27, the first conductive type. A first current injection region 36 from which the insulating layer has been removed on the mold clad layer, and an insulating layer non-formed portion 15 from which the insulating layer has been removed from the substrate surface and the side wall in the inter-device isolation trench 13 are formed.

The insulating layer 30 on the second conductivity type side electrode 27 is removed such that the peripheral portion of the second conductivity type side electrode 27 is covered with the insulating layer 30. That is, the surface area of the exposed portion of the second conductivity type side electrode is smaller than the area of the second current injection region. Here, a part of the second conductivity type side electrode 27 is covered with the insulating layer 30 in order to prevent an occurrence of an unintentional short circuit due to a margin of a photolithography process, particularly a photolithography process, or a solder material. The width (L _2w ) of the narrowest portion is preferably 15 μm or more as described above. More desirably, it is 100 μm or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can.

For the removal of the insulating layer 30, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer 30 is a single SiN _x layer, dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer 30 is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

  The second conductivity type side electrode exposed portion 37, the first current injection region 36, and the insulating layer non-formed portion 15 may be formed separately, but are usually formed by etching at the same time.

  In order to provide the insulating layer non-formed portion 15 by removing the insulating layer 30 on the side wall near the substrate in the inter-device separation groove, for example, the following process can be used. First, a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device separation groove 13 is formed by photolithography, and then wet etching is performed using an etchant that can etch the insulating layer 30. The removal of the insulating layer 30 on the substrate surface in the separation groove proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer 30 covering the substrate side of the groove sidewall is removed with a wet etchant. As shown in FIG. A shape without 30 is obtained. When the insulating layer 30 is removed as described above, the side wall of the thin film crystal layer where the insulating layer 30 does not exist is preferably the side wall of the undoped layer. This is because an unintended electrical short circuit does not occur even when solder for joining to the support or the like adheres to the side wall when flip chip mounting is performed. Such a removed shape of the insulating layer 30 is a desirable shape, particularly when the substrate 21 is removed during the manufacturing process of the light emitting element, because an unintended defect such as peeling of the insulating layer 30 is not accompanied. It is.

Next, as shown in FIG. 2-12, the first conductivity type side electrode 28 is formed. In the type B light emitting device, the first conductivity type side electrode 28 is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are: It is characterized by having no spatial overlap. This is because when the element is flip-chip mounted with solder or the like, the second conductivity type side electrode 27 and the first conductivity type side are secured while securing a sufficient area to ensure sufficient adhesion with a support or the like. This is important for securing a sufficient distance to prevent an unintended short circuit due to a solder material or the like between the electrode 28 and the like. Among the widths of the portion where the first conductivity type side electrode 28 is in contact with the insulating layer 30, the width (L _1w ) of the narrowest portion is set to be in the above-described range. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from any one of Ti, Al, Ag, and Mo. Further, Al is usually exposed in the direction facing the first light extraction direction of the n-side electrode.

  Various film formation techniques such as sputtering, vacuum evaporation, plating, etc. can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique, a metal mask, or the like was used. Site selective vapor deposition or the like can be used as appropriate.

  In this example, the first conductivity type side electrode 28 is formed so as to be in contact with a part of the first conductivity type clad layer 24. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact therewith. can do.

  In this manufacturing method, the first conductivity type side electrode 28 is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is formed with Al on the surface of the electrode material in a preferred embodiment. In this case, if the n-side electrode is formed before the formation of the insulating layer 30 like the second conductivity type side electrode 27, the surface of the n-side electrode, that is, the Al metal, has a history of the etching process of the insulating layer 30. Will do. As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching the insulating layer 30, but Al has low resistance to various etchants including hydrofluoric acid, and this process is effective. If implemented, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in the manufacture of the type B light emitting device, the first conductivity type side electrode 28 is formed after the formation of the insulating layer 30 and after the removal of a predetermined unnecessary portion of the insulating layer 30. It is effective in reducing.

  After the structure of FIG. 2-12 is formed in this way, preparations for removing the substrate 21 are made. Usually, the structure shown in FIG. 2-12 is bonded to the support 40 as shown in FIG. 2-13, as a whole wafer or a part thereof. This is because the thickness of the thin film crystal layer as a whole is about 15 μm at the maximum. Therefore, if the substrate 21 is peeled off, the mechanical strength becomes insufficient and it becomes difficult to stand alone and undergo subsequent processes. Because. The material of the support 40 is as described above.

  As shown in FIG. 2-13, the metal layer 41 (electrode wiring or the like) on the support 40 is connected and mounted by, for example, metal solder 42.

  At this time, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged so as not to spatially overlap each other, and the first conductivity type side electrode 28 is located more than the first current injection region. Since it is large and has a sufficient area, it is desirable to prevent unintentional short-circuiting and ensure high heat dissipation. Further, since the side walls of the other thin film crystal layers are also protected by the insulating layer 30 except at least a part of the buffer layer, in particular, the undoped portion, even if there is a solder ooze, the inside of the thin film crystal layer, for example, the active layer structure A short circuit or the like in the side wall does not occur.

  Next, after bonding the element to the support 40, the substrate 21 is peeled off. For removing the substrate 21, any method such as polishing, etching, laser debonding or the like can be used. When polishing a sapphire substrate, the substrate 21 can be removed using an abrasive such as diamond. It is also possible to remove the substrate 21 by dry etching. Furthermore, for example, when a thin-film crystal growth portion is formed of an InAlGaN-based material on a sapphire substrate, the sapphire substrate transmits from the sapphire substrate side and is absorbed by, for example, GaN used for the buffer layer 22. It is also possible to perform laser debonding in which a part of GaN in the buffer layer 22 is decomposed into metal Ga and nitrogen by using a 248 nm KrF excimer laser and the substrate 21 is peeled off. FIG. 2-14 schematically shows the state where the substrate 21 is peeled off by laser debonding.

In addition, when ZnO, ScAlMgO ₄ or the like is used as the substrate 21, the substrate 21 can be removed by wet etching using an etchant such as HCl.

  In the type B light emitting element, since there is no portion where the insulating layer 30 is in contact with the substrate 21, the peeling of the insulating layer 30 or the like does not occur when the substrate is peeled off.

  Thereafter, as shown in FIG. 2-14, the light emitting element is separated together with the support 40 in the separation region 47 corresponding to the location where the inter-device separation groove exists, to obtain a single light emitting element. Here, it is preferable that no metal wiring exists in the separation region 47 of the support 40. This is because separation between devices is difficult if metal wiring exists here.

  For the cutting of the separation region portion of the support 40, an appropriate process such as dicing, scribing and braking can be selected depending on the base material of the support 40. Further, when the inter-device separation groove is formed up to the middle of the combined layer of the light homogenizing layer 23 and the buffer layer 22, the inter-device separation groove is used to damage by the diamond scribe or laser scribe. By performing ablation of a part of the light homogenizing layer 23 and / or the buffer layer 22, separation between the light emitting elements in the thin film crystal layer portion can be easily realized. Thereafter, the support 40 can be separated into light emitting elements by dicing. In some cases, separation between the light emitting elements can be performed by dicing the thin film crystal layer and the support 40 at the same time.

  As described above, the light-emitting element of the first mode shown in FIGS. 2-1A to 2-2C is completed.

<The manufacturing method of the light emitting element of a 2nd aspect>
To manufacture the light emitting device of the second mode shown in FIGS. 2-3A to 2-3C, in the description of the manufacturing method of the first mode, the light homogenizing layer is formed when the inter-device separation groove is formed. 23 or etching is stopped in the middle of the buffer layer 22. Similarly, when the insulating layer 30 is formed and the insulating layer 30 is etched, as shown in FIGS. 2-4B and 2-4C, the insulating layer 30 is removed from the region including the center of the inter-device separation groove, A scribe region is formed. In the first mode, all of the insulating layer 30 on the bottom surface of the groove is removed, but in this mode, the side layer is not intentionally etched so that the insulating layer 30 remains on the bottom surface of the groove. The width of the scribe region 14 can be set so as to obtain a predetermined L _ws as described above. Thereafter, in the same manner as in the first embodiment, the light emitting device shown in FIGS. 2-3A to 2-3C is completed.

  In common with the first aspect and the second aspect, in this manufacturing method, as described, formation of a thin film crystal layer, formation of the second conductivity type side electrode 27, etching process (first etching process and second etching process) ), Formation of the insulating layer 30, removal of the insulating layer 30 (formation of the exposed portion of the second conductivity type side electrode, formation of the first current injection region, formation of the scribe region), formation of the first conductivity type side electrode 28 It is desirable that the steps be performed in this order, and by this order of the steps, a light-emitting element can be obtained in which the thin film crystal layer directly under the second conductivity type side electrode is not damaged and the first conductivity type side electrode 28 is not damaged. . The device shape reflects the process flow. That is, the light emitting element has a structure in which the second conductivity type side electrode 27, the insulating layer 30, and the first conductivity type side electrode 28 are laminated in this order. That is, the second conductivity type side electrode 27 is in contact with the second conductivity type clad layer 26 (or other second conductivity type thin film crystal layer) without the insulating layer 30 interposed therebetween. There is a portion covered with an insulating layer 30 around the upper portion, and the area around the electrode is between the first conductivity type side electrode 28 and the first conductivity type side cladding layer 24 (or other first conductivity type thin film crystal layer). There is a portion where the insulating layer 30 is interposed.

<< 2-3. Features of manufacturing methods of type A and B light emitting elements >>
The manufacturing method of the above-described type A and type B light-emitting elements is characterized by the following matters.

1. (A) a step (a) of forming a buffer layer and a light uniformizing layer in this order on a substrate;
(B) At least a first conductive type semiconductor layer including a first conductive type cladding layer, an active layer structure, and a thin film crystal layer having a second conductive type semiconductor layer including a second conductive type cladding layer from the substrate side. A step (b) of sequentially forming a film;
(C) a step (c) of forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
(D) a first etching step (d) in which a part of the portion where the second conductivity type side electrode is not formed is etched to expose a part of the first conductivity type semiconductor layer;
(E) In order to form an inter-device separation groove for separating adjacent light emitting elements, a part of the portion where the second conductivity type side electrode is not formed is separated from the surface, (i) the light uniformizing layer Etching is performed at a depth until at least a portion is removed, (ii) at least a portion of the buffer layer is removed, or (iii) at least reaches the substrate. Two etching steps (e);
(F) a step (f) of forming an insulating layer on the entire surface including the second conductivity type side electrode, the first conductivity type semiconductor layer exposed by the first etching step, and the inside of the inter-device isolation trench;
(G) removing an insulating layer in a region including at least the groove center of the groove bottom surface in the inter-device separation groove;
(H) removing a part of the insulating layer formed on the surface of the first conductivity type semiconductor layer and forming an opening to be a first current injection region;
(I) removing a part of the insulating layer formed on the surface of the second conductivity type side electrode and exposing a part of the second conductivity type side electrode;
(J) A method of manufacturing a light emitting device, comprising: a step (j) of forming a first conductivity type side electrode in contact with the first current injection region opened in the step (h).

  2. In the step (g), only the insulating layer in the region including the groove center on the groove bottom surface is removed while leaving the insulating layer formed on the sidewall of the inter-device separation groove. The method described.

  3. In the step (g), all of the insulating layer formed on the bottom surface of the groove in the inter-device separation groove and the insulating layer formed on at least a portion of the side wall in the inter-device separation groove on the groove bottom surface side. 2. The method according to 1 above, which is removed.

  4). 4. The method according to any one of the above items 1 to 3, wherein the layer constituting the surface exposed by removing the insulating layer is an undoped type.

5). After step (j)
Isolating the substrate in the inter-device separation groove;
The method according to any one of the above items 1 to 4, further comprising the step of joining the first conductivity type side electrode and the second conductivity type side electrode to a metal layer on a submount.

6). After step (j)
Bonding the first conductivity type side electrode and the second conductivity type side electrode to the metal layer on the support and mounting the support on the support; and
Removing the substrate;
The method according to any one of 1 to 4 above, further comprising a step of dividing the support to separate elements.

  7. 7. The method according to any one of 1 to 6 above, wherein the buffer layer and the light uniformizing layer are performed as a part of the thin film crystal layer prior to the formation of the first conductivity type semiconductor layer.

8). When the average refractive index of the substrate at the emission wavelength is expressed as n _sb , the average refractive index of the light uniformizing layer is expressed as n _oc , and the average refractive index of the first conductive semiconductor layer is expressed as n ₁ ,
n _sb <n _oc and n ₁ <n _oc
The method according to any one of 1 to 7 above, wherein the relationship is satisfied.

9. The light emitting wavelength of the light emitting element is λ (nm), the average refractive index of the substrate at the light emitting wavelength is n _sb , the average refractive index of the light uniformizing layer is no _oc , and the physical thickness of the light uniformizing layer is _toc (Nm), and the relative refractive index difference Δ _(oc−sb) between the light homogenization layer and the substrate is Δ _(oc−sb) ≡ ((n _oc ) ² − (n _sb ) ² ) / (2 × ( _noc ) ² )
Defined as
(√ (2 × Δ _(oc−sb) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_9. The method according to any one of 1 to 8 above, wherein t _oc is selected so as to satisfy

10. The emission wavelength of the light emitting element is λ (nm), the average refractive index at the emission wavelength of the light homogenizing layer is n _oc , the average refractive index at the emission wavelength of the first conductivity type semiconductor layer is n ₁ , and the light homogenizing layer. the physical thickness and _t oc (nm), the relative refractive index difference of the light uniformizing layer and the first conductivity type semiconductor layer delta a _{(oc-1) Δ (oc} -1) ≡ ((n oc) 2 - ( n ₁ ) ² ) / (2 × (n _oc ) ² )
When defined as
(√ (2 × Δ _(oc−1) ) × n _oc × π × t _oc ) / λ ≧ π / 2
_10. The method according to any one of 1 to 9 above, wherein t _oc is selected so as to satisfy

11. The specific resistance ρ _oc (Ω · cm) of the entire light homogenizing layer is
0.5 ≦ ρ _oc
The light-emitting element according to any one of 1 to 10 above, wherein:

  12 12. The method according to any one of 1 to 11 above, wherein the light homogenizing layer is laminated as a plurality of layers.

13. In the step (j), the first conductivity type side electrode is _adjusted such that the width _{L1w of the} narrowest portion of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. 13. The method according to any one of 1 to 12 above, which is formed.

14 In the step (i), among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer, the width L _{2w of the} narrowest portion is not less than 15 μm. 14. The method according to any one of 1 to 13, wherein a part of the electrode is exposed.

15. 15. The method according to 14 above, wherein the L _2w is 30 μm or more.

  16. Any one of the above 1 to 15, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. The method of crab.

  17. Said 1-16, wherein said second conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ni, Pt, Pd, Mo, Au and combinations of two or more thereof. The method in any one of.

18. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The method according to any one of 1 to 17 above, wherein the method is a single layer.

  19. 19. The method according to any one of 1 to 18 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  20. 20. The method according to 19 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

21. It said _{fluoride, AlF x, BaF x, CaF} x, the method of the 20, wherein the selected from the group consisting of SrF _x and MgF _x.

22. Any of the above 1 to 21, wherein the thin film crystal layer is formed on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ and MgO. The method of crab.

  23. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 23. The method according to any one of 1 to 22 above, wherein an element selected from the group consisting of Al is contained.

24. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The method according to any one of 1 to 23, wherein:

  25. 25. The method according to any one of 1 to 24 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  26. 6. The method according to claim 5, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal layer by soldering.

  27. 7. The method according to claim 6, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having the metal layer by soldering.

  28. 26. The above-described 26, wherein the first conductivity type side electrode and the second conductivity type side electrode and the metal layer of the submount or the support are joined by metal solder alone, or metal solder and metal bumps. Or the method according to 27.

29. The method according to any one of the above 26 to 28 base material of the submount, or support, characterized _{AlN, Al 2 O 3, Si} , glass, SiC, diamond, to be selected from the group consisting of BN and CuW .

  30. 30. The method according to any one of 26 to 29, wherein a metal layer is not formed on a separation portion between the light emitting elements of the submount or the support.

  31. 6. The method according to 5 above, wherein a surface of the substrate on the first light extraction direction side is not flat.

  32. 7. The method according to claim 6, wherein the surface of the buffer layer on the first light extraction direction side is not flat.

33. The reflectance of the light having the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is R3, and the light emission of the light emitting element is perpendicularly incident on the first light extraction direction side space from the substrate. When the reflectance at which the wavelength of light is reflected at the interface with the space is represented by R4,
R4 <R3
6. The method according to 5 above, wherein a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above.

34. The reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the light uniformizing layer is reflected by the buffer layer is R3, and the light is perpendicularly incident on the first light extraction direction side space from the buffer layer. When the reflectance at which the light of the emission wavelength of the light emitting element is reflected at the interface with the space is represented by R4,
R4 <R3
7. The method according to claim 6, wherein a low reflection optical film is provided on the first light extraction direction side of the buffer layer so as to satisfy the above condition.

  35. 35. The method according to any one of the above items 1 to 34, wherein the substrate is GaN, and all of the buffer layer is formed of GaN at a temperature of 900 ° C. or higher.

  According to the manufacturing method described above, a flip-chip mount type light emitting device capable of emitting blue or ultraviolet light and having high output, high efficiency, and high uniformity of brightness on the first light extraction direction side. The manufacturing method of the semiconductor light-emitting device can be provided.

  In the above manufacturing method, since process damage in each step in the manufacturing process is eliminated, a highly reliable element can be manufactured without impairing the function of the light emitting element.

  According to said manufacturing method, the light emitting element disclosed in type A and type B can be manufactured. This manufacturing method has steps (a) to (j), and the order of the steps is shown in the flowchart of FIG. Steps (a), (b) and (c) are performed in this order. Steps (d) and (e) are carried out after step (c), but the order of steps (d) and (e) may be either. Then, after implementing a process (f), processes (g), (h), and (i) may be performed in any order, and may be performed simultaneously.

  When peeling off the substrate used for thin film crystal growth, it is carried out after the step (j).

  The specific contents of each step are as already described in Type A and Type B, and the above manufacturing method includes all of the contents. However, in the light-emitting element disclosed in type A, since the buffer layer has an arbitrary configuration, the step of forming the buffer layer is omitted when a light-emitting element having no buffer layer is manufactured.

  Further, the shape of the element end, the shape of the groove bottom surface and the side wall surface of the insulating layer are different depending on the difference of the step (e) and the step (g).

<< 2-4. Type C >>
The characteristics of the type C light emitting element are specified by the following matters.

1. On the substrate transparent to the emission wavelength, the first conductive type semiconductor layer including the buffer layer, the first conductive type cladding layer, the active layer structure, and the second conductive type semiconductor layer including the second conductive type cladding layer are provided. A compound semiconductor light emitting device having a compound semiconductor thin film crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer.

2. For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which a part of the buffer layer forms a receding side wall surface, and an end step surface is formed between the buffer layer and a non-backed side wall surface that is not receded, or (ii) A shape in which the buffer layer is all receded and the exposed portion of the substrate forms an end step surface,
Having any of the following shapes;
2. The light emitting device as described in 1 above, wherein the insulating layer covers a surface on an end step surface from a position away from an end of the light emitting element and a surface coinciding with a receding side wall surface of the first conductivity type semiconductor layer. element.

3. For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which part of the buffer layer forms a receding side wall surface and an end step surface is formed between the buffer layer and the non-backed side wall surface that is not receded, or (ii) All of the buffer layers recede, and the exposed portion of the substrate has any shape that forms an end step surface;
2. The light emitting device according to 1 above, wherein the insulating layer covers at least a part of the receding side wall surface of the buffer layer but is not formed on the end step surface.

4). 4. The light emitting device according to any one of 1 to 3 above, wherein the width _{L1w of the} narrowest portion among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. .

5). 4. The width L _{2w of the} narrowest part among the widths of the part where the second conductivity type side electrode is covered with the insulating layer is 15 μm or more, Light emitting element.

6). 6. The light emitting device according to 5 above, wherein the L _2w is 100 μm or more.

7). The width L _ws of the narrowest portion of the end surface portion that is not covered with the insulating layer among the substrate surface exposed by the receding side wall surface of the thin film crystal layer is 15 μm or more. The light emitting element in any one.

  8). Any one of the above 1 to 7, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. A light emitting device according to any one of the above.

  9. Said 1-8, wherein said second conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ni, Pt, Pd, Mo, Au and combinations of two or more thereof. The light emitting element in any one of.

10. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The light-emitting element according to any one of 1 to 9 above, wherein the light-emitting element is a single layer.

  11. 10. The light emitting device as described in any one of 1 to 9 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  12 12. The light-emitting element according to 11 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

13. 13. The light emitting device as described in 12 above, wherein the fluoride is selected from the group consisting of AlF _x , BaF _x , CaF _x , SrF _x and MgF _x .

14 Wherein the substrate, _sapphire, SiC, GaN, LiGaO 2, _ZnO, light-emitting device according to any one of the above 1 to 13, characterized in that it is selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO.

  15. 15. The light-emitting element according to any one of 1 to 14 above, wherein a surface of the substrate on the first light extraction direction side is not flat.

16. The reflectance of the light having the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is R3, and the light emission of the light emitting element is perpendicularly incident on the first light extraction direction side space from the substrate. When the reflectance at which the wavelength of light is reflected at the interface with the space is represented by R4,
R4 <R3
16. The light emitting device according to any one of 1 to 15, wherein a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above.

  17. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 17. The light emitting device as described in any one of 1 to 16 above, which contains an element selected from the group consisting of Al.

18. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
18. The light-emitting element according to any one of 1 to 17 above, wherein

  19. 19. The light emitting device as described in any one of 1 to 18 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  20. 20. The light emitting device according to any one of 1 to 19, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal layer by solder.

  According to the type C light emitting element, it is possible to provide a flip chip mount type semiconductor light emitting element which is a light emitting element capable of emitting blue or ultraviolet light and which has high output and high efficiency.

  In the structure of the light emitting element of type C, process damage in each step in the manufacturing process is eliminated, so that the function of the light emitting element is not impaired and the element is highly reliable.

  FIGS. 4-1A and 4-2A show typical examples of type C compound semiconductor light emitting devices (hereinafter simply referred to as light emitting devices). FIGS. 4-1B and 4-2B are diagrams in which a part of FIGS. 4-1A and 4-2A is omitted for explanation, and FIGS. 4A and 4B illustrate the structure of the light emitting element. It is a figure which shows the shape in the middle of preparation in order to demonstrate in detail. Hereinafter, a description will be given with reference to FIGS. 4-1A to 4-3B.

  As shown in FIGS. 4A and 4A, the type C light emitting device 10 includes a first conductive semiconductor layer, a second conductive type, and a buffer layer 22 and a first conductive clad layer 24 on a substrate 21. A second conductive type semiconductor layer including the cladding layer 26, a compound semiconductor thin film crystal layer having an active layer structure 25 sandwiched between the first and second conductive type semiconductor layers, a second conductive type side electrode 27, and A first conductivity type side electrode 28 is provided.

  The second conductivity type side electrode 27 is arranged on a part of the surface of the second conductivity type clad layer 26, and the portion where the second conductivity type clad layer 26 and the second conductivity type side electrode 27 are in contact is the second current. An injection region 35 is formed. Further, the second conductivity type cladding layer 26, a part of the active layer structure 25, and a part of the first conductivity type cladding layer 24 are removed, and the first conductivity type cladding exposed at the removed portion. By arranging the first conductivity type side electrode 28 in contact with the layer 24, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the substrate 21. It is configured. The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are respectively connected to the metal layer 41 on the submount 40 via the metal solder 42.

  In the light emitting element 10 of type C, the first conductivity type side electrode 28 and the second conductivity type side electrode 27 do not spatially overlap each other. This means that the shadow does not overlap when the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are projected onto the substrate surface, as shown in FIG. 4A.

  When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” or the like. At the same time, in the type C light emitting element, the insulating layer 30 is arranged at an optimal position so as not to damage the element and affect the performance or affect the yield.

  The type C light emitting element 10 can take different forms at two locations: (I) a stepped shape at the end of the light emitting element 10 and (II) a shape of the insulating layer 30 at the end of the light emitting element. (I) The stepped shape at the end of the light emitting element 10 is roughly divided by the etching depth when forming the inter-device separation groove 13 (see FIG. 4-3A and the like) in the manufacturing process. (I) The buffer layer 22 There are two options: (ii) to the substrate surface (or deeper). Further, since the wall surface of the inter-device isolation groove 13 recedes from the element end after element isolation, in the type C light-emitting element 10, the surface that appears as the side wall surface when forming the inter-device isolation groove 13 is used as the element after element isolation. Is referred to as "retreating side wall surface". Further, the side wall surface that appears at the element end due to element isolation is referred to as a “non-retreat side wall surface”. A stepped surface is formed at the end of the light emitting element 10 between the receding side wall surface and the non-backed side wall surface, and this is referred to as an “end stepped surface”.

  Corresponding to the depths (i) to (ii) of the inter-device separation groove 13, in (i), part of the buffer layer 22 forms a receding side wall surface with respect to the receding side wall surface of the thin film crystal layer. The side wall of the remaining buffer layer 22 (on the first light extraction direction side) is a non-retreating side wall surface, and has an end step surface 55 at the end of the buffer layer 22. In (ii), the side wall of the buffer layer 22 also forms a receding side wall surface (because it becomes the side wall surface of the inter-device separation groove 13), so that the portion where the substrate 21 is exposed becomes the end step surface 55. .

  FIGS. 4-1C and 4-2C correspond to (i). FIG. 4-1A (FIG. 4-1B) and FIG. 4-2A (FIG. 4-2B) correspond to (ii).

  (II) Regarding the shape of the insulating layer 30 at the end of the light emitting element, in the manufacturing process, (i) a region including the center on the groove bottom surface while leaving the insulating layer 30 formed on the side wall of the inter-device separation groove 13 (Ii) In addition to all of the insulating layer 30 formed on the bottom surface of the groove, the insulating layer 30 including part of the side wall in the groove is removed. In the light emitting device 10 manufactured as a result, there are two types: (i) a shape in which the insulating layer 30 is attached to the groove bottom surface, and (ii) a shape in which the insulating layer 30 is separated from the groove bottom surface. FIG. 4-1A (FIG. 4-1B) and FIG. 4-1C correspond to (i). FIG. 4-2A (FIG. 4-2B) and FIG. 4-2C correspond to (ii).

  The shape of the light emitting element 10 of type C will be described separately according to (II) the shape of the insulating layer 30 at the end of the light emitting element as (i): the first mode and (ii): the second mode.

[First embodiment]
The forms belonging to the first mode are shown in FIGS. 4-1A to 4-1C. First, a typical form will be described with reference to FIG. Among the thin film crystal layers, at least the first conductive semiconductor layer, the active layer structure 25 and the side wall surfaces of the second conductive semiconductor layer are recessed from the end of the substrate 21. This shape appears in all forms of Type C. As shown in FIG. 4-3A, after the thin film crystal layer is formed in the manufacturing process, the thin film crystal layer is removed to a predetermined depth by a method described later in order to separate each element. This is because the separation groove 13 is formed and the elements are separated in the separation groove. FIG. 4-1A shows an example in which the thin film crystal layer is removed until the substrate 21 is reached, and is one of the preferred forms of type C. In the type C light emitting device 10, the thin film crystal layer, in particular, the first conductive type semiconductor layer, the active layer structure 25 and the second conductive type semiconductor layer, which are parts related to essential functions such as current injection and light emission, are generally used. Since the device is separated without undergoing a process of device separation such as scribe and braking, the thin film crystal layer related to performance is not directly damaged. For this reason, performances such as tolerance and reliability are excellent particularly in large current injection.

  The side wall surface exposed when the thin film crystal layer is removed is covered with the insulating layer 30.

  Further, before the element division, as shown in FIG. 4A, the insulating layer 30 does not cover the entire groove bottom surface of the inter-device isolation groove 13, but the insulating layer 30 is formed on the substrate surface (that is, the groove bottom surface). A scribe region 14 that is not formed is formed. Since only the substrate 21 has to be scribed and braked during element separation such as scribe and braking during the manufacturing process, the thin film crystal layer is not directly damaged. In addition, since the insulating layer 30 does not peel off, reliable insulation can be maintained, and the thin film crystal layer is not damaged by the tension generated when the insulating layer 30 peels off.

In the separated light-emitting element 10 obtained as a result, as shown in part A of FIGS. 4-1A and 4-1B, the entire surface of the substrate surface exposed by retreating the side wall surface of the thin film crystal layer is covered with the insulating layer. 30 does not cover, but covers the substrate surface inside the position away from the end of the substrate 21 by _Lws . If it is divided from the center of the width of the scribe region 14, the distance L _ws not covered by the insulating layer 30 corresponds to approximately ½ of the width of the scribe region 14 in the range of manufacturing fluctuations. That is, as a result of ensuring that the insulating layer 30 is not peeled off from the side surface of the thin film crystal layer by this shape, the light-emitting element 10 has an unintentional short circuit even if the solder wraps around. In addition to being prevented, the thin film crystal layer is not damaged, so that the function of the light emitting element 10 is not impaired and the element is highly reliable.

L _ws may be larger than 0 in a completed device, but is usually 10 μm or more, preferably 15 μm or more. As a design value, if the width of the scribe region 14 is 2L _ws , 2L _ws is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _WS is usually 300 μm or less, preferably 200 μm or less.

  It is also a preferred form that the inter-device separation groove 13 is formed partway through the buffer layer 22. As a result, in the completed light-emitting element 10, at least the first conductive type semiconductor layer, the active layer structure 25, and the second conductive type semiconductor layer are retracted inward from the end (substrate end) of the device, and are stepped based on the bottom surface of the groove. A surface parallel to the substrate surface (end parallel surface) exists at the end of the light emitting element 10. In FIG. 4A, the substrate surface itself corresponds to a surface parallel to the substrate surface.

FIG. 4C shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the buffer layer 22. As shown in part A, a part of the buffer layer 22 exists as a non-retreat side wall surface to the light emitting element end, and the wall surface retreats from the element end from the middle of the buffer layer 22 together with the side wall surface of the second conductivity type semiconductor layer A receding side wall surface (side wall of the inter-device separation groove) is formed. Between the non-retreat side wall surface and the retreat side wall surface, an end step surface 55 based on the bottom surface of the inter-device separation groove exists. Of the side wall of the buffer layer 22, the part of the non-retreating side wall surface is exposed, the part of the retreating side wall surface is covered with the insulating layer 30, and the end step surface 55 is located away from the end (FIG. 4B). The inner side is continuously covered with the receding side wall surface from the position corresponding to L _ws . This corresponds to a form in which the inter-device separation groove is stopped in the middle of the buffer layer 22 in FIG. 4A (FIG. 4B).

  As in these examples, even when the inter-device isolation groove 13 is formed up to the middle of the buffer layer 22, the insulating layer 30 covering the side wall does not reach the end of the light emitting element 10. The device is assured that the insulating layer 30 is not peeled, and the exposed layer is made of a highly insulating material, so that the device is as reliable as the light emitting element 10 in the form of FIG. It becomes.

[Second embodiment]
A form belonging to the second mode is shown in FIGS. 4-2A to 4-2C. The second aspect is the same as the first aspect in the layer configuration and the like, and (II) differs in the shape of the insulating layer 30 at the end of the light emitting element.

  First, as shown in FIG. 4A, the side wall surfaces of at least the first conductive semiconductor layer, the active layer structure 25, and the second conductive semiconductor layer among the thin film crystal layers are retreated from the edge of the substrate 21 to form the retreated side wall surface. Is configured. This shape appears in all forms of Type C. As shown in FIG. 4-3B, in the manufacturing process, after the thin film crystal layer is formed, the thin film crystal layer is removed by a method described later in order to separate the elements from each other. This is because the device is separated in the separation groove. As in the other aspects of Type C, at least the first conductivity type semiconductor layer (first conductivity type clad layer 24 in the figure) of the side wall surface exposed when the thin film crystal layer is removed, the active layer structure 25. The sidewall surfaces of the second conductivity type semiconductor layer (second conductivity type clad layer 26 in the figure) are covered with an insulating layer 30.

  In the second embodiment, the insulating layer 30 does not exist on the surface of the substrate 21 (the bottom surface of the inter-device separation groove). The insulating layer non-formed portion 15 which is not covered with the insulating layer 30 on the receding side wall surface of the thin film crystal layer is present at least on the first light extraction direction side of the side wall surface of the buffer layer 22. It may extend over the entire 22 side wall surfaces. In addition, when the inter-device separation groove 13 is formed by etching up to a part of the substrate 21, only the substrate portion of the wall surface of the groove is exposed and the buffer layer 22 may be covered.

  In this case, it is preferable that the buffer layer 22 of the insulating layer non-forming portion 15 that is not covered with the insulating layer 30 is an undoped undoped layer. If the exposed part is a highly insulating material, there is no possibility of short circuit due to the wrapping of solder, and the element is highly reliable.

  As shown in FIG. 4B, this structure corresponds to the shape before the element division during the manufacturing process, and the insulating layer 30 includes a substrate surface in the groove of the inter-device separation groove 13 and a groove adjacent to the substrate surface. It is removed from the insulating layer non-forming portion 15 on the side wall surface.

  Since the insulating layer 30 is not formed on the portion in contact with the substrate 21, only the substrate 21 has to be scribed and braked when separating elements such as scribe and braking during the manufacturing process. There is no direct damage. In addition, since the insulating layer 30 does not peel off, reliable insulation can be maintained, and the thin film crystal layer is not damaged by the tension generated when the insulating layer 30 peels off.

  In the resulting light-emitting device after separation, the insulating layer 30 covers the exposed substrate surface as the side wall surface of the thin film crystal layer recedes as shown in part A of FIGS. 4-2A and 4-2B. Not. As a result of ensuring that the insulating layer 30 is not peeled off from the side surface of the thin film crystal layer by this shape, the light-emitting element prevents an unintended short circuit even if the solder wraps around. In addition, since the thin film crystal layer is not damaged, the function of the light emitting element is not impaired and the element is highly reliable.

  Also in the second aspect, it is also a preferred form that the inter-device separation groove 13 is formed partway through the buffer layer 22. As a result, in the completed light emitting device, at least the first conductive type semiconductor layer, the active layer structure 25, and the second conductive type semiconductor layer are retracted inward from the end (substrate end) of the device, and the substrate is formed by a step based on the groove bottom surface. A plane parallel to the plane (end parallel plane) exists at the end of the light emitting element.

  FIG. 4-2C shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the buffer layer 22. As shown in part A, a part of the buffer layer 22 exists as a non-retreat side wall surface to the light emitting element end, and the wall surface retreats from the element end from the middle of the buffer layer 22 together with the side wall surface of the second conductivity type semiconductor layer. A receding side wall surface (side wall of the inter-device separation groove) is formed. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. The non-retreat side wall surface (side wall portion of the element end) and the end step surface are not covered with the insulating layer 30, and the retreat side wall surface (side wall of the inter-device isolation groove) is covered with the insulating layer 30. The non-insulating layer non-forming portion 15 exists on the first light extraction direction side. The insulating layer non-forming portion 15 may extend over the entire side wall surface of the buffer layer 22 in some cases.

  Even when the inter-device separation groove is formed partway through the buffer layer 22 as in this example, the device in which the insulating layer 30 covering the side wall has a shape that does not reach the end of the light emitting element is By ensuring that the insulating layer 30 is not peeled off and the exposed layer is made of a highly insulating material, the device can be as reliable as the light emitting element 10 in the form of FIG. 4-2A.

In common with the first mode and the second mode, in the type C light emitting device, the insulating layer 30 is formed of the first conductivity type side electrode 28 as shown in B part of FIGS. 4-1B and 4-2B. Is in contact with a part of the substrate side (first light extraction direction side). That is, the insulating layer 30 is interposed between the first conductivity type side electrode 28 and the first conductivity type semiconductor layer (in this embodiment, the first conductivity type cladding layer 24). As a result, the area of the first conductivity type side electrode 28 is larger than the area of the first current injection region 36. As shown in FIGS. 4-1B and 4-2B, if the width of the narrowest portion among the widths of the portions where the first conductivity type side electrode 28 is in contact with the insulating layer 30 is L _1w , L _1w is It is preferably 7 μm or more, particularly preferably 9 μm or more. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

Furthermore, the insulating layer 30 covers a part of the sub-mount side (opposite to the first light extraction direction) of the second conductivity type side electrode 27 as shown in part C of FIGS. 4-1B and 4-2B. ing. That is, the area of the electrode exposed portion 37 of the second conductivity type side electrode 27 is smaller than the area of the second conductivity type side electrode 27, and the area of the second current injection region 35 is equal to the area of the second conductivity type side electrode 27. equal. As shown in FIGS. 4-1B and 4-2B, if the width of the narrowest portion of the width covered by the insulating layer 30 from the periphery of the second conductivity type side electrode 27 is L _2W , L _2W Is preferably 15 μm or more. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can. L _2w is usually 2000 μm or less, preferably 750 μm or less.

  In addition, the first conductivity type semiconductor layer (first conductivity type clad layer 24 in this embodiment) and the submount side (first light extraction direction) of the second conductivity type semiconductor layer (second conductivity type clad layer 26 in this embodiment). The exposed portion of the surface on the opposite side is usually covered with an insulating layer 30 as shown in FIG.

  Due to such a positional relationship between the insulating layer 30 and the electrodes 27 and 28, it is possible to manufacture by a process with little process damage.

  In the type C light emitting device, as described above, the insulating layer 30 is arranged in consideration of process damage, heat dissipation when flip chip mounting is performed, insulation, and the like.

  Below, each member and structure which comprise a light emitting element are demonstrated in detail.

<Board>
The material of the substrate 21 is not particularly limited as long as it is optically approximately transparent with respect to the light emission wavelength of the element. Here, “substantially transparent” means that there is no absorption with respect to the emission wavelength, or even if there is absorption, the light output is not reduced by 50% or more due to absorption of the substrate.

The substrate is preferably an electrically insulating substrate. This is because even when a solder material or the like adheres to the periphery of the substrate when flip chip mounting is performed, current injection into the light emitting element is not affected. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light emitting material or an InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. In particular, sapphire, GaN, and ZnO substrates are preferable. In particular, when a GaN substrate is used, the Si doping concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or less, more preferably 8 × 10 ¹⁷ cm ⁻ when an undoped substrate is intentionally used. ^It is desirable that it is ³ or less from the viewpoints of electrical resistance and crystallinity.

  The substrate used in the type C light emitting device is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off-substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. There can also be. Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when a sapphire c + plane substrate is used as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture a compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. In addition, the substrate is intentionally roughened in relation to the buffer layer, which will be described later, thereby introducing a threading transition that occurs at the interface between the thin film crystal layer and the substrate near the active layer of the light emitting device. It is also possible not to do so.

  As for the thickness of the substrate, in one type of type C light emitting element, it is usually about 250 to 700 μm at the initial stage of element production, and the crystal growth of the light emitting element and the mechanical strength in the element production process are ensured. It is normal to do so. After growing a thin film crystal layer using this, in order to make it easy to separate each element, it is appropriately thinned during the process by a polishing process, and finally the apparatus has a thickness of about 100 μm or less. desirable. Moreover, it is the thickness of 30 micrometers or more normally.

  Further, in a different form of the type C light emitting element, the thickness of the substrate may be thick unlike the conventional case, and may be about 350 μm, further about 400 μm, or about 500 μm.

Further, it is desirable that a so-called low reflection coating layer or low reflection optical film is formed on the surface of the substrate on the first light extraction direction side. Reflection due to a difference in refractive index at the substrate-air interface can be suppressed, so that high output and high efficiency of the device can be achieved. Here, the reflectance of the light emitting wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is R3, and the reflectance of the light emitting element that is perpendicularly incident on the first light extraction direction side space from the substrate is R3. When the reflectance at which the light of the emission wavelength is reflected at the interface with the space is represented by R4,
R4 <R3
It is preferable that a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above condition. For example, when the substrate is sapphire, it is desirable to use MgF ₂ or the like as the low reflection coating film. Relative refractive index n _s of the substrate at the emission wavelength, the refractive index of the low reflecting coating film, since it is desirable near √n _s, relative to the square root of the refractive index of the sapphire, the refractive index of MgF ₂ are close It is.

It is also preferable that the surface on the first light extraction direction side of the substrate is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Further, when the emission wavelength of the element is λ (nm), the roughness of the rough surface is the average roughness Ra (nm).
λ / 5 (nm) <Ra (nm) <10 × λ (nm)
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

<Buffer layer>
The buffer layer 22 is mainly a thin film, such as suppressing transition, mitigating imperfections in the substrate crystal, and reducing various mutual mismatches between the substrate crystal and the desired thin film crystal layer when the thin film crystal is grown on the substrate. Formed for the purpose of crystal growth.

  The buffer layer is formed by thin film crystal growth, and thin film crystal growth of InAlGaN-based material, InAlBGaN-based material, InGaN-based material, AlGaN-based material, GaN-based material, etc., which is a desirable form for a type C light-emitting element, is performed on a different substrate. In this case, the buffer layer is particularly important because the lattice constant matching with the substrate is not necessarily ensured. For example, when a thin film crystal layer is grown by metal organic vapor phase epitaxy (MOVPE), a low temperature growth AlN layer near 600 ° C. is used as a buffer layer, or a low temperature growth GaN layer formed near 500 ° C. is used. It can also be used. Also, AlN, GaN, AlGaN, InAlGaN, InAlBGaN, etc. grown at a high temperature of about 800 ° C. to 1000 ° C. can be used. These layers are generally thin and about 5-40 nm.

  The buffer layer 22 is not necessarily a single layer, and a GaN layer grown at a temperature of about 1000 ° C. without doping is further formed on the GaN buffer layer grown at a low temperature in order to improve the crystallinity. You may make it have about several micrometers. Actually, it is usual to have such a thick film buffer layer, and the thickness is about 0.5 to 7 μm. The buffer layer may be doped with Si or the like, or may be formed by stacking a doped layer and an undoped layer in the buffer layer.

  Two typical forms are a low-temperature buffer layer in which a thin film crystal is grown at a low temperature of about 350 ° C. to less than 650 ° C. in contact with the substrate, and a high-temperature buffer layer in which a thin film crystal is grown at a high temperature of about 650 ° C. to 1100 ° C. The thing of a layer structure is mentioned. When the substrate is GaN, all of the buffer layer can be GaN formed at a high temperature of 900 ° C. or higher.

  For the formation of the buffer layer, lateral growth technology (ELO), which is a kind of so-called microchannel epitaxy, can also be used, thereby reducing the density of threading transitions generated between a substrate such as sapphire and an InAlGaN-based material. It can also be greatly reduced. Furthermore, even when using a processed substrate in which the surface of the substrate is processed to have irregularities, it is possible to eliminate some of the dislocations during lateral growth, and such a substrate and a buffer layer It is preferable to apply this combination to the present invention. Further, in this case, the unevenness formed on the substrate has an effect of improving the light extraction efficiency, which is preferable.

  Further, although the buffer layer may become an exposed portion of the inter-device separation groove, the exposed portion is preferably an undoped portion. Thereby, the insulation failure by the solder | pewter etc. at the time of apparatus assembly can be suppressed.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
In the type C light emitting device, since the light uniformizing layer does not exist, the first conductive type semiconductor layer including the first conductive type cladding layer is the same as that described in the type A except that it exists in contact with the buffer layer. The configuration can be adopted.

<Active layer structure>
The active layer structure in the type C light emitting device can employ the same structure as that used in the type A light emitting device.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductive type semiconductor layer and the second conductive type cladding layer in the type C light emitting element can adopt the same configuration as that used in the type A light emitting element.

<Second conductivity type side electrode>
The second conductivity type side electrode in the type C light emitting element can adopt the same configuration as that used in the type A light emitting element.

<First conductivity type side electrode>
The first conductivity type side electrode in the type C light emitting element can adopt the same configuration as that used in the type A light emitting element.

<Insulating layer>
The insulating layer in the type C light emitting element can adopt the same configuration as that used in the type A light emitting element.

<Submount>
The submount in the type C light emitting element can adopt the same configuration as that used in the type A light emitting element.

[Method for Manufacturing Type C Light-Emitting Element]
Next, a method for manufacturing a type C light emitting device will be described.

<Embodiment 1 of Manufacturing Method>
In Embodiment 1 of the manufacturing method, a method for manufacturing the light emitting element shown in FIG. 4-1C will be described mainly using the light emitting element shown in FIG. As shown in FIG. 4-5, first, a substrate 21 is prepared, and a buffer layer 22, a first conductivity type cladding layer 24, an active layer structure 25, and a second conductivity type cladding layer 26 are sequentially formed on the surface by thin film crystal growth. Film. The MOCVD method is preferably used for forming these thin film crystal layers. However, the MBE method, the PLD method, the PED method, the VPE method, the LPE method, and the like can also be used to form the entire thin film crystal layer or a part of the thin film crystal layer. These layer configurations can be appropriately changed according to the purpose of the element. Further, after the formation of the thin film crystal layer, various kinds of treatments may be performed. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  In order to realize the shape shown in FIGS. 4-1A, 4-1B, and 4-3A after the thin film crystal layer growth, as shown in FIG. It is preferable to form. That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. When the p-type electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface when the second conductivity type is p-type as a desirable form, this is compared with GaN-based materials. This is because the hole concentration in the p-GaN clad layer with a low effective activation rate is lowered by process damage. For example, if the step of forming the insulating layer by p-CVD is performed before the formation of the second conductivity type side electrode, plasma damage remains on the surface. Therefore, after the thin film crystal growth, the formation of the second conductivity type side electrode may be performed in other process steps (for example, a first etching step, a second etching step, or an insulating layer forming step, which will be described later, the exposed portion of the second conductivity type side electrode). It is desirable to carry out prior to the forming step, the first current injection region forming step, the first conductivity type side electrode forming step, and the like.

  When the second conductivity type is p-type, as described above, the case where the surface of the second conductivity type side electrode is Au is assumed as a typical example. If the metal is stable, the possibility of process damage is low even after the subsequent process. Also from this viewpoint, it is desirable that the formation of the second conductivity type side electrode is performed before the other process steps after the thin film crystal growth.

  Similarly, when the layer on which the second conductivity type side electrode is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer can be reduced.

  Various film formation techniques such as sputtering, vacuum deposition, and plating can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique or a metal A place-selective vapor deposition using a mask or the like can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 4-6, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, since the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask as will be described in detail in the second etching step described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, process damage received by the second conductivity type side electrode 27 is reduced.

  Next, as shown in FIG. 4-7, the inter-device separation groove 13 is formed by the second etching step. In Type C, the inter-device separation groove 13 needs to be formed by dividing at least the first conductivity type cladding layer. In this embodiment, the inter-device separation groove 13 is formed so as to reach the substrate 21. Is done. In this case, in order to separate the light emitting element, the GaN-based material is peeled off from the sapphire substrate even when diamond scribing is performed from the side where the thin film crystal layer is formed in a process such as scribing or breaking. Can be suppressed. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to form an inter-device separation groove by etching up to a part of a sapphire substrate (the same applies to other substrates such as GaN).

  On the other hand, a mode in which the inter-device separation groove 13 does not reach the substrate 21 is also a preferable mode. For example, if the inter-device isolation groove 13 is formed up to the middle of the buffer layer 22, the insulating layer 30 can be formed on the side wall of the first conductivity type clad layer 24. Insulation can be maintained (refer to FIG. 4C for the form after the light emitting element is completed). In this case, the groove bottom surface is formed in the middle of the buffer layer 22, and this becomes the end step surface 55 at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Since the bottom surface of the groove is subjected to processing such as scribing at the time of element isolation, the end step surface 55 after element isolation is often not high in terms of planarity as a surface and parallelism with the layer direction. The layer exposed from the side wall without being covered with the insulating layer 30 preferably has high insulating properties.

  In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. In general, the total sum of the layers etched by the first etching process is usually about 0.5 μm. However, in the second etching process, all of the first conductivity type cladding layer 24 and at least a part of the buffer layer 22 are used. In some cases, since it is necessary to etch the whole, it may be 3 to 7 μm, and in some cases, it may be in the range of 3 to 10 μm, and may exceed 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that requires etching of the system material, a relatively thick SiN _x film is required. For example, when a 10 μm GaN-based material is etched in the second dry etching step, a SiN _x mask exceeding 2 μm is required. However, at the SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the inter-device separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first and second etching steps, while it can be easily etched for patterning etching (preferably wet etching). In addition, a patterning shape, particularly one having good linearity in the side wall portion is required. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in controllability of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, when a mask such as SrF ₂ is exposed to plasma such as chlorine during dry etching of a semiconductor layer, the etching rate at the time of subsequent mask layer removal is lower than before exposure to plasma such as chlorine. Have a tendency to For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _4-16, SiN x, SiO ₂ or the like mask 51, Even if it does not exist in the entire lower part of the metal fluoride mask layer 52, it should be formed on a material that is at least sensitive to acids.

  By such a second etching step, an inter-device separation groove 13 is formed as shown in FIG. 4-7.

Note that the first etching step and the second etching step may be performed either first or later. In order to simplify the process, it is also preferable to perform the first etching step first and then perform the second etching step without removing the etching mask at that time. As shown in FIG. 4-16, first, a first etching mask 51 is formed of an acid-resistant material such as SiN _x and SiO ₂ (preferably SiN _x ), and etching is performed so that the first conductivity type cladding layer 24 appears. The second etching mask 52 made of a metal fluoride layer is formed without removing the mask 51. And after implementing a 2nd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the device manufacturing process and further for securing the scribe region.

  The “recessed side wall surface” defined in the description of type C is a side wall surface that appears as a side wall in the second etching step, that is, the formation of the inter-device separation groove, and is not a wall surface that appears only in the first etching.

  After the second etching step, an insulating layer 30 is formed as shown in FIG. 4-8. The insulating layer 30 can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

Next, as shown in FIG. 4-9A, a predetermined portion of the insulating layer 30 is removed, and the second conductivity type side electrode exposed portion 37 from which the insulating layer 30 is removed on the second conductivity type side electrode 27, the first A first current injection region 36 from which the insulating layer 30 has been removed on the conductive clad layer 24 and a scribe region 14 from which the insulating layer 30 has been removed in the inter-device isolation trench 13 are formed. The insulating layer 30 on the second conductivity type side electrode 27 is removed such that the peripheral portion of the second conductivity type side electrode 27 is covered with the insulating layer 30. That is, the surface area of the second conductivity type side electrode exposed portion 37 is smaller than the area of the second current injection region. Here, a part of the second conductivity type side electrode 27 is covered with the insulating layer 30 in order to prevent an occurrence of an unintentional short circuit due to a margin of a photolithography process, particularly a photolithography process, or a solder material. The width (L _2w ) of the narrowest portion is preferably 15 μm or more as described above. More desirably, it is 100 μm or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can.

For the removal of the insulating layer 30, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer 30 is a single SiN _x layer, dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer 30 is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

As already described, the width of the scribe region 14 can be set so as to obtain a predetermined L _ws .

  Further, the second conductivity type side electrode exposed portion 37, the first current injection region 36, and the scribe region 14 may be formed separately, but are usually formed by etching at the same time. Even when the inter-device separation groove 13 is formed up to the middle of the buffer layer 22, when the insulating layer 30 is deposited by the above-described process, it differs in that it is deposited not on the substrate surface but on the groove bottom surface. The same process can be employed.

Next, as shown in FIG. 4-10, the first conductivity type side electrode 28 is formed. In Type C, the first conductivity type side electrode 28 is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are spatially separated. The feature is that there is no overlap. This is because when the element is flip-chip mounted with solder or the like, the second conductivity type side electrode 27 and the first conductivity type side are secured while ensuring a sufficient area to ensure sufficient adhesion with the submount or the like. This is important for securing a sufficient distance to prevent an unintended short circuit due to a solder material or the like between the electrode 28 and the like. Among the widths of the portion where the first conductivity type side electrode 28 is in contact with the insulating layer 30, the width (L _1w ) of the narrowest portion is set to be in the above-described range. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from any one of Ti, Al, Ag, and Mo. Further, Al is usually exposed in the direction facing the first light extraction direction of the n-side electrode.

  Various film formation techniques such as sputtering, vacuum evaporation, plating, etc. can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique, a metal mask, or the like was used. Site selective vapor deposition or the like can be used as appropriate.

  In this example, the first conductivity type side electrode 28 is formed so as to be in contact with a part of the first conductivity type clad layer 24. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact therewith. can do.

  In the method for manufacturing a type C light emitting device, the first conductivity type side electrode 29 is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is preferably formed with Al on the surface of the electrode material. In this case, if the n-side electrode is formed before the formation of the insulating layer 30 like the second conductivity type side electrode 27, the surface of the n-side electrode, that is, the Al metal, has a history of the etching process of the insulating layer 30. Will do. As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching the insulating layer 30, but Al has low resistance to various etchants including hydrofluoric acid, and this process is effective. If implemented, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, the formation of the first conductivity type side electrode 28 after the formation of the insulating layer 30 and after the removal of a predetermined unnecessary portion of the insulating layer 30 is effective in reducing damage to the electrode.

  After the structure of FIG. 4-10 is formed in this way, diamond scribing is performed on the substrate 21 using the inter-device separation grooves 13 in order to separate each compound semiconductor light emitting element one by one. A part of the substrate material is ablated by laser scribing.

  In addition, the inter-device separation groove 13 may be formed up to the middle of the buffer layer 22. In this case, the inter-device separation groove 13 is used to damage the substrate 21 by diamond scribe. A part of the substrate material is ablated by laser scribing.

  In this embodiment, since there is no thin film crystal layer that affects the performance in the inter-device isolation groove 13 during the element isolation step, no process damage is introduced into the thin film crystal layer. Further, since the insulating layer 30 does not exist in the scribe region 14, there is no possibility that the insulating layer 30 is peeled off at the time of scribing.

  After the scribe is completed, the compound semiconductor light-emitting element is divided into one device at a time in the braking process, and is preferably mounted on the submount with a solder material or the like.

  As described above, the light-emitting element 10 illustrated in FIG. 4A is completed. Similarly, the light-emitting element shown in FIG. 4-1C can also be manufactured.

  In this manufacturing method, as described, formation of the thin film crystal layer, formation of the second conductivity type side electrode 27, etching process (first etching process and second etching process), formation of the insulating layer 30, removal of the insulating layer 30 ( The formation of the second conductivity type side electrode exposed portion, the formation of the first current injection region, the formation of the scribe region) and the formation of the first conductivity type side electrode 28 are preferably performed in this order. A light emitting element can be obtained in which the thin film crystal layer directly under the second conductivity type side electrode is not damaged and the first conductivity type side electrode 28 is not damaged. The device shape reflects the process flow. That is, the light emitting element has a structure in which the second conductivity type side electrode 27, the insulating layer 30, and the first conductivity type side electrode 28 are laminated in this order. That is, the second conductivity type side electrode 27 is in contact with the second conductivity type clad layer 26 (or other second conductivity type thin film crystal layer) without the insulating layer 30 interposed therebetween. There is a portion covered with an insulating layer 30 around the upper portion, and the area around the electrode is between the first conductivity type side electrode 28 and the first conductivity type side cladding layer 24 (or other first conductivity type thin film crystal layer). There is a portion where the insulating layer 30 is interposed.

<Embodiment 2 of Manufacturing Method>
In Embodiment 2 of the manufacturing method, a method for manufacturing the light-emitting element shown in FIG. 4-2C will be described mainly using the light-emitting element shown in FIG. 4-2A. In the second embodiment, the process up to the formation of the insulating layer 30 in the first embodiment is the same (FIGS. 4-5 to 4-8). Thereafter, in the first embodiment, only the region including the central portion of the inter-device separation groove on the substrate surface (groove bottom surface) is removed. However, in the second embodiment, as shown in FIG. Then, all of the insulating layer 30 on the substrate 21 (that is, the groove bottom surface) is removed, and a portion of the insulating layer 30 formed on the sidewall in the groove on the substrate 21 side (that is, the groove bottom surface side) is removed. The non-formed part 15 is used. As a forming method, the following process is possible. First, a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device separation groove 13 is formed by photolithography, and then wet etching is performed using an etchant that can etch the insulating layer 30. Removal of the insulating layer 30 on the substrate surface in the separation groove 13 proceeds. Thereafter, when etching is continued for a longer time, side etching occurs, and the insulating layer 30 covering the substrate side of the trench sidewall is removed by a wet etchant, and the insulating layer 30 is formed on the substrate side wall as shown in FIG. 4-9B. A shape that does not exist is obtained.

  The side wall exposed by removing the insulating layer 30 is at least a portion of the side wall of the buffer layer 22 on the substrate side. In some embodiments, the entire side wall of the buffer layer 22 may be exposed. The exposed side wall where the insulating layer 30 is not present is preferably the side wall of the undoped layer. This is because, when flip chip mounting is performed, an unintended electrical short circuit does not occur even if solder for bonding with the submount adheres to the side wall. When the inter-device separation groove 13 is formed by etching up to a part of the substrate 21, only the substrate portion of the wall surface of the separation groove is exposed and the buffer layer 22 is covered with the insulating layer 30. There is.

  As in the first embodiment, the second conductivity type side electrode exposed portion 37, the first current injection region 36, and the insulating layer non-formed portion 15 may be formed separately, but are usually formed simultaneously by etching. .

  After that, the light-emitting element shown in FIG. 4-2A can be completed by a process similar to that of Embodiment 1.

  In the second embodiment of the manufacturing method, as in the first embodiment, a mode in which the inter-device separation groove 13 does not reach the substrate 21 is also a preferable mode. For example, if the inter-device isolation groove 13 is formed up to the middle of the buffer layer 22, the insulating layer 30 can be formed on the side wall of the first conductivity type clad layer 24. Insulation can be maintained (the light emitting element after completion is shown in FIG. 4-2C). In this case, the groove bottom surface is formed in the middle of the buffer layer 22, and this becomes the end step surface 55 at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. The layer exposed from the side wall without being covered with the insulating layer 30 preferably has high insulating properties. When the insulating layer 30 is deposited, the same process can be adopted although the insulating layer 30 is deposited not on the substrate surface but on the groove bottom surface. Otherwise, the light-emitting element shown in FIG. 4-2C can be manufactured in the same manner as in Embodiment 2.

  The light-emitting element manufactured by the process of Embodiment 2 (and its modification process) is also a device in which the insulating layer 30 covering the side wall is shaped so as not to reach the end of the light-emitting element, and the insulating layer 30 is peeled off. If the exposed layer is made of a highly insulating material, the device is as reliable as the light emitting element 10 in the form of FIG. 4A.

<< 2-5. Type D >>
The characteristics of the type D light emitting device are specified as follows.

1. A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
The first conductivity type side electrode and the second conductivity type side electrode are connected and have a support for supporting the light emitting element;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) When a part of the buffer layer constitutes a receding side wall surface and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that has not receded, At least an insulating layer formed from a position away from the end of the light emitting element, or (ii) when the buffer layer forms a receding side wall surface and has no end step surface, the buffer A compound semiconductor light emitting element comprising an insulating layer which covers the receding side wall surface from the middle of the buffer layer without being formed at least in a first light extraction direction portion of the layer.

2. For the receding sidewall surface of the thin film crystal layer,
(Ii) The buffer layers together form a receding side wall surface and there is no end step surface,
2. The light-emitting element according to claim 1, further comprising an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed on at least the first light extraction direction side portion of the buffer layer.

3. For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
2. The light emitting device according to 1 above, wherein the insulating layer covers at least a part of the receding side wall surface of the buffer layer but is not formed on the end step surface.

4). For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
2. The light emitting device according to 1 above, wherein the insulating layer covers a surface on an end step surface from a position away from an end of the light emitting element and a surface coinciding with a side wall receding surface of the first conductivity type semiconductor layer. element.

  5). 5. The light emitting device according to 4 above, wherein a layer constituting a portion of the buffer layer whose side wall surface is not covered with the insulating layer is an undoped type.

6). 6. The light emitting device according to any one of ₁ to 5 above, wherein the width _{L1w of the} narrowest portion among the widths of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. .

7). The width L _{2w of the} narrowest portion among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer is 15 μm or more, Light emitting element.

8). 8. The light emitting device as described in 7 above, wherein the L _2w is 100 μm or more.

  9. Any one of the above 1 to 8, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo, and combinations of two or more thereof. A light emitting device according to any one of the above.

  10. Said 1-9 characterized by said 2nd conductivity type side electrode including the layer which consists of a material containing the element chosen from the group which consists of Ni, Pt, Pd, Mo, Au, and those 2 or more types of combinations. The light emitting element in any one of.

11. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The light-emitting element according to any one of 1 to 10 above, wherein the light-emitting element is a single layer.

  12 12. The light-emitting element according to any one of 1 to 11 above, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  13. 13. The light-emitting element according to 12 above, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

14 14. The light emitting device as described in 13 above, wherein the fluoride is selected from the group consisting of AlF _x , BaF _x , CaF _x , SrF _x and MgF _x .

15. 1 to 14 above, wherein the thin film crystal layer is formed on a substrate selected from the group consisting of sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. The light emitting element in any one of.

  16. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 16. The light emitting device as described in any one of 1 to 15 above, which contains an element selected from the group consisting of Al.

17. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The light-emitting element according to any one of the above 1 to 16, wherein:

  18. 18. The light emitting device as described in any one of 1 to 17 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  19. 19. The light emitting device according to any one of 1 to 18 above, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having a metal layer by solder.

  20. 20. The above-described 19, wherein the first conductive type side electrode and the second conductive type side electrode and the metal layer of the support are joined only by metal solder or by metal solder and metal bumps. Light emitting element.

21. 21. The light emitting device as described in 19 or 20 above, wherein the base material of the support is selected from the group consisting of AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN and CuW.

  22. The light emitting device according to any one of the above 19 to 21, wherein a metal layer is not formed in a separation region between the light emitting devices of the support.

  23. 3. The light emitting device according to 2 above, wherein a surface of the substrate on the first light extraction direction side is not flat.

  24. 4. The light-emitting element according to 3 above, wherein a surface of the buffer layer on the first light extraction direction side is not flat.

25. The reflectance of the light having the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is R3, and the light emission of the light emitting element is perpendicularly incident on the first light extraction direction side space from the substrate. When the reflectance at which the wavelength of light is reflected at the interface with the space is represented by R4,
R4 <R3
3. The light emitting device according to 2, wherein a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above.

26. The reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer is reflected by the buffer layer is R3, and the reflectance from the buffer layer is perpendicular to the space on the first light extraction direction side. When the reflectance at which the light having the emission wavelength of the light emitting element that is incident is reflected at the interface with the space is represented by R4,
R4 <R3
4. The light-emitting element according to 3 above, wherein a low-reflection optical film is provided on the first light extraction direction side of the buffer layer so as to satisfy the above.

  According to the type D light emitting element, it is possible to provide a flip chip mount type semiconductor light emitting element which is a light emitting element capable of emitting blue or ultraviolet light and which has high output and high efficiency.

  In the structure of the type D light emitting element, process damage in each step in the manufacturing process is eliminated, so that the function of the light emitting element is not impaired and the element is highly reliable.

  FIGS. 5-1A, 5-2, and 5-3A show typical examples of type D compound semiconductor light-emitting elements (hereinafter simply referred to as light-emitting elements). FIGS. 5-1B and FIGS. 5-3B are FIGS. 5A and 5B with parts of FIGS. 5-1A and 5-3A omitted for the sake of explanation. FIG. 5-4A and FIG. 5-4B are diagrams showing shapes in the course of fabrication in order to explain the structure of the light emitting element in detail. Hereinafter, a description will be given with reference to FIGS. 5-1A to 5-4B.

  As shown in FIGS. 5-1A, 5-2, and 5-3A, the type D light emitting device includes a buffer layer 22, a first conductivity type semiconductor layer including a first conductivity type cladding layer 24, and a second conductivity type cladding. A second conductive type semiconductor layer including a layer 26, a compound semiconductor thin film crystal layer having an active layer structure 25 sandwiched between the first and second conductive type semiconductor layers, a second conductive type side electrode 27, and first A one-conductivity-type side electrode 28 is provided.

  The second conductivity type side electrode 27 is arranged on a part of the surface of the second conductivity type clad layer 26, and the portion where the second conductivity type clad layer 26 and the second conductivity type side electrode 27 are in contact is the second current. An injection region 35 is formed. Further, the second conductivity type cladding layer 26, a part of the active layer structure 25, and a part of the first conductivity type cladding layer 24 are removed, and the first conductivity type cladding exposed at the removed portion. By arranging the first conductivity type side electrode 28 in contact with the layer 24, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged on the same side with respect to the buffer layer 22. It is configured. The second conductivity type side electrode 27 and the first conductivity type side electrode 28 are connected to a metal layer 41 on the support 40 via a metal solder 42, respectively.

  In the light emitting element 10 of type D, the first conductivity type side electrode 28 and the second conductivity type side electrode 28 do not spatially overlap each other. As shown in FIGS. 5-1A, 5-2, and 5-3A, shadows appear when the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are projected onto the substrate surface. It means not overlapping.

  When the flip-chip mounting is performed, the insulating layer 30 is made of a mounting solder, a conductive paste material, etc. “between the second conductive type side electrode and the first conductive type side electrode”, “a thin film such as an active layer structure” This is to prevent an unintended short circuit from occurring around the “side wall of the crystal layer” or the like. At the same time, in the type D light emitting device 10, the insulating layer 30 is disposed at an optimal position so as not to damage the device and affect the performance or affect the yield.

  The type D light emitting element 10 can take different forms at two locations: (I) a stepped shape at the end of the light emitting element 10 and (II) a shape of the insulating layer 30 at the end of the light emitting element. (I) The step shape at the end of the light emitting element 10 is roughly divided by the etching depth when forming the inter-device isolation groove 13 (see FIG. 5-4A, etc.) for element isolation in the manufacturing process. There are two choices: (i) halfway through the buffer layer 22, (ii) up to the substrate surface (or deeper). In addition, since the wall surface of the inter-device isolation groove 13 recedes from the end of the element after element isolation, in Type D, the surface that appears as the side wall surface when forming the inter-device isolation groove 13 is referred to as “retreat. It is called “side wall surface”. Further, the side wall surface that appears at the element end due to element isolation is referred to as a “non-retreat side wall surface”. A stepped surface is formed at the end of the light emitting element 10 between the receding side wall surface and the non-backed side wall surface, and this is referred to as an “end stepped surface”.

  Corresponding to the depths (i) to (ii) of the inter-device separation groove 13, in (i), part of the buffer layer 22 forms a receding side wall surface with respect to the receding side wall surface of the thin film crystal layer. The side wall of the remaining buffer layer 22 (on the first light extraction direction side) is a non-retreating side wall surface, and has an end step surface 55 at the end of the buffer layer 22. In (ii), the side wall of the buffer layer 22 also constitutes a receding side wall surface (because it becomes the side wall surface of the inter-device separation groove 13), so in the type D light emitting device 10 in which the substrate 21 does not exist after the device is completed, There is no step surface. Even in the case of (ii), the wall surface of the inter-device separation groove 13 is receded compared to the element end face when separated without forming the inter-device separation groove 13. This is called the “retreat side wall surface”.

  FIGS. 5-2 and 5-3A (FIGS. 5-3B) correspond to (i). (Ii) It is FIG. 5-1A (FIG. 5-1B).

  (II) Regarding the shape of the insulating layer 30 at the end of the light emitting element, in the manufacturing process, (i) a region including the center on the groove bottom surface while leaving the insulating layer 30 formed on the side wall of the inter-device separation groove 13 (Ii) In addition to all of the insulating layer 30 formed on the bottom surface of the groove, the insulating layer 30 including part of the side wall in the groove is removed. In the light emitting device 10 manufactured as a result, there are two types: (i) a shape in which the insulating layer 30 is attached to the groove bottom surface, and (ii) a shape in which the insulating layer 30 is separated from the groove bottom surface. FIG. 5-3A (FIG. 5-3B) corresponds to (i). FIGS. 5-1A (FIG. 5-1B) and FIG. 5-2 correspond to (ii).

  In the light emitting element 10 of type D, since the growth substrate is removed during the manufacturing process, it is not preferable that the insulating layer 30 is attached to the substrate 21 when removing the substrate. Therefore, in combination with the above, (I) the step shape of the end of the light emitting element 10 is (ii) the shape in which the buffer layer 22 has no step, and (II) the shape of the insulating layer 30 at the end of the light emitting element is (I) The combination of the shape in which the insulating layer 30 is attached to the bottom surface of the groove is a form not included in the type D light-emitting element 10.

  The shape of the light emitting element 10 of type D is (II) the shape of the insulating layer 30 at the end of the light emitting element, the first aspect: (ii) the shape in which the insulating layer 30 is separated from the groove bottom surface, the second aspect: ( i) The insulating layer 30 will be described in the order of the shape attached to the bottom surface of the groove.

  However, in common with the light emitting element 10 of type D, the insulating layer 30 does not reach the end of the buffer layer 22 in the first light extraction direction.

[First embodiment]
The forms belonging to the first mode are shown in FIGS. 5-1A to 5-2. First, a typical form will be described with reference to FIG. As shown in FIG. 5A, the type D light-emitting element 10 does not have a substrate in the first light extraction direction. The insulating layer 30 includes at least a first conductivity type semiconductor layer (first conductivity type cladding layer 24 in the figure), an active layer structure 25, and a second conductivity type among the side wall surfaces exposed when the thin film crystal layer is removed. The side wall surface of the semiconductor layer (the second conductivity type cladding layer 26 in the figure) is covered. In addition, there is an insulating layer non-formation portion 15 that is not covered with the insulating layer 30 at least on the first light extraction direction side of the side wall surface of the buffer layer 22. It may be all over. As described above, in the type D light-emitting element 10, the insulating layer 30 does not exist at the element end of the buffer layer 22 on the first light extraction direction side. This is the same even when the buffer layer has an end step surface in other embodiments.

  In addition, the buffer layer 22 of the insulating layer non-forming portion 15 that is not covered with the insulating layer 30 is preferably an undoped portion that is not doped. If the exposed part is a highly insulating material, there is no possibility of short circuit due to the wrapping of solder, and the element is highly reliable.

  This structure passes through the shape shown in FIG. 5-4A before element separation during the manufacturing process. In the middle of the manufacturing process, the insulating layer 30 is removed from the substrate surface (groove bottom surface) in the groove of the inter-device separation groove 13 and the insulating layer non-forming portion 15 on the groove side wall surface adjacent to the substrate surface (groove bottom surface). Yes. In the type D light emitting device 10, the substrate 21 is peeled off during the manufacturing process. At this time, since the insulating layer 30 is not in contact with the substrate 21, the insulating layer 30 is not peeled when the substrate 21 is peeled off. Therefore, in addition to ensuring reliable insulation, the thin film crystal layer is not damaged by the tension generated when the insulating layer 30 is peeled off.

  In the separated light-emitting element 10 obtained as a result, as shown in part A of FIG. 5A, the insulating layer not covered with the insulating layer 30 on the first light extraction direction side of the wall surface of the buffer layer 22 A non-formed portion 15 is present. That is, as a result of this shape being ensured that the insulating layer 30 is not peeled off on the side surface of the thin film crystal layer, the light-emitting element 10 has an unintentional short circuit even if the solder wraps around. In addition to being prevented, the thin film crystal layer is not damaged, so that the function of the light emitting element 10 is not impaired and the element is highly reliable.

Furthermore, the insulating layer 30 is in contact with a part of the first conductivity type side electrode 28 on the substrate side (first light extraction direction side) as shown in a portion B of FIG. 5-1B. That is, the insulating layer 30 is interposed between a portion between the first conductivity type side electrode 28 and the first conductivity type semiconductor layer (first conductivity type cladding layer 24 in this embodiment). As a result, the area of the first conductivity type side electrode 28 is larger than the area of the first current injection region 36. As shown in FIG. 5B, when the width of the narrowest portion of the width of the portion where the first conductivity type side electrode 28 is in contact with the insulating layer 30 is L _1w , L _1w is preferably 7 μm or more. Particularly, 9 μm or more is preferable. Moreover, _L1w is 500 micrometers or less normally, Preferably it is 100 micrometers or less. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

Furthermore, the insulating layer 30 covers a part of the second conductivity type side electrode 27 on the support 40 side (opposite side to the first light extraction direction) as shown in a portion C of FIG. 5-1B. That is, the area of the electrode exposed portion 37 of the second conductivity type side electrode 27 is smaller than the area of the second conductivity type side electrode 27, and the area of the second current injection region 35 is equal to the area of the second conductivity type side electrode 27. equal. As shown in FIG. 5C, when the width of the narrowest portion of the width covered by the insulating layer 30 from the periphery of the second conductivity type side electrode 27 is L _2W , L _2W is 15 μm or more. It is preferable. More preferably, it is 30 micrometers or more, Most preferably, it is 100 micrometers or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can. L _2w is usually 2000 μm or less, preferably 750 μm or less.

  Further, the first conductive semiconductor layer (first conductive clad layer 24 in this embodiment) and the second conductive semiconductor layer (second conductive clad layer 26 in this embodiment) on the support 40 side (first The exposed portion of the surface on the opposite side of the light extraction direction is also usually covered with an insulating layer 30 as shown in the figure to prevent short circuits.

  Due to such a positional relationship between the insulating layer 30 and the electrodes 27 and 28, it is possible to manufacture by a process with little process damage.

[First aspect 2]
Other forms belonging to the first mode will be described with reference to FIG. 5A is different from the light emitting device 10 of FIG. 5A in that (I) the step shape of the end of the light emitting device 10 is (ii) the buffer layer 22 has no step. On the other hand, the light emitting element 10 shown in FIG. 5B is that (i) the end of the buffer layer 22 has an end step surface 55 based on the inter-device separation groove.

  This shape is produced by forming the inter-device isolation groove partway in the buffer layer 22, and as a result, in the completed eight light emitting element 10, at least the first conductive type semiconductor layer, the active layer structure 25, and the second conductive type The semiconductor layer recedes inward from the end of the light emitting element 10 to form a receding side wall surface, and an end step surface 55 exists between the element end wall surface (non-backward side wall surface).

  FIG. 5-2 shows an example of a light emitting device manufactured by forming the inter-device separation groove partway through the buffer layer 22. As shown in part A, a part of the buffer layer 22 exists as a non-retreat side wall surface up to the light emitting element end, the wall surface recedes from the element end from the middle of the buffer layer 22, and the side wall surface of the second conductivity type semiconductor layer In addition, a receding side wall surface (side wall of the inter-device separation groove) is formed. An end step surface 55 based on the bottom surface of the inter-device separation groove exists between the non-retreat side wall surface and the retreat side wall surface. The non-retreating side wall surface (side wall portion of the element end) is not covered with the insulating layer 30, the end step surface 55 is not covered with the insulating layer 30, and the retreating side wall surface (the separation groove between the devices) is not covered. In the side wall), the insulating layer non-forming portion 15 that is not covered with the insulating layer 30 exists on the first light extraction direction side. The insulating layer non-forming portion 15 may extend over the entire side wall surface of the buffer layer 22 in some cases.

  Even in the case where the inter-device isolation groove is formed up to the middle of the layer including the buffer layer 22 as in this example, the insulating layer 30 covering the side wall does not reach the end of the light emitting element 10. In the element, it is guaranteed that the insulating layer 30 is not peeled off, and the exposed layer is made of a highly insulating material, so that the reliability is the same as that of the light emitting element 10 in the form of FIG. It becomes a high element.

[Second embodiment]
In the second aspect, (II) the shape of the insulating layer at the end of the light emitting element is (i) the shape in which the insulating layer is attached to the bottom surface of the groove. As shown in FIG. 5-4B, the device isolation groove is formed up to the middle of the buffer layer 22 and the insulating layer 30 is formed on the bottom surface of the device isolation groove 13 before the device is divided. Rather than covering all, a scribe region 14 in which the insulating layer 30 is not formed is formed on the bottom surface of the groove. Therefore, the buffer layer 22 may be braked during element isolation such as scribe and braking during the manufacturing process, and the layer related to device performance among the thin film crystal layers, that is, the first conductivity type semiconductor layer and the active layer. The structure 25 and the second conductivity type semiconductor layer are not directly damaged. Further, since the insulating layer 30 is divided from the scribe region 14 without the insulating layer 30 at the bottom of the groove, the insulating layer 30 does not peel off, so that in addition to maintaining reliable insulation, the tensile force generated when the insulating layer 30 peels off, The thin film crystal layer is not damaged.

In the separated light-emitting device obtained as a result, as shown in part A of FIGS. 5-3A and 5-3B, the entire surface of the end step surface (groove bottom surface) formed in the buffer layer 22 is covered with an insulating layer. 30 does not cover, but covers the substrate surface on the inner side from the position separated by L _ws from the element end. When divided from the center of the width of the scribe region 14, the distance L _ws that is not covered with the insulating layer 30 corresponds to approximately ½ of the width of the scribe region 14 in the range of manufacturing fluctuation or the like. That is, this shape ensures that the insulating layer 30 is not peeled off from the side surface of the thin film crystal layer. As a result, the light-emitting element prevents an unintended short circuit even if the solder wraps around. In addition, since the thin film crystal layer is not damaged, the function of the light emitting element is not impaired and the element is highly reliable.

L _ws may be larger than 0 in a completed device, but is usually 10 μm or more, preferably 15 μm or more. As a design value, if the width of the scribe region 14 is 2L _ws , 2L _ws is preferably 30 μm or more. Moreover, since it is useless even if it is too large, 2L _WS is usually 300 μm or less, preferably 200 μm or less.

  Also in the light emitting element of the second embodiment, by forming the exposed layer with a highly insulating material, the element is as reliable as the light emitting element 10 in the form of FIG. Further, the shape of the other parts of the second aspect is the same as that of the first aspect.

  Below, each member and structure which comprise a light emitting element are demonstrated in detail.

<Board>
In the type D light emitting device, no substrate remains on the completed light emitting device. As the substrate, a substrate on which a semiconductor layer can be grown is selected, and a substrate that can be finally removed is used. The substrate need not be transparent, but when the substrate is peeled off by laser debonding, which will be described later, in the manufacturing process, it is preferable to transmit laser light having a specific wavelength. Further, it is preferably an electrically insulating substrate. This is because, in the manufacturing process, when the substrate is similarly peeled by the laser debonding method, it is difficult to adopt such a substrate peeling method due to absorption by free electrons or the like in the conductive substrate.

All the substrate materials described in the above type C can also be used in the manufacture of type D light emitting devices. As a specific material, for example, in order to grow a thin film crystal on an InAlGaN-based light-emitting material or InAlBGaN-based material, it is selected from sapphire, SiC, GaN, LiGaO ₂ , ZnO, ScAlMgO ₄ , NdGaO ₃ , and MgO. Are desirable, and sapphire, GaN, and ZnO substrates are particularly preferred. In particular, when a GaN substrate is used, the Si doping concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or less, more preferably 8 × 10 ¹⁷ cm ⁻ when an undoped substrate is intentionally used. ^It is desirable that it is ³ or less from the viewpoints of electrical resistance and crystallinity. In addition, when chemical etching is premised when removing the substrate, ZnO that can be easily removed with hydrochloric acid or the like is desirable.

  The substrate used in the manufacture of the type D light emitting device is not only a just substrate that is completely determined by a so-called plane index, but also a so-called off substrate (miss oriented substrate) from the viewpoint of controlling crystallinity during thin film crystal growth. ). Since the off-substrate has an effect of promoting good crystal growth in the step flow mode, it is effective in improving the morphology of the device and is widely used as a substrate. For example, when a sapphire c + plane substrate is used as a substrate for crystal growth of an InAlGaN-based material, it is preferable to use a plane inclined by about 0.2 degrees in the m + direction. As an off-substrate, a substrate having a slight inclination of about 0.1 to 0.2 degrees is widely used. However, in an InAlGaN-based material formed on sapphire, it is a light emitting point in an active layer structure. In order to cancel the electric field due to the piezoelectric effect applied to the quantum well layer, a relatively large off angle can be set.

  The substrate may be subjected to chemical etching, heat treatment, or the like in advance in order to manufacture a compound semiconductor light emitting device using a crystal growth technique such as MOCVD or MBE. In addition, the substrate is intentionally roughened in relation to the buffer layer described later, so that a threading transition that occurs at the interface between the thin film crystal layer and the substrate can be activated in the light emitting element or the light emitting unit described later. It is also possible not to introduce it in the vicinity of the layer.

  As for the thickness of the substrate, in one type of type D, it is usually about 250 to 700 μm at the initial stage of device fabrication, so that crystal growth of the light emitting device and mechanical strength in the device fabrication process are ensured. It is normal to leave. After the necessary semiconductor layer is grown using the substrate, the substrate is removed by, for example, polishing, etching, laser debonding, or the like. In particular, when the film is peeled off by an optical method such as laser debonding, it is desirable to use a double-sided polished substrate during the growth of a thin film crystal. This is because if a single-side polished substrate is used for a laser irradiated from a surface on which no thin film crystal is grown, it will be incident from a rough surface, and an unnecessarily large laser output is required during laser debonding. It is.

<Buffer layer>
With respect to the buffer layer, all of the matters described for type C also apply to type D. In the case of the type D light emitting device, since the substrate does not remain after the device is completed, preferable matters will be further described.

In the light emitting element of type D, since the substrate is removed during the manufacturing process, in one embodiment of this aspect, the surface of the buffer layer becomes the surface on the first light extraction direction side. As will be described later, as one method of peeling the substrate, a part of the buffer layer is optically decomposed and peeled off using light that is transparent to the substrate and absorbs the buffer layer. A method is mentioned. When such a method is adopted, a material suitable for the method is selected. For example, when the substrate is sapphire and the buffer layer is GaN, a KrF excimer laser having a wavelength of 248 nm is irradiated from the substrate side where the thin film crystal growth is not performed, and the buffer layer GaN is decomposed into metal Ga and nitrogen. As a result, laser debonding for peeling off the substrate can also be performed.
In the type D light emitting element, since there is no substrate in the first light extraction direction, a so-called low reflection coating layer or low reflection optical film may be formed on the surface of the buffer layer on the first light extraction direction side. desirable. Reflection due to a difference in refractive index at the buffer layer-air interface can be suppressed, and higher output and higher element efficiency can be achieved. Here, R3 is a reflectance at which light of the light emitting wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer side, which will be described later, is reflected by the buffer layer, and the first light extraction direction from the buffer layer When the reflectance at which the light of the emission wavelength of the light emitting element that is perpendicularly incident on the side space is reflected at the interface with the space is represented by R4,
R4 <R3
It is desirable that a low reflection optical film be provided on the first light extraction direction side of the buffer layer so as to satisfy the above. For example, when the buffer layer is GaN, it is desirable to use Al ₂ O ₃ or the like as the low reflection coating film. This is because it is desirable that the refractive index of the low-reflection coating film is close to √n _bf with respect to the refractive index n _bf of the buffer layer at the light emission wavelength of the device, so that Al ₂ O with respect to the square root of the refractive index of GaN. _{This is because} the refractive index of ₃ is close.

It is also preferable that the surface of the buffer layer on the first light extraction direction side is a non-flat surface or a rough surface. As a result, light emitted from the quantum well layer can be extracted with high efficiency, which is desirable from the viewpoint of increasing the output and efficiency of the device. Here, when the light emission wavelength of the device is λ (nm), the roughness of the buffer layer is such that the average roughness Ra (nm) is λ / 5 (nm) <Ra (nm) <10 × λ (nm).
It is desirable to satisfy
λ / 2 (nm) <Ra (nm) <2 × λ (nm)
It is more desirable to satisfy.

  In the type D light emitting device, at least a part of the buffer layer is exposed at the device end. Therefore, at least the exposed portion is preferably an undoped portion, since insulation failure due to solder or the like during device assembly can be suppressed.

<First conductivity type semiconductor layer and first conductivity type cladding layer>
The first conductive type semiconductor layer and the first conductive type clad layer in the type D light emitting element can adopt the same configuration as that used in the type C light emitting element.

<Active layer structure>
The active layer structure in the type D light emitting element can adopt the same configuration as that used in the type C light emitting element.

<Second conductivity type semiconductor layer and second conductivity type cladding layer>
The second conductive type semiconductor layer and the second conductive type cladding layer in the type D light emitting element can adopt the same configuration as that used in the type C light emitting element.

<Second conductivity type side electrode>
The second conductivity type side electrode in the type D light emitting element can adopt the same configuration as that used in the type C light emitting element.

<First conductivity type side electrode>
The first conductivity type side electrode in the type D light emitting element can adopt the same configuration as that used in the type C light emitting element.

<Insulating layer>
The insulating layer in the type D light emitting element can adopt the same configuration as that used in the type C light emitting element.

<Support>
Although it is essential that the support 40 can serve as a support for the thin film crystal layer when the substrate is peeled off, the support 40 can also have functions of current introduction and heat dissipation after device completion. Highly desirable. From this viewpoint, the base material of the support is preferably selected from the group consisting of metal, AlN, SiC, diamond, BN, and CuW. These materials are preferable in that they are excellent in heat dissipation and can efficiently suppress the problem of heat generation that is unavoidable for high-power light-emitting elements. Al ₂ O ₃ , Si, glass and the like are also inexpensive and are widely used as a support. In addition, when a portion of the thin film crystal layer is decomposed into metal Ga and nitrogen by laser irradiation when removing the substrate, which will be described later, it is desirable to perform wet etching when removing the metal Ga. The body is preferably made of a material that is not etched. When the base material of the support is selected from metal, it is desirable to cover the periphery with a dielectric material having etching resistance. As the metal base material, a material having high reflectance at the light emission wavelength of the light emitting element is desirable, and Al, Ag, and the like are desirable. Further, when covered with a dielectric such as, _SiN x was formed by various CVD methods, SiO ₂ or the like is desirable.

  From the viewpoint that the support further has a function of current introduction and heat dissipation after completion of the element, it is desirable that the support has an electrode wiring for current introduction on the base material, and the element is arranged on the electrode wiring. It is desirable that the mounting portion has an adhesive layer for joining the element and the support appropriately. Here, although it is possible to use a paste containing Ag, a metal bump, or the like as the adhesive layer, it is very desirable from the viewpoint of heat dissipation that it is made of metal solder. The metal solder can realize a flip chip mount that is overwhelmingly excellent in heat dissipation compared with a paste material containing Ag, a metal bump, and the like. Here, examples of the metal solder include In, InAg, InSn, SnAg, PbSn, AuSn, AuGe, and AuSi. In particular, a high melting point solder such as AuSn, AuSi, or AuGe is more desirable. This is because when a large current is injected to operate the light emitting element at an ultrahigh output, the temperature in the vicinity of the element rises to about 200 ° C. The melting point of the solder material is higher than the element temperature during driving. The metal solder which has is more preferable. In some cases, it is also desirable to use bumps in order to cancel out the level difference of the elements at the time of flip chip mounting, and further to join the metal solder material while filling the periphery thereof.

Further, since the device is usually separated by dividing the support as will be described later, in the completed light emitting device, it is preferable that an isolation region where no metal wiring exists is present around the support 40. As shown in FIG. 5-5, the width of the region where the metal wiring does not exist is L _WSPT2 (in FIG. 5-5, the left side is _represented by L _{WSPT2 (left)} and the right side is represented by L _{WSPT2 (right))} . , L _WSPT2 may be larger than 0 in the completed device, but the preferred range varies depending on what method is used in the separation step as described below.

When separating by scribing, it is usually 10 μm or more, preferably 15 μm or more. Therefore, it is preferable that 2L _WSPT2 is 30 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 300 μm or less, preferably 200 μm or less.

Further, when separating by dicing, L _WSPT2 is usually 100 μm or more, preferably 500 μm or more. Therefore, it is preferable that 2L _WSPT2 is 1000 μm or more as the separation region 47. Moreover, since it is useless even if it is too large, 2L _WSPT2 is usually 2000 μm or less, preferably 1500 μm or less.

  An embodiment in which the support is not divided is also possible. For example, a plurality of light emitting elements can be mounted on one support. By freely changing the metal wiring on the support, each light emitting element on one support can be connected in parallel, connected in series, or mixed.

[Method for Manufacturing Type D Light-Emitting Element]
Next, a method for manufacturing a type D semiconductor light emitting device will be described.

<The manufacturing method of the light emitting element of a 1st aspect>
In one example of the manufacturing method, as shown in FIGS. 5-7, first, a substrate 21 is prepared, and a buffer layer 22, a first conductivity type cladding layer 24, an active layer structure 25, and a second conductivity type cladding layer 26 are formed on the surface thereof. Are sequentially formed by thin film crystal growth. The MOCVD method is preferably used for forming these thin film crystal layers. However, the MBE method, the PLD method, the PED method, the VPE method, the LPE method, and the like can also be used to form the entire thin film crystal layer or a part of the thin film crystal layer. These layer configurations can be appropriately changed according to the purpose of the element. Further, after the formation of the thin film crystal layer, various kinds of treatments may be performed. In this specification, the term “thin film crystal growth” includes heat treatment after the growth of the thin film crystal layer.

  In order to realize the shape shown in FIGS. 5-1A to 5-2 after the thin film crystal layer growth, it is preferable to form the second conductivity type side electrode 27 as shown in FIG. 5-7. . That is, the formation of the second conductivity type side electrode 27 in the planned second current injection region 35 is more than the formation of the insulating layer 30, the first current injection region 36, and the first It is desirable that this is performed earlier than the formation of the conductive side electrode 28. In the case where the second conductivity type is p-type as a preferred embodiment, if the p-side electrode is formed after various processes are performed on the surface of the p-type cladding layer exposed on the surface, This is because the hole concentration in the p-GaN cladding layer having a relatively low activation rate is reduced by process damage. For example, if the step of forming the insulating layer 30 by p-CVD is performed before the formation of the second conductivity type side electrode 27, plasma damage will remain on the surface. For this reason, in the type D, after the thin film crystal growth, the formation of the second conductivity type side electrode 27 is performed in other process steps (for example, the first etching step, the second etching step, or the insulating layer forming step described later, the second conductivity type). It is desirable to carry out before the side electrode exposed portion forming step, the first current injection region forming step, the first conductivity type side electrode forming step, and the like.

  Further, in the manufacture of the type D light emitting device, when the second conductivity type is p-type, the case where the surface of the second conductivity type side electrode 27 is Au as described above is assumed as a typical example. However, when the exposed surface is made of a relatively stable metal such as Au, the possibility of process damage is low even after the subsequent process. Also from this point of view, it is desirable that the second conductivity type side electrode 27 is formed prior to other process steps after the thin film crystal growth.

  In the case of the type D light emitting device, when the layer on which the second conductivity type side electrode 27 is formed is the second conductivity type contact layer, the process damage to the second conductivity type semiconductor layer is similarly caused. Can be reduced.

  Various film formation techniques such as sputtering, vacuum deposition, and plating can be applied to the formation of the second conductivity type side electrode 27. In order to obtain a desired shape, a lift-off method using a photolithography technique or a metal A place-selective vapor deposition using a mask or the like can be used as appropriate.

  After forming the second conductivity type side electrode 27, as shown in FIG. 5-8, a part of the first conductivity type cladding layer 24 is exposed. In this step, it is preferable to remove a part of the second conductivity type cladding layer 26, the active layer structure 25, and further the first conductivity type cladding layer 24 by etching (first etching step). In the first etching step, the first conductivity type side electrode, which will be described later, is intended to expose the semiconductor layer in which the first conductivity type carriers are injected, so that another layer such as a cladding layer is formed on the thin film crystal layer. In the case of two layers or when there is a contact layer, etching may be performed including that layer.

In the first etching step, since the etching accuracy not much required, the use of known dry etch of nitride or oxide such as SiO _x such as SiN _x by plasma etching method using Cl ₂ or the like as an etching mask Can do. However, it is also desirable to perform dry etching using a metal fluoride mask as will be described in detail in the second etching step described later. In particular, using an etching mask including a metal fluoride layer selected from the group consisting of SrF ₂ , AlF ₃ , MgF ₂ , BaF ₂ , CaF ₂ and combinations thereof, Cl ₂ , SiCl ₄ , BCl ₃ , SiCl _4, etc. Etching is preferably performed by plasma-excited dry etching using the above gas. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

Here, the second conductivity type side electrode 27 has a history of forming a SiN _x mask formed by plasma CVD or the like, or a history of the SiN _x mask removing process performed after the first etching process. Is formed on the surface, process damage received by the second conductivity type side electrode 27 is reduced.

  Next, as shown in FIG. 5-9, the inter-device separation groove 13 is formed by the second etching step. In the type D light emitting element, the inter-device separation groove 13 needs to be formed by dividing at least the first conductivity type cladding layer 24. In this embodiment, the inter-device separation groove 13 is formed on the substrate 21. Formed to reach. In this case, the GaN-based material on the sapphire substrate is peeled off even when diamond scribe is performed from the side on which the thin film crystal layer is formed in steps such as scribing and breaking in order to separate the elements. It is possible to suppress. Also, when laser scribing is performed, there is an advantage that the thin film crystal layer is not damaged. Furthermore, it is also preferable to form an inter-device separation groove 13 by etching to a part of a sapphire substrate (the same applies to other substrates such as GaN).

  On the other hand, a mode in which the inter-device separation groove 13 does not reach the substrate 21 is also a preferable mode. If the inter-device separation groove 13 is formed up to the middle of the buffer layer 22, the insulating layer 30 can be formed on the side wall of the first conductivity type cladding layer 24, and is insulative against wraparound of solder or the like. (See FIG. 5-2 for the form after the light emitting element is completed). In this case, the bottom surface of the groove is formed in the middle of the layer including the buffer layer 22, and this becomes the end step surface 55 at the end of the light emitting element. The bottom surface of the groove is a surface including irregularities that can be obtained by etching. Since the bottom surface of the groove is subjected to processing such as scribing at the time of element isolation, the end step surface 55 after element isolation is often not high in terms of planarity as a surface and parallelism with the layer direction. The layer exposed from the side wall without being covered with the insulating layer 30 preferably has high insulating properties. The layer exposed from the side wall without being covered with the insulating layer 30 preferably has high insulating properties.

  In the second etching step, it is necessary to etch the GaN-based material deeper than in the first etching step. In general, the total sum of the layers etched by the first etching process is usually about 0.5 μm. However, in the second etching process, all of the first conductivity type cladding layer 24 and at least a part of the buffer layer 22 are used. In some cases, since it is necessary to etch the whole, it may be 3 to 7 μm, and in some cases, it may be in the range of 3 to 10 μm, and may exceed 10 μm.

In general, a metal mask, a nitride mask such as SiN _x , an oxide mask such as SiO _{x, and the} like have a selectivity ratio of about 5 to a GaN-based material exhibiting etching resistance to Cl ₂ -based plasma, and are thick GaN In order to perform the second etching step that requires etching of the system material, a relatively thick SiN _x film is required. For example, when a 10 μm GaN-based material is etched in the second dry etching step, a SiN _x mask exceeding 2 μm is required. However, at the SiN _x mask for this degree of thickness, SiN _x mask may cause etched, it alters also horizontal shape not only the thickness of the longitudinal, desired GaN material part during implementation dry etching It becomes impossible to selectively etch only.

Therefore, when forming the inter-device separation groove in the second etching step, dry etching using a mask including a metal fluoride layer is preferable. The material constituting the metal fluoride layer is preferably MgF ₂ , CaF ₂ , SrF ₂ , BaF ₂ , or AlF ₃ in consideration of the balance between dry etching resistance and wet etching property, and among these, SrF ₂ is most preferable.

  The metal fluoride film is sufficiently resistant to dry etching performed in the first and second etching steps, while it can be easily etched for patterning etching (preferably wet etching). In addition, a patterning shape, particularly one having good linearity in the side wall portion is required. By setting the film formation temperature of the metal fluoride layer to 150 ° C. or more, excellent adhesion to the base is formed, and a dense film is formed. At the same time, after patterning by etching, the mask sidewall is also excellent in linearity. The film forming temperature is preferably 250 ° C. or higher, more preferably 300 ° C. or higher, and most preferably 350 ° C. or higher. In particular, a metal fluoride layer formed at 350 ° C. or higher is excellent in adhesion to all bases, becomes a dense film, exhibits high dry etching resistance, and has a patterning shape with linearity on the side wall portion. It is extremely excellent and the controllability of the width of the opening is ensured, which is most preferable as an etching mask.

In this way, it has excellent adhesion to the substrate and becomes a dense film, and exhibits high dry etching resistance, and the patterning shape is also excellent in controllability of the linearity of the side wall and the width of the opening. In order to obtain an etching mask, it is preferable to form a film at a high temperature. On the other hand, if the film forming temperature is too high, the resistance to wet etching with respect to hydrochloric acid or the like, which is preferably performed when patterning a metal fluoride, is more than necessary. And the removal is not easy. In particular, when a mask such as SrF ₂ is exposed to plasma such as chlorine during dry etching of a semiconductor layer, the etching rate at the time of subsequent mask layer removal is lower than before exposure to plasma such as chlorine. Have a tendency to For this reason, film formation of metal fluoride at an excessively high temperature is not preferable from the viewpoint of patterning and final removal.

  First, in the case of a metal fluoride before being exposed to plasma during dry etching of a semiconductor layer, the etching rate with respect to an etchant such as hydrochloric acid is larger and the etching proceeds faster as the layer is deposited at a lower temperature, and the deposition temperature is increased. The etching rate is lowered and the etching progress is slowed down. When the film forming temperature is 300 ° C. or higher, the etching rate is more markedly lower than the film having a film forming temperature of about 250 ° C. However, when the film forming temperature is about 350 ° C. to 450 ° C., the etching rate is in a very convenient range. However, when the film forming temperature exceeds 480 ° C., the absolute value of the etching rate becomes unnecessarily small, and excessive time is required for patterning the metal fluoride, and the resist mask layer or the like is not peeled off. Patterning may be difficult. Furthermore, the metal fluoride after being exposed to plasma during dry etching of the semiconductor layer has a property of reducing the wet etching rate against hydrochloric acid during removal, and excessive high-temperature growth removes the metal fluoride. Makes it difficult.

  From such a viewpoint, the deposition temperature of the metal fluoride layer is preferably 480 ° C. or less, more preferably 470 ° C. or less, and particularly preferably 460 ° C. or less.

Dry etching is performed using a mask (which may be laminated with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer) in consideration of such a situation. The gas species for dry etching is preferably selected from Cl ₂ , BCl ₃ , SiCl ₄ , CCl ₄ and combinations thereof. In the dry etching, the selection ratio of the SrF ₂ mask to the GaN-based material exceeds 100, so that the thick film GaN-based material can be easily etched with high accuracy. Further, as a dry etching method, ICP type dry etching capable of generating high-density plasma is optimal.

When a metal fluoride layer mask that has become unnecessary after etching is removed with an etchant such as hydrochloric acid, there is a material that is vulnerable to acid under the metal fluoride mask, for example, when the electrode material is vulnerable to acid. May be a laminated mask with SiN _x , SiO ₂ or the like so that the metal fluoride layer becomes a surface layer. In this _case, SiN x, the SiO ₂ and the like, may be present in the entire lower portion of the metal fluoride mask layer, or for example, as shown in FIG. _5-19, SiN x, SiO ₂ or the like mask 51, Even if it does not exist in the entire lower part of the metal fluoride mask layer 52, it should be formed on a material that is at least sensitive to acids.

  By such a second etching step, an inter-device separation groove 13 is formed as shown in FIGS.

Note that the first etching step and the second etching step may be performed either first or later. In order to simplify the process, it is also preferable to perform the first etching step first and then perform the second etching step without removing the etching mask at that time. As shown in FIG. 5-19, first, a first etching mask 51 is formed with an acid-resistant material such as SiN _x , SiO ₂ (preferably SiN _x ), and etching is performed so that the first conductivity type cladding layer 24 appears. The second etching mask 52 made of a metal fluoride layer is formed without removing the mask 51. And after implementing a 2nd etching process, it is preferable to remove the mask 52 with an acid, and to remove the mask 51 suitably after that.

_Assuming that the width of the narrowest portion between the device isolation grooves to be formed is 2L _WSPT1 , it is desirable that L _WSPT1 is 20 μm or more, for example, 30 μm or more when element separation is performed by braking. Further, when implemented by dicing or the like, L _WSPT1 is desirably 300 μm or more. Moreover, since it is useless even if it is too large, L _WSPT1 is usually 2000 μm or less. This is because it is necessary for the margin of the device manufacturing process and further for securing the scribe region.

  The “recessed side wall surface” defined in the description of type D is a side wall surface that appears as a side wall in the second etching step, that is, the formation of the inter-device separation groove, and is not a wall surface that appears only in the first etching.

  After the second etching step, an insulating layer 30 is formed as shown in FIGS. The insulating layer 30 can be appropriately selected as long as it is a material that can ensure electrical insulation, and details are as described above. As a film forming method, a known method such as a plasma CVD method may be used.

  Next, as shown in FIG. 5-11, a predetermined portion of the insulating layer 30 is removed, and the second conductivity type side electrode exposed portion 37 from which the insulating layer 30 is removed on the second conductivity type side electrode 27, the first A first current injection region 36 from which the insulating layer 30 has been removed on the conductive clad layer 24 and an insulating layer non-formed portion 15 from which the insulating layer 30 has been removed from the substrate surface and side walls in the inter-device isolation trench 13 are formed.

The insulating layer 30 on the second conductivity type side electrode 27 is removed such that the peripheral portion of the second conductivity type side electrode 27 is covered with the insulating layer 30. That is, the surface area of the second conductivity type side electrode exposed portion 37 is smaller than the area of the second current injection region 36. Here, a part of the second conductivity type side electrode 27 is covered with the insulating layer 30 in order to prevent an occurrence of an unintentional short circuit due to a margin of a photolithography process, particularly a photolithography process, or a solder material. The width (L _2w ) of the narrowest portion is preferably 15 μm or more as described above. More desirably, it is 100 μm or more. By covering most of the area of the second conductivity type side electrode 27 with the insulating layer 30, it is possible to reduce unintentional short-circuits with other parts such as the first conductivity type side electrode 28 due to the metal solder material in particular. it can.

For the removal of the insulating layer 30, an etching technique such as dry etching or wet etching can be selected depending on the selected material. For example, when the insulating layer 30 is a single SiN _x layer, dry etching using a gas such as SF ₆ or wet etching using a hydrofluoric acid-based etchant is possible. Further, when the insulating layer 30 is a dielectric multilayer film made of SiO _x and TiO _x , a desired portion of the multilayer film can be removed by Ar ion milling.

  The second conductivity type side electrode exposed portion 37, the first current injection region 36, and the insulating layer non-formed portion 15 may be formed separately, but are usually formed by etching at the same time.

  In order to provide the insulating layer non-formed portion 15 by removing the insulating layer 30 on the side wall near the substrate in the inter-device separation groove, for example, the following process can be used. First, a resist mask having an opening substantially equal to or slightly smaller than the area of the inter-device separation groove 13 is formed by photolithography, and then wet etching is performed using an etchant that can etch the insulating layer 30. The removal of the insulating layer 30 on the substrate surface in the separation groove proceeds. After that, when etching is continued for a longer time, side etching occurs, and the insulating layer 30 covering the substrate side of the groove sidewall is removed with a wet etchant. As shown in FIG. 5-11, the insulating layer in the vicinity of the inter-device separation groove is removed. A shape without 30 is obtained. When the insulating layer 30 is removed as described above, the side wall of the thin film crystal layer where the insulating layer 30 does not exist is preferably the side wall of the undoped layer. This is because an unintended electrical short circuit does not occur even when solder for joining to the support or the like adheres to the side wall when flip chip mounting is performed. Such a removed shape of the insulating layer 30 is a desirable shape, particularly when the substrate 21 is removed during the manufacturing process of the light emitting element, because an unintended defect such as peeling of the insulating layer 30 is not accompanied. It is.

Next, as shown in FIGS. 5-12, the first conductivity type side electrode 28 is formed. In the type D light emitting device, the first conductivity type side electrode 28 is formed in an area larger than the size of the first current injection region, and the first conductivity type side electrode 28 and the second conductivity type side electrode 27 are It is characterized by having no spatial overlap. This is because when the element is flip-chip mounted with solder or the like, the second conductivity type side electrode 27 and the first conductivity type side are secured while securing a sufficient area to ensure sufficient adhesion with a support or the like. This is important for securing a sufficient distance to prevent an unintended short circuit due to a solder material or the like between the electrode 28 and the like. Among the widths of the portion where the first conductivity type side electrode 28 is in contact with the insulating layer 30, the width (L _1w ) of the narrowest portion is set to be in the above-described range. Usually, if it is 5 μm or more, a process margin by the photolithography process and the lift-off method can be secured.

  As described above, when the first conductivity type is n-type as described above, it is desirable to include, as a constituent element, a material selected from any one of Ti, Al, Ag, and Mo. Further, Al is usually exposed in the direction facing the first light extraction direction of the n-side electrode.

  Various film formation techniques such as sputtering, vacuum evaporation, plating, etc. can be applied to the film formation of the electrode material. In order to obtain an electrode shape, a lift-off method using a photolithography technique, a metal mask, or the like was used. Site selective vapor deposition or the like can be used as appropriate.

  In this example, the first conductivity type side electrode 28 is formed so as to be in contact with a part of the first conductivity type clad layer 24. However, when the first conductivity type side contact layer is formed, it is formed so as to be in contact therewith. can do.

  In this manufacturing method, the first conductivity type side electrode 28 is manufactured at the final stage of forming the laminated structure, which is advantageous from the viewpoint of reducing process damage. When the first conductivity type is n-type, the n-side electrode is formed with Al on the surface of the electrode material in a preferred embodiment. In this case, if the n-side electrode is formed before the formation of the insulating layer 30 like the second conductivity type side electrode 27, the surface of the n-side electrode, that is, the Al metal, has a history of the etching process of the insulating layer 30. Will do. As described above, wet etching using a hydrofluoric acid-based etchant is simple for etching the insulating layer 30, but Al has low resistance to various etchants including hydrofluoric acid, and this process is effective. If implemented, the electrode itself will be damaged. Even if dry etching is performed, Al is relatively reactive and damage including oxidation may be introduced. Therefore, in the manufacture of the type D light emitting device, the formation of the first conductivity type side electrode after the formation of the insulating layer and after the removal of the unnecessary portion scheduled for the insulating layer reduces the damage to the electrode. effective.

  After the structure of FIGS. 5-12 is formed in this way, preparations for removing the substrate 21 are made. Usually, the structure shown in FIGS. 5-12 is bonded to the support 40 as a whole wafer or a part thereof. This is because the thickness of the thin film crystal layer as a whole is about 15 μm at the maximum. Therefore, if the substrate 21 is peeled off, the mechanical strength becomes insufficient and it becomes difficult to stand alone and undergo subsequent processes. Because. The material of the support 40 is as described above.

  As shown in FIG. 5-13, the metal layer 41 (electrode wiring or the like) on the support 40 is connected and mounted by, for example, metal solder 42.

  At this time, in the type D light emitting element, the second conductivity type side electrode 27 and the first conductivity type side electrode 28 are arranged so as not to spatially overlap each other, and the first conductivity type side electrode 28 is Since it is larger than the first current injection region and has a sufficient area, it is desirable that both prevention of unintended short-circuiting and securing of high heat dissipation are achieved. Further, the side walls of the other thin film crystal layers are also protected by the insulating layer 30 except for a part of the buffer layer 22, particularly the undoped portion. A short circuit or the like in the side wall does not occur.

  Next, after bonding the element to the support 40, the substrate 21 is peeled off. For removing the substrate 21, any method such as polishing, etching, laser debonding or the like can be used. When polishing a sapphire substrate, the substrate 21 can be removed using an abrasive such as diamond. It is also possible to remove the substrate 21 by dry etching. Further, when a thin film crystal growth portion is formed of an InAlGaN-based material on a substrate 21 made of, for example, sapphire, the sapphire substrate transmits from the sapphire substrate side, for example, to GaN used for the buffer layer 22. It is also possible to perform laser debonding using a 248 nm KrF excimer laser that is absorbed to decompose part of the GaN of the buffer layer 22 into metal Ga and nitrogen and peel off the substrate 21. FIG. 5-14 schematically shows the state where the substrate 21 is peeled off by laser debonding.

In addition, when ZnO, ScAlMgO ₄ or the like is used as the substrate 21, the substrate 21 can be removed by wet etching using an etchant such as HCl.

  In the type D light emitting element, since there is no portion where the insulating layer 30 is in contact with the substrate 21, when the substrate 21 is peeled off, the insulating layer 30 is not peeled off secondarily.

  Thereafter, as shown in FIG. 5-14, the light emitting element is separated together with the support 40 in the separation region 47 corresponding to the location where the inter-device separation groove is present to obtain a single light emitting element. Here, it is preferable that no metal wiring exists in the separation region 47 of the support 40. This is because separation between devices is difficult if metal wiring exists here.

  For the cutting of the separation region portion of the support 40, an appropriate process such as dicing, scribing, and braking can be selected depending on the base material. Also, when the inter-device separation groove is formed up to the middle of the buffer layer 22, the inter-device separation groove is used to perform damage by diamond scribe, ablation of a part of the buffer layer by laser scribe, etc. By doing so, separation between the light emitting elements in the thin film crystal growth layer portion can be easily realized. Thereafter, the support 40 can be separated into light emitting elements by dicing. In some cases, the light emitting elements can be separated from the thin film crystal growth layer and the support 40 simultaneously by dicing.

  As described above, the light-emitting element having the mode illustrated in FIGS. 5-1A to 5-2 is completed.

<The manufacturing method of the light emitting element of a 2nd aspect>
To manufacture the light emitting device of the second mode shown in FIG. 5-3A, the etching is stopped in the middle of the buffer layer when forming the inter-device isolation groove in the description of the manufacturing method of the first mode. Similarly, when the insulating layer 30 is formed and the insulating layer 30 is etched, the insulating layer 30 is removed from the region including the center of the inter-device isolation trench 13 as shown in FIG. Form. In the first mode, all of the insulating layer on the bottom surface of the groove is removed, but in this mode, the insulating layer 30 remains on the bottom surface of the groove, and intentional side etching is not performed. The width of the scribe region 14 can be set so as to obtain a predetermined L _ws as described above. Thereafter, the light emitting device shown in FIG. 5-3A is completed in the same manner as in the first embodiment.

  In common with the first aspect and the second aspect, in this manufacturing method, as described, formation of a thin film crystal layer, formation of the second conductivity type side electrode 27, etching process (first etching process and second etching process) ), Formation of the insulating layer 30, removal of the insulating layer 30 (formation of the exposed portion of the second conductivity type side electrode, formation of the first current injection region, formation of the scribe region), formation of the first conductivity type side electrode 28 It is desirable that the steps be performed in this order, and by this order of the steps, a light-emitting element can be obtained in which the thin film crystal layer directly under the second conductivity type side electrode is not damaged and the first conductivity type side electrode 28 is not damaged. . The device shape reflects the process flow. That is, the light emitting element has a structure in which the second conductivity type side electrode 27, the insulating layer 30, and the first conductivity type side electrode 28 are laminated in this order. That is, the second conductivity type side electrode 27 is in contact with the second conductivity type clad layer 26 (or other second conductivity type thin film crystal layer) without the insulating layer 30 interposed therebetween. There is a portion covered with an insulating layer 30 around the upper portion, and the area around the electrode is between the first conductivity type side electrode 28 and the first conductivity type side cladding layer 24 (or other first conductivity type thin film crystal layer). There is a portion where the insulating layer 30 is interposed.

<< 2-6. Features of type C and D light emitting device manufacturing method >>
The manufacturing method of the above-mentioned type C and type D light emitting elements is characterized by the following matters.

1. (A) a step (a) of forming a buffer layer on the substrate;
(B) At least a first conductive type semiconductor layer including a first conductive type cladding layer, an active layer structure, and a thin film crystal layer having a second conductive type semiconductor layer including a second conductive type cladding layer from the substrate side. A step (b) of sequentially forming a film;
(C) a step (c) of forming a second conductivity type side electrode on the surface of the second conductivity type semiconductor layer;
(D) a first etching step (d) in which a part of the portion where the second conductivity type side electrode is not formed is etched to expose a part of the first conductivity type semiconductor layer;
(E) In order to form an inter-device separation groove for separating adjacent light emitting elements, a part of the portion where the second conductivity type side electrode is not formed is separated from the surface, and (i) at least one of the buffer layers Or (ii) a second etching step (e) in which etching is performed at a depth that reaches at least the substrate to form the inter-device separation groove;
(F) a step (f) of forming an insulating layer on the entire surface including the second conductivity type side electrode, the first conductivity type semiconductor layer exposed by the first etching step, and the inside of the inter-device isolation trench;
(G) removing an insulating layer in a region including at least the groove center of the groove bottom surface in the inter-device separation groove;
(H) removing a part of the insulating layer formed on the surface of the first conductivity type semiconductor layer and forming an opening to be a first current injection region;
(I) removing a part of the insulating layer formed on the surface of the second conductivity type side electrode and exposing a part of the second conductivity type side electrode;
(J) A method of manufacturing a light emitting device, comprising: a step (j) of forming a first conductivity type side electrode in contact with the first current injection region opened in the step (h).

  2. 2. In the step (g), only the insulating layer in the region including the groove center on the groove bottom surface is removed while leaving the insulating layer formed on the sidewall of the inter-device separation groove. the method of.

  3. In the step (g), all of the insulating layer formed on the bottom surface of the groove in the inter-device separation groove and the insulating layer formed on at least a portion of the side wall in the inter-device separation groove on the groove bottom surface side. 2. The method according to 1 above, which is removed.

  4). 4. The method according to any one of the above items 1 to 3, wherein the layer constituting the surface exposed by removing the insulating layer is an undoped type.

5). After step (j)
Isolating the substrate in the inter-device separation groove;
The method according to any one of the above items 1 to 4, further comprising the step of joining the first conductivity type side electrode and the second conductivity type side electrode to a metal layer on a submount.

6). After step (j)
Bonding the first conductivity type side electrode and the second conductivity type side electrode to the metal layer on the support and mounting the support on the support; and
Removing the substrate;
The method according to any one of the above 1 to 4, further comprising a step of dividing the support and separating the elements (however, etching is performed until reaching the substrate in the step (e), and (Excluding the case where only the insulating layer in the region including the center on the bottom surface of the groove is removed in the step (g)).

  7. 7. The method according to claim 1, wherein the buffer layer is performed as a part of the thin film crystal layer prior to the formation of the first conductivity type semiconductor layer.

8). In the step (j), the first conductivity type side electrode is _adjusted such that the width _{L1w of the} narrowest portion of the portion where the first conductivity type side electrode is in contact with the insulating layer is 5 μm or more. 8. The method according to any one of 1 to 7 above, which is formed.

9. In the step (i), among the widths of the portion where the second conductivity type side electrode is covered with the insulating layer, the width L _{2w of the} narrowest portion is not less than 15 μm. 9. The method according to any one of 1 to 8 above, wherein a part of the electrode is exposed.

10. 10. The method according to 9 above, wherein the L _2w is 30 μm or more.

  11. Any one of the above 1 to 10, wherein the first conductivity type side electrode includes a layer made of a material containing an element selected from the group consisting of Ti, Al, Ag, Mo and combinations of two or more thereof. The method of crab.

  12 Said 1-11 characterized by said 2nd conductivity type side electrode including the layer which consists of a material containing the element chosen from the group which consists of Ni, Pt, Pd, Mo, Au, and those 2 or more types of combinations. The method in any one of.

13. The insulating layer is a material selected from the group consisting of SiO _x , AlO _x , TiO _x , TaO _x , HfO _x , ZrO _x , SiN _x , AlN _x , AlF _x , BaF _x , CaF _x , SrF _x and MgF _x. The method according to any one of 1 to 12 above, wherein the method is a single layer.

  14 14. The method according to any one of 1 to 13, wherein the insulating layer is a dielectric multilayer film composed of a plurality of layers.

  15. 15. The method according to claim 14, wherein at least one of the layers constituting the insulating layer is made of a material containing fluoride.

16. 16. The method according to 15 above, wherein the fluoride is selected from the group consisting of AlF _x , BaF _x , CaF _x , SrF _x and MgF _x .

17. The thin-film crystal layer, _sapphire, SiC, GaN, LiGaO 2, _ZnO, any of the above 1 to 16, characterized in that formed by deposition on a substrate selected from the group consisting of ScAlMgO 4, NdGaO ₃ and MgO The method of crab.

  18. The compound semiconductor thin film crystal layer is made of a III-V group compound semiconductor containing a nitrogen atom as a group V. In the first conductivity type cladding layer, the active layer structure and the second conductivity type cladding layer, In, Ga and 18. The method according to any one of 1 to 17 above, wherein an element selected from the group consisting of Al is contained.

19. When the active layer structure is composed of a quantum well layer and a barrier layer, the number of barrier layers is represented by B, and the number of quantum well layers is represented by W.
B = W + 1
The method according to any one of 1 to 18 above, wherein

  20. 20. The method according to any one of 1 to 19 above, wherein the first conductivity type is n-type and the second conductivity type is p-type.

  21. 6. The method according to claim 5, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a submount having a metal layer by soldering.

  22. 7. The method according to claim 6, wherein the first conductivity type side electrode and the second conductivity type side electrode are joined to a support having the metal layer by soldering.

  23. 21. The bonding of the first conductivity type side electrode and the second conductivity type side electrode and the metal layer of the submount or the support is performed only by metal solder or by metal solder and metal bumps. Or the method according to 22.

24. 24. The method according to any one of 21 to 23, wherein the base material of the submount or the support is selected from the group consisting of AlN, Al ₂ O ₃ , Si, glass, SiC, diamond, BN, and CuW. .

  25. 25. The method according to any one of 21 to 24, wherein a metal layer is not formed at a separation portion between the light emitting elements of the submount or the support.

  26. 6. The method according to 5 above, wherein a surface of the substrate on the first light extraction direction side is not flat.

  27. 7. The method according to claim 6, wherein the surface of the buffer layer on the first light extraction direction side is not flat.

28. The reflectance of the light having the emission wavelength of the light emitting element that is perpendicularly incident on the substrate side from the buffer layer is R3, and the light emission of the light emitting element is perpendicularly incident on the first light extraction direction side space from the substrate. When the reflectance at which the wavelength of light is reflected at the interface with the space is represented by R4,
R4 <R3
6. The method according to 5 above, wherein a low reflection optical film is provided on the first light extraction direction side of the substrate so as to satisfy the above.

29. The reflectance at which the light having the emission wavelength of the light emitting element that is perpendicularly incident on the buffer layer side from the first conductivity type semiconductor layer is reflected by the buffer layer is R3, and the reflectance from the buffer layer is perpendicular to the space on the first light extraction direction side. When the reflectance at which the light having the emission wavelength of the light emitting element that is incident is reflected at the interface with the space is represented by R4,
R4 <R3
7. The method according to claim 6, wherein a low reflection optical film is provided on the first light extraction direction side of the buffer layer so as to satisfy the above condition.

  30. 30. The method according to any one of 1 to 29, wherein the substrate is GaN, and all of the buffer layer is formed of GaN at a temperature of 900 ° C. or higher.

  According to the above manufacturing method, it is possible to provide a manufacturing method of a flip-chip mount type semiconductor light emitting device which is a light emitting device capable of emitting blue or ultraviolet light and has high output and high efficiency.

  In the above manufacturing method, since process damage in each step in the manufacturing process is eliminated, a highly reliable element can be manufactured without impairing the function of the light emitting element.

  According to said manufacturing method, the light emitting element disclosed in type C and type D can be manufactured. This manufacturing method has steps (a) to (j), and the order of the steps is shown in the flowchart of FIG. In the invention disclosed here, steps (a), (b) and (c) are performed in this order. Steps (d) and (e) are carried out after step (c), but the order of steps (d) and (e) may be either. Then, after implementing step (f), steps (g), (h) and (i) may be performed in any order, but are preferably performed simultaneously. Thereafter, step (j) is performed.

  When the substrate used for the thin film crystal growth is peeled off, that is, when the light emitting device disclosed in type D is manufactured, the step is performed after the step (j).

  The specific contents of each step are as already described in Type C and Type D, and the above manufacturing method includes all of the contents. However, in the light-emitting element disclosed in type C, since the buffer layer has an arbitrary configuration, the step of forming the buffer layer is omitted when a light-emitting element having no buffer layer is manufactured.

  Further, the shape of the element end, the shape of the groove bottom surface and the side wall surface of the insulating layer are different depending on the difference of the step (e) and the step (g).

<< 2-7. Form of integrated light source of the present invention >>
The light emitting elements of type A to type D can be incorporated into the integrated light source of the present invention in various forms.

  In the type A form, as shown in FIG. 11, the submount 40 provided in the light emitting element 10 can be mounted on the main support 100 to form an integrated light source. In this integrated light source, a sub-mant 40 exists corresponding to the light emitting element, apart from the main support 100. Any of the above-mentioned (i) to (v) is possible for the light extraction material 110 to be attached. FIG. 11 shows the adhesion form (v).

  Alternatively, as shown in FIG. 11A, a mount component 105 having a reflector that surrounds the outer periphery in a wall shape can be used as the main support. In this integrated light source, the light emitting element 10 with the submount 40 is mounted on the part surrounded by the reflector on the mount component 105, and the light extraction material 110 is filled in the space inside the reflector. It has a structure. In FIG. 11A, the form (v) is shown as the form of adhesion of the light extraction material 110, but any of the above-mentioned (i) to (v) is possible.

  Further, a form in which no submount exists is also possible. That is, by forming the necessary metal wiring on the main support 100 in advance, the main support 100 can also serve as the submount 40 in the description of Type A. In this example, as already shown in FIGS. 7-1, 7-2, 8-1, 8-2, 9 and 10, the metal wiring on the main support 100 is connected with metal solder or the like. The light emitting element 10 is directly mounted. Furthermore, as shown in FIG. 12, one or more of the elements in which the plurality of light emitting elements 10 are mounted on one submount 40 are further mounted on the main support 100 to obtain the integrated light source of the present invention. You can also As an example of the form of attachment of the light extraction material 110 to the light emitting element 10, FIG. 12 shows the form of attachment (v), but any of the above-mentioned (i) to (v) is possible.

  Although not shown, even when a type C light emitting element (that is, a light emitting element without a light uniformizing layer as shown in FIG. 4A, for example) is used, a plurality of light emitting elements on the main support are used. The arrangement form of the light emitting elements and the attachment form of the light extraction material to the light emitting elements can be the same as in the case of using the type A light emitting elements.

  Similarly, in the type B form, as shown in FIG. 13, a support 40 provided for each light-emitting element 10 is mounted on the main support 100, or as shown in FIG. One or more elements in which the light emitting elements 10 are mounted on one support 40 are mounted on the main support 100, or as shown in FIG. 15, the plurality of light emitting elements 10 are connected to the main via metal solder or the like. By directly mounting on the support 100, an integrated light source can be obtained. When the light emitting element 10 in the form of type B is directly mounted on the main support 100 without using the support 40, the device in the process of being manufactured with the substrate 21 attached is not the support 40 but the main support 100. Can be manufactured by peeling the substrate 21. Also in the type C form, as the attachment form of the light extraction material 110, the attachment form of (v) is shown in FIGS. 12 to 14, but any of the above-mentioned (i) to (v) is possible.

  Although not shown, even when a type D light emitting element (that is, a light emitting element having no light uniformizing layer as shown in FIG. 5A for example) is used, a plurality of light emitting elements on the main support are used. The arrangement form of the light emitting elements and the attachment form of the light extraction material to the light emitting elements can be the same as in the case of using the type B light emitting elements.

  Further, the configuration shown in FIG. 11A only shows a typical example using the mount component 105 as a main support, and can be applied to all forms of the integrated light source described above.

<< 3. Light extraction material >>
The light extraction material used for this invention will not be specifically limited if it is material which has transparency, a suitable refractive index, and adhesiveness. More preferably, the material has heat resistance and long-term stability of each of these characteristics.

<< 3-1. Specific materials for light extraction materials >>
As the light extraction material, it is possible to use a curable material that is attached (applied) in a liquid state to the light emitting element and then cured by applying some curing treatment to become a solid. Here, “liquid” includes not only a liquid form used in a general sense but also a gel form. In the present application, the term “light extraction material” generally means a material after curing, and a liquid material is distinguished by a term such as “before curing”. The term “curing” includes all changes from a liquid state to a solid state, and includes solidification by cooling from a molten state and drying by solvent evaporation in addition to curing by polymerization and / or crosslinking.

  The curable material is not particularly limited as long as it secures the role of the light extraction material to increase the extraction efficiency of light emitted from the light emitting element. Moreover, only 1 type may be used for a curable material and it may use 2 or more types together by arbitrary combinations and a ratio. Therefore, as the curable material, any of inorganic materials, organic materials, and mixtures thereof can be used.

  As the inorganic material, for example, a solution obtained by hydrolytic polymerization of a solution containing a metal alkoxide, a ceramic precursor polymer or a metal alkoxide by a sol-gel method, or a combination thereof is solidified (for example, a siloxane bond). Inorganic materials having

  On the other hand, examples of the organic material include a thermosetting resin and a photocurable resin. Specific examples include (meth) acrylic resins such as poly (meth) acrylic acid methyl; styrene resins such as polystyrene and styrene-acrylonitrile copolymers; polycarbonate resins; polyester resins; phenoxy resins; butyral resins; Cellulose resins such as cellulose acetate and cellulose acetate butyrate; epoxy resins; phenol resins; silicone resins and the like.

  Among these curable materials, it is particularly preferable to use a silicon-containing compound that has little deterioration with respect to light emission from the light emitting element and is excellent in heat resistance. A silicon-containing compound is a compound having a silicon atom in the molecule, organic materials such as polyorganosiloxane (silicone-based materials), inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride, and borosilicates and phosphosilicates. Examples thereof include glass materials such as salts and alkali silicates. Of these, silicone materials are preferred from the viewpoints of transparency, adhesion, ease of handling, mechanical and thermal adaptability relaxation characteristics, and the like.

<< 3-2. Silicone-based material >>
The silicone material generally refers to an organic polymer having a siloxane bond as a main chain, and examples thereof include compounds represented by the following general composition formula (1) and / or mixtures thereof.
(R ¹ R ² R ³ SiO _1/2 ) _M (R ⁴ R ⁵ SiO _2/2 ) _D (R ⁶ SiO _3/2 ) _T (SiO _4/2 ) _Q Formula (1)
In the general composition formula (1), R ¹ to R ⁶ represent those selected from the group consisting of organic functional groups, hydroxyl groups and hydrogen atoms. R ¹ to R ⁶ may be the same or different.

  In the general composition formula (1), M, D, T, and Q represent a number of 0 or more and less than 1. However, the number satisfies M + D + T + Q = 1.

  When a silicone material is used as the curable material, the liquid silicone material may be attached to the light emitting element and then cured by heat or light.

Types of silicone materials:
When silicone materials are classified according to the curing mechanism, silicone materials such as an addition polymerization curing type, a condensation polymerization curing type, an ultraviolet curing type, and a peroxide vulcanization type can be generally cited. Among these, addition polymerization curing type (addition type silicone resin), condensation curing type (condensation type silicone resin), and ultraviolet curing type are preferable. Hereinafter, the addition type silicone material and the condensation type silicone material will be described.

Addition type silicone materials:
The addition-type silicone material refers to a material in which a polyorganosiloxane chain is crosslinked by an organic addition bond. Typical examples include compounds having a Si—C—C—Si bond at the cross-linking point obtained by reacting vinylsilane and hydrosilane in the presence of an addition catalyst such as a Pt catalyst. As these, commercially available products can be used. Specific examples of addition polymerization curing type trade names include “LPS-1400”, “LPS-2410”, and “LPS-3400” manufactured by Shin-Etsu Chemical Co., Ltd.

Condensed silicone material:
Examples of the condensation type silicone material include a compound having a Si—O—Si bond obtained by hydrolysis and polycondensation of an alkylalkoxysilane at a crosslinking point. Specific examples include polycondensates obtained by hydrolysis and polycondensation of compounds represented by the following general formula (2) and / or (3) and / or oligomers thereof.
M ^{m +} X _n Y ¹ _mn (2)
(In Formula (2), M represents at least one element selected from the group consisting of silicon, aluminum, zirconium, and titanium, X represents a hydrolyzable group, and Y ¹ represents a monovalent group. Represents an organic group, m represents an integer of 1 or more representing the valence of M, and n represents an integer of 1 or more representing the number of X groups, provided that m ≧ n.
_{^{(M s + X t Y 1}} st-1) u Y 2 (3)
(In Formula (3), M represents at least one element selected from the group consisting of silicon, aluminum, zirconium, and titanium, X represents a hydrolyzable group, and Y ¹ represents a monovalent group. Represents an organic group, Y ² represents a u-valent organic group, s represents an integer of 1 or more representing the valence of M, t represents an integer of 1 or more and s−1 or less, u represents Represents an integer of 2 or more.)

  The condensation type silicone material may contain a curing catalyst. Any curing catalyst can be used as long as the effects of the present invention are not significantly impaired. For example, a metal chelate compound can be suitably used. The metal chelate compound preferably contains one or more selected from the group consisting of aluminum, zirconium, tin, zinc, titanium and tantalum, and more preferably contains Zr. In addition, only 1 type may be used for a curing catalyst and it may use 2 or more types together by arbitrary combinations and a ratio.

  Examples of such condensation-type silicone materials include, for example, JP-A-2006-77234, JP-A-2006-291018, JP-A-2006-316264, JP-A-2006-336010, and JP-A-2006-348284. And a member for a semiconductor light emitting device described in International Publication No. 2006/090804 pamphlet are suitable.

  Of the condensed silicone materials, particularly preferred materials will be described below.

  In general, silicone materials often have low adhesion to semiconductor light emitting elements, substrates on which the elements are arranged, packages, and the like. Therefore, it is preferable to use a silicone material having high adhesion as the curable material used in the present invention, and in particular, a condensed silicone material having one or more of the following features <1> to <3>. More preferably, it is used.

  <1> The silicon content is 20% by weight or more.

<2> The solid Si-nuclear magnetic resonance (NMR) spectrum measured by the method described in detail later has at least one peak derived from Si in the following (a) and / or (b).
(A) A peak whose peak top position is in the region of chemical shift −40 ppm or more and 0 ppm or less with respect to silicone rubber, and the peak half-value width is 0.3 ppm or more and 3.0 ppm or less.
(B) A peak whose peak top position is in a region where the chemical shift is −80 ppm or more and less than −40 ppm with respect to the silicone rubber, and the half width of the peak is 0.3 ppm or more and 5.0 ppm or less.

  <3> The silanol content is 0.01% by weight or more and 10% by weight or less.

  The curable material used in the present invention is preferably a silicone material having the characteristic <1> among the above characteristics <1> to <3>. More preferably, a silicone material having the above characteristics <1> and <2> is preferable. Particularly preferably, a silicone material having all of the above features <1> to <3> is preferable. Hereinafter, the features <1> to <3> will be described.

[Feature <1> (silicon content)]
The silicon content of a silicone material suitable as a curable material that can be used in the present invention is usually 20% by weight or more, preferably 25% by weight or more, and more preferably 30% by weight or more. On the other hand, the upper limit is usually in the range of 47% by weight or less because the silicon content of the glass composed solely of SiO ₂ is 47% by weight.

  Note that the silicon content of the silicone-based material is calculated based on the results obtained by performing inductively coupled plasma spectroscopy (hereinafter abbreviated as “ICP” as appropriate), for example, using the following method. be able to.

Measurement of silicon content:
Silicone material is baked in a platinum crucible in the air at 450 ° C. for 1 hour, then at 750 ° C. for 1 hour, and at 950 ° C. for 1.5 hours to remove the carbon component, and then a small amount of residue is obtained. Add more than 10 times the amount of sodium carbonate and heat with a burner to melt, cool this, add demineralized water, and adjust the pH to neutral with hydrochloric acid to a few ppm as silicon. ICP analysis is performed.

[Characteristic <2> (Solid Si-NMR spectrum)]
When a solid Si-NMR spectrum of a silicone material suitable as a curable material that can be used in the present invention is measured, the above (a) and / or (b) derived from a silicon atom to which a carbon atom of an organic group is directly bonded. At least one, preferably a plurality of peaks are observed in the peak region.

  When arranged for each chemical shift, in the silicone material suitable as the curable material that can be used in the present invention, the half width of the peak described in the above (a) is generally the above ( It is smaller than the peak described in b) and is usually 3.0 ppm or less, preferably 2.0 ppm or less, and usually 0.3 ppm or more.

  On the other hand, the half width of the peak described in (b) is usually 5.0 ppm or less, preferably 4.0 ppm or less, and usually 0.3 ppm or more, preferably 0.4 ppm or more.

  If the half-value width of the peak observed in the chemical shift region is too large, the molecular motion is constrained and strain is large, cracks are likely to occur, and the member may be inferior in heat resistance and weather resistance. For example, when a large amount of tetrafunctional silane is used, or when a large internal stress is accumulated by rapid drying in the drying process, the full width at half maximum may be larger than the above range.

  In addition, if the half width of the peak is too small, Si atoms in the environment will not be involved in siloxane crosslinking, and heat resistance is higher than substances formed mainly from siloxane bonds, such as examples where trifunctional silane remains in an uncrosslinked state. -It may be a member inferior in weather resistance.

  However, in a silicone material containing a small amount of Si component in a large amount of organic component, good heat resistance / light resistance and coating performance can be obtained even if the peak of the above-mentioned half-value range is observed at -80 ppm or more. There may not be.

  The chemical shift value of a silicone material suitable as a curable material that can be used in the present invention can be calculated based on the results of solid Si-NMR measurement using the following method, for example. In addition, analysis of measurement data (half-width or silanol amount analysis) is performed by a method of dividing and extracting each peak by, for example, waveform separation analysis using a Gaussian function or a Lorentz function.

[Solid Si-NMR spectrum measurement]
When performing a solid Si-NMR spectrum about a silicone type material, a solid Si-NMR spectrum measurement and waveform separation analysis are performed on condition of the following. Further, from the obtained waveform data, the half width of each peak is determined for the silicone material.

[Equipment conditions]
Equipment: Chemagnetics Infinity CMX-400 Nuclear Magnetic Resonance Spectrometer
²⁹ Si resonance frequency: 79.436 MHz
Probe: 7.5 mmφ CP / MAS probe Measurement temperature: room temperature Sample rotation speed: 4 kHz
Measurement method: Single pulse method
¹ H decoupling frequency: 50 kHz
²⁹ Si flip angle: 90 °
²⁹ Si 90 ° pulse width: 5.0μs
Repeat time: 600s
Integration count: 128 Observation width: 30 kHz
Broadening factor: 20Hz
Reference sample: Silicone rubber

[Data processing example]
For silicone-based materials, 512 points are taken as measurement data, zero-filled to 8192 points, and Fourier transformed.

[Waveform separation analysis method]
For each peak of the spectrum after Fourier transform, optimization calculation is performed by a non-linear least square method with the center position, height, and half width of the peak shape created by Lorentz waveform and Gaussian waveform or a mixture of both as variable parameters.

  In addition, the identification of a peak is AIChE Journal, 44 (5), p. Refer to 1141, 1998, etc.

[Feature <3> (silanol content)]
A silicone material suitable as a curable material that can be used in the present invention has a silanol content of usually 0.01% by weight or more, preferably 0.1% by weight or more, more preferably 0.3% by weight or more, Moreover, it is usually 10% by weight or less, preferably 8% by weight or less, and more preferably 5% by weight or less. By reducing the silanol content, the silanol-based material has excellent performance with little change over time, excellent long-term performance stability, and low moisture absorption and moisture permeability. However, since a member containing no silanol is inferior in adhesion, there exists an optimum range for the silanol content as described above.

  The silanol content of the silicone-based material is measured, for example, by measuring the solid Si-NMR spectrum using the method described in the above section [Measurement of solid Si-NMR spectrum], and the ratio of the peak area derived from silanol to the total peak area. Thus, the ratio (%) of silicon atoms which are silanols in all silicon atoms can be obtained and calculated by comparing with the silicon content analyzed separately.

  In addition, since a silicone material suitable as a curable material that can be used in the present invention contains an appropriate amount of silanol, a polar portion present on the surface of a member such as a substrate or a weir constituting the light guide member Silanol is hydrogen-bonded to the surface to develop adhesiveness. Examples of the polar part include a hydroxyl group and a metalloxane-bonded oxygen.

  Furthermore, a silicone material suitable as a curable material that can be used in the present invention is heated with the presence of an appropriate catalyst to form a hydroxyl group on the surface of a member such as a substrate or a weir constituting the light guide member. A covalent bond can be formed between them by dehydration condensation, and stronger adhesion can be expressed.

  On the other hand, if there is too much silanol, the inside of the system will thicken and it will be difficult to apply, or it will become more active and solidify before the light-boiling components volatilize by heating, leading to increased foaming and internal stress. It may occur and induce cracks.

Other ingredients:
As long as the effects of the present invention are not significantly impaired, the curable material may be used by further mixing other components with the above-described inorganic material and / or organic material. In addition, only 1 type may be used for another component and it may use 2 or more types together by arbitrary combinations and ratios.

Inorganic particles:
The curable material may further contain inorganic particles for the purpose of improving optical characteristics and workability and for the purpose of obtaining any of the following effects [1] to [5]. In addition, inorganic particle | grains may use only 1 type and may use 2 or more types together by arbitrary combinations and a ratio.

  [1] By making the curable material contain inorganic particles as a light scattering agent, a layer formed of the curable material is used as a scattering layer. Thereby, the light transmitted from the light source can be scattered in the scattering layer, and the directivity angle of the light emitted from the light guide member to the outside can be widened. If inorganic particles are contained as a light scattering agent in combination with the phosphor, the amount of light hitting the phosphor can be increased and the wavelength conversion efficiency can be improved.

  [2] By containing inorganic particles as a binder in the curable material, it is possible to prevent the occurrence of cracks in the layer formed of the curable material.

  [3] By containing inorganic particles as a viscosity modifier in the curable material, the viscosity of the curable material can be increased.

  [4] By containing inorganic particles in the curable material, shrinkage of the layer formed of the curable material can be reduced.

  [5] By incorporating inorganic particles in the curable material, the refractive index of the layer formed of the curable material can be adjusted, and the light extraction efficiency can be improved.

  However, when inorganic particles are included in the curable material, the effect obtained depends on the type and amount of the inorganic particles.

  For example, ultrafine silica particles having a particle diameter of about 10 nm, fumed silica (dry silica. For example, “Nippon Aerosil Co., Ltd., trade name: AEROSIL # 200”, “Tokuyama Co., Ltd., trade name: Leolo Seal”, etc. ), The thixotropic property of the curable material is increased, so that the effect [3] is great.

  In addition, for example, when the inorganic particles are crushed silica or true spherical silica having a particle size of about several μm, there is almost no increase in thixotropic property, and the function as an aggregate of the layer containing the inorganic particles is the center. The effects [2] and [4] are great.

  In addition, for example, when inorganic particles having a particle size of about 1 μm, which has a refractive index different from those of other compounds (such as the inorganic material and / or organic material) used in the curable material, Since the light scattering at the interface increases, the effect [1] is great.

  In addition, for example, the median particle size is usually 1 nm or more, preferably 3 nm or more, and usually 10 nm or less, preferably 5 nm or less, specifically, the emission wavelength or less, having a larger refractive index than other compounds used in the curable material. When the inorganic particles having a particle size of are used, the refractive index can be improved while maintaining the transparency of the layer containing the inorganic particles, and thus the effect [5] is great.

  Accordingly, the type of inorganic particles to be mixed may be selected according to the purpose. Moreover, the kind may be single and may combine multiple types. Moreover, in order to improve dispersibility, it may be surface-treated with a surface treatment agent such as a silane coupling agent.

Types of inorganic particles:
Examples of the inorganic particles used include inorganic oxide particles such as silica, barium titanate, titanium oxide, zirconium oxide, niobium oxide, aluminum oxide, cerium oxide, yttrium oxide, and diamond particles. Other materials can be selected accordingly, but are not limited thereto.

  The form of the inorganic particles may be any form such as powder, slurry, etc. depending on the purpose, but if it is necessary to maintain transparency, the refractive index of other materials contained in the layer containing the inorganic particles is set. It is preferable that they are equivalent or added to the curable material as a water-based or solvent-based transparent sol.

Median particle size of inorganic particles:
The median particle size of these inorganic particles (primary particles) is not particularly limited, but is usually about 1/10 or less of the phosphor particles. Specifically, those having the following median particle diameter are used according to the purpose. For example, if inorganic particles are used as the light scattering material, the median particle size is usually 0.05 μm or more, preferably 0.1 μm or more, and usually 50 μm or less, preferably 20 μm or less. For example, if inorganic particles are used as the aggregate, the median particle diameter is preferably 1 μm to 10 μm. Further, for example, if inorganic particles are used as a thickener (thixotropic agent), the center particle is preferably 10 to 100 nm. For example, if inorganic particles are used as the refractive index adjuster, the median particle size is preferably 1 to 10 nm.

Inorganic particle mixing method:
The method for mixing the inorganic particles is not particularly limited. Usually, it is recommended to mix while defoaming using a planetary stirring mixer or the like in the same manner as the phosphor. For example, when mixing small particles that easily aggregate, such as Aerosil, after mixing the particles, break up the aggregated particles using a bead mill or three rolls if necessary, then mix large particles such as phosphor You may mix an ingredient.

Content of inorganic particles:
The content of the inorganic particles in the curable material is arbitrary as long as the effects of the present invention are not significantly impaired, and can be freely selected depending on the application form. However, the content of the inorganic particles in the layer containing the inorganic particles is preferably selected according to the application form. For example, when inorganic particles are used as the light scattering agent, the content in the layer is preferably 0.01 to 10% by weight. For example, when inorganic particles are used as the aggregate, the content in the layer is preferably 1 to 50% by weight. For example, when using inorganic particles as a thickener (thixotropic agent), the content in the layer is preferably 0.1 to 20% by weight. For example, when using inorganic particles as a refractive index adjuster, the content in the layer is preferably 10 to 80% by weight. If the amount of inorganic particles is too small, the desired effect may not be obtained, and if it is too large, various properties such as adhesion, transparency and hardness of the cured product may be adversely affected. Moreover, what is necessary is just to set the content rate of the inorganic particle in a fluid curable material so that the content rate of the inorganic particle in each layer may be settled in the said range. Therefore, when the fluid curable material does not change in weight in the drying step, the content of inorganic particles in the curable material is the same as the content of inorganic particles in each layer to be formed. Also, when the curable material changes in weight in the drying process, such as when the fluid curable material contains a solvent, the content of inorganic particles in the curable material excluding the solvent, What is necessary is just to make it become the same as the content rate of the inorganic particle in each layer formed.

  Further, when the hydrolysis / polycondensation product of alkylalkoxysilane is used as the curable material, the hydrolysis / polycondensation product has a lower viscosity than other curable materials such as epoxy resins and silicone resins. In addition, it has the advantage of being able to maintain sufficient coating performance even when dispersed at a high concentration of inorganic particles. In addition, it is possible to increase the viscosity by adjusting the degree of polymerization and adding a thixo material such as aerosil as necessary, and the adjustment range of the viscosity according to the target inorganic particle content is large. It is possible to provide a coating solution that can flexibly correspond to various coating methods such as potting, spin coating, and printing.

<< 3-3. Other >>
The light extraction material may be subjected to various post treatments as necessary. Examples of the post-treatment include surface treatment, production of an antireflection film, production of a fine uneven surface for improving light extraction efficiency, and the like.

  The light extraction material preferably has a thermal expansion coefficient as small as that of the material used for the integrated light source. However, when a preferable silicone material is used, it has an elastomeric property as described above. It is also preferable, and it can be appropriately set in consideration of the attached device part and the like. The more the branched structure and the crosslinked structure in the cured product, the smaller the thermal expansion coefficient, but generally it becomes harder and the elastomeric properties are lowered. Therefore, in a preferable silicone material, in addition to the monomer and / or oligomer having only bifunctional silicon, the crosslinking density can be appropriately adjusted by using a monomer and / or oligomer having trifunctional or higher silicon as a raw material. preferable.

  The light extraction material can also contain a phosphor. A plurality of layers can also be used.

<< 4. Manufacturing of integrated light source with light extraction material attached >>
In the present invention, it is preferable to manufacture an integrated light source by mounting a plurality of light emitting elements on a main support and then attaching a light extraction material to the light emitting elements. As a method for attaching the light extraction material, it is preferable to appropriately adjust the viscosity of the liquid material (light extraction material before curing) so as to obtain a desired shape.

  As described above, the light extraction material is attached to the light emitting element in the forms (i) to (v). For example, in the case of the adhesion form (i), it can be formed by sequentially depositing a relatively high viscosity material with a dispenser or the like. In the forms of adhesion (ii) to (v), in particular, the forms of (iii) to (v), a material having low viscosity and high fluidity may be used. As shown in FIG. 16, when the fluidity is very high, a liquid stopper 120 may be provided around the light emitting element. In addition, when the mount component 105 as shown in FIG. 11A is used as a main support, the reflector on the outer periphery of the mount component 105 can be used as a liquid stopper. Alternatively, as shown in FIG. 17, the integrated light source 200 is immersed upside down in the liquid material 113 in the potting container 121 to cure the liquid material, and then the potting container 121 is removed to form a light extraction material. May be.

  The integrated light source manufactured as described above can provide a large-area light source suitable for use for illumination by having a structure in which a plurality of light emitting elements are arranged on a main support. it can. In addition, since the light extraction material is attached to the light emitting element, the light extraction efficiency is improved, and the light emission element is more suitable for use for illumination. Furthermore, the uniformity of light extraction is also improved depending on the form of attachment of the light extraction material to the light emitting element.

  The features of the present invention will be described more specifically with reference to the following examples. Materials, usage amounts, ratios, processing contents, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the specific examples shown below. In the drawings referred to in the following embodiments, there are portions where the dimensions are intentionally changed in order to make the structure easy to grasp, but the actual dimensions are as described in the following text.

<< Production Example of Type A Light-Emitting Element >>
(Production Example A-1)
The light emitting element shown in FIG. 1-11 was manufactured by the following procedure. Refer to FIGS. 1-5 to 10 for related process diagrams.

A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a thickness of 10 nm is formed as a first buffer layer 22a on the first buffer layer 22a by using the MOCVD method. As the second buffer layer 22b, an undoped GaN layer having a thickness of 0.5 μm and a Si-doped (Si concentration: 7 × 10 ¹⁷ cm ⁻³ ) GaN layer having a thickness of 0.5 μm were stacked at 1040 ° C. Subsequently, an undoped GaN layer having a thickness of 3.5 μm was formed as the light uniformizing layer 23 at 1035 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps up to here generally corresponds to FIGS. 1-5. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, the photolithography process was performed again to pattern the SiN _x mask, and an SiN _x etching mask was produced. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIGS. 1-6.

Next, in order to carry out the second etching step for forming the inter-device separation groove 13, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region for forming the inter-device separation groove was removed, and the inter-device separation groove forming mask for the thin film crystal layer, that is, the second etching step SrF ₂ mask was formed.

Next, as the second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier layer corresponding to the device isolation trenches All of the thin film crystal layers of the active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, the undoped GaN light uniformizing layer 23, and the undoped GaN buffer layer 22 Was subjected to ICP etching using Cl ₂ gas. During this second etching step, the SrF ₂ mask was hardly etched. The width of the inter-device separation groove 13 was 150 μm, which was the same as the width of the mask.

After forming the inter-device separation groove 13 by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps so far generally corresponds to FIGS. 1-7.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. The structure completed through the steps so far generally corresponds to FIGS. 1-8.

Next, formation of the p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of the n-side current injection region (36) on the n-side contact layer 24c, and formation of the scribe region 14 in the inter-device isolation trench First, a resist mask was formed using a photolithography technique. Next, the portion of the dielectric multilayer film (insulating layer) not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm. The width of the scribe region (the _{L WS} in the device after separation 50 [mu] m) 100 [mu] m was formed to have a.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG. 1-9A.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (300 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region, and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another manufacturing example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this manufacturing example was obtained. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIGS. 1-10.

Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low-reflection optical film were braked along this scribe line to complete each compound semiconductor light emitting element. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element shown in FIG. 1-11. At this time, an unintended short circuit of the element did not occur.

(Production Example A-2)
The light-emitting element shown in FIG. 1-15 (similar to FIG. 1-2A) was manufactured by the following procedure.

  The process similar to that in Production Example A-1 was repeated until the dielectric multilayer film was formed as an insulating layer on the entire surface of the wafer (generally corresponding to FIGS. 1-8).

Next, formation of the p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of the n-side current injection region 36 on the n-side contact layer 24c, and the sidewall of the undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer existing on the substrate 21 side, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) that was not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Furthermore, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped buffer layer 22 was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 was covered with an insulating layer made of SiN _x and SiO _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIGS. 1-9B.

Next, the n-side electrode 28 was formed in the same manner as in Production Example A-1. Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low-reflection optical film were braked along this scribe line to complete each light emitting element. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element shown in FIG. 1-15. At this time, an unintended short circuit of the element did not occur.

(Production Examples A-3, 4)
In Production Examples A-1 and 2, Production Examples A-1 and 2 were repeated, except that the thin film crystal layer was formed as follows after the light uniformizing layer 23 was formed. That is, in Production Example A-1, after forming undoped GaN having a thickness of 3.5 μm as the light uniformizing layer 23 at 1035 ° C., the first conductivity type (n-type) second cladding layer 24b is further doped with Si (Si A GaN layer having a concentration of 5 × 10 ¹⁸ cm ⁻³ ) is formed to a thickness of 4 μm, and a Si-doped (Si concentration 8 × 10 ¹⁸ cm ⁻³ ) GaN layer is added as a first conductive type (n-type) contact layer 24c to a thickness of 0. Further, an Al _0.10 Ga _0.90 N layer doped with Si (Si concentration: 5.0 × 10 ¹⁸ cm ⁻³ ) is formed as a first conductivity type (n-type) first cladding layer 24a with a thickness of 5 μm. It was formed with a thickness of 1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, the light emitting devices shown in FIGS. 1-11 and 1-15 were completed in the same manner as in Production Examples A-1 and A-2. At this time, an unintended short circuit or the like of the element did not occur.

In the processes of Production Examples A-1 to A-4, the SiN _x mask is removed after the first etching step. However, the SiN _x mask may be removed after the second etching step without removing the SiN _x mask.

  Furthermore, in Production Example A-1 (and Production Example A-3), the light emitting element shown in FIG. 1-1D can be produced by stopping the etching in the second etching step in the middle of the buffer layer ( However, the insulating layer is a multilayer dielectric film). Moreover, the light emitting element shown to FIGS. 1-1C can be manufactured by stopping the etching by a 2nd etching process in the middle of a light uniformization layer. Similarly, in Production Example A-2 (and Production Example A-4), the etching in the second etching step is stopped in the middle of the buffer layer, and appropriate by photolithography suitable for the predetermined shape. The light emitting device shown in FIG. 1-2D or FIG. 1-2E can be manufactured by preparing an etching mask shape and the amount of side etching (however, the insulating layer is a multilayer dielectric film). Moreover, the light emitting element shown to FIGS. 1-2C can be manufactured by stopping the etching by a 2nd etching process in the middle of a light uniformization layer.

(Production Example A-5)
The light emitting element shown in FIG. 1-12 was manufactured by the following procedure. A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer grown at a low temperature of 20 nm is formed as a first buffer layer 22a on the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 1 μm was formed at 1040 ° C.

As the light uniformizing layer 23, an undoped GaN layer having a thickness of 2 μm including a laminated structure of 10 layers each having an undoped In _0.05 Ga _0.95 N layer of 3 nm thickness and an undoped GaN layer of 12 nm thickness was formed. Here, the undoped GaN layer was grown at 850 ° C., and the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 22a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to a thickness of 2 nm at 715 ° C. as a quantum well layer, The well layers were alternately formed so that the total number of well layers was three and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to carry out a second etching step for forming an inter-device separation groove, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. Active layer structure 25 composed of layers, n-AlGaN first cladding layer 24a, n-GaN contact layer 24c, n-GaN second cladding layer 24b, undoped InGaN / GaN light homogenizing layer 23 and undoped GaN buffer layer 22 All thin film crystal layers were ICP etched using Cl ₂ gas. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method. Next, a p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, an n-side current injection region on the n-side contact layer, and a scribe region 14 for an inter-device isolation trench are formed at the same time. For this purpose, first, a resist mask was formed using a photolithography technique, and then an insulating layer in a portion not covered with the resist mask was removed using RIE plasma of SF ₆ gas. Here, the periphery of the p-side electrode was covered with a SiN _x insulating layer. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Next, in order to form the n-side electrode 28, a resist pattern was formed by preparing to pattern the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, this element was joined to the metal layer 41 of the submount 40 using metal solder 42 to complete the light emitting element. At this time, an unintended short circuit of the element did not occur.

(Production Example A-6)
In Production Example A-5, a light emitting device was produced in the same manner as in Production Example A-5, except that the configuration of the substrate and the thin film crystal layer was changed as follows.

First, a c + -plane GaN substrate 21 (Si concentration: 1 × 10 ¹⁷ cm ⁻³ ) having a thickness of 330 μm is prepared. On top of this, undoped GaN having a thickness of 2 μm is first formed at 1040 ° C. as a buffer layer 22 using MOCVD. Formed.

Subsequently, 4 μm of undoped GaN including a laminated structure of 20 layers each of undoped In _0.05 Ga _0.95 N of 3 nm and undoped GaN of 12 nm as the light uniformizing layer 23 was formed. Here, the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C., the adjacent undoped GaN layer was grown at 850 ° C., and the other GaN layers were grown at 1035 ° C.

Next, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. Si-doped (Si concentration 7 × ¹⁰ 18 ^{cm -3)} of the GaN layer was formed to 0.5μm thick, Si-doped (Si concentration: 5 × ^{10 18} as a further first conductivity type (n-type) first cladding layer 24a as A cm ^-3 ) Al _0.10 Ga _0.90 N layer was formed to a thickness of 0.1 µm.

Further, as the active layer structure 25, an undoped GaN layer formed to 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to 2 nm at 715 ° C. as a quantum well layer, Films were alternately formed so that the total number of layers was 8 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  Thereafter, a light emitting device was completed in the same manner as in Production Example A-5. At this time, an unintended short circuit or the like of the device did not occur.

In Production Examples A-5 and 6, the second etching step was performed and then the first etching step was performed. However, the first etching step may be performed first, and then the second etching step may be performed. In that case, it is also preferable to perform the second etching step without removing the SiN _x mask used in the first etching step. In addition, when the insulating layer 30 is etched, an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape, and side etching is performed to manufacture a light-emitting element having the shape of the second aspect. You can also

<< Production Example of Type B Light Emitting Element >>
(Production Example B-1)
The light emitting element shown in FIG. 2-15 was manufactured by the following procedure. Refer to FIGS. 2-7 to 12 for related process drawings.

A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a thickness of 10 nm is formed as a first buffer layer 22a on the first buffer layer 22a by MOCVD, and then a 1 μm thickness is formed. As the second buffer layer 22b, an undoped GaN layer having a thickness of 0.5 μm and a Si-doped (Si concentration: 7 × 10 ¹⁷ cm ⁻³ ) GaN layer having a thickness of 0.5 μm were stacked at 1040 ° C. Subsequently, an undoped GaN layer having a thickness of 3.5 μm was formed as the light uniformizing layer 23 at 1035 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps up to this point generally corresponds to FIG. 2-7. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, the photolithography process was performed again to pattern the SiN _x mask, and an SiN _x etching mask was produced. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to this point generally corresponds to FIG.

Next, in order to carry out the second etching step for forming the inter-device separation groove 13, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region for forming the inter-device separation groove was removed, and the inter-device separation groove forming mask for the thin film crystal layer, that is, the second etching step SrF ₂ mask was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second cladding layer 26b, the p-AlGaN first cladding layer 26a, the InGaN quantum well layer, and the GaN barrier layer corresponding to the device isolation trenches All of the thin film crystal layers of the active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, the undoped GaN light uniformizing layer 23, and the undoped GaN buffer layer 22 Was subjected to ICP etching using Cl ₂ gas. During this second etching step, the SrF ₂ mask was hardly etched. The width of the inter-device separation groove 13 was 150 μm, which was the same as the width of the mask.

After forming the inter-device separation groove 13 by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to this point generally corresponds to FIG.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. The structure completed through the steps up to here generally corresponds to FIG.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer existing on the side of the substrate 21 on the side wall, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) on which the resist mask was not formed with a hydrofluoric acid-based etchant was removed. Furthermore, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped buffer layer 22 was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (300 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region, and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another manufacturing example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this manufacturing example was obtained. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIG.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (substrate 21) on which the light-emitting element was formed was bonded to this support using AuSn solder. At the time of bonding, the wafer (substrate 21) on which the support 40 and the light emitting elements are formed is heated to 300 ° C., and the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. It was made to be. At this time, an unintended short circuit or the like of the element did not occur at this time.

  Next, in order to perform substrate peeling, a laser beam emitted from a KrF excimer laser (wavelength 248 nm) was irradiated from the surface of the substrate 21 where thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). . Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, a separation region portion in the support and an inter-device separation groove in the wafer were simultaneously cut using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. In this way, the compound semiconductor light emitting device shown in FIG. 2-15 was completed.

(Production Example B-2)
In Production Example B-1, Production Examples B-1 and 2 were repeated, except that the thin film crystal layer was formed as follows after the light uniformizing layer 23 was formed. That is, in Production Example B-1, after forming 3.5 μm-thick undoped GaN at 1035 ° C. as the light homogenizing layer 23, the first conductivity type (n-type) second cladding layer 24 b is further doped with Si (Si A GaN layer having a concentration of 5 × 10 ¹⁸ cm ⁻³ ) is formed to a thickness of 4 μm, and a Si-doped (Si concentration 8 × 10 ¹⁸ cm ⁻³ ) GaN layer is added as a first conductive type (n-type) contact layer 24c to a thickness of 0. Further, an Al _0.10 Ga _0.90 N layer doped with Si (Si concentration: 5.0 × 10 ¹⁸ cm ⁻³ ) is formed as a first conductivity type (n-type) first cladding layer 24a with a thickness of 5 μm. It was formed with a thickness of 1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, the light emitting device shown in FIG. 2-15 was completed in the same manner as in Production Example B-1. At this time, an unintended short circuit or the like of the element did not occur.

In the processes of Production Examples B-1 and 2, the SiN _x mask is removed after the first etching step. However, the SiN _x mask may be removed after the second etching step without removing the SiN _x mask.

  Furthermore, in Manufacturing Example B-1 and Manufacturing Example B-2, the light emitting device shown in FIGS. 2-2B and 2-2C is manufactured by stopping the etching in the second etching process in the middle of the buffer layer. (However, the insulating layer is a multilayer dielectric film). Moreover, the light emitting element shown to FIGS. 2-2A can be manufactured by stopping the etching by a 2nd etching process in the middle of a light uniformization layer. For element isolation, the element isolation region in the support may be cut together with the light uniformizing layer and the buffer layer at the bottom of the inter-device isolation groove.

Further, in order to manufacture the light emitting device shown in FIGS. 2-3A to 2-3C, in the manufacturing examples B-1 and B-2, the etching in the second etching step is performed by using the light uniformizing layer or the buffer layer. In addition, an appropriate etching mask shape is prepared by photolithography suitable for the planned shape, and the width of the scribe region is, for example, 100 μm (element after separation) without proceeding the side etching of the insulating layer. as L _WS in is 50 [mu] m), it can be carried out by forming a scribe region while leaving the insulating layer in the groove bottom surface (where the insulating layer is a multilayer dielectric film).

(Production Example B-3)
The light emitting element shown in FIG. 2-16 was manufactured by the following procedure. A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer grown at a low temperature of 20 nm is formed as a first buffer layer 22a on the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 1 μm was formed at 1040 ° C.

As the light uniformizing layer 23, an undoped GaN layer having a thickness of 2 μm including a laminated structure of 10 layers each having an undoped In _0.05 Ga _0.95 N layer of 3 nm thickness and an undoped GaN layer of 12 nm thickness was formed. Here, the undoped GaN layer was grown at 850 ° C., and the undoped In _0.05 Ga _0.95 N layer was grown at 730 ° C.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to 2 nm at 715 ° C. as a quantum well layer, Films were alternately formed so that the total number of layers was 3 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to carry out a second etching step for forming an inter-device separation groove, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. Active layer structure 25 composed of layers, n-AlGaN first cladding layer 24a, n-GaN contact layer 24c, n-GaN second cladding layer 24b, undoped InGaN / GaN light homogenizing layer 23 and undoped GaN buffer layer 22 All thin film crystal layers were ICP etched using Cl ₂ gas. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer present on the substrate side portion of the sidewall, a resist mask was formed by using a photolithography technique. Next, the insulating layer on which the resist mask was not formed was removed with a hydrofluoric acid etchant. Further, the insulating layer on the substrate side portion of the side wall of the undoped buffer layer was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 is covered with an SiN _x insulating layer of 150 μm. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Next, in order to form the n-side electrode 28, a resist pattern was formed by preparing to pattern the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (substrate 21) on which the light-emitting element was formed was bonded to this support using AuSn solder. At the time of bonding, the wafer (substrate 21) on which the support 40 and the light emitting elements are formed is heated to 300 ° C., and the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. It was made to be. At this time, an unintended short circuit or the like of the element did not occur at this time.

  Next, in order to perform substrate peeling, a laser beam emitted from a KrF excimer laser (wavelength 248 nm) was irradiated from the surface of the substrate 21 where thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). . Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, a separation region portion in the support and an inter-device separation groove in the wafer were simultaneously cut using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the compound semiconductor light emitting device shown in FIG. 2-16 was completed.

<< Production Example of Type C Light-Emitting Element >>
(Production Example C-1)
The light emitting element shown in FIG. 4-11 was manufactured by the following procedure. Refer to FIGS. 4-5 to 10 for related process diagrams.

  A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a low-temperature growth having a thickness of 10 nm is first formed thereon as the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 4 μm was formed at 1040 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps up to this point generally corresponds to FIG. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, the photolithography process was performed again to pattern the SiN _x mask, and an SiN _x etching mask was produced. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to this point generally corresponds to FIG.

Next, in order to carry out the second etching step for forming the inter-device separation groove 13, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region for forming the inter-device separation groove was removed, and the inter-device separation groove forming mask for the thin film crystal layer, that is, the second etching step SrF ₂ mask was formed.

Next, as the second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier layer corresponding to the device isolation trenches The active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, and the undoped GaN buffer layer 22 are all made of Cl ₂ gas. ICP etching was performed. During this second etching step, the SrF ₂ mask was hardly etched. The width of the inter-device separation groove 13 was 150 μm, which was the same as the width of the mask.

After forming the inter-device separation groove 13 by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to this point generally corresponds to FIG.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. The structure completed through the steps up to here generally corresponds to FIGS.

Next, the p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, the n-side current injection region (36) on the n-side contact layer 24c, and the scribe region 14 in the inter-device isolation trench are formed simultaneously. In order to remove the insulating layer, a resist mask was formed using a photolithography technique. Next, the portion of the dielectric multilayer film (insulating layer) not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm. Further, the scribe region was formed to have a width of 100 μm (L _{ws in} the element after separation was 50 μm).

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIG. 4-9A.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (300 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region, and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another manufacturing example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this manufacturing example was obtained. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIGS.

Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low-reflection optical film were braked along this scribe line to complete each light emitting element. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element shown in FIG. 4-11. At this time, an unintended short circuit of the element did not occur.

(Production Example C-2)
The light emitting element shown in FIG. 4-15 (similar to FIG. 4-2A) was manufactured in the following procedure.

  The process similar to that of Production Example C-1 was repeated until the dielectric multilayer film was formed as an insulating layer on the entire surface of the wafer (generally corresponding to FIGS. 4-8).

Next, formation of the p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of the n-side current injection region 36 on the n-side contact layer 24c, and the sidewall of the undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer existing on the substrate 21 side, a resist mask was formed using a photolithography technique. Next, the dielectric multilayer film (insulating layer) that was not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Furthermore, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped buffer layer 22 was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 was covered with an insulating layer made of SiN _x and SiO _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIGS. 4-9B.

Next, the n-side electrode 28 was formed in the same manner as in Production Example C-1. Next, a low reflection optical film 45 made of MgF ₂ was formed on the back side of the sapphire substrate by a vacuum deposition method. In this case, MgF ₂ was formed to ¼ of the optical film thickness so as to be a low reflection coating with respect to the emission wavelength of the element.

Next, in order to divide each light emitting element formed on the wafer, a scribe line was formed in the inter-device separation groove 13 from the thin film crystal growth side using a laser scriber. Furthermore, only the sapphire substrate and the MgF ₂ low-reflection optical film were braked along this scribe line to complete each light emitting element. At this time, no damage was introduced into the thin film crystal layer, and the dielectric film was not peeled off.

  Next, this element was joined to the metal layer 41 of the submount 40 using the metal solder 42 to complete the light emitting element shown in FIG. 4-15. At this time, an unintended short circuit of the element did not occur.

(Production Example C-3, 4)
In Production Examples C-1 and 2, the same steps as Production Examples C-1 and 2 were repeated except that the thin film crystal layer was formed as follows after the buffer layer 22 was formed. That is, after the buffer layer 22 is formed in Production Example C-1, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is further formed as the first conductivity type (n-type) second cladding layer 24b. A GaN layer of Si doping (Si concentration 8 × 10 ¹⁸ cm ⁻³ ) is formed to a thickness of 0.5 μm as the first conductivity type (n-type) contact layer 24c, and the first conductivity type (n Type) An Al _0.10 Ga _0.90 N layer of Si doping (Si concentration 5.0 × 10 ¹⁸ cm ⁻³ ) was formed to a thickness of 0.1 μm as the first cladding layer 24a. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, the light emitting devices shown in FIGS. 4-11 and 4-15 were completed in the same manner as in Production Examples C-1 and C2. At this time, an unintended short circuit or the like of the element did not occur.

In the processes of Production Examples C-1 to C-4, the SiN _x mask is removed after the first etching step. However, the SiN _x mask may be removed after the second etching step without removing the SiN _x mask.

  Furthermore, in Production Example C-1 (and Production Example C-3), the light emitting device shown in FIG. 4-1C can be produced by stopping the etching in the second etching step in the middle of the buffer layer ( However, the insulating layer is a multilayer dielectric film). Similarly, in Production Example C-2 (and Production Example C-4), the light-emitting element shown in FIG. 4-2C can be produced by stopping the etching in the second etching step in the middle of the buffer layer. (However, the insulating layer is a multilayer dielectric film).

(Production Example C-5)
The light emitting element shown in FIG. 4-12 was manufactured by the following procedure. A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer grown at a low temperature of 20 nm is formed as a first buffer layer 22a on the first buffer layer 22a using the MOCVD method. An undoped GaN layer having a thickness of 2 μm was formed at 1040 ° C. as the buffer layer 22b.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to a thickness of 2 nm at 715 ° C. as a quantum well layer, The quantum well layers were alternately formed so that the total number of the quantum well layers was three and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to carry out a second etching step for forming an inter-device separation groove, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. All of the thin-film crystal layers up to the active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, and the undoped GaN buffer layer 22 are made of Cl ₂ gas. ICP etching was used. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method. Next, an insulating layer that simultaneously forms a p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, an n-side current injection region on the n-side contact layer, and a scribe region 14 of the inter-device isolation trench. Then, a resist mask was formed by using a photolithography technique, and then a portion of the insulating layer not covered with the resist mask was removed by using RIE plasma of SF ₆ gas. Here, the periphery of the p-side electrode was covered with a SiN _x insulating layer. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, this element was joined to the metal layer 41 of the submount 40 using metal solder 42 to complete the light emitting element. At this time, an unintended short circuit of the element did not occur.

(Production Example C-6)
A light emitting device was produced in the same manner as in Production Example C-5, except that in Production Example C-5, the configuration of the substrate and the thin film crystal layer was changed as follows.

First, a c + -plane GaN substrate 21 (Si concentration: 1 × 10 ¹⁷ cm ⁻³ ) having a thickness of 330 μm is prepared, and then an undoped GaN having a thickness of 6 μm is first formed at 1040 ° C. as a buffer layer 22 using MOCVD. did.

Next, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 4 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. Si-doped (Si concentration 7 × ¹⁰ 18 ^{cm -3)} of the GaN layer was formed to 0.5μm thick, Si-doped (Si concentration: 5 × ^{10 18} as a further first conductivity type (n-type) first cladding layer 24a as A cm ^-3 ) Al _0.10 Ga _0.90 N layer was formed to a thickness of 0.1 µm.

Further, as the active layer structure 25, an undoped GaN layer formed to 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to 2 nm at 715 ° C. as a quantum well layer, Films were alternately formed so that the total number of layers was 8 and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  Thereafter, a light emitting device was completed in the same manner as in Production Example C-5. At this time, an unintended short circuit or the like of the device did not occur.

In Production Examples C-5 and 6, the second etching step was performed and then the first etching step was performed. However, the first etching step may be performed first, and then the second etching step may be performed. In that case, it is also preferable to perform the second etching step without removing the SiN _x mask used in the first etching step. In addition, when the insulating layer 30 is etched, an appropriate etching mask shape is prepared by photolithography suitable for a predetermined shape, and side etching is performed to manufacture a light-emitting element having the shape of the second aspect. You can also

<< Example of Manufacturing Type D Light-Emitting Element >>
(Production Example D-1)
The light emitting element shown in FIG. 5-15 was manufactured by the following procedure. Refer to FIGS. 5-7 to 12 for related process diagrams.

  A c + -plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer having a low-temperature growth having a thickness of 10 nm is first formed thereon as the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 4 μm was formed at 1040 ° C.

Further, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were formed alternately so that the quantum well layers were 5 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode on the wafer on which the thin-film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode 27 by the lift-off method using a photolithography method. Here, Ni (20 nm thickness) / Au (500 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode. The structure completed through the steps up to here generally corresponds to FIGS. 5-7. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to perform the first etching step, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, the photolithography process was performed again to pattern the SiN _x mask, and an SiN _x etching mask was produced. At this time, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma using the RIE method, and a portion where the thin film crystal layer is not etched in the first etching step described later is left as a mask, and A portion of the SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed to the middle of the n-GaN contact layer 24c through the first cladding layer 24a to expose the n-type contact layer 24c serving as an n-type carrier injection portion.

After completion of the ICP plasma etching, the SiN _x mask was completely removed using buffered hydrofluoric acid. Also here, since Au was exposed on the surface of the p-side electrode, the p-side electrode was not altered at all even by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIGS.

Next, in order to carry out the second etching step for forming the inter-device separation groove 13, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the region for forming the inter-device separation groove was removed, and the inter-device separation groove forming mask for the thin film crystal layer, that is, the second etching step SrF ₂ mask was formed.

Next, as the second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier layer corresponding to the device isolation trenches The active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, and the undoped GaN buffer layer 22 are all made of Cl ₂ gas. ICP etching was performed. During this second etching step, the SrF ₂ mask was hardly etched. The width of the inter-device separation groove 13 was 150 μm, which was the same as the width of the mask.

After forming the inter-device separation groove 13 by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all. The structure completed through the steps up to here generally corresponds to FIGS.

Next, SiO _x and SiN _x were formed in this order on the entire surface of the wafer by the p-CVD method to obtain a dielectric multilayer film. The structure completed through the steps up to here generally corresponds to FIGS.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Ni—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer existing on the side of the substrate 21 on the side wall, a resist mask was formed using a photolithography technique. Next, the portion of the dielectric multilayer film (insulating layer) not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Further, due to the side etching effect using hydrofluoric acid, a part of the dielectric multilayer film (insulating layer) on the side wall of the undoped buffer layer was also removed. Here, the periphery of the p-side electrode 27 is covered with an insulating layer made of SiO _x and SiN _x of 150 μm.

Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. The structure completed through the steps up to here generally corresponds to FIGS.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (300 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by vacuum deposition, and unnecessary portions were removed in acetone by lift-off. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode is formed so that its periphery is in contact with the insulating layer by about 30 μm so that the area thereof is larger than that of the n-side current injection region, and does not overlap with the p-side electrode 27. Flip chip bonding with metal solder is easy, and heat dissipation is considered. In another manufacturing example, the light-emitting element was manufactured so as to be in contact with about 10 μm, and a light-emitting element having the same performance as this manufacturing example was obtained. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process. The structure completed through the steps up to here generally corresponds to FIGS.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (substrate 21) on which the light-emitting element was formed was bonded to this support using AuSn solder. At the time of bonding, the wafer (substrate 21) on which the support 40 and the light emitting elements are formed is heated to 300 ° C., and the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. It was made to be. At this time, an unintended short circuit or the like of the element did not occur at this time.

  Next, in order to perform substrate peeling, a laser beam emitted from a KrF excimer laser (wavelength 248 nm) was irradiated from the surface of the substrate 21 where thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). . Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, a separation region portion in the support and an inter-device separation groove in the wafer were simultaneously cut using a dicing saw. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the compound semiconductor light emitting device shown in FIG. 5-15 was completed.

(Production Example D-2)
In Production Example D-1, the same steps as in Production Examples D-1 and 2 were repeated except that the thin film crystal layer was formed as follows after the buffer layer 22 was formed. That is, after the buffer layer 22 is formed in Production Example D-1, a Si-doped (Si concentration 5 × 10 ¹⁸ cm ⁻³ ) GaN layer is further formed as the first conductivity type (n-type) second cladding layer 24b. A GaN layer of Si doping (Si concentration 8 × 10 ¹⁸ cm ⁻³ ) is formed to a thickness of 0.5 μm as the first conductivity type (n-type) contact layer 24c, and the first conductivity type (n Type) An Al _0.10 Ga _0.90 N layer of Si doping (Si concentration 5.0 × 10 ¹⁸ cm ⁻³ ) was formed to a thickness of 0.1 μm as the first cladding layer 24a. Furthermore, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.1 Ga _{0.9 formed} to a thickness of 2 nm at 720 ° C. as a quantum well layer. N layers were alternately formed so that the quantum well layers were 8 layers in total and both sides were barrier layers. Further, the growth temperature is set to 1025 ° C., and Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.10 Ga _0.90 N is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. Formed to a thickness. Further, Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN was formed to a thickness of 0.07 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN was formed to a thickness of 0.03 μm as the second conductivity type (p-type) contact layer 26c. Thereafter, the light emitting device shown in FIG. 5-15 was completed in the same manner as in Production Example D-1. At this time, an unintended short circuit or the like of the element did not occur.

In the processes of Production Examples D-1 and 2, the SiN _x mask is removed after the first etching step. However, the SiN _x mask may be removed after the second etching step without removing the SiN _x mask.

  Furthermore, in Production Example D-1 and Production Example D-2, the light emitting element shown in FIG. 5-2 can be manufactured by stopping the etching in the second etching step in the middle of the buffer layer (however, The insulating layer is a multilayer dielectric film). For element isolation, the element isolation region in the support may be cut together with the buffer layer at the bottom of the inter-device isolation groove.

Furthermore, in order to manufacture the light emitting element shown in FIG. 5-3A, in Manufacturing Example D-1 and Manufacturing Example D-2, the etching in the second etching step is stopped in the middle of the buffer layer, and further the planned shape by photolithography suitable to prepare the appropriate etching mask shape, and, without advancing the side etching of the insulating layer, for example, as the width of the scribe region becomes 100 [mu] m (L _WS is 50μm in the device after separation) In addition, it can be carried out by forming a scribe region while leaving the insulating layer on the bottom surface of the groove (however, the insulating layer is a multilayer dielectric film).

(Production Example D-3)
The light emitting element shown in FIG. 5-16 was manufactured by the following procedure. A c + plane sapphire substrate 21 having a thickness of 430 μm is prepared, and an undoped GaN layer grown at a low temperature of 20 nm is formed as a first buffer layer 22a on the first buffer layer 22a using the MOCVD method. As the buffer layer 22b, an undoped GaN layer having a thickness of 3 μm was formed at 1040 ° C.

Next, a Si-doped (Si concentration: 1 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 2 μm as the first conductivity type (n-type) second cladding layer 24b, and the first conductivity type (n-type) contact layer 24c is formed. A Si-doped (Si concentration 2 × 10 ¹⁸ cm ⁻³ ) GaN layer is formed to a thickness of 0.5 μm, and Si-doped (Si concentration 1.5 ×) is formed as the first conductivity type (n-type) first cladding layer 24a. A 10 ¹⁸ cm ⁻³ ) Al _0.15 Ga _0.85 N layer was formed to a thickness of 0.1 μm.

Further, as the active layer structure 25, an undoped GaN layer formed to a thickness of 13 nm at 850 ° C. as a barrier layer, and an undoped In _0.13 Ga _0.87 N layer formed to a thickness of 2 nm at 715 ° C. as a quantum well layer, The quantum well layers were alternately formed so that the total number of the quantum well layers was three and both sides were barrier layers.

Further, the growth temperature is set to 1025 ° C., and Mg doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) Al _0.15 Ga _0.85 N layer is 0.1 μm as the second conductivity type (p-type) first cladding layer 26a. The thickness was formed. Further, an Mg-doped (Mg concentration 5 × 10 ¹⁹ cm ⁻³ ) GaN layer was formed to a thickness of 0.05 μm as the second conductivity type (p-type) second cladding layer 26b. Finally, an Mg-doped (Mg concentration 1 × 10 ²⁰ cm ⁻³ ) GaN layer was formed to a thickness of 0.02 μm as the second conductivity type (p-type) contact layer 26c.

  Thereafter, the temperature was gradually lowered in the MOCVD growth furnace, the wafer was taken out, and the thin film crystal growth was completed.

  In order to form the p-side electrode 27 on the wafer on which the thin film crystal growth was completed, a resist pattern was formed by preparing to pattern the p-side electrode by a lift-off method using a photolithography method. Here, Pd (20 nm thickness) / Au (1000 nm thickness) was formed as a p-side electrode by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the p-side electrode 27. In the process up to here, there has been no process in which the p-side current injection region directly under the p-side electrode is damaged by a plasma process or the like.

Next, in order to carry out a second etching step for forming an inter-device separation groove, an SrF ₂ mask was formed on the entire surface of the wafer by using a vacuum deposition method. Next, the SrF ₂ film in the formation region of the inter-device separation groove was removed, and a separation etching mask for the thin film crystal layer, that is, an etching mask for performing the second etching step was formed.

Next, as a second etching step, the p-GaN contact layer 26c, the p-GaN second clad layer 26b, the p-AlGaN first clad layer 26a, the InGaN quantum well layer, and the GaN barrier in portions corresponding to the inter-device isolation trenches. All of the thin-film crystal layers up to the active layer structure 25, the n-AlGaN first clad layer 24a, the n-GaN contact layer 24c, the n-GaN second clad layer 24b, and the undoped GaN buffer layer 22 are made of Cl ₂ gas. ICP etching was used. During the second etching step, the SrF ₂ mask was hardly etched.

After forming the inter-device separation groove by the second etching process, the unnecessary SrF ₂ mask was removed. Also here, since the Au was exposed on the surface of the p-side electrode, it was not altered at all.

Next, in order to perform a first etching step of exposing the first conductivity type contact layer as a preparation for forming the first conductivity type side electrode, an etching mask was formed. Here, 0.4 μm thick SiN _x was deposited on the entire surface of the wafer at a substrate temperature of 400 ° C. using the p-CVD method. Here, since Au was exposed on the surface of the p-side electrode, it was not altered at all by the SiN _x film forming process by p-CVD. Next, a photolithography process was performed again to pattern the SiN _x layer, and a SiN _x etching mask was produced. In this case, etching of the unnecessary portion of the SiN _x film is performed using SF ₆ plasma by using the RIE method, and a portion where the thin film crystal layer is not etched is left in the first etching step to be described later, and is scheduled. The SiN _x film corresponding to the etched portion of the thin film crystal layer was removed.

Next, as a first etching step, a p-GaN contact layer 26c, a p-GaN second cladding layer 26b, a p-AlGaN first cladding layer 26a, an active layer structure 25 comprising an InGaN quantum well layer and a GaN barrier layer, n-AlGaN ICP plasma etching using Cl ₂ gas was performed through the first cladding layer 24a and halfway through the n-GaN contact layer 24c to expose the n-type contact layer serving as an n-type carrier injection portion.

After the completion of the ICP plasma etching, the SiN _x mask was completely removed by the RIE method using SF ₆ gas. Again, since Au was exposed on the p-side electrode surface, this process did not alter it at all.

Next, SiN _x having a thickness of 125 nm was formed on the entire surface of the wafer as the insulating layer 30 by the p-CVD method.

Next, formation of a p-side electrode exposed portion on the p-side electrode 27 made of Pd—Au, formation of an n-side current injection region (36) on the n-side contact layer 24c, and an undoped buffer layer in the inter-device isolation trench In order to simultaneously remove the insulating layer present on the substrate side portion of the sidewall, a resist mask was formed by using a photolithography technique. Next, the portion of the insulating layer not covered with the resist mask with a hydrofluoric acid-based etchant was removed. Further, the insulating layer on the substrate side portion of the side wall of the undoped buffer layer was also removed by the side etching effect using hydrofluoric acid. Here, the periphery of the p-side electrode 27 is covered with an SiN _x insulating layer of 150 μm. In addition, the sidewall of the thin film crystal layer is covered with the insulating layer except for the n-side current injection region.

  Thereafter, the resist mask that was no longer needed was removed with acetone, and was removed by ashing with oxygen plasma by the RIE method. Also at this time, since Au was exposed on the surface of the p-side electrode, no alteration occurred.

  Next, in order to form the n-side electrode 28, a resist pattern was formed in preparation for patterning the n-side electrode by a lift-off method using a photolithography method. Here, Ti (20 nm thickness) / Al (1500 nm thickness) as an n-side electrode was formed on the entire surface of the wafer by a vacuum deposition method, and unnecessary portions were removed in acetone by a lift-off method. Subsequently, heat treatment was then performed to complete the n-side electrode. The n-side electrode has an area larger than that of the n-side current injection region and does not overlap with the p-side electrode, so that flip chip bonding with metal solder is easy and heat dissipation is also achieved. Considered. The Al electrode is easily altered by a plasma process or the like, and is etched by hydrofluoric acid or the like, but was not damaged at all because the n-side electrode was formed at the end of the device fabrication process.

  Next, as a preparation for carrying out substrate peeling, an AlN substrate having a Ti / Pt / Au laminated metal wiring (metal layer 41) on the surface was prepared as a support 40. The entire wafer (substrate 21) on which the light-emitting element was formed was bonded to this support using AuSn solder. At the time of bonding, the wafer (substrate 21) on which the support 40 and the light emitting elements are formed is heated to 300 ° C., and the p-side electrode and the n-side electrode are fused to the designed metal wiring on the support by AuSn solder. It was made to be. At this time, an unintended short circuit of the element did not occur.

  Next, in order to perform substrate peeling, laser light emitted from a KrF excimer laser (248 nm) was irradiated from the surface of the substrate 21 on which thin film crystal growth was not performed, and the substrate was peeled off (laser debonding). Thereafter, Ga metal generated by part of the GaN buffer layer being decomposed into nitrogen and metal Ga was removed by wet etching.

  Finally, in order to divide each light emitting element one by one, a dicing saw was used to simultaneously cut the support body separation region and the inter-device separation groove in the wafer. Here, since there was no metal wiring or the like in the element isolation region in the support body, unintentional peeling of the wiring did not occur. Thus, the compound semiconductor light emitting device shown in FIG. 5-16 was completed.

<< Production Example of Light Extraction Material >>
<Production Example 5-1>
According to the synthesis method described in Example 1-1 of WO2006 / 303328, 698.3 g of both-end silanol dimethyl silicone oil XC96-723 (oligomer) manufactured by Momentive Performance Materials Japan GK and phenyltrimethoxysilane 69. 8 g, 153.4 g of 5 wt% aluminum acetylacetone salt methanol solution as a catalyst, and 18.3 g of water were weighed in three locorbenes equipped with a stirring blade and a condenser, and stirred at room temperature for 15 minutes under atmospheric pressure. After the initial hydrolysis, the mixture was refluxed with stirring at about 75 ° C. for 4 hours.

  Thereafter, methanol and low boiling silicon components were distilled off until the internal temperature reached 100 ° C., and the mixture was further refluxed with stirring at 100 ° C. for 4 hours. The reaction solution was cooled to room temperature, and a hydrolysis / polycondensation solution was prepared. The hydrolysis rate of this liquid is 192% with respect to phenyltrimethoxysilane. The raw material XC96-723 corresponds to a 200% hydrolyzed product.

  In order to confirm the physical properties of the light extraction material, 3 g of the thus obtained hydrolysis / polycondensation liquid was placed in a Teflon (registered trademark) petri dish with a diameter of 5 cm, and kept in an explosion-proof furnace at 50 ° C. for 30 minutes. The first drying was performed, followed by holding at 120 ° C. for 1 hour, followed by holding at 150 ° C. for 3 hours for the second drying, and an independent circular transparent elastomeric film having a thickness of about 0.5 mm was obtained. It was. Using this as a sample, solid Si-NMR spectrum measurement, silanol content calculation, hardness measurement, ultraviolet light resistance test, heat resistance test (transmittance), and silicon content measurement were performed. Furthermore, a reflow resistance test and a refractive index measurement were performed using the hydrolysis / polycondensation solution.

  These test conditions are shown below.

(Solid Si-NR spectrum measurement)
As described above.

(Calculation of silanol content)
As described above.

(hardness)
The hardness (Shore A) was measured according to JIS K6253 using an A type (durometer type A) rubber hardness meter manufactured by Furusato Seiki Seisakusho.

(Ultraviolet light resistance test)
The ultraviolet light resistance test was performed by irradiating the sample with ultraviolet light under the following conditions and comparing the state of the sample before and after irradiation.

Ultraviolet light irradiation conditions: A mercury Xenon lamp UV irradiation device Aicure (registered trademark) SPOT TYPE ANUP5203 (output at the optical fiber light exit surface: 28000 W / m ² ) manufactured by Matsushita Electric Works was used in combination with a UV cut filter having a wavelength of 385 nm or less. Ultraviolet light was irradiated for 24 hours with no gap between the irradiation fiber tip and the UV cut filter and between the UV cut filter and the sample. It was 4500 W / m < ² > when the illumination intensity of the light irradiated to the irradiated surface was measured with the 436 nm light receiving element illuminometer UVD-436PD (sensitivity wavelength range: 360 nm-500 nm) by the Ushio Electric company.

(Heat resistance test)
The sample was held for 500 hours in a ventilation dryer at a temperature of 200 ° C., and the transmittance of light having a wavelength of 400 nm before and after the holding was compared.

(Silicon content)
As described above.

(Reflow resistance test)
The reflow resistance test was performed according to the following procedure.

  (1) The above hydrolysis / polycondensation liquid is dropped into a copper cup having a diameter of 9 mm and a depth of 1 mm, the surface of which is Ag-plated, and cured under predetermined curing conditions to prepare 10 samples for a reflow resistance test. Individually produced.

  (2) Longitudinal length × horizontal length × thickness = 25 mm × 70 mm × 1 mm of aluminum sheet for heat dissipation is thinly applied, and the sample is arranged on top of it and the atmosphere is 85 ° C. and humidity is 85% (hereinafter referred to as “hygroscopic environment”) And soaked for 1 hour.

  (3) The moisture-absorbed sample was taken out from the hygroscopic environment and cooled to room temperature (20 ° C. to 25 ° C.). The cooled sample was placed together with the aluminum plate on a relieved plate set at 260 ° C. and held for 1 minute. Under this condition, the temperature of the sample reached 260 ° C. in about 50 seconds, and then this temperature was maintained for 10 seconds.

  (4) The heated sample was placed together with the aluminum plate on a stainless steel cooling plate at room temperature and cooled to room temperature. The presence or absence of peeling of the sample from the copper cup was observed visually and under a microscope. Even if slight peeling is observed, it is considered as “with peeling”.

  (5) Peeling was observed for all samples, and the peeling rate was determined. The peeling rate is calculated by “number of peeled samples / total number of samples”.

(Measurement of refractive index)
The refractive index of the light extraction material can be measured using a known method such as a Pulrich refractometer, an Abbe refractometer, a prism coupler method, an interferometry, and a minimum deflection method in addition to the immersion method (solid object). . Since the refractive index of the light extraction material according to this production example and the production example described below does not change before and after curing, the refractive index was measured with an Abbe refractometer (sodium D line (589 nm)) in a liquid state of the light preparation.

  The measurement results and test results are shown below.

  (A) The peak top position is in the region where the chemical shift is −40 ppm or more and 0 ppm or less with respect to the silicone rubber, and the peak half-value width is 0.3 ppm or more and 3.0 ppm or less: two or more peaks.

  (B) The peak top position is in a region where the chemical shift is -80 ppm or more and less than -40 ppm with respect to the silicone rubber, and the peak half-value width is 0.3 ppm or more and 5.0 ppm or less: two or more peaks.

Silanol content (% by weight): 0.30
Hardness (Shore A): 27
Ultraviolet light resistance test (72 hours): No change Heat resistance test (200 ° C.): No change Reflow resistance test: No peeling off (peeling rate = 0%)
Silicon content (% by weight): 38
Refractive index: 1.42

<Production Example 5-2>
140 g of Silanol Dimethyl Silicone Oil XC96-723 of both ends made by Momentive Performance Materials Japan G.K., 14 g of phenyltrimethoxysilane, and 0.308 g of zirconium tetraacetylacetonate powder as a catalyst were prepared. The mixture was weighed in a three-necked Kolben fitted with a condenser and stirred at room temperature for 15 minutes until the catalyst was sufficiently dissolved. Thereafter, the temperature of the reaction solution was raised to 120 ° C., and initial hydrolysis was carried out with stirring at 120 ° C. for 30 minutes under total reflux.

Subsequently, nitrogen was blown in with SV20 and stirred at 120 ° C. while distilling off the generated methanol, moisture and by-product low boiling silicon components, and the polymerization reaction was further advanced for 6 hours. Here, “SV” is an abbreviation for “Space Velocity” and refers to the volume of blown volume per unit time. Therefore, SV20 refers to blowing N ₂ in a volume 20 times that of the reaction liquid in one hour.

  After stopping the blowing of nitrogen and cooling the reaction solution to room temperature, the reaction solution was transferred to an eggplant-shaped flask, and methanol and moisture remaining in a minute amount at 120 ° C. and 1 kPa on an oil bath using a rotary evaporator, The low boiling silicon component was distilled off to obtain a solvent-free hydrolysis / polycondensation liquid.

  In order to confirm the physical properties of the light extraction material, 2 g of the hydrolysis / polycondensation liquid obtained as described above was placed in a Teflon (registered trademark) petri dish having a diameter of 5 cm, and 1 ° C. at 110 ° C. in an explosion-proof furnace. When held for 3 hours and then at 150 ° C. for 3 hours, an independent circular transparent elastomeric membrane having a thickness of about 1 mm was obtained. Using this, solid Si-NMR spectrum measurement, silanol content calculation, hardness measurement, ultraviolet light resistance test, heat resistance test, and silicon content measurement were performed under the same conditions as in Production Example 5-1. Furthermore, using the hydrolysis / polycondensation solution, a reflow resistance test and a refractive index measurement were performed under the same conditions as in Production Example 5-1. The results are as follows.

  (A) The peak top position is in the region where the chemical shift is −40 ppm or more and 0 ppm or less with respect to the silicone rubber, and the peak half-value width is 0.3 ppm or more and 3.0 ppm or less: two or more peaks.

  (B) The peak top position is in a region where the chemical shift is -80 ppm or more and less than -40 ppm with respect to the silicone rubber, and the peak half-value width is 0.3 ppm or more and 5.0 ppm or less: two or more peaks.

Silanol content (% by weight): 0.10
Hardness (Shore A): 33
UV light resistance test (24 hours): No change Heat resistance test (200 ° C): No change Reflow resistance test: No peeling off (peeling rate = 0%)
Silicon content (% by weight): 38
Refractive index: 1.42

<Production Example 5-3>
Momentive Performance Materials Japan G.K., both ends silanol dimethyl silicone oil XC96-723 70g, both ends silanol methyl phenyl silicone oil YF3804 70g, phenyltrimethoxysilane 14g, and zirconium tetraacetylacetonate powder as catalyst 0.308 g was prepared and weighed into a three-necked Kolben equipped with a stirring blade and a condenser, and stirred at room temperature for 15 minutes until the catalyst was sufficiently dissolved. Thereafter, the temperature of the reaction solution was raised to 120 ° C., and initial hydrolysis was performed while stirring at 120 ° C. under total reflux for 2 hours. Thereafter, the polymerization reaction and the low boiling silicon component were distilled off under the same conditions as in Production Example 5-2 to obtain a solvent-free hydrolysis / polycondensation liquid.

  In order to confirm the physical properties of the light extraction material, an elastomeric film was prepared from the obtained hydrolysis / polycondensation liquid under the same conditions as in Production Example 5-2, and the elastomeric film and the hydrolysis / polycondensation film were used. In the same manner as in Production Example 5-1, various physical properties were measured and tested. The results are as follows.

  (A) The peak top position is in the region where the chemical shift is −40 ppm or more and 0 ppm or less with respect to the silicone rubber, and the peak half-value width is 0.3 ppm or more and 3.0 ppm or less: two or more peaks.

  (B) The peak top position is in a region where the chemical shift is -80 ppm or more and less than -40 ppm with respect to the silicone rubber, and the peak half-value width is 0.3 ppm or more and 5.0 ppm or less: two or more peaks.

Silanol content (wt%): 0.6
Hardness (Shore A): 20
UV light resistance test (24 hours): No change Heat resistance test (200 ° C): No change Reflow resistance test: No peeling off (peeling rate = 0%)
Silicon content (% by weight): 31
Refractive index: 1.47

<Example 1>
Prepared as a main support, on a mounting part with a reflector as shown in FIG. 11A having a plane size of 10 mm × 10 mm and a thickness of 0.3 mm (wiring formed on an insulating substrate), The light emitting element manufactured in Production Example A-1 was mounted by flip chip bonding. The light-emitting elements have a planar size of 1 mm × 1 mm, and a total of 81 light-emitting elements are mounted in a 9 × 9 two-dimensional matrix form on the mounting component. The interval between adjacent light emitting elements was set to 100 μm. The electrical connection between the light-emitting elements was performed by connecting nine elements arranged in a row in series and connecting the columns in parallel.

  A current of 180 mA was passed through the integrated light source obtained at this stage to cause the integrated light source to emit light. The driving voltage at this time was 28.9V. The total radiant flux of light emitted from the integrated light source was 1155 mW.

  Further, 79 microliters of pre-curing light extraction material was dropped with a micropipette from the mount component onto the integrated light source obtained so far, and the light emitting element was covered. As the light extraction material before curing, the hydrolysis / polycondensation liquid obtained in Production Example 5-1 was used. The hydrolysis / polycondensation liquid filled the gaps between the light emitting elements and between the light emitting elements, and covered the surface on the first light extraction direction side in a wet state. By drying this, the hydrolysis / polycondensation liquid was cured, and an integrated light source as shown in FIG. 11A in which the light extraction material on the transparent elastomer without cracks adhered to the light emitting element was obtained.

  A current of 180 mA was passed through the obtained integrated light source to cause the integrated light source to emit light. The driving voltage at this time was 28.6V. The total radiant flux of light emitted from the integrated light source was 1653 mW, and the total radiant flux was improved by about 43% compared to before the light extraction material was attached to the light emitting element. This shows that the light extraction efficiency is improved by attaching the light extraction material to the light emitting element. Further, light emission from the integrated light source was uniform.

<Example 2>
An integrated light source was produced in the same manner as in Example 1 except that the hydrolysis / polycondensation liquid obtained in Production Example 5-3 was used as a light extraction material before curing. By drying the hydrolysis / polycondensation liquid, the hydrolysis / polycondensation liquid was cured, and an integrated light emitting source in which the light extraction material on the transparent elastomer without cracks adhered to the light emitting element was obtained.

  A current of 180 mA was passed through the obtained integrated light source to cause the integrated light source to emit light. The driving voltage at this time was 28.4V. The total radiant flux of light emitted from the integrated light source was 1733 mW, and the total radiant flux was improved by about 50% in Example 1 compared to before the light extraction material was attached to the light emitting element. This shows that the light extraction efficiency is further improved by using a light extraction material having a high refractive index. Further, light emission from the integrated light source was uniform.

It is a figure which shows an example of the light emitting element of the 1st aspect of the type A which can be used by this invention. It is a figure which abbreviate | omits one part structure and shows the light emitting element shown to FIGS. 1-1A. It is a figure which shows an example of the light emitting element of the 1st aspect of type A. It is a figure which shows an example of the light emitting element of the 1st aspect of type A. It is a figure which shows an example of the light emitting element of the 2nd aspect of type A. It is a figure which abbreviate | omits one part structure and shows the light emitting element shown to FIGS. 1-2A. It is a figure which shows an example of the light emitting element of the 2nd aspect of type A. It is a figure which shows an example of the light emitting element of the 2nd aspect of type A. It is a figure which shows an example of the light emitting element of the 2nd aspect of type A. It is a figure which shows the structure before completion of one example of the light emitting element of the 1st aspect of type A. It is a figure which shows the structure before completion of one example of the light emitting element of the 2nd aspect of Type A. It is a figure which shows typically the active layer structure disclosed by the type A. It is process sectional drawing explaining an example of the manufacturing method of a type A light emitting element. It is process sectional drawing explaining an example of the manufacturing method of a type A light emitting element. It is process sectional drawing explaining an example of the manufacturing method of a type A light emitting element. It is process sectional drawing explaining an example of the manufacturing method of a type A light emitting element. It is process sectional drawing explaining one example (1st aspect) of the manufacturing method of a type A light emitting element. It is process sectional drawing explaining one example (2nd aspect) of the manufacturing method of the light emitting element of a type A. It is process sectional drawing explaining an example of the manufacturing method of a type A light emitting element. It is a figure which shows the light emitting element of the type A manufactured by manufacture example A-1 and 3. FIG. It is a figure which shows the light emitting element of the type A manufactured by manufacture example A-5, 6. FIG. It is a figure which shows the light emitting element of the type A manufactured by manufacture example A-2 and 4. It is process sectional drawing explaining one Embodiment of the manufacturing method of the light emitting element of a type A. It is a figure which shows the example of the light emitting element of the 1st aspect of the type B which can be used by this invention. It is a figure which abbreviate | omits the structure of the light emitting element shown to FIGS. 2-1A, and abbreviate | omits it. It is a figure which shows the example of the light emitting element of the 1st aspect of a type B. It is a figure which abbreviate | omits the structure of the light emitting element shown to FIGS. 2-2A, and abbreviate | omits it. It is a figure which shows the example of the light emitting element of the 1st aspect of a type B. It is a figure which shows the example of the light emitting element of the 2nd aspect of Type B. It is a figure for showing the positional relationship of the light emitting element of the 2nd aspect of Type B. It is a figure which shows the example of the light emitting element of the 2nd aspect of Type B. It is a figure which shows one example of the structure before completion of the light emitting element of the 1st aspect of a type B. It is a figure which shows an example of the structure before completion of the light emitting element of the 2nd aspect of a type B. It is a figure which shows an example of the structure before completion of the light emitting element of the 2nd aspect of a type B. It is a figure for demonstrating the width | variety of the area | region where a metal wiring does not exist in one form of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type B. It is process sectional drawing explaining an example of the manufacturing method disclosed by Part B. It is a figure which shows the light emitting element of the type B manufactured by manufacture example B-1. It is a figure which shows the light emitting element of the type B manufactured by manufacture example B-3. It is process sectional drawing explaining one Embodiment of the manufacturing method of the light emitting element of a type B. It is a flowchart which shows the process order of the manufacturing method of the light emitting element of type A and type B. It is a figure which shows an example of the light emitting element of the 1st aspect of the type C which can be used by this invention. It is a figure which abbreviate | omits one part structure and shows the light emitting element shown to FIGS. 4-1A. It is a figure which shows one example of the light emitting element of the 1st aspect of type C. It is a figure which shows an example of the light emitting element of the 2nd aspect of Type C. It is a figure which abbreviate | omits the structure of the light emitting element shown to FIGS. 4-2A, and abbreviate | omits it. It is a figure which shows an example of the light emitting element of the 2nd aspect of Type C. It is a figure which shows the structure before completion of one example of the light emitting element of the 1st aspect of type C. It is a figure which shows the structure before completion of one example of the light emitting element of the 2nd aspect of Type C. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type C. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type C. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type C. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type C. It is process sectional drawing explaining one example (1st aspect) of the manufacturing method of the light emitting element of a type C. It is process sectional drawing explaining one example (2nd aspect) of the manufacturing method of the light emitting element of a type C. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type C. It is a figure which shows the light emitting element of the type C manufactured by manufacture example C-1 and 3. FIG. It is a figure which shows the light emitting element of the type C manufactured by manufacture example C-5, 6. FIG. It is a figure which shows the light emitting element of the type C manufactured by manufacture example C-2 and 4. It is process sectional drawing explaining one Embodiment of the manufacturing method of the light emitting element of type PA C. It is a figure which shows the example of the light emitting element of the 1st aspect of the type D which can be used by this invention. It is a figure which abbreviate | omits one part structure and shows the light emitting element shown to FIGS. 5-1A. It is a figure which shows the example of the light emitting element of the 1st aspect of type D. It is a figure which shows the example of the light emitting element of the 2nd aspect of Type D. It is a figure which abbreviate | omits one part structure and shows the light emitting element shown to FIGS. 5-3A. It is a figure which shows one example of the structure before completion of the light emitting element of the 1st aspect of a type D. FIG. It is a figure which shows one example of the structure before completion of the light emitting element of the 2nd aspect of a type D. FIG. It is a figure for demonstrating the width | variety of the area | region where a metal wiring does not exist in one form of the light emitting element of a type D. FIG. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is process sectional drawing explaining an example of the manufacturing method of the light emitting element of a type D. It is a figure which shows the light emitting element of the type D manufactured by manufacture example D-1. It is a figure which shows the light emitting element of the type D manufactured by manufacture example D-3. It is process sectional drawing explaining one Embodiment of the manufacturing method of the light emitting element of a type D. It is a flowchart which shows the process order of the manufacturing method of the light emitting element of type C and type D. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows one form of adhesion of the light extraction material in an integrated light source. It is a figure which shows an example of an integrated light source. It is a figure which shows an example of an integrated light source. It is a figure which shows an example of an integrated light source. It is a figure which shows an example of an integrated light source. It is a figure which shows an example of an integrated light source. It is a figure which shows one example of the manufacturing method of an integrated light source. It is a figure which shows one example of the manufacturing method of an integrated light source.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Light emitting element 13 Inter-device isolation groove 14 Scribe area | region 15 Insulation layer non-formation area | region 21 Substrate 22 Buffer layer 22a 1st buffer layer 22b 2nd buffer layer 23 Light equalization layer 24 1st conductivity type clad layer 24a 1st conductivity Type first cladding layer 24b first conductivity type second cladding layer 24c first conductivity type (n-type) contact layer 25 active layer structure 26 second conductivity type cladding layer 26a second conductivity type first cladding layer 26b second conductivity type Second clad layer 26c Second conductivity type (p-type) contact layer 27 Second conductivity type side electrode 28 First conductivity type side electrode 30 Insulating layer 35 Second current injection region 36 First current injection region 37 Second conductivity type side exposed surface 40 submount 41 metal layer 42 a metal solder 45 low-reflection optical film 50a light extracting surface 50b light extracting surface 51 first etch mask electrode (SiN _x )
52 Second etching mask (metal fluoride mask)
55 End step surface 90 Gap 110 Light extraction material 105 Mount component 120 Liquid stop
121 Potting container 200 Integrated light source

Claims (22)

A main support, a plurality of light-emitting elements defined on the following (A) arranged on the main support, and a material that is in close contact with and adheres to the light-emitting device and is transparent at an emission wavelength An integrated light source having a light extraction material.
(A):
A compound semiconductor thin film having a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer on a substrate transparent to the emission wavelength A compound semiconductor light emitting device having a crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenization layer for improving uniformity of light emitted from the surface on the first light extraction direction side between the substrate and the first conductivity type semiconductor layer, and optionally, the substrate and light homogenization as an arbitrary configuration Having a buffer layer between the layers;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which part of the light homogenization layer forms a receding side wall surface and an end step surface is formed between the light homogenization layer and a non-retreating side wall surface that does not recede, or (Ii) A shape in which a part of the light uniformizing layer and the buffer layer both constitute a receding side wall surface and an end step surface is formed between the buffer layer and the non-backed side wall surface that has not receded. Or (iii) a shape in which both the light homogenizing layer and the buffer layer are all receded and the exposed portion of the substrate forms an end step surface,
Having any of the following shapes;
2. The integrated light source according to claim 1, wherein the insulating film covers a surface on an end step surface from a position remote from the light emitting element end and a surface that coincides with a receding side wall surface of the first conductive type semiconductor layer. . The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which a part of the light homogenizing layer forms a receding side wall surface and an end step surface is formed between the light homogenizing layer and a non-retreating side wall surface that is not receded, or (Ii) A shape in which a part of the light uniformizing layer and the buffer layer constitutes a receding side wall surface, and an end step surface is formed between the buffer layer and the non-backed side wall surface that has not receded. Or (iii) the light homogenizing layer and the buffer layer are all retreated, and the portion where the substrate is exposed has any shape of an end step surface;
2. The integrated light source according to claim 1, wherein the insulating film covers at least a part of the receding side wall surfaces of the light homogenizing layer and the buffer layer, but is not formed on the end step surface. The light emitting element is
The integrated light emission according to any one of claims 1 to 3, wherein the light homogenizing layer is a layer provided between the substrate and the first conductivity type cladding layer as a part of the thin film crystal layer. source. A main support, a plurality of light emitting elements defined on the following (B) arranged on the main support, and a material transparent to the light emission wavelength that is in close contact with the light emitting device. An integrated light source having a light extraction material.
(B):
A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
A light homogenizing layer between the buffer layer and the first conductivity type semiconductor layer for improving uniformity of light emitted from the surface on the first light extraction direction side;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. And having an insulating layer formed at a position away from the light emitting element end, or (ii) the light uniform When the buffer layer and the buffer layer both form a receding side wall surface and have no end step surface, the buffer layer is not formed at least on the first light extraction direction side portion of the buffer layer. Having an insulating layer covering the receding sidewall surface from the middle or from the middle of the light homogenizing layer;
The compound semiconductor light-emitting element further comprising a support body to which the first conductivity-type side electrode and the second conductivity-type side electrode are connected to support the light-emitting element. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(Ii) The light homogenizing layer and the buffer layer both form a receding side wall surface and have no end step surface,
6. The insulating layer which covers the receding side wall surface from the middle of the buffer layer or from the middle of the light homogenizing layer without being formed at least in the first light extraction direction side portion of the buffer layer. The integrated light source as described. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I): A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer recedes. It is a shape that forms an end step surface with the non-retreating side wall surface that is not, and at least an insulating layer formed from a position away from the light emitting element end,
6. The integrated light source according to claim 5, wherein the insulating film covers at least part of the receding side wall surfaces of the light homogenizing layer and the buffer layer, but is not formed on the end step surface. . The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I): A part of the light homogenization layer, or all of the light homogenization layer and a part of the buffer layer together constitute a receding side wall surface, and the light homogenization layer or the buffer layer It is a shape that forms an end step surface between the non-retreated non-retreated side wall surface, and at least an insulating layer formed from a position away from the light emitting element end,
The integrated light source according to claim 5, wherein the insulating film covers a surface on the end step surface from a position away from the light emitting element end, and a surface coinciding with a side wall receding surface of the first conductivity type semiconductor layer. . A main support, a plurality of light-emitting elements defined on the following (C), arranged on the main support, and a material transparent to the light emission wavelength, which is in close contact with the light-emitting device. An integrated light source having a light extraction material.
(C):
On the substrate transparent to the emission wavelength, the first conductive type semiconductor layer including the buffer layer, the first conductive type cladding layer, the active layer structure, and the second conductive type semiconductor layer including the second conductive type cladding layer are provided. A compound semiconductor light emitting device having a compound semiconductor thin film crystal layer, a second conductivity type side electrode, and a first conductivity type side electrode, wherein the first light extraction direction is the substrate side,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
At the edge of the light emitting element, at least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the side wall surfaces of the thin film crystal layer are set back from the edge of the substrate. Forming;
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode A part of the second conductivity type side electrode that is in contact with a part on the direction side and covers a part of the second conductivity type side electrode opposite to the first light extraction direction; A compound semiconductor light emitting device comprising an insulating layer. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which a part of the buffer layer forms a receding side wall surface, and an end step surface is formed between the buffer layer and a non-backed side wall surface that is not receded, or (ii) A shape in which the buffer layer is all receded and the exposed portion of the substrate forms an end step surface,
Having any of the following shapes;
10. The integrated light source according to claim 9, wherein the insulating film covers a surface on an end step surface from a position remote from the light emitting element end and a surface that coincides with a receding side wall surface of the first conductive type semiconductor layer. . The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I) A shape in which part of the buffer layer forms a receding side wall surface and an end step surface is formed between the buffer layer and the non-backed side wall surface that is not receded, or (ii) All of the buffer layers recede, and the exposed portion of the substrate has any shape that forms an end step surface;
The integrated light source according to claim 9, wherein the insulating film covers at least a part of the receding side wall surface of the buffer layer but is not formed on the end step surface. A main support, a plurality of light emitting elements defined on the following (D) arranged on the main support, and a material that is in close contact with and adheres to the light emitting device and is transparent at an emission wavelength. An integrated light source having a light extraction material.
(D):
A compound semiconductor thin film crystal layer having a buffer layer, a first conductivity type semiconductor layer including a first conductivity type cladding layer, an active layer structure, and a second conductivity type semiconductor layer including a second conductivity type cladding layer in this order; A compound semiconductor light-emitting element having a two-conductivity-type side electrode and a first-conductivity-type side electrode, wherein the first light extraction direction is the buffer layer side when viewed from the active layer structure,
The first conductivity type side electrode and the second conductivity type side electrode do not overlap each other spatially and are formed on the opposite side to the first light extraction direction;
The first conductivity type side electrode and the second conductivity type side electrode are connected and have a support for supporting the light emitting element;
At least the first conductive semiconductor layer, the active layer structure, and the second conductive semiconductor layer among the sidewall surfaces of the thin film crystal layer at the edge of the light emitting element are formed by forming an inter-device separation groove during the manufacturing process. Constitutes the receding side wall surface,
An insulating layer covering at least the first conductive type semiconductor layer, the active layer structure, and the receding side wall surface of the second conductive type semiconductor layer, and (a) a first light extraction of the first conductive type side electrode In contact with a part on the direction side, covering a part on the opposite side to the first light extraction direction of the second conductivity type side electrode, and (b): against the receding side wall surface of the thin film crystal layer,
(I) When a part of the buffer layer constitutes a receding side wall surface and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that has not receded, At least an insulating layer formed from a position away from the end of the light emitting element, or (ii) when the buffer layer forms a receding side wall surface and does not have an end step surface, the buffer A compound semiconductor light emitting device comprising: an insulating layer which covers the receding side wall surface from the middle of the buffer layer without being formed at least in a first light extraction direction side portion of the layer. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(Ii) The buffer layers together form a receding side wall surface and there is no end step surface,
13. The integrated light source according to claim 12, further comprising an insulating layer that covers the receding side wall surface from the middle of the buffer layer without being formed at least in the first light extraction direction side portion of the buffer layer. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
The integrated light source according to claim 12, wherein the insulating film covers at least a part of the receding side wall surface of the buffer layer but is not formed on the end step surface. The light emitting element is
For the receding sidewall surface of the thin film crystal layer,
(I) A part of the buffer layer forms a receding side wall surface, and has a shape that forms an end step surface between the buffer layer and the non-backed side wall surface that does not recede, An insulating layer formed from a position away from the light emitting element end,
The integrated light source according to claim 12, wherein the insulating film covers a surface on an end step surface from a position away from an end of the light emitting element and a surface coinciding with a side wall receding surface of the first conductivity type semiconductor layer. . The light extraction material is attached in the following form: (i) The form attached to the surface of the light emitting element on the first light extraction direction side;
(Ii) a form covering the whole of the light emitting element;
(Iii) A form in which the space between the light emitting elements is filled;
(Iv) a form covering a plurality of light emitting elements; and (v) a form covering all the light emitting elements;
The integrated light source according to claim 1, wherein the integrated light source is attached to the light emitting element so as to satisfy at least one of the following forms.   The integrated light source according to claim 1, wherein the light extraction material contains a silicon-containing compound.   18. The integrated light source according to claim 17, wherein the silicon-containing compound is a condensation type silicone material. The condensed silicone material has the following conditions (1) to (3):
(1) The silicon content is 20% by weight or more;
(2) In a solid Si-nuclear magnetic resonance (NMR) spectrum, it has at least one peak derived from Si in the following (a) and / or (b);
(A) The peak top position is in the region of chemical shift −40 ppm or more and 0 ppm or less with respect to the silicone rubber, and the peak half width is 0.3 ppm or more and 3.0 ppm or less. (B) The peak top position. In the region where the chemical shift is −80 ppm or more and less than −40 ppm based on the silicone rubber, and the peak half-value width is 0.3 ppm or more and 5.0 ppm or less (3) Silanol content is 0.01% by weight or more, Up to 10% by weight;
19. The integrated light source according to claim 18, wherein at least one of the following is satisfied. A light emitting device defined by (A) in claim 1, a light emitting device defined by (B) in claim 5, a light emitting device defined by (C) in claim 9, and (D) in claim 12 A step of producing a plurality of light-emitting elements selected from the group consisting of light-emitting elements defined by:
Arranging the plurality of light emitting elements on a main support;
A step of closely attaching a light extraction material made of a material transparent to the light emission wavelength of the light emitting element to the plurality of light emitting elements arranged on the main support; and
A method for manufacturing an integrated light source comprising: The step of attaching the light extraction material comprises:
(I) a form attached to a surface on the first light extraction direction side of the light emitting element;
(Ii) a form covering the whole of the light emitting element;
(Iii) A form in which the space between the light emitting elements is filled;
(Iv) a form covering a plurality of light emitting elements; and (v) a form covering all the light emitting elements;
21. The method of manufacturing an integrated light source according to claim 20, further comprising attaching the light extraction material to the light emitting element so as to satisfy at least one form of the above. The step of attaching the light extraction material comprises:
Attaching a liquid silicone material to the light emitting element;
Curing the adhered silicone material;
The manufacturing method of the integrated light source of Claim 20 or 21 containing these.

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