JP2009100305A - Method and apparatus for slot id identification of card in transmission device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus and a method capable of identifying a Slot ID in at least ternary manner without using an analog-to-digital converter (ADC). <P>SOLUTION: An identification signal (digital pulse signal) of a predetermined pattern is applied to a slot ID input terminal (Slot ID_I) of a detection circuit (13) which identifies a slot ID corresponding to mount position information of a card mounted in a device, and the detection circuit (13) detects the slot ID inputted from a back wired board (BWB) (11) of the device to the slot ID input terminal (Slot ID_I) in at least ternary manner. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to slot ID identification technology, and more particularly to a card slot ID identification method, circuit, and apparatus in a transmission apparatus.

  In recent years, as the transmission signal has a large capacity, the mounting density in the card accommodated in the transmission device has become higher, and the types of cards in the transmission device have become more diverse. Therefore, there are cases where many slot IDs (Slot IDs) are required when the mounting density of the cards is severe or for identifying the cards.

  FIG. 6 is a perspective view schematically showing a card mounted in the transmission apparatus. As illustrated in FIG. 6, the slot ID (mounting position information) in the transmission apparatus 10 is identified by binary values “0” and “1” using a signal from a BWB (Back Wired Board) 11. In FIG. 6, the slot IDs of the five types of cards 12 connected to the BWB 11 are identified by 3 bits. In the circuit for identifying the slot ID in the five cards 12, “1” and “0” are set according to the signal potential of each bit of the 3-bit slot ID, and “000”, “001”, and “010”, respectively. , “011”, “100” are detected.

  FIG. 7 shows a typical example in the case where the slot ID is identified by binary values as a related technique. The configuration of FIG. 7 corresponds to one bit of the slot ID of FIG. A slot ID input terminal (Slot ID_I) of an FPGA (Floating Programmable Gate Array) 13 in the card 12 is connected to a high potential power supply VCC via a resistor R1. The resistance value of the resistor R1 is a resistance value for making the Slot ID show High when the signal from the BWB 11 is Open (open state, unconnected state). For example, R1 = 4.7 kΩ. The FPGA 13 is provided in the card 12 and detects the slot ID based on the voltage of the slot ID_I terminal.

  As shown in FIG. 7A, when the signal from the BWB 11 is Open, the Slot ID_I terminal is at the power supply potential VCC, and the Slot ID is High as shown in FIG. 7B.

  As shown in FIG. 7C, when the signal from the BWB 11 is at the GND level (Low), the Slot ID_I terminal is set to the potential on the GND side, and the Slot ID is as shown in FIG. 7D. , Low.

  In the example shown in FIG. 7, the input circuit (not shown) connected to the Slot ID_I terminal of the FPGA 13 is High (for example, logic 1) when the signal from the BWB 11 is Open, and Low (for example, logic 0) when the signal is at the GND potential. Thus, the slot ID is identified by a binary value.

  Usually, in order to identify a signal having three or more values, a method of identifying the potential of an analog signal, converting it to a digital signal having three or more values, and identifying a slot ID by three or more values has been conventionally used.

  FIG. 8 shows a typical example of a case where an input analog signal representing a slot ID state from the BWB 11 is converted into a digital signal using an ADC (Analog-to-Digital Converter) 14 in the card 12 as a related technique. Indicates. In the example shown in FIG. 8, the output of the ADC 14 is 2 bits, and the FPGA 13 identifies the slot ID with three values.

  As shown in FIG. 8, in the card 12, a resistor R2 is connected between the analog input terminal of the ADC 14 and the power supply VCC, and a resistor R3 is connected between the analog input terminal of the ADC 14 and GND. The resistance values of the resistors R2 and R3 are resistance values for preventing the signal from the BWB 11 from being shown as High or Low when the signal is open. For example, R2 = 4.7 kΩ and R3 = 4.7 kΩ.

In FIG. 8, the signal from the BWB 11 is converted into a digital signal via the ADC 13 in the card 12 and input to the slot ID input terminal (Slot ID_I) of the FPGA 13. In the FPGA 13 in the card 12,
When the digital signal from the ADC 14 is “11”, the slot ID is High (FIGS. 8A and 8B),
When the digital signal from the ADC 14 is “00”, the slot ID is Low (FIGS. 8C and 8D),
When the digital signal from the ADC 14 is other than that (that is, “10” or “01”), the slot ID is identified by three values such as Open (FIGS. 8E and 8F).

  In Patent Document 1, as a circuit to be inspected, in which an electronic component constant is to be inspected in an electronic component inspection apparatus, a resistor and a capacitor connected between a power source and GND, and a connection between the resistor and a capacitance to be inspected A configuration in which a CPU I / O port is connected to a point via a resistor is disclosed. However, the invention described in Patent Document 1 is completely different from the detection of the slot ID. Patent Document 2 discloses a ternary input for discriminating three input states (first fixed potential, second fixed potential, and floating state) without requiring a third fixed potential as the input potential of the external terminal. A configuration of the discrimination circuit is disclosed. However, the configuration of the invention described in Patent Document 2 is completely different from that of the present invention described later.

JP 2001-264398 A JP-A-8-18439

  The slot ID identification method in the related art transmission apparatus described above has the following problems.

  Since one bit can identify the binary values of the high and low signals, when various slot IDs are required, the number of bits of the slot ID increases, and thus the slot ID_I terminal increases.

  On the other hand, in order to identify three or more values with one bit, an additional circuit such as an ADC is required for the card as shown in FIG. For this reason, the mounting density cannot be increased.

  Accordingly, an object of the present invention is to provide an apparatus and method that can identify a slot ID per bit by at least three values without using an ADC or the like.

  In order to solve the above-described problems, the invention disclosed in the present application is generally configured as follows.

In the method according to one aspect of the present invention, a slot ID corresponding to mounting position information in a device mounted on a device is identified by the card.
Supplying an identification signal of a predetermined pattern to a slot ID input terminal on the card side for inputting a slot ID signal from the device side;
The slot ID is detected with at least three values from the slot ID input terminal to which the slot ID signal and the identification signal are supplied.

  In the present invention, the identification signal includes a pulse signal.

  In the present invention, the slot ID is detected by at least three values of high potential, low potential, and open.

  In the present invention, the identification signal includes a pulse signal having a smooth waveform.

  In the present invention, the identification signal includes a plurality of types of pulses having different high potential periods and / or low potential periods of a pulse waveform.

  In the present invention, the slot ID is detected as at least three values of a high potential, a low potential, and at least one intermediate potential between the high potential and the low potential.

A detection circuit according to another aspect of the present invention is a detection circuit that is provided in a card mounted on a device and detects a slot ID corresponding to mounting position information of the card in the device. ,
Means for supplying an identification signal of a predetermined pattern to a slot ID input terminal on the card side for inputting a slot ID signal from the device side;
The slot ID is detected with at least three values from the slot ID input terminal to which the slot ID signal and the identification signal are supplied.

  In the detection circuit according to the present invention, the identification signal includes a pulse signal.

  In the detection circuit according to the present invention, the slot ID is detected by at least three values of high potential, low potential, and open.

  In the detection circuit according to the present invention, the identification signal may include a pulse signal having a waveform.

  In the detection circuit according to the present invention, the identification signal may include a plurality of types of pulses having different high potential periods and / or low potential periods of a pulse waveform.

  In the detection circuit according to the present invention, at least three values of the high potential, the low potential, and at least one intermediate potential between the high potential and the low potential are detected from the binary signal of the pulse train at the slot ID input terminal.

  In the detection circuit according to the present invention, a resistor may be inserted between the identification signal output terminal and the slot ID input terminal.

  In the detection circuit according to the present invention, a resistor is inserted between the output terminal of the identification signal and the slot ID input terminal, and a capacitive element that forms the CR circuit with the resistor is connected to the slot ID input terminal. It is good also as a structure.

  In the detection circuit according to the present invention, the slot ID input terminal may be connected to a high potential power supply via a resistor.

In the detection circuit according to the present invention, the slot ID input terminal is connected to the device on which the card is mounted.
High potential,
Low potential,
Connected to one terminal of a predetermined intermediate potential between the high potential and the low potential, or
It may be configured to be in an open state.

  In the present invention, the detection circuit is incorporated in a semiconductor device such as an FPGA. According to the present invention, a card provided with the detection circuit is provided. Moreover, according to this invention, the transmission apparatus which mounts the said card | curd is provided.

  According to the present invention, the slot ID can be identified by at least three values of high potential, low potential, and open without using an ADC or the like.

  In addition, according to the present invention, by inputting a pulse train having a time constant to the slot ID input terminal, the slot ID can be discriminated even at a high potential, a low potential, or an intermediate potential other than an open state. Identification with three or more values is possible.

  Examples will be described in order to describe the present invention described above in more detail. According to the present invention, an identification signal (for example, a digital pulse) is applied to the slot ID input terminal (Slot ID_I) of the detection circuit (13) for identifying the slot ID corresponding to the mounting position information of the card mounted on the device. Signal), and the detection circuit (13) uses a slot ID (Slot ID) input from the device side to one (1 bit) slot ID input terminal (Slot ID_I) without using an ADC. Detection is performed by at least three values (for example, three values of High), Low, and Open (Open).

  Further, according to the present invention, a pulse signal having a pulse waveform smoothed as the identification signal is supplied to the slot ID input terminal (Slot ID_I), and the temporal change of the pulse train of the slot ID input terminal (Slot ID_I) The slot ID input to one (1 bit) slot ID input terminal (Slot ID_I) is detected by at least three values of a high potential, a low potential, and at least one intermediate potential between a high potential and a low potential. In this case, the slot ID at one (1 bit) slot ID input terminal (Slot ID_I) can be determined by an intermediate potential other than a high potential, a low potential, and an open state.

  In the present invention, the identification signal may include a plurality of types of pulse signals whose High period and / or Low period of the pulse waveform change on the time axis. According to the present invention, it is possible to cope with a case where the mounting density in the card is severe or when various slot IDs are required. In the following, description will be made in accordance with examples.

  FIG. 1 is a diagram showing a configuration for identifying a slot ID (in the case of 1 bit) with three values in an embodiment of the present invention. In the card 12 mounted on the transmission device, the slot ID_I terminal of the FPGA (Field Programmable Gate Array) 13 (corresponding to the detection circuit of the present invention) having a slot ID identification function is connected to the power supply terminal VCC via the resistor R4. Connected to the Slot_ID_O terminal via the resistor R5. The resistance value of R5 is sufficiently smaller than the resistance value of resistance R4. Although not particularly limited, in this embodiment, the resistance value of the resistor R4 is 4.7 kΩ, and the resistance value of the resistor R5 is 330Ω. The resistor R5 is a resistor for preventing a load on the slot_ID_O terminal on the output side when the slot ID_I terminal is connected to the power supply terminal VCC or the ground terminal GND. Note that the card 12 of this embodiment is mounted on the transmission apparatus 10 shown in FIG. 6, for example, and the BWB 11 in FIG. 1 corresponds to the BWB 11 in FIG.

  In FIG. 1, the FPGA 13 for identifying the slot ID outputs a digital signal (identification signal) having a predetermined pattern from the slot ID_O terminal, and has a resistance value (330Ω) sufficiently with respect to the resistance value (4.7 kΩ) of the resistor R4. Is applied to the Slot ID_I terminal through a small resistor R5. With this configuration, the FPGA 13 that identifies the slot ID can identify the slot ID with three values of High, Low, and Open from the state of the Slot ID_I terminal.

  FIG. 1A shows a case where the signal from the BWB 11 is at a high level (VCC). In this case, as illustrated in FIG. 1B, the Slot ID_I terminal is High.

  FIG. 1C shows a case where the signal from the BWB 11 is at a low level (GND). In this case, as shown in FIG. 1D, the Slot ID_I terminal is Low (DC signal).

  FIG. 1E shows a case where the signal from the BWB 11 is Open. In this case, as shown in FIG. 1F, a pattern from the Slot ID_O terminal is given to the Slot ID_I terminal.

  FIG. 2 to FIG. 5 are diagrams for explaining a technique for identifying a slot ID (in the case of 1 bit) with four values of three or more in another embodiment of the present invention. That is, FIG. 2 shows that the signal from BWB 11 is High (VCC), FIG. 3 shows that the signal from BWB 11 is (2/3) VCC, and FIG. 4 shows that the signal from BWB 11 is (1/3) VCC. These are figures explaining the case where the signal from BWB11 is Low (GND electric potential). 2 to 5 is mounted on, for example, the transmission apparatus 10 shown in FIG. 6, and the BWB 11 in FIGS. 2 to 5 corresponds to the BWB 11 in FIG.

  In the present embodiment, a time constant is given to the identification signal (pulse signal) applied from the Slot ID_O terminal to the Slot ID_I terminal with respect to the configuration shown in FIG. ) As a method for providing a time constant, for example, a CR circuit is configured using a capacitor, or the current capacity (current drive capability) of an output buffer (not shown) of the Slot ID_O terminal of the FPGA 13 is changed. Alternatively, any configuration that adjusts (lowers) the slew rate of the rise and fall of the pulse signal from the output buffer (not shown) of the Slot ID_O terminal is used.

  A digital signal (identification signal) having a predetermined pattern is output from the Slot ID_O terminal of the FPGA 13 as in the above embodiment. In the present embodiment, the pulse width (High period or Low period) and / or the pulse cycle time (Low period + High period) includes a pulse train that varies on the time axis as the identification signal of the predetermined pattern.

  As shown in FIG. 2A, in the card 12, a capacitor C1 (= 1 uF) is connected between the Slot ID_I terminal for inputting a signal from the BWB 11 and GND to give a time constant. That is, the resistor R7 and the capacitor C1 constitute a CR circuit (time constant τ = CR).

  Although not particularly limited, in this embodiment, as shown in FIG. 2B, FIG. 3B, FIG. 4B, and FIG. 5B, an identification signal having a predetermined pattern from the Slot ID_O terminal. As shown, a pulse train that starts with a pulse with a small pulse width (High pulse) and includes a pulse with a large pulse width (High pulse) with time (the Low period of the pulse also becomes longer in sequence) is output, and the waveform is smoothed by the CR circuit. A pulse is input to the Slot ID_I terminal.

  In FIG. 2A, the resistance R6 is 4.7 kΩ, and the resistance R7 is 330Ω. In FIG. 3A, the resistor R8 is 4.7 kΩ, the resistor R9 is 8.2 kΩ, and the resistor R10 is 330 Ω. The potential at the connection point of the resistors R8 and R9 is equivalent to (2/3) VCC. In FIG. 4A, the resistor R12 is 4.7 kΩ, the resistor R11 is 10 kΩ, and the resistor R13 is 330 Ω. The potential at the connection point of the resistors R11 and R12 is equivalent to (1/3) VCC. The resistance R14 in FIG. 5 is 330Ω.

  These resistance values are shown in VCC (High) (FIG. 2), shown in 2/3 VCC (FIG. 3), shown in 1/3 VCC (FIG. 4), and shown in GND (Low) (FIG. 5). ) Resistance value. R7, R10, R13, and R14 are resistors for preventing a load from being applied to the slot ID_O terminal on the output side when VCC or GND is connected to the slot ID_I terminal.

  In FIG. 2 to FIG. 5, a pulse train of patterns having several kinds of pulse widths changing with time is output from the Slot ID_O terminal from the FPGA 13 for identifying the Slot ID, and the resistors (R7, R10, R13) are respectively output. , R14) to the slot ID_I terminal.

  The FPGA 13 for identifying the slot ID identifies the slot ID with four values of High, 2/3 VCC, 1/3 VCC, and Low from the state of the Slot ID_I terminal.

  In FIG. 2, when the signal from the BWB 11 is the power supply potential VCC, the Slot ID_I terminal of the FBGA 13 remains High for a certain period (see the input potential in FIG. 2B and the Slot ID_I in FIG. 2C). .

  As shown in FIG. 5, when the signal from the BWB 11 is the GND potential, the Slot ID_I terminal of the FBGA 13 becomes Low for a certain period of time (the input potential in FIG. 5B, the Slot ID_I in FIG. 5C). reference).

  In FIG. 3, when the signal from BWB 11 is 2/3 VCC, the pattern signal output from the Slot ID_O terminal (output by changing the pulse width with time) is blunted with the time constant of the CR circuit of resistor R10 and capacitor C1. , The slot ID_I terminal has a high level (the potential of the slot ID_I terminal is lower than the threshold potential) for a certain period of time (low, the potential of the slot ID_I terminal exceeds the threshold potential), and then the potential of the slot ID_I terminal is lower than the threshold potential. The potential of the Slot ID_I terminal exceeds the threshold potential). As described above, the (2/3) VCC level can be identified from the temporal change of the input pulse at the Slot ID_I terminal.

  Note that the voltage C2 divided by the resistors R8 and R9 on the BWB11 side (2/3) VCC is applied to one end of the capacitor C1, and a pulse from the Slot ID_O terminal is further applied, which is shown in FIG. 3B. Thus, from the disclosure of application of a pulse from the Slot ID_O terminal (which is dull with the CR time constant as shown by the broken line), the terminal voltage of the capacitor C1 (and hence the voltage of the Slot ID_I terminal) is a threshold voltage (for example, 0. Higher than 5 VCC) and becomes a high pulse (see FIG. 3C). The FPGA 13 identifies the slot ID as (2/3) VCC by serially comparing the temporal change (see FIG. 3B) of the input pulse of the Slot ID_I terminal with the expected value pattern. May be. The level of the signal from the BWB 11 may be derived by calculating the time average (time integration) or effective value (root mean square value) of the input pulse of the Slot ID_I terminal for a predetermined period.

  In the case of FIG. 4, the signal from the BWB 11 shows the Open state as 1/3 VCC. That is, the pattern signal output from the Slot ID_O terminal (output by changing the pulse width in time) is blunted by the time constant of the CR circuit of R13 and C1, and the Slot ID_I terminal has a Low (Slot ID_I terminal) for a certain period of time. High potential appears for a moment (the potential at the Slot ID_I terminal exceeds the threshold potential), and then a slightly wider high pulse (the potential at the Slot ID_I terminal exceeds the threshold potential). Visible, followed by a high pulse. Thus, the (1/3) VCC level can be identified from the temporal change of the input pulse at the Slot ID_I terminal.

  Note that (a divided voltage (1/3) VCC equal to or lower than the threshold voltage) is applied to one end of the capacitor C1 by the resistors R11 and R12 on the BWB 11 side, and a pulse from the Slot ID_O terminal is applied. As shown in (B), the terminal voltage of the capacitor C1 (and hence the voltage of the Slot ID_I terminal) at the time of disclosure of the application of the pulse from the Slot ID_O terminal (dulled by the CR time constant as shown by the broken line) is the threshold voltage ( When the terminal voltage of the capacitor C1 exceeds the threshold voltage due to the charging action of the capacitor C1 by the pulse from the Slot ID_O terminal, the FPGA 13 becomes a high pulse (see FIG. 4C). The time variation of the input pulse at the Slot ID_I terminal (see FIG. 4B) is shown. It may be possible to identify that the slot ID is (1/3) VCC by comparing the expected value pattern with the actual value.The time average (time integration) or effective value of the input pulse of the slot ID_I terminal for a predetermined period. The level of the signal from the BWB 11 may be derived by obtaining (root mean square value) or the like.

  In FIG. 3, the resistance value of the resistor R10 needs to be sufficiently smaller than the resistance values of the resistors R8 and R9. In FIG. 4, the resistance value of R13 needs to be sufficiently smaller than the resistance values of R11 and R12.

  Thus, according to the present embodiment, a serial bit signal (digital pulse train signal) is further supplied as an identification signal to one (1 bit) Slot ID_I terminal that inputs a slot ID without using an ADC. Thus, one (1 bit) Slot ID_I terminal can be identified by at least three values (for example, High, Low, Open).

  Further, as shown in FIGS. 2 to 5, when the signal is given a time constant by the capacitor C1, the circuit is mounted in the card, and the time ID is changed from the slot ID_O terminal of the FPGA for identifying the slot ID. By outputting a pattern signal having various widths, the slot ID is identified by at least three values (High, Low, at least one intermediate potential) from the state of one (1 bit) Slot ID_I terminal. be able to. That is, according to the embodiment, a configuration in which an identification signal of a digital signal pattern having a time constant and several kinds of widths changing in time is applied, and only one bit is used and an intermediate other than High, Low, and Open. It can also be identified by potential.

  Although FIGS. 2 to 5 show the case of identifying a four-value (VCC, 2/3 VCC, 1/3 VCC, GND) slot ID, the present invention is of course not limited to such a configuration. .

In this example,
A time-varying pattern signal output from the Slot ID_O terminal;
How to have a time constant (such as changing the current capacity of the output buffer of the FPGA or using a variable capacitor)
Depending on the resistance value to be set, the slot ID that can be identified can be identified over a wide variety.

  According to the present embodiment, a high-level, low-level, and three-level signal can be identified by using a digital pulse train signal without using an ADC for slot ID detection in the card. Three types of cards can be identified by (one slot ID_I terminal). Furthermore, by giving a time constant to the pulse train signal (identification signal) and changing the pulse waveform with time, three or more kinds of cards can be identified by one bit. The present invention that can identify various cards using only digital signals without using an ADC is particularly effective when the card has a high mounting density or when there are many types of cards in the transmission apparatus.

  In the above embodiment, an example is shown in which an FPGA is used as a detection circuit for identifying a slot ID. However, the present invention is not limited to an FPGA, and may be constituted by another semiconductor integrated circuit or a discrete element. Although the pattern of the pulse train applied to the Slot ID_I terminal is output from the FPGA, it is of course possible to output the pattern of the pulse train applied to the Slot ID_I terminal from another unit (or circuit). In this case, another unit (or circuit) constitutes a part of the detection circuit for identifying the slot ID.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

It is a figure explaining one Example of this invention. It is a figure explaining one Example of this invention. It is a figure explaining one Example of this invention. It is a figure explaining one Example of this invention. It is a figure explaining one Example of this invention. It is a figure explaining a transmission apparatus. It is a figure explaining an example of the typical structure of related technology. It is a figure explaining another example of the typical structure of related technology.

Explanation of symbols

10 Transmission equipment 11 BWB
12 cards 13 FPGA
14 ADC

Claims (19)

In identifying the slot ID corresponding to the mounting position information in the device of the card mounted on the device by the card,
Supplying an identification signal of a predetermined pattern to a slot ID input terminal on the card side for inputting a slot ID signal from the device side;
A slot ID identification method characterized by detecting at least three values of a slot ID from the slot ID input terminal to which the slot ID signal and the identification signal are supplied.   2. The slot ID identification method according to claim 1, wherein the identification signal includes a pulse signal.   3. The slot ID identification method according to claim 1, wherein the slot ID is detected by at least three values of high potential, low potential, and open.   2. The slot ID identification method according to claim 1, wherein the identification signal includes a pulse signal having a waveform.   5. The slot ID identification method according to claim 1, wherein the identification signal includes a plurality of types of pulses having different high potential periods and / or low potential periods of a pulse waveform.   6. The slot ID identification method according to claim 4, wherein at least three values of at least one intermediate potential between a high potential, a low potential, and a high potential and a low potential are detected as the slot ID. A detection circuit which is provided in a card mounted on the device and detects a slot ID corresponding to mounting position information of the card in the device;
Means for supplying an identification signal having a predetermined pattern to a slot ID input terminal on the card side for inputting a slot ID signal from the device side;
A detection circuit, wherein a slot ID is detected by at least three values from the slot ID input terminal to which the slot ID signal and the identification signal are supplied.   The detection circuit according to claim 7, wherein the identification signal includes a pulse signal.   8. The detection circuit according to claim 7, wherein the slot ID is detected by at least three values of high potential, low potential, and open.   8. The detection circuit according to claim 7, wherein the identification signal includes a pulse signal having a waveform.   The detection circuit according to claim 7, wherein the identification signal includes a plurality of types of pulses having different high potential periods and / or low potential periods of a pulse waveform.   The at least three values of at least one intermediate potential between a high potential, a low potential, and a high potential and a low potential are detected from a binary signal of a pulse train of the slot ID input terminal. Detection circuit.   The detection circuit according to claim 7, wherein a resistor is inserted between an output terminal of the identification signal and the slot ID input terminal.   The resistance element is inserted between the output terminal of the identification signal and the slot ID input terminal, and the capacitive element that forms the CR circuit with the resistor is connected to the slot ID input terminal. The detection circuit according to any one of 10 to 12.   10. The detection circuit according to claim 7, wherein the slot ID input terminal is connected to a high-potential power supply via a resistor. The slot ID input terminal is
On the device side where the card is mounted,
High potential,
Low potential,
Connected to one terminal of a predetermined intermediate potential between the high potential and the low potential, or
The detection circuit according to claim 7, wherein the detection circuit is in an open state.   A semiconductor device comprising the detection circuit according to claim 7.   A card comprising the detection circuit according to claim 7.   A transmission apparatus for mounting the card according to claim 18.

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