JP2009100278A - Peak hold circuit, and operational amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operational amplifier and a peak hold circuit, that are favorable to drive at a low voltage and can improve an NF. <P>SOLUTION: An input terminal 102 is connected to the input terminal of a CMOS invertor 103. The output terminal of the CMOS invertor 103 is connected to the gate of an NMOS 107. The source of the NMOS 107 is grounded, and the drain is connected to one end of a resistor 106, one end of a capacitor 108, the input terminal of a CMOS invertor 105, and an output terminal 109. The other end of the resistor 106 is connected to a drive power supply (not shown). The other end of the capacitor 108 is grounded. An NMOS 107 is turned on and off depending on voltages Vin, Vout. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a peak hold circuit and an operational amplifier, and more particularly to a peak hold circuit and an operational amplifier that are advantageous for driving at a low voltage.

  FIG. 1 is a diagram illustrating a configuration of an example of a gain control amplifier. The gain control amplifier is used to keep the signal constant. The gain control amplifier includes a gain control unit 11 and a level detection unit 12. The gain control unit 11 performs control so that the level of the input signal becomes a preset signal level. The control is based on an instruction from the level detection unit 12.

  The output from the gain control unit 11 is output to other parts not shown and supplied to the level detection unit 12. The level detection unit 12 compares the level of the preset signal with the level of the supplied signal, and the input signal is weak so that the level of the supplied signal becomes the level of the set signal. In such a case, an instruction is given to increase the sensitivity, and an instruction is issued to decrease the sensitivity if the input signal is strong.

  The level detection unit 12 of such a gain control amplifier includes a circuit called a peak hold circuit. The peak hold circuit is a circuit that holds the maximum value of an input signal.

  This peak hold circuit includes an operational amplifier. The operational amplifier is configured by a semiconductor element such as BJT (Bipolar Junction Transistor) or MOS (Metal Oxide Semiconductor). The circuit configuration of the operational amplifier is almost the same regardless of whether the semiconductor element constituting the operational amplifier is BJT or MOS.

  FIG. 2 is a circuit diagram showing a configuration of an example of a conventional operational amplifier composed of a MOS (see, for example, Patent Document 1). In FIG. 2, the operational amplifier 21 includes a subtraction circuit 22, an output amplifier circuit 23, an inverting input terminal 24, a non-inverting input terminal 25, and an output terminal 26.

  The subtraction circuit 22 includes PMOS (Positive Metal Oxide Semiconductor) 31 and 32, NMOS (Negative Metal Oxide Semiconductor) 33 and 34, and a constant current source 35. In the subtraction circuit 22, the gate of the PMOS 31 is connected to the inverting input terminal 24, and the gate of the PMOS 32 is connected to the non-inverting input terminal 25. The source of the PMOS 31 and the source of the PMOS 32 are connected to one end of the constant current source 35, and the other end of the constant current source 35 is connected to a power source (not shown) that supplies the drive voltage E1.

  In the subtraction circuit 22, the drain of the PMOS 31 and the drain of the NMOS 33 are connected, the drain of the PMOS 32 and the drain of the NMOS 34 are connected, and the sources of the NMOS 33 and the NMOS 34 are grounded. The gate of the NMOS 33 and the gate of the NMOS 34 are connected, and the connection point between the gate of the NMOS 33 and the gate of the NMOS 34 and the connection point between the drain of the PMOS 31 and the drain of the NMOS 33 are connected. The connection point between the drain of the PMOS 32 and the drain of the NMOS 34 is connected to the output amplifier circuit 23.

  The output amplifier circuit 23 includes an NMOS 41, a capacitor 42, and a constant current source 43. In the output amplifier circuit 23, the gate of the NMOS 41 and one end of the capacitor 42 are connected, and the connection point between the gate of the NMOS 41 and one end of the capacitor 42 is the connection point between the drain of the PMOS 32 and the drain of the NMOS 34 in the subtraction circuit 22. It is connected to the. The source of the NMOS 41 is grounded, and the drain of the NMOS 41 is connected to the other end of the capacitor 42, one end of the constant current source 43, and the output terminal 26. The other end of the constant current source 43 is connected to a power source (not shown) that supplies the drive voltage E1.

  In the operational amplifier 21, the first input voltage is input to the inverting input terminal 24, the second input voltage is input to the non-inverting input terminal 25, and the voltage obtained by subtracting the first input voltage from the second input voltage. Is supplied from the subtraction circuit 22 to the output amplification circuit 23. Then, the voltage supplied from the subtraction circuit 22 is amplified by the output amplification circuit 23, and the voltage amplified by the output amplification circuit 23 is output from the output terminal 26 as an output voltage.

  The operational amplifier 21 configured as described above is generally called a Barton amplifier, and is generally used in a bipolar process or a MOS process.

  Here, the constant current source 35 is also configured by a semiconductor element, and the subtraction circuit 22 of the operational amplifier 21 has a configuration in which three stages of semiconductor elements are stacked. That is, as shown in FIG. 2, the subtraction circuit 22 includes a constant current source 35, a PMOS 31 or 32, and an NMOS 33 or 34 connected in series between the drive voltage E1 supplied to the constant current source 35 and the ground level. Connected configuration.

  Accordingly, the voltages supplied to the constant current source 35, the PMOS 31 or 32, and the NMOS 33 or 34 are lower than the drive voltage E1. Thus, in order to drive each of the constant current source 35, PMOS 31 or PMOS 32, NMOS 33 or NMOS 34, the voltage required for driving the constant current source 35, PMOS 31 or 32, NMOS 33 or 34 is equal to or higher than the sum of the voltages. Must be the drive voltage E1.

As described above, since the voltage equal to or higher than the voltage required for driving the constant current source 35, the PMOS 31 or the PMOS 32, the NMOS 33 or the NMOS 34 needs to be set as the driving voltage E1, the subtraction circuit 22, and thus the operational amplifier No. 21 was unsuitable for driving at a low voltage.
JP 4-185005

  As described above, since the subtraction circuit 22 has a differential input structure in which three stages of semiconductor elements are stacked, it is difficult to drive with a low voltage. In recent years, there has been a demand for incorporating the above-described operational amplifier 21 in a device such as a cellular phone that is desired to keep the driving voltage low.

  However, it is difficult to incorporate the operational amplifier 21 that is difficult to be driven at a low voltage into a device for which the drive voltage is desired to be kept low. Furthermore, it is difficult to incorporate the level detection unit 12 including the operational amplifier 21 and the gain control amplifier including the level detection unit 12 into a device that is desired to suppress a low voltage.

  Further, since the subtraction circuit 22 has a differential input structure in which three stages of semiconductor elements are stacked, the frequency characteristics are poor, so that it is difficult to use in the RF (radio frequency) band. .

  In addition, in order to improve the NF (Noise Figure) of the circuit, there is a limitation that the size of the transistor of the first-stage differential input section must be increased, and the frequency characteristic is deteriorated due to this. . In addition, in order to improve the NF of the circuit, there is a limitation that the bias current of the transistor in the first-stage differential input section must be increased, which increases power consumption.

  The present invention has been made in view of such a situation, and provides an operational amplifier and a peak hold circuit which are advantageous for driving at a low voltage and can improve NF.

  A peak hold circuit according to an aspect of the present invention is a peak hold circuit including first to third semiconductor elements that invert a voltage input to an input terminal and output the inverted voltage from an output terminal, wherein the first semiconductor element The input terminal of the second semiconductor element is connected to the input terminal of the first semiconductor element, the input terminal of the second semiconductor element is connected to the output terminal of the first semiconductor element, and the output of the third semiconductor element. And a gate of a fourth semiconductor element having a configuration different from that of the first semiconductor element to the third semiconductor element is connected to the output terminal of the second semiconductor element. One end of a resistor, one end of a capacitor, an input terminal of the third semiconductor element, and an output terminal for outputting a signal to the outside are connected to the drain of the semiconductor element.

  The first to third semiconductor elements may be CCMOS (Complementary Metal Oxide Semiconductor) configured by a pair of PMOS (Positive Metal Oxide Semiconductor) and NMOS (Negative Metal Oxide Semiconductor). it can.

  The fourth semiconductor element may be an NMOS or a PMOS.

  The same semiconductor element as the first to third semiconductor elements may be further added by an even number of units.

  The peak hold circuit according to one aspect of the present invention includes three CMOS inverters and at least an NMOS or PMOS, a resistor, and a capacitor, and the NMOS or PMOS is configured to serve as a switch.

  An operational amplifier according to one aspect of the present invention is an operational amplifier including a plurality of semiconductor elements that invert a voltage input to an input terminal and output the output from an output terminal, and is input to the input terminal of the first semiconductor element from the outside. A signal input terminal is connected, an output terminal of the second semiconductor element is connected to an output terminal of the first semiconductor element, and an output terminal of the third semiconductor element is connected to an output terminal of the second semiconductor element. An input terminal is connected, an output terminal of the fourth semiconductor element is connected to an output terminal of the third semiconductor element, and an output terminal for outputting a signal to the outside is connected, and an output terminal of the fourth semiconductor element is connected to the output terminal of the fourth semiconductor element, An output terminal of the first semiconductor element and an input terminal of the second semiconductor element are connected.

  The first to fourth semiconductor elements may be CCMOS (Complementary Metal Oxide Semiconductor) configured by a pair of PMOS (Positive Metal Oxide Semiconductor) and NMOS (Negative Metal Oxide Semiconductor). it can.

  The same semiconductor element as the first to fourth semiconductor elements may be further added by an even number unit.

  The first to fourth semiconductor elements having different conductances are configured, and the gain is determined by the ratio of the conductance of the first semiconductor element to the conductance of the fourth semiconductor element. be able to.

  The operational amplifier according to one aspect of the present invention includes at least four CMOS inverters, and the first to third CMOS inverters are connected in series, and the first CMOS inverter and the second CMOS inverter are connected. A signal from the fourth CMOS inverter is fed back between the inverter and the inverter.

  According to one aspect of the present invention, it is possible to provide a circuit that is advantageous for driving at a low voltage.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 3 is a diagram showing a configuration of an embodiment of an operational amplifier to which the present invention is applied. The operational amplifier 61 shown in FIG. 3 includes an input terminal 62, a CMOS (complementary mental-oxide semiconductor) inverter 63, a CMOS inverter 64, a CMOS inverter 65, a CMOS inverter 66, and an output terminal 67.

  The description will be continued assuming that the CMOS inverter 63, the CMOS inverter 64, the CMOS inverter 65, and the CMOS inverter 66 have the same circuit configuration. Each of these CMOS inverters 63 to 66 has a function as an inverter that inverts and outputs an input signal.

  The input terminal 62 is connected to the input terminal of the CMOS inverter 63. The output terminal of the CMOS inverter 63 is connected to the input terminal of the CMOS inverter 64. The output terminal of the CMOS inverter 64 is connected to the input terminal of the CMOS inverter 65. The output terminal of the CMOS inverter 65 is connected to the input terminal of the CMOS inverter 66 and the output terminal 67. The output terminal of the CMOS inverter 66 is connected to a line connecting the output terminal of the CMOS inverter 63 and the input terminal of the CMOS inverter 64.

  Here, the circuit configuration of the CMOS inverters 63 to 66 will be described with reference to FIG. As described above, since the CMOS inverters 63 to 66 have the same circuit configuration, the CMOS inverter 63 will be described as an example here.

  The CMOS inverter 63 includes a PMOS (Positive Metal Oxide Semiconductor) 81 and an NMOS (Negative Metal Oxide Semiconductor) 82. The input terminal of the CMOS inverter 63 is connected to the gate of the PMOS 81 and the gate of the NMOS 82. The source of the PMOS 81 is connected to a power supply (not shown) that supplies the drive voltage E2, and the source of the NMOS 82 is grounded. The drain of the PMOS 81 and the drain of the NMOS 82 are connected to the output terminal of the CMOS inverter 63.

Further, since the CMOS inverter 63 controls the current output from the output terminal in accordance with the voltage input to the input terminal, the voltage supplied to the input terminal of the CMOS inverter 63 is V, and the output terminal of the CMOS inverter 63 is Assuming that the current output from (flowing in the direction of the arrow shown in FIG. 4) is I, the voltage V and the current I have the relationship shown in the following equation.

  Here, gm represents conductance, and the conductance gm is a value indicating the ability of the CMOS inverter 63 to control the current I according to the voltage V (that is, voltage-current conversion ability). As described above, since the circuit configurations of the CMOS inverters 63 to 66 are all the same, the conductances gm of the CMOS inverters 63 to 66 are also the same value.

  Next, the voltage Vin input to the input terminal 62 and the voltage Vout output from the output terminal 67 in the operational amplifier 61 shown in FIG. 3 will be described. In the following description, the connection points in the operational amplifier 61 shown in FIG. 3 are defined as follows.

The voltage input to the input terminal 62 is the voltage Vin
The voltage output from the output terminal 67 is the voltage Vout
A connection point between the output terminal of the CMOS inverter 63, the input terminal of the CMOS inverter 64, and the output terminal of the CMOS inverter 66 is a connection point e.
The voltage at connection point e is expressed as voltage Ve
The voltage at the connection point between the output terminal of the CMOS inverter 64 and the input terminal of the CMOS inverter 65 is the voltage V1.
The current flowing through the CMOS inverter 63 (current input to the connection point e) is changed to the current iin
The current flowing through the CMOS inverter 66 (current input to the connection point e) is changed to current i2.

When defined in this way, first, the current iin can be expressed as follows. That is, since the voltage Vin is input from the input terminal 62 to the input terminal of the CMOS inverter 63 and satisfies the relationship of the above-described equation (1), the current iin output from the output terminal of the CMOS inverter 63 is expressed by the following equation: It is represented by (2).

A voltage equal to the voltage Vout output from the output terminal 67 is input to the input terminal of the CMOS inverter 66. Accordingly, in this case as well, since the CMOS inverter 66 satisfies the relationship of the above-described formula (1), the current i2 output from the output terminal of the CMOS inverter 66 is expressed by the following formula (3).

  Each of the CMOS inverters 63 to 66 includes a constant current source that outputs a current corresponding to a voltage input to the input terminal from the output terminal, and a resistor (one end connected to the output terminal and the other end grounded). Hereinafter, it can be considered as an equivalent circuit consisting of a drain resistance).

  Therefore, the connection point e is a circuit in which a drain resistance that is considered to be connected to the output terminal of the CMOS inverter 63 and a drain resistance that is considered to be connected to the output terminal of the CMOS inverter 66 are connected in parallel. And can be regarded as being grounded. Accordingly, when the resistance value of the drain resistance of each of the CMOS inverters 63 to 66 is Rd, the connection point e can be regarded as being grounded through a resistance having a resistance value Re (Re = Rd / 2).

Further, assuming that the input impedances of the CMOS inverters 63 to 66 are very high and no current flows into the input terminal of the CMOS inverter 64 connected to the connection point e, the CMOS inverter 63. When the current iin output from the output terminal and the current i2 output from the output terminal of the CMOS inverter 66 flow to the ground level via the resistance having the resistance value Re considered to be connected to the connection point e. Can be considered. From this, the voltage Ve at the connection point e is expressed by the following equation (4).

Substituting the current iin represented by the formula (2) and the current i2 represented by the formula (3) into the formula (4) and transforming, the following formula (5) is obtained.

Next, the voltage V1 is considered. The voltage V1 can be obtained from the current flowing through the CMOS inverter 64 (here, the current i1) and the resistance of the CMOS inverter 64. Since the resistance of the CMOS inverter 64 can be expressed by the resistance value Rd as described above, the voltage V1 is expressed by the following equation (6).

Similarly, the voltage Vout can be obtained from the current flowing through the CMOS inverter 65 and the resistance of the CMOS inverter 65. Therefore, the voltage Vout is expressed by the following equation (7).

By substituting equation (6) into equation (7), the following equation (8) can be obtained.

By substituting the voltage Ve obtained by the equation (4) into the equation (8) and putting it together, the following equation (9) can be obtained.

By transforming equation (9), the following equation (10) can be obtained.

Furthermore, the following equation (11) can be obtained by modifying the equation (10).

  Here, the resistance value Rd of the drain resistance is generally several hundred kΩ to several tens of MΩ, and the value of the third power of the resistance value Rd is much larger than 1. Therefore, in the expression (11), the value of the term including the third power of the resistance value Rd is much larger than 1, and therefore, the numerical value “1” in the denominator can be ignored. As a result, the denominator and the numerator are values that are considered to be the same value. Considering this, the ratio of the voltage Vin to the voltage Vout, that is, the gain, can be approximated to −1 as shown in the equation (11). The minus sign means that the phase of the input voltage Vin and the output voltage Vout are inverted.

  By obtaining the transfer function in this way, it can be seen that the operational amplifier 61 shown in FIG. 3 can be used as a two-terminal inverting amplifier.

  Referring again to FIG. 3, at the connection point e, the signal from the CMOS inverter 63 and the signal from the CMOS inverter 66 are input, and these signals are added. The signal fed back from the CMOS inverter 66 is an antiphase signal. Therefore, the operational amplifier 61 operates so that currents generated at the connection point e are balanced. In other words, the configuration is such that the bias points are automatically determined by operating in a balanced manner. Note that “automatically” means that a special process for performing control is performed without providing a control unit and without bothering the user. Therefore, the operational amplifier 61 shown in FIG. 3 is a two-terminal inverting amplifier whose bias point is automatically determined.

  In the above-described embodiment, the CMOS inverters 63 to 66 have been described as having the same conductance gm. Here, when the conductance gm of the CMOS inverter 63 is the conductance gm3, the conductance gm of the CMOS inverter 64 is the conductance gm4, the conductance gm of the CMOS inverter 65 is the conductance gm5, and the conductance gm of the CMOS inverter 66 is the conductance gm6. 11) is expressed by the following equation (12).

Since Expression (12) can be derived by performing transformation and substitution in the same manner as Expression (2) to Expression (11) described above, description thereof is omitted here. In the equation (12), it can be considered that the term of the following equation (13) satisfies the relationship of the following equation (13).

  That is, as described above, since the resistance value Rd of the drain resistance is generally several hundred kΩ to several tens MΩ, the conductance gm3, the conductance gm4, the conductance gm5, and the conductance gm6 are each larger than 1. It is considered to be. Therefore, it is considered that the value of conductance gm3 × conductance gm4 × conductance gm5 is much larger than 1 as shown in Expression (13).

Similarly, the relationship of the following formula (14) is also satisfied.

By satisfying the relationship of the equation (14), the value “1” in the denominator can be ignored. Therefore, the expression (12) can be considered as an expression composed of only the conductances gm3 to 6 and the resistance value Rd. In consideration of this, the equation (12) can be simplified as the following equation (15).

  From the equation (15), it can be seen that the gain of the operational amplifier 61 can be set by the ratio of the conductance gm3 of the CMOS inverter 63 and the conductance gm6 of the CMOS inverter 66. Therefore, by making the conductance gm3 of the CMOS inverter 63 and the conductance gm6 of the CMOS inverter 66 variable, a variable inverting amplifier can be configured with the configuration of the operational amplifier 61 shown in FIG. Further, when the conductance gm3 of the CMOS inverter 63 and the conductance gm6 of the CMOS inverter 66 are fixed values, the operational amplifier 61 having a desired gain can be configured by setting the fixed values to a desired gain. it can.

  Although the operational amplifier 61 shown in FIG. 3 is composed of four CMOS inverters 63 to 66, the operational amplifier 61 of the present invention is limited to four CMOS inverters. is not. The operational amplifier 61 to which the present invention is applied may be composed of an even number (excluding 2) of CMOS inverters. That is, a configuration in which a CMOS inverter is further added to the configuration of the operational amplifier 61 shown in FIG. For example, the operational amplifier 61 to which the present invention is applied can be configured from six CMOS inverters or eight CMOS inverters.

  The operational amplifier 61 to which the present invention is applied has the following effects. First, as shown in FIG. 3, the operational amplifier 61 is composed only of a CMOS inverter. Therefore, it has good frequency characteristics and can be applied to an RF (Radio Frequency) circuit. In addition, the input dynamic range is wide and the output dynamic range is wide. Since there is such an effect, there is also an effect that an operational amplifier advantageous for low voltage operation can be configured. Further, since the operational amplifier 61 shown in FIG. 3 is composed of a CMOS inverter, it can be an operational amplifier advantageous in low power consumption.

  Further, if the conductance gm of the input section, that is, the conductance gm3 of the CMOS inverter 63 is increased, the noise figure can be suppressed low. Since it is possible to increase the value of the conductance gm3, it is possible to suppress such a noise figure to be low.

  Further, since such an effect is obtained, it is possible to reduce the bias current required to ensure the same noise figure, and it is possible to configure an operational amplifier that is advantageous for low consumption. Furthermore, since it is advantageous for operation at a low voltage and can be manufactured by a FULL-CMOS process, it is considered to be an effective means for a digital-analog mixed chip. Since the input unit has a CMOS configuration, a very high input impedance is realized, which is very advantageous for the circuit configuration.

  Such an effect can be expected from the operational amplifier 61 of the present invention.

  Next, a description will be given of a peak hold circuit realized by changing a part of the configuration of the operational amplifier 61. The peak hold circuit 101 shown in FIG. 5 includes an input terminal 102, a CMOS inverter 103, a CMOS inverter 104, a CMOS inverter 105, a resistor 106, an NMOS (n-channel metal-oxide semiconductor) 107, a capacitor 108, and an output terminal 109. It is configured to include.

  The input terminal 102 is connected to the input terminal of the CMOS inverter 103. The output terminal of the CMOS inverter 103 is connected to the gate of the NMOS 107. The source of the NMOS 107 is grounded, and the drain is connected to one end of the resistor 106, one end of the capacitor 108, the input terminal of the CMOS inverter 105, and the output terminal 109. The other end of the resistor 106 is connected to a drive power supply (not shown). The other end of the capacitor 108 is grounded. The output terminal of the CMOS inverter 105 is connected to the output terminal of the CMOS inverter 103 and the input terminal of the CMOS inverter 104.

  Comparing the operational amplifier 61 shown in FIG. 3 with the peak hold circuit 101 shown in FIG. 5, the peak hold circuit 101 has a configuration in which the CMOS inverter 65 of the operational amplifier 61 is replaced with a resistor 106, an NMOS 107, and a capacitor 108. ing. With such a configuration, a peak hold circuit can be realized using an operation in which self-bias is determined by applying feedback.

The operation of the peak hold circuit 101 shown in FIG. 5 will be described. In the following description, the connection points of the peak hold circuit 101 shown in FIG. 5 are defined as follows.
The voltage input to the input terminal 102 is expressed as voltage Vin
The voltage output from the output terminal 109 is the voltage Vout
A connection point between the output terminal of the CMOS inverter 103, the input terminal of the CMOS inverter 104, and the output terminal of the CMOS inverter 105 is defined as a connection point g.
The voltage at the connection point g is expressed as voltage Vg
The current flowing through the CMOS inverter 103 (current input to the connection point g) is expressed as current iin
The current flowing through the CMOS inverter 105 (current input to the connection point g) is expressed as current io

  With this definition, the operation of the peak hold circuit 101 will be described. The peak hold circuit 101 shown in FIG. 5 adds the input signal (input voltage Vin) via the CMOS inverter 103 and the signal fed back with the voltage Vout via the CMOS inverter 105 at the connection point g. The level added at the connection point g controls the on / off (ON / OFF) of the NMOS 107.

  That is, on / off of the NMOS 107 is controlled by the relationship between the voltage Vin and the voltage Vout. The NMOS 107 serves as a switch for the threshold value Vth. The threshold value Vth is a value that is variably set according to the relationship between the voltage Vin and the voltage Vout.

  First, the case where the input voltage Vin is a high peak voltage will be described. At this time, since the peak hold circuit 101 operates such that the voltage Vg at the connection point g is balanced with the input voltage Vin, the voltage Vout moves in the direction of decreasing the voltage. Therefore, since the gate voltage of the NMOS 107 increases, the NMOS 107 is turned on. When the NMOS 107 is in an ON state, discharging is performed from the capacitor 108 via the NMOS 107 as shown in FIG. In FIG. 6, the flow of current due to this discharge is indicated by thick arrows. When the NMOS 107 is on, the voltage Vout at the output terminal 109 drops.

  On the other hand, when the input voltage Vin decreases, the peak hold circuit 101 operates so that the voltage Vg is balanced with the voltage Vin, so that the output Vout moves in the direction of increasing the voltage. Therefore, since the gate voltage of the NMOS 107 is lowered, the NMOS 107 is turned off when it becomes equal to or lower than the threshold value Vth. When the NMOS 107 is in an OFF state, as shown in FIG. 7, power is supplied to the capacitor 108 from a power source (not shown) via the resistor 106, and the capacitor 108 is charged. In FIG. 7, the current flow by this charge is shown by the thick arrow. When the NMOS 107 is off, the voltage Vout at the output terminal 109 rises. The rising level and time are determined by the time constants of the resistor 106 and the capacitor 108.

  This will be further described with reference to FIG. In FIG. 8, a broken line A represents a change in the input voltage Vin, a broken line B represents a change in the output voltage Vouta in the operational amplifier 61 shown in FIG. 3, and a dotted line C represents the peak hold circuit 101 shown in FIG. Represents a change in the voltage Vout. In FIG. 8, the waveforms of the operational amplifier 61 and the peak hold circuit 101 are overlapped for easy understanding of the peak hold operation in the peak hold circuit 101.

  Until the time t1, the NMOS 107 is in an off state, a current flows in the direction of the thick line shown in FIG. 7, and power is supplied from a power source (not shown) to the capacitor 108 and charged. . Therefore, the output voltage Vout is in a state of increasing with the time constant of the resistor 106 and the capacitor 108. When the level of the input voltage Vin is further increased, the output voltage Vout is controlled so as to be balanced with the voltage Vg, and the gate voltage of the NMOS 107 is increased. Therefore, at the time t1, the NMOS 107 is switched from the off state to the on state, the current flows in the direction of the thick line shown in FIG. 6, and the discharge from the capacitor 108 is started.

  At time t2 when the input voltage Vin starts to decrease, the output voltage Vout moves in the increasing direction with respect to the input voltage Vin. As a result, the gate voltage of the NMOS 107 is lowered, the NMOS 107 is switched from the on state to the off state, and charging of the capacitor 108 is started.

  The input voltage Vin varies from time t2 to time t3, but does not exceed the voltage equal to or higher than the peak at time t1, so that the NMOS 107 is kept off and the capacitor 108 is kept charged.

  At time t3, the input voltage Vin is the next peak voltage, and the output voltage Vout is controlled to decrease so as to match Vg, and the NMOS 107 is switched from the off state to the on state. When the NMOS 107 is turned on, a current flows in the direction of the thick line shown in FIG. 6, and discharge from the capacitor 108 is started.

  Similarly, at time t4, the NMOS 107 is switched off, at time t5, switched on, and at time t6, switched off.

  As described above, the output voltage Vout from the peak hold circuit 101 detects and holds the peak of the input signal up to the present time, and when the next peak voltage comes, the NMOS 107 is turned on. Detects the peak level of the input signal. Thus, in the peak hold circuit 101, peak hold is realized by turning on and off the NMOS 107.

  As described above, the peak hold circuit 101 shown in FIG. 5 can be configured by modifying the operational amplifier 61 shown in FIG. Therefore, the effect expected from the operational amplifier 61 can also be expected from the peak hold circuit 101, and the effect of the operational amplifier 61 described above can also be obtained from the peak hold circuit 101.

  Note that the switch constituted by the NMOS 107 may be a switch constituted by the PMOS. That is, a PMOS may be used instead of the NMOS 107. When the PMOS is used, a peak having a polarity opposite to that when the NMOS 107 is used can be detected.

  Although the peak hold circuit 101 shown in FIG. 5 is configured to include three CMOS inverters, CMOS inverters 103 to 105, the peak hold circuit 101 of the present invention is used when there are three CMOS inverters. Is not limited. The peak hold circuit 103 to which the present invention is applied only needs to be composed of an odd number (however, excluding 1) of CMOS inverters. In other words, a configuration in which a CMOS inverter is further added to the configuration of the peak hold circuit 101 shown in FIG. For example, it is also possible to configure the peak hold circuit 101 to which the present invention is applied, including five CMOS inverters and seven CMOS inverters.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a figure which shows the structure of an example of the conventional gain control circuit. It is a figure which shows the structure of an example of the conventional operational amplifier. It is a figure which shows the structure of one Embodiment of the operational amplifier to which this invention is applied. It is a figure which shows the structural example of a CMOS inverter. It is a figure which shows the structure of one Embodiment of the peak hold circuit to which this invention is applied. It is a figure explaining the flow of an electric current when NMOS is on. It is a figure explaining the flow of an electric current when NMOS is OFF. It is a figure explaining ON / OFF of NMOS in a peak hold circuit.

Explanation of symbols

  63 to 66 CMOS inverter, 103 to 105 CMOS inverter, 106 resistor, 107 NMOS, 108 capacitor

Claims (8)

A peak hold circuit including first to third semiconductor elements that invert a voltage input to an input terminal and output from an output terminal,
A terminal for inputting an externally input signal is connected to the input terminal of the first semiconductor element,
The output terminal of the first semiconductor element is connected to the input terminal of the second semiconductor element and the output terminal of the third semiconductor element,
The output terminal of the second semiconductor element is connected to the gate of a fourth semiconductor element having a different configuration from the first semiconductor element to the third semiconductor element,
A peak hold circuit, wherein one end of a resistor, one end of a capacitor, an input terminal of the third semiconductor element, and an output terminal for outputting a signal to the outside are connected to the drain of the fourth semiconductor element. The first semiconductor element to the third semiconductor element are CCMOS (Complementary Metal Oxide Semiconductor) configured by a pair of PMOS (Positive Metal Oxide Semiconductor) and NMOS (Negative Metal Oxide Semiconductor). Peak hold circuit. The peak hold circuit according to claim 1, wherein the fourth semiconductor element is an NMOS or a PMOS. The peak hold circuit according to claim 1, wherein the same semiconductor element as the first to third semiconductor elements is further added by an even number unit. An operational amplifier comprising a plurality of semiconductor elements that invert the voltage input to the input terminal and output from the output terminal,
A terminal for inputting a signal input from the outside is connected to the input terminal of the first semiconductor element,
An input terminal of a second semiconductor element is connected to an output terminal of the first semiconductor element;
An input terminal of a third semiconductor element is connected to an output terminal of the second semiconductor element;
An output terminal of the fourth semiconductor element and an output terminal for outputting a signal to the outside are connected to the output terminal of the third semiconductor element,
An operational amplifier in which an output terminal of the first semiconductor element and an input terminal of the second semiconductor element are connected to an output terminal of the fourth semiconductor element. The first semiconductor element to the fourth semiconductor element are CCMOS (Complementary Metal Oxide Semiconductor) configured by a pair of PMOS (Positive Metal Oxide Semiconductor) and NMOS (Negative Metal Oxide Semiconductor). Peak hold circuit. The peak hold circuit according to claim 5, wherein the same semiconductor element as the first to fourth semiconductor elements is further added by an even number unit. The first to fourth semiconductor elements having different conductances are configured,
The operational amplifier according to claim 5, wherein the gain is determined by a ratio of conductance of the first semiconductor element and conductance of the fourth semiconductor element.

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