JP2009099750A - Semiconductor package - Google Patents

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JP2009099750A
JP2009099750A JP2007269635A JP2007269635A JP2009099750A JP 2009099750 A JP2009099750 A JP 2009099750A JP 2007269635 A JP2007269635 A JP 2007269635A JP 2007269635 A JP2007269635 A JP 2007269635A JP 2009099750 A JP2009099750 A JP 2009099750A
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semiconductor package
chip
package according
chip carrier
bump set
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Wen-Jeng Fan
文正 范
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Powertech Technology Inc
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a stackable semiconductor package which enhances durability of a product and suppresses crevice spreading. <P>SOLUTION: The semiconductor package has a chip carrier 210, a chip 220, and a plurality of lower bump sets 230. The chip carrier 210 has an upper surface 211 on which a plurality of transfer pads 213 are installed and a lower surface 212 where a plurality of circumscribed pads 214 are installed. The chip 220 is installed at or electrically connected to the chip carrier 210. The lower bump sets 230 are made to correspond to or installed at a circumscribed pad group 214. The lower bump sets 230 coupled to the respective circumscribed pads 214 are composed of a plurality of conductor columns 231 and 232, and a solder material filling gap is formed between adjacent conductor columns 231 and 232 of the same lower bump set 230. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体パッケージを立体的に積み上げる技術に関し、特に多柱体を有する積み上げ可能な半導体パッケージに関する。このような半導体パッケージは高密度ＰＯＰ（Ｐａｃｋａｇｅ−Ｏｎ−Ｐａｃｋａｇｅ）モジュールに適用することができる。   The present invention relates to a technique for three-dimensionally stacking semiconductor packages, and particularly to a stackable semiconductor package having a multi-column body. Such a semiconductor package can be applied to a high-density POP (Package-On-Package) module.

電子機器の小型、軽量、および薄型化の発展に伴い、半導体パッケージの搭載に使用されるプリント回路基板の面積の小型化が求められている。ゆえに、半導体パッケージの立体積み上げ技術を用い、複数の積み上げ可能な半導体パッケージを縦方向に積み上げてＰＯＰモジュールを形成することにより、表面接合面積の小型化と素子配置の高密度化との要求を実現することが可能となる。しかし半導体パッケージの積み上げ過程において、半田付け欠陥が大きな課題として存在している。半導体パッケージ間の微小間隔、例えば端子と端子との間の半田接合界面は、応力に起因する断裂現象が生じることにより、電気ショートするという問題がある。
Ｆｕｊｉｔｓｕ（登録商標）社は特許文献１において、またＴｅｓｓｅｒａ（登録商標）社は特許文献２において、それぞれパッケージ積み上げに応用可能な微接触構造を開示しており、これらの微接触構造は柱状や針状のバンプを介して半田材内に半田接合される。 As electronic devices become smaller, lighter, and thinner, there is a need to reduce the area of printed circuit boards used for mounting semiconductor packages. Therefore, the three-dimensional stacking technology of semiconductor packages is used to form a POP module by stacking a plurality of stackable semiconductor packages in the vertical direction, thereby realizing the demands for reducing the surface junction area and increasing the element arrangement density. It becomes possible to do. However, soldering defects exist as a major problem in the process of stacking semiconductor packages. There is a problem that a short interval between semiconductor packages, for example, a solder joint interface between terminals, causes an electrical short circuit due to a tearing phenomenon caused by stress.
Fujitsu (registered trademark) in Patent Document 1 and Tessera (registered trademark) in Patent Document 2 disclose fine contact structures applicable to package stacking, and these fine contact structures are columnar or needle-shaped. Soldered into the solder material via the bumps.

図１に示すように、周知の積み上げ可能な半導体パッケージ１００は主に、チップキャリア１１０、チップ１２０および複数の単柱バンプ１３０を有する。前記チップキャリア１１０は、複数の転送パッド１１３を設置する上面１１１と複数の外接パッド１１４を設置する下面１１２とを有する。前記チップ１２０はチップキャリア１１０上に設置され、かつチップキャリア１１０のワイヤボンディング孔１１５を通る複数のボンディングワイヤ１２１を介してチップキャリア１１０に電気的に接続され、さらに封止体１４０を用い前記ボンディングワイヤ１２１を密封している。前記単柱バンプ１３０は、それぞれ外接パッド１１４群に対応または設置され、さらに半田材１５０を介して下方の積み上げ可能な半導体パッケージ１００の転送パッド１１３群と半田接合される。このように、微接触の形態が生み出されることにより信号ピン数と配線面積との増加を可能にし、さらにＰＯＰパッケージ積み上げの隙間を縮小することもできる。   As shown in FIG. 1, a known stackable semiconductor package 100 mainly includes a chip carrier 110, a chip 120, and a plurality of single pillar bumps 130. The chip carrier 110 has an upper surface 111 on which a plurality of transfer pads 113 are installed and a lower surface 112 on which a plurality of circumscribed pads 114 are installed. The chip 120 is installed on the chip carrier 110 and is electrically connected to the chip carrier 110 through a plurality of bonding wires 121 passing through the wire bonding holes 115 of the chip carrier 110, and the bonding is further performed using the sealing body 140. The wire 121 is sealed. The single pillar bumps 130 correspond to or are respectively installed on the circumscribed pads 114 group, and are soldered to the transfer pads 113 group of the semiconductor package 100 that can be stacked below via the solder material 150. As described above, the form of fine contact can be created, so that the number of signal pins and the wiring area can be increased, and further, the gap for stacking POP packages can be reduced.

しかし、応力に対する抵抗力が影響され易く、単柱バンプ群１３０の半田付け界面は応力を受ける際、裂け目は単柱バンプ群１３０の表面に沿い拡散して、電気ショートの問題が生じる。なお、パッケージ積み上げを行う際、前記半田材１５０のリフローにより半田材１５０は流動的になり、チップキャリア１１０の反りや押圧力が不均等になる場合、半田材１５０が溢れて拡散することにより、単柱バンプ群１３０間の微接点が電気ショートしてしまう。   However, resistance to stress is easily affected, and when the soldering interface of the single-column bump group 130 is subjected to stress, the cracks diffuse along the surface of the single-column bump group 130, resulting in a problem of electrical short. When the packages are stacked, the solder material 150 becomes fluid due to the reflow of the solder material 150, and when the warp or pressing force of the chip carrier 110 becomes uneven, the solder material 150 overflows and diffuses, The fine contact between the single pillar bump groups 130 is electrically short-circuited.

米国特許第６４７６５０３号明細書US Pat. No. 6,476,503 米国特許出願公開第２００６／０１３８６４７号明細書US Patent Application Publication No. 2006/0138647

本発明の主な目的は，多柱体を有する積み上げ可能な半導体パッケージを提供することである。このような半導体パッケージにおいて、各外接パッド上に設置されるバンプセットは複数の導体柱により構成され、半田付け面積を増大することが可能であり、製品の耐用性を大幅に向上させることができる。なお、バンプセットの半田付け界面形状を複雑化し、裂け目の悪化を防ぐことも可能となる。   A main object of the present invention is to provide a stackable semiconductor package having a multi-column body. In such a semiconductor package, the bump set installed on each circumscribed pad is composed of a plurality of conductor pillars, which can increase the soldering area, and can greatly improve the durability of the product. . It is also possible to complicate the soldering interface shape of the bump set and prevent the tear from getting worse.

本発明のもう一つの目的は、多柱体を有する積み上げ可能な半導体パッケージを提供することである。このような半導体パッケージにおいて、各外接パッド上に設置されるバンプセットは半田材充填隙間を有し、それにより、バンプセットは半田材が注入および収蔵される役割を果たし、たとえ基板に傾きあるいは反りが生じても半田材を圧縮し、電気ショート現象が発生するおそれはない。   Another object of the present invention is to provide a stackable semiconductor package having a multi-column body. In such a semiconductor package, the bump set installed on each circumscribed pad has a solder material filling gap, whereby the bump set serves to inject and store the solder material, even if it is tilted or warped on the substrate. Even if this occurs, there is no possibility that the solder material is compressed and an electrical short phenomenon occurs.

前記目的を達成するために、本発明は後記の技術的手段を採用している。本発明による積み上げ可能な半導体パッケージは主に、チップキャリア、チップおよび複数の下バンプセットを有する。チップキャリアは複数の転送パッドを設置する上面と複数の外接パッドを設置する下面とを有する。チップはチップキャリアに設置され電気的に接続される。下バンプセットは外接パッド群に対応または設置される。各外接パッドと連結する下バンプセットは複数の導体柱により構成され、同一下バンプセットの隣接する導体柱間に半田材充填隙間が形成される。   In order to achieve the above object, the present invention employs the following technical means. The stackable semiconductor package according to the present invention mainly comprises a chip carrier, a chip and a plurality of lower bump sets. The chip carrier has an upper surface on which a plurality of transfer pads are installed and a lower surface on which a plurality of circumscribed pads are installed. The chip is installed in a chip carrier and electrically connected. The lower bump set corresponds to or is installed on the circumscribed pad group. The lower bump set connected to each circumscribed pad is composed of a plurality of conductor pillars, and a solder material filling gap is formed between adjacent conductor pillars of the same lower bump set.

前記目的を達成するため、本発明による積み上げ可能な半導体パッケージは、さらに後記の技術を採用している。
前記積み上げ可能な半導体パッケージにおいて、半田材充填隙間は隣接する導体柱の頂部から底部に収束してもよい。
前記積み上げ可能な半導体パッケージにおいて、同一下バンプセットの導体柱はマトリックス配列にしてもよい。 In order to achieve the above object, the stackable semiconductor package according to the present invention further employs the following technology.
In the stackable semiconductor package, the solder material filling gap may converge from the top to the bottom of the adjacent conductor pillar.
In the stackable semiconductor package, the conductor pillars of the same lower bump set may be arranged in a matrix.

前記積み上げ可能な半導体パッケージにおいて、各下バンプセットは中央導体柱と複数の周辺導体柱を有してもよい。
前記積み上げ可能な半導体パッケージにおいて、さらに複数の上バンプセットを備えてもよく、上バンプセットは転送パッド群に対応または設置され、各転送パッド上に設置される上バンプセットは複数の導体柱により構成され、同一上バンプセットの隣接する導体柱間に半田材充填隙間が形成される。 In the stackable semiconductor package, each lower bump set may have a central conductor pillar and a plurality of peripheral conductor pillars.
The stackable semiconductor package may further include a plurality of upper bump sets, wherein the upper bump set corresponds to or is installed in a transfer pad group, and the upper bump set installed on each transfer pad is formed by a plurality of conductor pillars. Constructed, a solder material filling gap is formed between adjacent conductor columns of the same bump set.

前記積み上げ可能な半導体パッケージにおいて、各上バンプセットの導体柱は、縦方向に対応する下バンプセットの導体柱と交錯配置される。
前記積み上げ可能な半導体パッケージにおいて、上バンプセットの隣接する導体柱間に位置する半田材充填隙間は、対応する下バンプセットの隣接する導体柱間に位置する半田材充填隙間と同一距離、または直交している。 In the stackable semiconductor package, the conductor columns of each upper bump set are arranged so as to intersect with the conductor columns of the lower bump set corresponding to the vertical direction.
In the stackable semiconductor package, the solder material filling gap located between adjacent conductor columns of the upper bump set is equal to or orthogonal to the solder material filling gap located between adjacent conductor columns of the corresponding lower bump set. is doing.

前記積み上げ可能な半導体パッケージにおいて、チップキャリアは多層プリント回路基板にしてもよい。
前記積み上げ可能な半導体パッケージにおいて、チップキャリアはワイヤボンディング孔を有してもよく、複数のボンディングワイヤはワイヤボンディング孔を通りチップとチップキャリアとを電気的に接続させる。 In the stackable semiconductor package, the chip carrier may be a multilayer printed circuit board.
In the stackable semiconductor package, the chip carrier may have a wire bonding hole, and the plurality of bonding wires pass through the wire bonding hole to electrically connect the chip and the chip carrier.

前記積み上げ可能な半導体パッケージにおいて、さらに封止体を備えてもよく、封止体はワイヤボンディング孔に形成され、かつチップキャリアの下面に突出してボンディングワイヤ群を密封する。
前記積み上げ可能な半導体パッケージにおいて、チップの能動面をチップキャリアの上面に貼り付けてもよい。 The stackable semiconductor package may further include a sealing body. The sealing body is formed in a wire bonding hole and protrudes from the lower surface of the chip carrier to seal the bonding wire group.
In the stackable semiconductor package, the active surface of the chip may be attached to the upper surface of the chip carrier.

前記積み上げ可能な半導体パッケージにおいて、チップの背面はチップキャリアの上面に露出されてもよい。
前記積み上げ可能な半導体パッケージにおいて、チップはチップキャリアの下面に設置されてもよく、下バンプセットはチップの側辺に配列される。
前記積み上げ可能な半導体パッケージにおいて、チップの背面はチップキャリアの下面に露出されてもよい。 In the stackable semiconductor package, the back surface of the chip may be exposed on the top surface of the chip carrier.
In the stackable semiconductor package, the chip may be installed on the lower surface of the chip carrier, and the lower bump set is arranged on the side of the chip.
In the stackable semiconductor package, the back surface of the chip may be exposed on the bottom surface of the chip carrier.

前記積み上げ可能な半導体パッケージにおいて、さらに熱電対素子を備えてもよく、熱電対素子はチップの露出背面に形成される。
前記積み上げ可能な半導体パッケージにおいて、さらに密封フィルムを有してもよく、密封フィルムはチップキャリアの下面に形成される。
前記積み上げ可能な半導体パッケージにおいて、導体柱は狭い頂部と広い底部を備えた台形断面を有してもよい。 The stackable semiconductor package may further include a thermocouple element, and the thermocouple element is formed on the exposed back surface of the chip.
The stackable semiconductor package may further include a sealing film, and the sealing film is formed on the lower surface of the chip carrier.
In the stackable semiconductor package, the conductor post may have a trapezoidal cross section with a narrow top and a wide bottom.

（第１実施例）
本発明の第１実施例による積み上げ可能な半導体パッケージについて説明する。
図２には二個の積み上げ可能な半導体パッケージ２００が積み上げされた形状を示しているが、これに限らず上方により多くの積み上げ可能な半導体パッケージ２００を積み上げることができ、例えば、三個、四個あるいはより多くの積み上げ可能な半導体パッケージ２００を積み上げることが可能となる。各積み上げ可能な半導体パッケージ２００は主に、チップキャリア２１０、チップ２２０および複数の下バンプセット２３０を備える。チップキャリア２１０は多層プリント回路基板とすることが可能で、両面電気導通構造となる。またチップキャリア２１０は、チップキャリア２１０の第１パッドとしての複数の転送パッド２１３を設置する上面２１１と、第２パッドとしての複数の外接パッド２１４を設置する下面２１２とを有する。 (First embodiment)
A stackable semiconductor package according to a first embodiment of the present invention will be described.
Although FIG. 2 shows a shape in which two stackable semiconductor packages 200 are stacked, the present invention is not limited to this, and a larger number of stackable semiconductor packages 200 can be stacked, for example, three or four. Individual or more stackable semiconductor packages 200 can be stacked. Each stackable semiconductor package 200 mainly includes a chip carrier 210, a chip 220, and a plurality of lower bump sets 230. The chip carrier 210 can be a multilayer printed circuit board and has a double-sided electrical conduction structure. The chip carrier 210 also has an upper surface 211 on which a plurality of transfer pads 213 as first pads of the chip carrier 210 are installed, and a lower surface 212 on which a plurality of circumscribed pads 214 are installed as second pads.

前記チップ２２０はチップキャリア２１０に設置され電気的に接続されている。例えば、ダイアタッチ材を用いチップ２２０の能動面をチップキャリア２１０の上面２１１に貼り付け、さらにワイヤボンディング方式により形成されるボンディングワイヤ２２１を介してチップ２２０のボンディングパッドをチップキャリア２１０のインナーフィンガー（ｉｎｎｅｒ ｆｉｎｇｅｒ、図中未表示）に電気的に接続する。第１実施例では、チップキャリア２１０はワイヤボンディング孔２１５を有し、前記ボンディングワイヤ２２１はワイヤボンディング孔２１５を通り、チップ２２０とチップキャリア２１０とを電気的に接続する。チップ２２０の背面はチップキャリア２１０の上面２１１に露出させてもよい。また、チップ２２０の設置と電気接続を実現すべく、バンプ（図中未表示）を利用してチップ２２０をチップキャリア２１０にフリップチップ接合してもよい。   The chip 220 is installed on and electrically connected to the chip carrier 210. For example, a die attach material is used to attach the active surface of the chip 220 to the upper surface 211 of the chip carrier 210, and the bonding pads of the chip 220 are connected to the inner fingers of the chip carrier 210 via bonding wires 221 formed by a wire bonding method. Electrical connection to the inner finger (not shown in the figure). In the first embodiment, the chip carrier 210 has a wire bonding hole 215, and the bonding wire 221 passes through the wire bonding hole 215 to electrically connect the chip 220 and the chip carrier 210. The back surface of the chip 220 may be exposed on the upper surface 211 of the chip carrier 210. Further, the chip 220 may be flip-chip bonded to the chip carrier 210 using bumps (not shown in the drawing) in order to realize the installation and electrical connection of the chip 220.

さらに、積み上げ可能な半導体パッケージ２００は封止体２４０を有し、封止体２４０はモールディング（ｍｏｌｄｉｎｇ）やディスペンス（ｄｉｓｐｅｎｓｅ）の方式によりワイヤボンディング孔２１５に形成され、かつチップキャリア２１０の下面２１２より突出し、ボンディングワイヤ群２２１を密封する。   Further, the stackable semiconductor package 200 has a sealing body 240, which is formed in the wire bonding hole 215 by a molding or dispensing method, and from the lower surface 212 of the chip carrier 210. It protrudes and the bonding wire group 221 is sealed.

前記下バンプセット２３０は外接パッド群２１４に対応かつ設置され、前記各外接パッド２１４の上に下バンプセット２３０が連接している。図３に示すように、各外接パッド２１４上の下バンプセット２３０は複数の導体柱２３１、２３２より構成されている。各下バンプセット２３０は中央導体柱２３１と複数の周辺導体柱２３２とを有し、中央導体柱２３１により周辺導体柱２３２間の隙間が大き過ぎないように確保することが可能で、かつ中央導体柱２３１と周辺導体柱群２３２との間は等距離な微間隔となる。中央導体柱２３１および複数の周辺導体柱２３２は、電解メッキで形成される銅柱、ワイヤボンディングで形成される金柱、厚い銅層をエッチングした銅柱もしくは他の金属柱体としてもよい。さらに、同一下バンプセット２３０の中央導体柱２３１および複数の周辺導体柱２３２は、マトリックス配列にするのが望ましい。図４Ａと図４Ｂに示すように、同一下バンプセット２３０の隣接する中央導体柱２３１と周辺導体柱２３２との間に半田材充填隙間Ｓ１もしくはＳ２が形成される。半田材充填隙間Ｓ１は隣接する中央導体柱２３１と周辺導体柱２３２との間の頂部における距離であり、半田材充填隙間Ｓ２は隣接する中央導体柱２３１と周辺導体柱２３２との間の底部における距離である。また、半田材充填隙間は隣接する中央導体柱２３１と周辺導体柱２３２との頂部から底部に向かって収束すれば望ましく、すなわち半田材充填隙間Ｓ１は半田材充填隙間Ｓ２よりも大きくなり、リフロー温度となった半田材２５０は液状となり、毛細現象により中央導体柱２３１と周辺導体柱２３２との間の半田材充填隙間Ｓ１、およびＳ２内に注入、充満し、押圧により外へ溢れるという問題が発生しない。半田材２５０は、上方に位置する積み上げ可能な半導体パッケージ２００の外接パッド群２１４上の下バンプセット２３０と、下方に位置する積み上げ可能な半導体パッケージ２００の転送パッド群２１３とを半田付けし、ＰＯＰ形態にすることが可能となる。すなわち、前記中央導体柱２３１および周辺導体柱２３２は、半円錐体や半方錐体など、狭い頂部と広い底部を有する台形断面を有し、また、正負フォトレジストの選択とエッチング液の配分により露光過度、露光不足やエッチング不足の技術を用いることにより、中央導体柱２３１および周辺導体柱２３２の形状を作り出すことが可能である。   The lower bump set 230 is installed corresponding to the circumscribed pad group 214, and the lower bump set 230 is connected to the outer circumscribed pad 214. As shown in FIG. 3, the lower bump set 230 on each circumscribed pad 214 includes a plurality of conductor pillars 231 and 232. Each lower bump set 230 has a central conductor column 231 and a plurality of peripheral conductor columns 232, and the central conductor column 231 can ensure that the gap between the peripheral conductor columns 232 is not too large, and the central conductor column 231 The columns 231 and the peripheral conductor column group 232 are finely spaced at equal distances. The central conductor column 231 and the plurality of peripheral conductor columns 232 may be copper columns formed by electrolytic plating, gold columns formed by wire bonding, copper columns obtained by etching a thick copper layer, or other metal columns. Furthermore, it is desirable that the central conductor column 231 and the plurality of peripheral conductor columns 232 of the same lower bump set 230 are arranged in a matrix. As shown in FIGS. 4A and 4B, a solder material filling gap S <b> 1 or S <b> 2 is formed between the adjacent central conductor column 231 and the peripheral conductor column 232 of the same lower bump set 230. The solder material filling gap S1 is the distance at the top between the adjacent central conductor pillar 231 and the peripheral conductor pillar 232, and the solder material filling gap S2 is at the bottom between the adjacent central conductor pillar 231 and the peripheral conductor pillar 232. Distance. The solder material filling gap is preferably converged from the top to the bottom of the adjacent central conductor column 231 and the peripheral conductor column 232, that is, the solder material filling gap S1 is larger than the solder material filling gap S2, and the reflow temperature is increased. The solder material 250 becomes liquid, and the capillarity causes a problem that the solder material filling gaps S1 and S2 between the central conductor column 231 and the peripheral conductor column 232 are injected and filled, and overflows by pressing. do not do. The solder material 250 solders the lower bump set 230 on the circumscribed pad group 214 of the stackable semiconductor package 200 positioned above and the transfer pad group 213 of the stackable semiconductor package 200 positioned below to solder the POP. It becomes possible to form. That is, the central conductor column 231 and the peripheral conductor column 232 have a trapezoidal cross section having a narrow top and a wide bottom, such as a half cone and a half cone, and the selection of positive and negative photoresists and the distribution of the etchant. The shapes of the central conductor column 231 and the peripheral conductor column 232 can be created by using a technique of overexposure, underexposure, and etching.

半田材２５０は鉛フリー半田材にしてもよく、例えば錫９６．５%−銀３%−銅０．５%の半田材を使用した場合、リフロー温度は約２１７℃以上、最高約２４５℃から２６０℃にまで達し、半田接合の濡れ性が生じる。よって中央導体柱２３１および周辺導体柱２３２は銅柱、金柱もしくは前記リフロー温度よりも高い融点を有する金属から製造されてもよい。   The solder material 250 may be a lead-free solder material. For example, when a solder material of 96.5% tin, 3% silver, and 0.5% copper is used, the reflow temperature is about 217 ° C. or higher and the maximum is about 245 ° C. The temperature reaches 260 ° C., and wettability of the solder joint occurs. Therefore, the central conductor pillar 231 and the peripheral conductor pillar 232 may be manufactured from a copper pillar, a gold pillar, or a metal having a melting point higher than the reflow temperature.

したがって、下バンプセット２３０を使用した場合、半田付け面積の増大と半田付け形状の複雑化とにより、半田付けの信頼性を向上させ、半田付け裂け目の悪化を低下することが可能となる。たとえ応力の影響を受けて一つの周辺導体柱２３２が半田材２５０から断裂しても、中央導体柱２３１やほかの導体柱２３２は依然、半田材２５０と半田接合の状態を維持すれば断裂による電気ショート現象が生じることなく、ＰＯＰ製品耐用性をより向上させることができる。   Therefore, when the lower bump set 230 is used, the soldering reliability can be improved and the deterioration of the soldering tear can be reduced by increasing the soldering area and complicating the soldering shape. Even if one peripheral conductor column 232 is torn off from the solder material 250 due to the influence of stress, the central conductor column 231 and the other conductor columns 232 are still broken if the solder material 250 and the solder joint state are maintained. The POP product durability can be further improved without causing an electrical short phenomenon.

（第２実施例）
本発明の第２実施例による積み上げ可能な半導体パッケージについて説明する。
図５に示すように、積み上げ可能な半導体パッケージ３００は、主にチップキャリア３１０、チップ３２０および複数の下バンプセット３３０を備え、第１実施例とおおよそ同様であるが、さらに複数の上バンプセット３４０を備える。 (Second embodiment)
A stackable semiconductor package according to a second embodiment of the present invention will be described.
As shown in FIG. 5, a stackable semiconductor package 300 mainly includes a chip carrier 310, a chip 320, and a plurality of lower bump sets 330, which is substantially the same as the first embodiment, but further includes a plurality of upper bump sets. 340 is provided.

チップキャリア３１０は、複数の転送パッド３１３を設置する上面３１１と複数の外接パッド３１４を設置する下面３１２とを有する。チップ３２０は、チップキャリア３１０に設置され電気的に接続される。下バンプセット３３０は、外接パッド群３１４に対応かつ設置され、各外接パッド３１４と連結する下バンプセット３３０は複数の導体柱３３１から構成される。また、半田材３６０の充填と収蔵のために同一下バンプセット３３０の隣接する導体柱３３１間に、半田材充填隙間Ｓ３が形成される。   The chip carrier 310 has an upper surface 311 on which a plurality of transfer pads 313 are installed and a lower surface 312 on which a plurality of circumscribed pads 314 are installed. The chip 320 is installed on the chip carrier 310 and electrically connected thereto. The lower bump set 330 is installed corresponding to the circumscribed pad group 314, and the lower bump set 330 connected to each circumscribed pad 314 includes a plurality of conductor columns 331. Further, a solder material filling gap S <b> 3 is formed between adjacent conductor columns 331 of the same lower bump set 330 for filling and storing the solder material 360.

図５と図６に示すように、上バンプセット３４０は転送パッド群３１３に対応かつ設置され、各転送パッド３１３と連結する上バンプセット３４０は複数の導体柱３４１から構成される。また、同一の上バンプセット３４０の隣接する導体柱３４１間にも半田材充填隙間Ｓ４が形成される。好ましくは、各上バンプセット３４０の導体柱３４１は縦方向に対応する下バンプセット３３０の導体柱３３１と交錯配置すると、噛合いの効果が生ずる。なお、上バンプセット３４０の隣接する導体柱３４１の半田材充填隙間Ｓ４は、下バンプセット３３０の隣接する導体柱３３１の半田材充填隙間Ｓ３と、同一距離かつ直交している。よって、前記積み上げ可能な半導体パッケージ３００を積み上げする際、半田材３６０を用い、対応する下バンプセット３３０と上バンプセット３４０とを互いに連結するため、より大きな半田付け面積とより複雑な半田付け形状を得ることができ、ＰＯＰ装置の半田接合点の信頼性を高め、かつ半田材３６０の溢れ性も防止することが可能となる。   As shown in FIGS. 5 and 6, the upper bump set 340 corresponds to and is installed in the transfer pad group 313, and the upper bump set 340 connected to each transfer pad 313 includes a plurality of conductor columns 341. Also, a solder material filling gap S4 is formed between adjacent conductor columns 341 of the same upper bump set 340. Preferably, when the conductor pillars 341 of each upper bump set 340 intersect with the conductor pillars 331 of the lower bump set 330 corresponding to the vertical direction, a meshing effect is generated. It should be noted that the solder material filling gap S4 between adjacent conductor columns 341 of the upper bump set 340 is the same distance and orthogonal to the solder material filling gap S3 between adjacent conductor columns 331 of the lower bump set 330. Therefore, when stacking the stackable semiconductor packages 300, the solder material 360 is used and the corresponding lower bump set 330 and upper bump set 340 are connected to each other, so that a larger soldering area and a more complicated soldering shape are obtained. It is possible to improve the reliability of the solder joint point of the POP device and to prevent the solder material 360 from overflowing.

（第３実施例）
図７は、本発明の第３実施例による複数の積み上げ可能な半導体パッケージ４００が、プリント回路基板１０の上に積み上げられた状態を示している。積み上げ可能な半導体パッケージ４００は主にチップキャリア４１０、チップ４２０および複数の下バンプセット４３０を備える。チップキャリア４１０は、複数の第１パッド４１３、例えば転送パッドを設置する上面４１１、複数の第２パッド４１４、例えば外接パッドを設置する下面４１２を有する。第３実施例では、前記チップ４２０は、複数のバンプ４２１を有し、かつフリップチップ接合技術により前記バンプ４２１を介してチップキャリア４１０に設置かつ電気的に接続され、さらに前記バンプ４２１を底部充填剤を例とする封止体４４０により密封している。 (Third embodiment)
FIG. 7 illustrates a plurality of stackable semiconductor packages 400 according to the third embodiment of the present invention stacked on the printed circuit board 10. The stackable semiconductor package 400 mainly includes a chip carrier 410, a chip 420, and a plurality of lower bump sets 430. The chip carrier 410 has a plurality of first pads 413, for example, an upper surface 411 on which transfer pads are installed, and a plurality of second pads 414, for example, a lower surface 412 on which circumscribed pads are installed. In the third embodiment, the chip 420 has a plurality of bumps 421 and is installed and electrically connected to the chip carrier 410 via the bumps 421 by a flip chip bonding technique, and further, the bumps 421 are filled at the bottom. It is sealed by a sealing body 440 taking an agent as an example.

積み上げ可能な半導体パッケージ４００は、チップ４２０がチップキャリア４１０の下面４１２に設置されており、下バンプセット４３０はチップ４２０の側辺に配列されているため、チップキャリア４１０の上面４１１は平坦状になっているものの、チップ４２０の下バンプセット群４３０がぶつかり、損傷する可能性が低下する。一方放熱を有利にするため、チップ４２０の背面は、チップキャリア４１０の下面４１２に露出されてもよい。
下バンプセット４３０を第２パッド群４１４に対応かつ設置し、前記各第２パッド４１４と連結する下バンプセット４３０は複数の導体柱４３１から構成される。また、同一下バンプセット４３０と隣接する導体柱４３１間にも、半田材４５０が流入する半田材充填隙間が形成される。 In the stackable semiconductor package 400, the chip 420 is installed on the lower surface 412 of the chip carrier 410, and the lower bump set 430 is arranged on the side of the chip 420, so the upper surface 411 of the chip carrier 410 is flat. However, the lower bump set group 430 of the chip 420 collides and the possibility of damage decreases. On the other hand, the rear surface of the chip 420 may be exposed to the lower surface 412 of the chip carrier 410 in order to favor heat dissipation.
The lower bump set 430 is provided corresponding to the second pad group 414 and connected to the second pads 414, and the lower bump set 430 includes a plurality of conductor columns 431. A solder material filling gap into which the solder material 450 flows is also formed between the same lower bump set 430 and the adjacent conductor pillars 431.

図７に示すように、複数の積み上げ可能な半導体パッケージ４００はプリント回路基板１０の上に積み上げされる際、各積み上げ可能な半導体パッケージ４００はさらに、熱電対素子４６０、例えばＴＩＭ（Ｔｈｅｒｍａｌ Ｉｎｔｅｒｆａｃｅ Ｍａｔｅｒｉａｌ）もしくは放熱ソルタ（ｓｏｌｄｅｒ）を有すれば好ましい。前記熱電対素子４６０はチップ４２０の露出背面に形成され、均等放熱のためプリント回路基板１０や下方の積み上げ可能な半導体パッケージ４００のチップキャリア４１０に結合することができる。また各積み上げ可能な半導体パッケージ４００は、さらに底部充填剤を例とする密封フィルム４７０を有し、前記密封フィルム４７０はチップキャリア４１０の下面４１２に形成され、ＰＯＰ積み上げ隙間へのゴミの落下や沈積を避け、汚染や電気ショートを防ぐべく、半田材４５０とチップ４２０とを密封している。
以上、本発明をその好適な実施例に基づいて説明したが、本発明の保護範囲は別添の特許請求の範囲で限定されていて、この保護範囲を基準として、本発明の精神と範囲内に触れるいかなる変更や修正も、本発明の保護範囲に属する。 As shown in FIG. 7, when a plurality of stackable semiconductor packages 400 are stacked on the printed circuit board 10, each stackable semiconductor package 400 further includes a thermocouple element 460, for example, a TIM (Thermal Interface Material). Alternatively, it is preferable to have a heat dissipation solder. The thermocouple element 460 is formed on the exposed back surface of the chip 420 and can be coupled to the printed circuit board 10 or the chip carrier 410 of the semiconductor package 400 that can be stacked below for uniform heat dissipation. Each stackable semiconductor package 400 further includes a sealing film 470 exemplifying a bottom filler, and the sealing film 470 is formed on the lower surface 412 of the chip carrier 410 to drop or deposit dust in the POP stacking gap. The solder material 450 and the chip 420 are hermetically sealed in order to prevent contamination and electrical short circuit.
Although the present invention has been described based on the preferred embodiments thereof, the scope of protection of the present invention is limited by the appended claims, and within the spirit and scope of the present invention based on this scope of protection. Any changes or modifications that come into contact with the invention belong to the protection scope of the present invention.

周知の複数の積み上げ可能な半導体パッケージの断面図である。1 is a cross-sectional view of a plurality of known stackable semiconductor packages. 本発明の第１実施例による積み上げ可能な半導体パッケージが積み上げられた状態を示す断面図である。1 is a cross-sectional view illustrating a stacked state of stackable semiconductor packages according to a first embodiment of the present invention. 本発明の第１実施例による積み上げ可能な半導体パッケージの下バンプセットを示す斜視図である。It is a perspective view showing a lower bump set of a stackable semiconductor package according to a first embodiment of the present invention. 本発明の第１実施例による積み上げ可能な半導体パッケージにおいて、下バンプセットの複数の導体柱の頂部の位置関係を示す模式図である。In the semiconductor package which can be stacked by 1st Example of this invention, it is a schematic diagram which shows the positional relationship of the top part of the several conductor pillar of a lower bump set. 本発明の第１実施例による積み上げ可能な半導体パッケージにおいて、下バンプセットの複数の導体柱の底部の位置関係を示す模式図である。In the semiconductor package which can be stacked | stacked by 1st Example of this invention, it is a schematic diagram which shows the positional relationship of the bottom part of the several conductor pillar of a lower bump set. 本発明の第２実施例による積み上げ可能な半導体パッケージが積み上げられた状態を示す断面図である。It is sectional drawing which shows the state by which the stackable semiconductor package by 2nd Example of this invention was stacked. 本発明の第２実施例による積み上げ可能な半導体パッケージにおいて、上バンプセットおよび対応する下バンプセットの導体柱の位置関係を示す模式図である。In the semiconductor package which can be stacked | stacked by 2nd Example of this invention, it is a schematic diagram which shows the positional relationship of the conductor pillar of an upper bump set and a corresponding lower bump set. 本発明の第３実施例による積み上げ可能な半導体パッケージがプリント回路基板上に積み上げされた状態を示す断面図である。FIG. 6 is a cross-sectional view illustrating a stackable semiconductor package according to a third embodiment of the present invention stacked on a printed circuit board.

符号の説明Explanation of symbols

１０：プリント回路基板、２００：積み上げ可能な半導体パッケージ、２１０：チップキャリア、２１１：上面、２１２：下面、２１３：転送パッド、２１４：外接パッド、２１５：ワイヤボンディング孔、２２０：チップ、２２１：ボンディングワイヤ、２３０：下バンプセット、２３１：中央導体柱、２３２：周辺導体柱、２４０：封止体、２５０：半田材、３００：積み上げ可能な半導体パッケージ、３１０：チップキャリア、３１１：上面、３１２：下面、３１３：転送パッド、３１４：外接パッド、３２０：チップ、３２１：ボンディングワイヤ、３３０：下バンプセット、３３１：導体柱、３４０：上バンプセット、３４１：導体柱、３５０：封止体、３６０：半田材、４００：積み上げ可能な半導体パッケージ、４１０：チップキャリア、４１１：上面、４１２：下面、４１３：第１パッド、４１４：第２パッド、４２０：チップ、４２１：バンプ、４３０：下バンプセット、４３１：導体柱、４４０：封止体、４５０：半田材、４６０：熱電対素子、４７０：密封フィルム、Ｓ１：半田材充填隙間、Ｓ２：半田材充填隙間、Ｓ３：半田材充填隙間、Ｓ４：半田材充填隙間   10: printed circuit board, 200: stackable semiconductor package, 210: chip carrier, 211: upper surface, 212: lower surface, 213: transfer pad, 214: circumscribed pad, 215: wire bonding hole, 220: chip, 221: bonding Wire: 230: Lower bump set, 231: Central conductor column, 232: Peripheral conductor column, 240: Sealing body, 250: Solder material, 300: Stackable semiconductor package, 310: Chip carrier, 311: Upper surface, 312: Lower surface, 313: transfer pad, 314: circumscribed pad, 320: chip, 321: bonding wire, 330: lower bump set, 331: conductor pillar, 340: upper bump set, 341: conductor pillar, 350: sealing body, 360 : Solder material, 400: Stackable semiconductor package, 410: Chip Carrier, 411: upper surface, 412: lower surface, 413: first pad, 414: second pad, 420: chip, 421: bump, 430: lower bump set, 431: conductor pillar, 440: sealing body, 450: solder Material: 460: Thermocouple element, 470: Sealing film, S1: Solder material filling gap, S2: Solder material filling gap, S3: Solder material filling gap, S4: Solder material filling gap

Claims (15)

複数の第１パッドを設置する上面と複数の第２パッドを設置する下面を有するチップキャリアと、
チップキャリアに設置され電気的に接続されているチップと、
複数の下バンプセットであって、第２パッド群に対応して設置され、各第２パッド上の下バンプセットは複数の導体柱より構成され、同一下バンプセットの隣接する導体柱間に半田材充填隙間が形成される複数の下バンプセットと、
を備えることを特徴とする半導体パッケージ。 A chip carrier having an upper surface for installing a plurality of first pads and a lower surface for installing a plurality of second pads;
A chip installed in a chip carrier and electrically connected;
A plurality of lower bump sets, which are installed corresponding to the second pad group, the lower bump set on each second pad is composed of a plurality of conductor pillars, and solder is provided between adjacent conductor pillars of the same lower bump set. A plurality of lower bump sets in which a material filling gap is formed;
A semiconductor package comprising: 前記半田材充填隙間は、隣接する導体柱の頂部から底部に収束していることを特徴とする請求項１記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the solder material filling gap converges from a top portion to a bottom portion of adjacent conductor pillars. 同一下バンプセットの導体柱はマトリックス配列していることを特徴とする請求項１記載の半導体パッケージ。   2. The semiconductor package according to claim 1, wherein the conductor columns of the same lower bump set are arranged in a matrix. 各下バンプセットは中央導体柱と複数の周辺導体柱とを有することを特徴とする請求項１記載の半導体パッケージ。   2. The semiconductor package according to claim 1, wherein each lower bump set includes a central conductor pillar and a plurality of peripheral conductor pillars. 複数の上バンプセットを有し、前記上バンプセットは第一パッド群と対応し、かつ第一パッド群に設置され、各第一パッド上に設置される上バンプセットは複数の導体柱により構成され、同一上バンプセットの隣接導体柱の間に半田材充填隙間が形成されることを特徴とする請求項１記載の半導体パッケージ。   A plurality of upper bump sets, wherein the upper bump sets correspond to the first pad group and are installed in the first pad group, and the upper bump set installed on each first pad is constituted by a plurality of conductor pillars; 2. The semiconductor package according to claim 1, wherein a solder material filling gap is formed between adjacent conductor columns of the same upper bump set. 各上バンプセットの導体柱は、縦方向に対応する下バンプセットの導体柱と交錯配置されていることを特徴とする請求項５記載の半導体パッケージ。   6. The semiconductor package according to claim 5, wherein the conductor columns of each upper bump set are arranged in a crossing manner with the conductor columns of the lower bump set corresponding to the vertical direction. 前記上バンプセットの隣接導体柱間に位置する半田材充填隙間は、対応する下バンプセットの隣接導体柱間に位置する半田材充填隙間と同一距離または直交していることを特徴とする請求項５記載の半導体パッケージ。   The solder material filling gap located between adjacent conductor columns of the upper bump set is equal to or perpendicular to the solder material filling gap located between adjacent conductor columns of the corresponding lower bump set. 5. The semiconductor package according to 5. 前記チップキャリアは、多層プリント回路基板であることを特徴とする請求項１記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the chip carrier is a multilayer printed circuit board. 前記チップキャリアはワイヤボンディング孔を有し、複数のボンディングワイヤがワイヤボンディング孔を通りチップとチップキャリアとを電気的に接続していることを特徴とする請求項８記載の半導体パッケージ。   9. The semiconductor package according to claim 8, wherein the chip carrier has a wire bonding hole, and a plurality of bonding wires pass through the wire bonding hole to electrically connect the chip and the chip carrier. 封止体を有し、前記封止体はワイヤボンディング孔に形成され、チップキャリアの下面に突出し、ボンディングワイヤ群を密封することを特徴とする請求項９記載の半導体パッケージ。   The semiconductor package according to claim 9, further comprising a sealing body, wherein the sealing body is formed in a wire bonding hole, protrudes from a lower surface of the chip carrier, and seals the bonding wire group. 前記チップはチップキャリアの下面に設置され、前記下バンプセットはチップの側辺に配列されることを特徴とする請求項１記載の半導体パッケージ。   The semiconductor package according to claim 1, wherein the chip is installed on a lower surface of a chip carrier, and the lower bump set is arranged on a side of the chip. 前記チップの背面は、チップキャリアの下面に露出していることを特徴とする請求項１１記載の半導体パッケージ。   12. The semiconductor package according to claim 11, wherein a back surface of the chip is exposed on a lower surface of the chip carrier. 熱電対素子を有し、前記熱電対素子はチップの露出する背面に形成されることを特徴とする請求項１２記載の半導体パッケージ。   13. The semiconductor package according to claim 12, further comprising a thermocouple element, wherein the thermocouple element is formed on an exposed back surface of the chip. 密封フィルムを有し、前記密封フィルムはチップキャリアの下面に形成されることを特徴とする請求項１１記載の半導体パッケージ。   12. The semiconductor package according to claim 11, further comprising a sealing film, wherein the sealing film is formed on a lower surface of the chip carrier. 前記導体柱は、狭い頂部と広い底部のような台形断面を有することを特徴とする請求項１記載の半導体パッケージ。   2. The semiconductor package according to claim 1, wherein the conductive pillar has a trapezoidal cross section such as a narrow top and a wide bottom.
JP2007269635A 2007-10-17 2007-10-17 Semiconductor package Pending JP2009099750A (en)

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