JP2009099617A - Method of manufacturing semiconductor apparatus - Google Patents
Method of manufacturing semiconductor apparatus Download PDFInfo
- Publication number
- JP2009099617A JP2009099617A JP2007267135A JP2007267135A JP2009099617A JP 2009099617 A JP2009099617 A JP 2009099617A JP 2007267135 A JP2007267135 A JP 2007267135A JP 2007267135 A JP2007267135 A JP 2007267135A JP 2009099617 A JP2009099617 A JP 2009099617A
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- film
- nickel
- gold film
- substrate
- semiconductor device
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
Description
本発明は、半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device.
近年、大規模集積回路(LSI:Large Scale Integrated Circuit)に代表される半導体装置の高集積化に伴って、半導体装置の入出力ピンの多ピン化、狭ピッチ化が進展している。 In recent years, with the high integration of semiconductor devices typified by large scale integrated circuits (LSIs), the number of input / output pins of the semiconductor devices has been increased and the pitch has been reduced.
従来、半導体装置のボンディングパッドには、アルミニウム(Al)が用いられていた。入出力ピンの狭ピッチ化により、ボンディングパッドの面積が縮小するので、ボンディングパッドに接合されるワイヤのボンディング強度を維持するために、アルミニウム(Al)より、高いボンディング強度が得られる金(Au)が用いられるようになってきている。 Conventionally, aluminum (Al) has been used for bonding pads of semiconductor devices. Since the area of the bonding pad is reduced by narrowing the pitch of the input / output pins, gold (Au) that provides higher bonding strength than aluminum (Al) in order to maintain the bonding strength of the wire bonded to the bonding pad. Has come to be used.
然しながら、下地金属膜上に金膜を形成したボンディングパッドは、半導体装置の製造工程での熱履歴に起因して、下地金属が金膜の表面にパイルアップし、金膜の表面に下地金属の酸化物および水酸化物などの被膜が形成されるので、金本来のボンディング強度が得られないという問題がある。 However, in the bonding pad in which the gold film is formed on the base metal film, the base metal piles up on the surface of the gold film due to the thermal history in the manufacturing process of the semiconductor device, and the base metal is not formed on the surface of the gold film. Since a film of oxide, hydroxide, or the like is formed, there is a problem that the original bonding strength of gold cannot be obtained.
金膜の表面に形成された被膜の除去を、例えばアルゴン(Ar)プラズマを用いたスパッタリング法により行う場合、スパッタリング法は選択性を有していないので、ボンディングパッドの周りにダメージを与え、半導体装置の信頼性に影響を及ぼす問題がある。 When removing the coating formed on the surface of the gold film by, for example, a sputtering method using argon (Ar) plasma, the sputtering method has no selectivity. There are problems that affect the reliability of the device.
ボンディングパッドの周りの有機系保護膜などから飛散した炭素(C)がボンディングパッドに付着してボンディングパッドが汚染され、期待したボンディング強度が得られなくなる問題がある。 There is a problem that carbon (C) scattered from the organic protective film around the bonding pad adheres to the bonding pad, contaminates the bonding pad, and the expected bonding strength cannot be obtained.
金膜の表面に形成される被膜には、膜厚のばらつきがあるので、Arプラズマによるスパッタ条件(プラズマ出力、スパッタ時間など)を適正化するのに多大の労力を要するという問題がある。 Since the film formed on the surface of the gold film has a variation in film thickness, there is a problem that much labor is required to optimize the sputtering conditions (plasma output, sputtering time, etc.) by Ar plasma.
一方、半導体装置の電気的特性の検査において、半導体チップに形成されたテスト用アルミニウムパッドにテスターのプローブピンを当接して押圧し、テスト用パッド表面の酸化膜を除去して内部のアルミニウムを露出させることにより、テスト用パッドとテスターのプローブピンとの電気的接触を確保する方法が知られている(例えば、特許文献1参照。)。 On the other hand, in the inspection of the electrical characteristics of the semiconductor device, the tester probe pin is brought into contact with and pressed against the test aluminum pad formed on the semiconductor chip, and the oxide film on the surface of the test pad is removed to expose the inner aluminum. By doing so, a method for ensuring electrical contact between the test pad and the probe pin of the tester is known (see, for example, Patent Document 1).
特許文献1においては、テスト用パッドとテスターのプローブピンとの電気的接触が確保されればよいので、パッド表面の酸化物のみを除去し、パッド自体にはできるだけ傷をつけないようにしている。
然しながら、接合強度が要求されるボンディング用パッドについては何ら開示していない。
However, there is no disclosure of bonding pads that require bonding strength.
本発明は、信頼性の高い半導体装置の製造方法を提供することを目的とする。 An object of this invention is to provide the manufacturing method of a highly reliable semiconductor device.
本発明の一態様の半導体装置の製造方法は、第1の面にアルミニウム膜と、ニッケル系合金膜と、金膜とが積層されたボンディングパッドを有する半導体チップを形成する工程と、前記第1の面と反対の第2の面を基板側にして、前記半導体チップを前記基板上に載置する工程と、前記ボンディングパッドにピンを斜めに当接し、前記基板を前記ピンに対して相対的に上昇させ、前記ピンの先端を水平方向にスライドさせることにより前記金膜の表層を除去する工程と、前記表層が除去された金膜に接続導体を接合する工程と、を具備することを特徴としている。 According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including: a step of forming a semiconductor chip having a bonding pad in which an aluminum film, a nickel-based alloy film, and a gold film are stacked on a first surface; A step of placing the semiconductor chip on the substrate with the second surface opposite to the surface of the substrate facing the substrate; slopingly contacting a pin to the bonding pad; and relative to the pin And removing the surface layer of the gold film by sliding the tip of the pin in the horizontal direction, and joining the connection conductor to the gold film from which the surface layer has been removed. It is said.
本発明によれば、信頼性の高い半導体装置得られる。 According to the present invention, a highly reliable semiconductor device can be obtained.
以下、本発明の実施例について図面を参照しながら説明する。 Embodiments of the present invention will be described below with reference to the drawings.
本発明の実施例に係る半導体装置の製造方法について、図1乃至図3を用いて説明する。図1は半導体装置を示す図で、図1(a)はその断面図、図1(b)はその要部を示す拡大断面図、図2は半導体装置の製造工程を示すフローチャート、図3は半導体装置の製造工程の要部を順に示す断面図である。 A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B are diagrams showing a semiconductor device, FIG. 1A is a sectional view thereof, FIG. 1B is an enlarged sectional view showing an essential part thereof, FIG. 2 is a flowchart showing a manufacturing process of the semiconductor device, and FIG. It is sectional drawing which shows the principal part of the manufacturing process of a semiconductor device in order.
図1に示すように、半導体装置10は、第1の面11aにアルミニウム膜12と、ニッケル系合金膜13と、金膜14とが積層されたボンディングパッド15を有する半導体チップ11と、第1の面11aと反対の第2の面11bに対向し、半導体チップ11を載置する基板16と、半導体チップ11のボンディングパッド15と、ボンディングパッド15と半導体チップ11を囲うように基板16上に形成されたボンディングパッド17とを接続するワイヤ18(接続導体)とを具備している。
As shown in FIG. 1, the
ボンディングパッド15の周りは、絶縁膜20、例えばシリコン酸化膜およびシリコン窒化膜で囲われ、絶縁膜20上に保護膜21、例えばポリイミドが形成されている。これにより、ボンディングパッド15が保護されている。
The
基板16のボンディングパッド17は、基板16を貫通するビア(図示せず)を介して、基板16の底面に形成されたハンダボール19に接続されている。
The
半導体チップ11のボンディングパッド15、および基板16のボンディングパッド17は、例えば40μmの狭ピッチで、それぞれ配列されている。
The
半導体チップ11上には、別の複数の半導体チップが積層されている。積層された複数の半導体チップのボンディングパッド15は、それぞれワイヤ18を介して基板16のボンディングパッド17に接続されている。
On the
基板16の底面を露出して、基板16、半導体チップ11およびワイヤ18が一括して樹脂22でモールドされている。
The bottom surface of the
基板16のボンディングパッド17は、例えば半導体チップ11のボンディングパッド15と同様に、アルミニウム膜12と、ニッケル系合金膜13と、金膜14とが積層されている。
For example, the
ワイヤ18は、例えば金線で、一端が半導体チップ11のボンディングパッド15の金膜12の表層が、例えば4乃至10nm除去された後に露出した表面で、ニッケルの濃度が金に対するニッケルの存在比で0.1以下の表面に接合され、他端が基板16のボンディングパッド17の金膜12の表面に接合されている。
The
次に、半導体装置10の製造方法について説明する。図2は半導体装置の製造工程を示すフローチャート、図3は半導体装置の製造工程の要部を示す断面図である。
図2に示すように、周知の方法により半導体基板に電子回路、例えば集積回路を形成し、アルミニウムを真空蒸着し、フォトリソグラフィ法によりパターンニグして集積回路の周りにアルミニウム膜12を有するパッドを形成する。
Next, a method for manufacturing the
As shown in FIG. 2, an electronic circuit, for example, an integrated circuit is formed on a semiconductor substrate by a well-known method, aluminum is vacuum-deposited, and a pattern having a pattern is formed by photolithography to form a pad having an
次に、フォトリソグラフィ法により、半導体基板上にアルミニウム膜12を有するパッドに対応した開口を有するレジスト膜を形成する。
次に、レジスト膜をマスクとして、無電解メッキ法により、アルミニウム膜12上にニッケル合金膜13として、例えば燐(P)を1パーセント程度含有するニッケル膜を形成し、続けてニッケル合金膜13上に金膜14を形成し、アルミニウム膜12とニッケル合金膜13と金膜14とが積層されたボンディングパッド15を形成する。
Next, a resist film having an opening corresponding to the pad having the
Next, a nickel film containing, for example, about 1% of phosphorus (P) is formed as a
図3(a)は形成された後のボンディングパッド15を示す断面図である。
図3に示すように、無電解メッキ法による金膜14は緻密性が低く、粒界30が多数存在している。
FIG. 3A is a cross-sectional view showing the
As shown in FIG. 3, the
次に、半導体基板上にボンディングパッド15を囲うように絶縁膜20として、例えばCVD(Chemical Vapor Deposition)法によりTEOS(Tetra Ethyl Ortho Silicate)膜を形成し、プラズマCVD法によりシリコン窒化膜を形成する。
このとき、半導体基板は200〜400℃程度に加熱されるので、ボンディングパッド15に第1の熱履歴が加えられる。
Next, a TEOS (Tetra Ethyl Ortho Silicate) film is formed as an
At this time, since the semiconductor substrate is heated to about 200 to 400 ° C., the first thermal history is applied to the
次に、絶縁膜20を含む半導体基板の全面に保護膜21として、ポリイミドを塗布した後、半導体基板の裏面を研削して所定の厚さに仕上げ、半導体基板の裏面に樹脂フィルムを貼り付けた後、ブレードを用いて半導体基板をダイシングすることにより、半導体チップ11を得る。
Next, after applying polyimide as a
次に、半導体チップ11を、樹脂フィルムを介して基板16上に載置し、樹脂フィルムをキュアすることにより、半導体チップ11を基板16上にマウントする。
このとき、半導体基板は100〜150℃程度に加熱されるので、ボンディングパッド15に第2の熱履歴が加えられる。
Next, the
At this time, since the semiconductor substrate is heated to about 100 to 150 ° C., a second thermal history is applied to the
図3(b)は第1および第2の熱履歴が加えられた後のボンディングパッド15を示す断面図である。但し、絶縁膜20は省略されている。
図3(b)に示すように、第1の熱履歴が加えられたことにより、金膜14の下地のニッケル合金膜13から、ニッケルが粒界30を這い上がって、金膜14の表面にパイルアップすることにより、金膜14の表面にニッケルの被膜31が形成される。
FIG. 3B is a sectional view showing the
As shown in FIG. 3 (b), when the first thermal history is applied, nickel scoops up the
第1および第2の熱履歴が加えられている間に、ニッケルの被膜31が大気に晒されると、ニッケルは大気中の水分と反応し、ニッケルの酸化物および水酸化物が形成される。以後、ニッケルの酸化物および水酸化物を含むニッケルの被膜31を、単にニッケルの被膜31と称する。
When the
次に、金膜14の表面のニッケル濃度を求める。ニッケル濃度の測定は、例えばAES(Auger Electron Spectroscopy)により行なう。AESでは表面をスパッタリングして、濃度測定を繰り返すことにより、深さ方向分布を求めることができる。
Next, the nickel concentration on the surface of the
図4は金膜14中のニッケルの深さ方向分布の一例を示す図で、破線40が熱履歴(150℃×500h)を加えた場合のニッケルの深さ方向分布を示す図、実線41は熱履歴を加えない場合のニッケルの深さ方向分布を示す図ある。
FIG. 4 is a diagram showing an example of the depth direction distribution of nickel in the
図4に示すように、熱履歴を加えない場合は、ニッケル濃度(金に対するニッケルの存在比率)は0.03以下である。
一方、熱履歴を加えた場合は、ニッケル濃度は表面で0.2程度、深さ方向には徐々に減少し、深さ20nm程度で0.03程度とほぼ一定値を示した。
これから、金膜14の表面にニッケルがパイルアップしてニッケルの被膜31が形成されていることが認められる。
As shown in FIG. 4, when no thermal history is applied, the nickel concentration (the abundance ratio of nickel to gold) is 0.03 or less.
On the other hand, when the thermal history was applied, the nickel concentration was about 0.2 on the surface and gradually decreased in the depth direction, and showed a substantially constant value of about 0.03 at a depth of about 20 nm.
From this, it is recognized that nickel piles up on the surface of the
このように、ボンディングパッド15の熱履歴に応じて、金膜14中のニッケルの深さ方向分布データを予め求め、蓄積しておく。
As described above, according to the thermal history of the
次に、ニッケルの被膜31が形成された金膜14は十分なボンディング強度が得られないので、十分なボンディング強度が得られるように金膜14の表層の除去量を求める。
Next, since the
図5は金膜14の表面のニッケル濃度とボンディング強度との関係を示す図である。ボンディング強度の測定は、ボンディングパッド15に金ワイヤ18をボンディングし、引張り試験機にてワイヤ18に静荷重を印加し、破断した時の荷重からシェア強度を求めることにより行った。
FIG. 5 is a diagram showing the relationship between the nickel concentration on the surface of the
図5に示すように、ニッケル濃度が0〜0.4と大きくなるほど、シェア強度が280mN〜120mNと低下することが分かる。
破断モードはニッケル濃度により異なる。ニッケル濃度が0〜0.17程度の間では、破断モードはワイヤ18のボール内で破断するモードであり、金膜14とワイヤ18のボールとの接合強度は十分保たれていることが分かる。
As shown in FIG. 5, it can be seen that the shear strength decreases to 280 mN to 120 mN as the nickel concentration increases from 0 to 0.4.
The fracture mode depends on the nickel concentration. It can be seen that when the nickel concentration is about 0 to 0.17, the fracture mode is a mode in which the ball of the
一方、ニッケル濃度が0.28程度以上になると、破断モードは金膜14とワイヤ18のボールとの接合界面で破断するモードになり、金膜14とワイヤ18のボールとの接合強度が不足していることが分かる。
On the other hand, when the nickel concentration is about 0.28 or more, the fracture mode is a mode in which the fracture occurs at the bonding interface between the
ニッケル濃度が0.21〜0.26程度の間では、破断モードはボール内で破断するモードと界面で破断するモードが混在し、金膜14とワイヤ18のボールとの接合強度にばらつきがあることが分かる。
When the nickel concentration is about 0.21 to 0.26, the fracture mode includes a mode in which the fracture occurs in the ball and a mode in which the fracture occurs at the interface, and the bonding strength between the
これにより、マージン、例えば安全係数を2倍に見込んで、金膜14とワイヤ18のボールとの十分な接合強度を得るためには、ニッケル濃度を0.1以下に抑えることが必要である。
Thus, in order to obtain a sufficient bonding strength between the
図4に示すニッケル元素濃度の深さ方向分布から、十分な接合強度を得るためには、金膜14の表層を4nm以上削り取ることが望ましい。
但し、金膜14の表層を過剰に削り取っても効果は変わらないこと、および切削量のバラツキを考慮すると10nm以下とすることが望ましい。
In order to obtain sufficient bonding strength from the depth direction distribution of the nickel element concentration shown in FIG. 4, it is desirable to scrape the surface layer of the
However, if the surface layer of the
従って、金膜14の表面のニッケル濃度から、ニッケル濃度が所定値(0.1)以下になるように、予め求めたニッケルの深さ方向分布に基づいて金膜14の除去量が求められる。
Therefore, the removal amount of the
次に、半導体チップ11がマウントされた基板16をステージ上に載置し、表面にニッケルの被膜31が形成されたボンディングパッド15にピンを斜めに当接し、基板16をピンに対して相対的に上昇させ、ピンの先端を水平方向にスライドさせることにより金膜14の表層を除去する。
Next, the
図6は基板16の上昇量と金膜14の除去量の関係を示す図である。金膜14の除去量は、AFM(Atomic Force Microscopy)により表面状態を測定し、除去部と非除去部との段差から求めた。
FIG. 6 is a diagram showing the relationship between the amount of rise of the
図6に示すように、基板16の上昇量が10μm乃至80μm程度で、安定した除去量が得られることが判明した。
これは、上昇量が10μm以下と少な過ぎると、ピンの初期位置や、ピンの形状のバラツキにより、ピンとボンディングパッド15の当接が安定しなくなり、80μm以上と多すぎると、押圧力が過大になり金膜14を平滑に削り取ることが困難となるためである。ここで、上昇量の上限は固定されたものではなく、使用するピンの弾性などに依存して変化するものである。
このように、基板16の上昇量と金膜14の除去量との相関データを予め求め、蓄積しておく。
As shown in FIG. 6, it has been found that a stable removal amount can be obtained when the rising amount of the
This is because if the rising amount is too small as 10 μm or less, the contact between the pin and the
In this way, correlation data between the rising amount of the
図3(c)は金膜14の表層が除去された後のボンディングパッド15を示す断面図である。但し、絶縁膜20は省略されている。
図3(c)に示すように、ピン32を斜め上方から金膜14に当接し、例えばステージを10μm乃至80μm程度上昇させ、ピン32の先端32aをX方向(水平方向)にスライドさせることにより金膜14の表層が4nm乃至10nm平滑に削ぎ取られ、ニッケルの被膜31が除去される。
FIG. 3C is a cross-sectional view showing the
As shown in FIG. 3C, the
種々検討の結果、先端32aの表面粗さRaが0.04μm以下のときに、再現性よく金膜14の表層が4nm乃至10nm程度削り取ることができ、金膜14の表面33と表層が除去された金膜14の表面34との間に、4nm乃至10nmの段差Hが形成される。これにより、ニッケルの被膜31の無い清浄な金膜14を露出させることが可能である。
As a result of various studies, when the surface roughness Ra of the
また、ピン32の寸法精度、ピン32の進入角度のバラツキなどを考慮すると、ピン32の先端32aの曲率半径Rと直径Dの比(R/D)は、6以下であることが望ましい。
In consideration of the dimensional accuracy of the
図7はボンディングパッド15の金膜14の切削領域の表面状態を示す図である。表面状態の測定は、AFM(Atomic Force Microscopy)により行った。
図7に示すように、金膜14の切削領域は、ニッケルの被膜31が形成された領域より、平坦になっていることが分かる。
FIG. 7 is a view showing the surface state of the cutting region of the
As shown in FIG. 7, it can be seen that the cutting region of the
次に、半導体チップ11のボンディングパッド15と基板16のボンディングパッド17とにワイヤ18をボンディングする。
図8はボンディングパッド15の金膜14の切削領域とワイヤ18の接続領域との関係を示す図である。
図8に示すように、金膜14の切削領域50のサイズは、ボンディングパッド15にワイヤ18をボンディングしたときに、切削領域50とワイヤ18の接続部に形成されるボール51との重なり合う領域52が、ボール51の接合面積の1/2以上となるようにすることが望ましい。
Next,
FIG. 8 is a diagram showing the relationship between the cutting region of the
As shown in FIG. 8, the size of the cutting
次に、基板16の底面を露出して、基板16と、半導体チップ11と、ワイヤ18とを一体に樹脂22でモールドすることにより、図1に示す半導体装置が得られる。
Next, the bottom surface of the
以上説明したように、本実施例の半導体装置の製造方法は、アルミニウム膜12と、ニッケル系合金膜13と、金膜14とが積層されたボンディングパッド15にピンを当接して押圧し、金膜14の表層を削り取り、金膜14の表面に形成されたニッケルの被膜31を除去している。
As described above, the method of manufacturing the semiconductor device according to the present embodiment is such that the pin is brought into contact with and pressed against the
その結果、ニッケルの被膜31の無い清浄な金膜14が露出したボンディングパッド15とワイヤ18とを接合することができるので、十分に信頼性の高い理想的な接合状態が得られ、ボンディング強度が向上する。従って、信頼性の高い半導体装置得られる。
As a result, the
ここでは、ニッケルの表面濃度、金膜の除去量、基板上昇量を求める工程は、製造ロットごとに毎回行う必要はなく、経時変化の補償、製造条件の変更などに応じて適宜行えば十分である。 Here, the steps for determining the nickel surface concentration, the amount of removed gold film, and the amount of increase in the substrate do not have to be performed for each production lot, and it is sufficient if they are performed appropriately according to compensation for changes over time, changes in production conditions, etc. is there.
ワイヤ18が金ワイヤである場合について説明したが、アルミニウムワイヤ、銅ワイヤとすることも可能である。
Although the case where the
ニッケル系合金膜が、燐(P)を含有するニッケルである場合について説明したが、ニッケル(Ni)単体、硼素(B)を含有するニッケル、硼素(B)およびタングステン(W)を含有するニッケルであっても構わない。 Although the case where the nickel-based alloy film is nickel containing phosphorus (P) has been described, nickel (Ni) alone, nickel containing boron (B), nickel containing boron (B) and tungsten (W) It does not matter.
また、ニッケルの替わりに、コバルト(Co)単体、燐(P)を含有するコバルト、硼素(B)を含有するコバルト、燐(P)およびタングステン(W)を含有するコバルト、硼素(B)およびタングステン(W)を含有するコバルトなどでも構わない。 Further, instead of nickel, cobalt (Co) alone, cobalt containing phosphorus (P), cobalt containing boron (B), cobalt containing phosphorus (P) and tungsten (W), boron (B) and Cobalt containing tungsten (W) may be used.
10 半導体装置
11 半導体チップ
12 アルミニウム膜
13 ニッケル合金膜
14 金膜
15、17 ボンディングパッド
16 基板
18 ワイヤ(接続導体)
19 ハンダボール
20 絶縁膜
21 保護膜
22 樹脂
30 粒界
31 被膜
32 ピン
50 切削領域
51 ボール
52 重なり領域
DESCRIPTION OF
19
Claims (5)
前記第1の面と反対の第2の面を基板側にして、前記半導体チップを前記基板上に載置する工程と、
前記ボンディングパッドにピンを斜めに当接し、前記基板を前記ピンに対して相対的に上昇させ、前記ピンの先端を水平方向にスライドさせることにより前記金膜の表層を除去する工程と、
前記表層が除去された金膜に接続導体を接合する工程と、
を具備することを特徴とする半導体装置の製造方法。 Forming a semiconductor chip having a bonding pad in which an aluminum film, a nickel-based alloy film, and a gold film are laminated on a first surface;
Placing the semiconductor chip on the substrate with the second surface opposite to the first surface facing the substrate;
Removing the surface layer of the gold film by causing the pins to contact the bonding pads diagonally, raising the substrate relative to the pins, and sliding the tips of the pins in a horizontal direction;
Bonding the connection conductor to the gold film from which the surface layer has been removed;
A method for manufacturing a semiconductor device, comprising:
前記金膜の表面のニッケル濃度が所定値以下になるように、予め求めた前記ニッケルの深さ方向分布に基づいて前記金膜の除去量を求める工程と、
前記金膜が除去できる前記基板の上昇量を、予め求めた前記上昇量と前記除去量との関係に基づいて求める工程と、
を具備することを特徴とする請求項1に記載の半導体装置の製造方法。 Obtaining a nickel concentration on the surface of the gold film;
A step of determining the removal amount of the gold film based on a distribution in the depth direction of the nickel obtained in advance so that the nickel concentration on the surface of the gold film is a predetermined value or less;
A step of determining a rising amount of the substrate from which the gold film can be removed based on a relationship between the rising amount and the removal amount obtained in advance;
The method of manufacturing a semiconductor device according to claim 1, comprising:
Priority Applications (1)
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JP2007267135A JP2009099617A (en) | 2007-10-12 | 2007-10-12 | Method of manufacturing semiconductor apparatus |
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JP2007267135A JP2009099617A (en) | 2007-10-12 | 2007-10-12 | Method of manufacturing semiconductor apparatus |
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Family
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2007
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