JP2009094978A - Logarithmic amplifying circuit and ask demodulating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a logarithmic amplifying circuit and an ASK demodulating circuit capable of outputting with sufficient output characteristics without reducing an output amplitude remarkably even if a power of an input signal is small or large. <P>SOLUTION: In an input amplifying part 12, saturated amplifying circuits 32 and 42 of a saturated amplifying part 20 are cascaded. Each output from the saturated amplifying circuits 32 and 42 is rectified by a rectifying part 22 separated into rectifiers 60 and 64 and rectifiers 66 and 70. Output signals 72 and 76 from the rectifiers 60 and 64 are added by an adder 24, and output signals 78 and 82 from the rectifiers 66 and 70 are added by an adder 26. A weighting circuit 30 carries out weighting to the added output signal 86, and an adder 28 adds an added output 84 to a weighted added output 88. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a logarithmic amplifier circuit and an ASK (Amplitude Shift-Keying) demodulating circuit, and the logarithmic amplifier circuit according to the present invention is particularly suitable for application to a signal demodulating circuit for ASK modulated waves. The ASK demodulation circuit according to the present invention is suitable for use in a radio communication system.

  In general, an ASK (Amplitude Shift-Keying) demodulating circuit includes, for example, a logarithmic amplifier circuit, an integrating circuit, a comparator, and a data processing circuit, and the data processing circuit includes a bit synchronization circuit. In particular, the logarithmic amplifier circuit has a function of increasing linearly with respect to the logarithm of input power, and includes a plurality of saturation amplifier circuits, rectifiers and adders corresponding to the saturation amplifier circuits. The first stage saturation amplifier circuit is supplied with two input signals, and the first stage saturation amplifier circuit inputs the two output signals to the next stage saturation amplifier circuit. The next stage saturation amplifier circuit further receives the next stage saturation amplifier circuit. In this way, the saturation amplifier circuits are connected in cascade.

  The saturation amplifier circuit also supplies these two output signals to the rectifiers corresponding to each of the saturation amplifier circuits. Each rectifier supplies the rectified output signal to the adder. The adder adds the supplied rectified signals and supplies them to one end side of the integrating circuit and the comparator. Specifically, Japanese Patent Application Laid-Open No. H10-228707 discloses a logarithmic amplifier circuit.

  Here, when the saturation amplifier circuit is saturated in the logarithmic amplifier circuit, the DC (Direct Current) level of the rectifier is also saturated. If the gains of the saturation amplification circuits at all stages are the same, the output of the second stage saturation amplification circuit is the square of the output of the first stage saturation amplification circuit, and the output of the third stage saturation amplification circuit is the third power. Amplify. Thus, the nth stage saturation amplifier circuit amplifies the output signal to the power of n and the exponent. The logarithmic amplifier circuit is a sum of signals obtained by rectifying the outputs from the n saturation amplifier circuits, and increases in an approximate straight line with respect to the logarithm of input power.

  In addition, the logarithmic amplifier circuit has an output unit that changes the output current to a voltage. Generally, the output part of the logarithmic amplifier circuit includes a current mirror circuit using, for example, a p-channel FET (Field Effect Transistor). The output unit connects a resistor between the source and ground of the FET on the output side, and outputs an output signal between the source and ground. That is, the output unit converts a current flowing between the drain and source of the FET on the output side into a voltage by passing it through the resistor, and outputs the voltage at both ends of the resistor as an output voltage.

  Next, the ASK demodulation circuit is described. The ASK modulation signal is a signal on the amplitude of a carrier wave. For this reason, it is a modulated wave whose amplitude changes. When this modulated wave is input to the logarithmic amplifier circuit, the output signal output from the logarithmic amplifier circuit does not depend on the input power when the output signal indicated by the output voltage is in the linear region, and the modulation degree of the input ASK Thus, the output amplitude is determined, and a waveform corresponding to this is output.

  For example, when the input ASK modulated signal changes in the level range of the input signal, the output is output in the output level range indicated by the linear region. The waveform output from the logarithmic amplifier circuit is subjected to voltage comparison by a comparator with a reference voltage signal obtained by integrating the output waveform by an integrator, thereby discriminating between signals “1” and “0”.

Note that the slope of the output voltage with respect to the input power of the logarithmic amplifier circuit can be easily changed by a method such as changing the mirror ratio of the current mirror circuit described above.
JP-A-62-292010 JP 07-030353 A

  However, in the ASK demodulating circuit described above, when the power of the input signal is small, a part of the demodulated signal is buried in noise. Since the logarithmic amplifier circuit has a small output amplitude, the ASK demodulator circuit cannot be demodulated or the error rate is deteriorated. As a countermeasure, the ASK demodulator circuit can increase the output amplitude of the logarithmic amplifier circuit by increasing the slope of the input power versus the output voltage of the logarithmic amplifier circuit. However, if the power of the input signal is large due to this increase in slope, the output characteristics of the ASK demodulator circuit will be saturated, and the output amplitude of the logarithmic amplifier circuit will be significantly reduced. It gets worse.

  In view of such a problem, the present invention provides a logarithmic amplifier circuit and an ASK demodulator circuit that can output with sufficient output characteristics without significantly reducing the output amplitude regardless of whether the power of the input signal is small or large. Objective.

  In order to solve the above-described problems, the present invention rectifies the differential amplifying means cascaded in multiple stages and the outputs or inputs of the differential amplifying means at least divided into one and the other groups. Rectification means, first and second addition means for adding the rectified output signals for each of one and the other groups, and weighting means for weighting the output signals obtained by adding the rectified output signals in the other group And a third adding means for adding the added output of the rectified output signal and the added output of the weighted rectified output signal in one group.

  Further, in order to solve the above-mentioned problem, the present invention is configured such that the differential amplification means cascaded in multiple stages and the output or input of each of the differential amplification means are divided into at least one group and the other group. Rectifying means for rectifying, weighting means for weighting each rectified output signal in the other group, and adding means for adding each rectified output signal in one group and each rectified output signal in the weighted group It is characterized by that.

  Further, in order to solve the above-mentioned problems, the present invention provides an ASK demodulator circuit that demodulates an input signal modulated by ASK (Amplitude Shift-Keying). The ASK recovery circuit includes an input that amplifies the modulated input signal. The input amplifying means includes a differential amplifying means cascaded in multiple stages, and an output or an input of each of the differential amplifying means divided into at least one group and the other group to be rectified. Means, first and second adding means for adding the rectified output signals for each of the one and other groups, and weighting means for weighting the added output signals of the rectified output signals in the other group And a third adding means for adding the added output of the rectified output signal and the added output of the weighted rectified output signal in one group.

  In order to solve the above-described problems, the present invention provides an ASK demodulator that demodulates an input signal modulated by ASK (Amplitude Shift-Keying). The ASK recovery circuit is configured to amplify the modulated input signal. The input amplifying means includes a differential amplifying means cascaded in multiple stages, and an output or an input of each of the differential amplifying means divided into at least one group and the other group to be rectified. Means, weighting means for weighting each of the rectified output signals in the other group, and addition means for adding each of the rectified output signals in one group to each of the rectified output signals in the weighted group. And

  According to the logarithmic amplifier circuit of the present invention, the differential amplifying means are cascade-connected in multiple stages, and the outputs or inputs of the differential amplifying means are rectified by the rectifying means divided into at least one group and the other group. Then, for each of the one and other groups, the output signals rectified by the first and second adding means are added, and the weighted output signals of the rectified output signals in the other group are weighted by the weighting means. By adding the summed output of the rectified output signal in one group and the summed output of the weighted rectified output signal in the third adding means, input / output (voltage) in a region where the input power is small at the boundary An output characteristic having a large characteristic gradient and a small input / output (voltage) characteristic gradient in a large region can be obtained.

  Further, according to the logarithmic amplifier circuit according to the present invention, the same output characteristics can be obtained even when the rectified output signals are added after the weighting process.

  According to the ASK demodulator circuit of the present invention, the differential amplifying means are cascaded in the input amplifying means, and the outputs or inputs of the differential amplifying means are divided into at least one group and the other group, An output signal obtained by rectifying by the rectifying means, adding the output signals rectified by the first and second adding means for each of the one and other groups, and adding the rectified output signals in the other group by the weighting means. And the addition output of the rectified output signal in one group by the third addition means and the addition output of the weighted rectified output signal are added to the area where the input signal includes noise or the saturation area. Even in this case, a sufficient demodulated signal output can be obtained, and a reduction in error rate can be prevented.

  Further, according to the ASK demodulating circuit according to the present invention, it is possible to obtain satisfactory output characteristics from the input amplifying means even when the rectified output signals are respectively added after the weighting processing in the input amplifying means. A demodulated signal output can be obtained, and a reduction in error rate can be prevented.

  Next, an embodiment of a logarithmic amplifier circuit according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, in the logarithmic amplifier circuit according to the embodiment of the present invention, the saturation amplifier circuits 32 to 42 of the saturation amplifier 20 are cascaded, and the outputs of the saturation amplifier circuits 32 to 42 are connected to the rectifiers 60 to 64 and the rectifiers. Rectified by the rectifier 22 divided into 66 to 70, the output signals 72 to 76 from the rectifiers 60 to 64 are added by the adder 24, and the output signals 78 to 82 from the rectifiers 66 to 70 are added by the adder 26. Addition, weighting the output signal 86 added by the weighting circuit 30, and adding the addition output 88 weighted with the addition output 84 by the adder 28, input / output in a region where the input power is small at the boundary An output characteristic having a large (voltage) characteristic gradient and a small input / output (voltage) characteristic gradient in a large region can be obtained.

  In this embodiment, the logarithmic amplifier circuit of the present invention is applied to the ASK demodulator circuit 10. The illustration and description of parts not directly related to the present invention are omitted. In the following description, the signal is indicated by the reference number of the connecting line in which it appears.

  As shown in FIG. 2, the ASK demodulator circuit 10 includes an input amplifier 12, an integrator 14, a comparator 16, and a data processing circuit 18. The input amplifying unit 12 applies the logarithmic amplifier circuit of the present invention, and a schematic configuration is shown in FIG. The input amplifier 12 includes a saturation amplifier 20, a rectifier 22, adders 24, 26 and 28, and a weighting circuit 30. The saturation amplification unit 20 has n stages of saturation amplification circuits, and the variable n is an integer of 2 or more.

  The saturation amplification unit 20 in FIG. 1 includes saturation amplification circuits 32, 34,..., 36, 38, 40,. The saturation amplification circuits 32, 34,..., 36, 38, 40,..., And 42 are respectively in the first stage, the second stage, the m stage, the m + 1 stage, the m + 2 and the n stage. Indicates. The saturation amplification circuit 32 is supplied with an input signal 44 (Vin) from the outside to the input terminals (+) and (−). The saturation amplification circuit 32 supplies the output signal 46 to the saturation amplification circuit 34. The saturation amplifier circuit 34 receives the output signal 46 as an input signal. Subsequent saturation amplification circuits 34,..., 36, 38, 40,. That is, the saturation amplifier circuit 34 outputs the output signal 48 to the next stage. The saturation amplification circuit 36 inputs the output signal 50 of the previous stage as an input signal.

  The saturation amplification circuit 36 inputs the output signal 52 to the saturation amplification circuit 38 as an input signal. Similarly, the saturation amplification circuits 38, 40,..., And 42 supply output signals 54, 56,..., 58 to the saturation amplification circuits 40,.

  The rectifying unit 22 has n rectifiers, and the variable n is an integer of 2 or more. The rectifying unit 22 of the present embodiment includes rectifiers 60, 62,..., 64, 66, 68,. The rectifiers 60, 62, ..., 64, 66, 68, ..., 70 have outputs of saturation amplifier circuits 30, 32, 34, ..., 36, 38, 40, ..., and 42. Signals 46, 48, ..., 52, 54, 56, ..., and 58 are input as input signals, respectively. The rectifiers 60, 62, ..., 64 output m rectified output signals 72, 74, ..., and 76 to the adder 24. The rectifiers 66, 68,..., And 70 output (nm) rectified output signals 78, 80,. As described above, the rectifying unit 22 has two parts, that is, a part that outputs m output signals and a part that outputs (nm) output signals.

  The adder 24 adds the m rectified signals 72, 74,..., And 76 and outputs an output signal 84 resulting from the addition to the adder 28. Further, the adder 26 adds (nm) rectified output signals 78, 80,..., And 62 and outputs an output signal 86 resulting from the addition to the weighting circuit 30.

  The weighting circuit 30 has a function of inputting the output signal 86, multiplying the input signal by a weighting factor, and outputting the result. The weighting circuit 30 outputs the weighted output signal 88 to the adder 28.

  The adder 28 inputs the output signals 84 and 88 as input signals. The adder 28 adds the two input signals 84 and 88 and outputs the result as an output signal 90. The input amplifying unit 12 inputs the output signal 90 to the (+) input terminal 92 of the comparator 16 and the integrator 14.

  The integrator 14 integrates the supplied signal 90 over a predetermined time. The integrator 14 smoothes the signal by integrating, and supplies the smoothed signal 94 to the (−) input terminal 96 of the comparator 16.

  The comparator 16 compares the signal levels of the input signal 90 and the input signal 96. The comparator 16 outputs an output signal 98 indicating “1” or “0” to the data processing circuit 18 as an input signal according to whether the comparison results of the signal levels of the two input signals 90 and 96 are equal.

  The data processing circuit 18 includes a bit synchronization circuit 100. The bit synchronization circuit 100 receives an input signal 98, detects synchronization, and outputs a detection result. The ASK demodulation circuit 10 performs digital processing on ASK demodulation thereafter based on the detection result.

  Next, FIG. 3 and FIG. 4 show examples of essential circuits of the input amplifier 12 to which the logarithmic amplifier circuit according to the present invention is applied. In these main circuits, the N-channel FET is called an NMOS transistor, and the P-channel FET is called a PMOS transistor. FIG. 3 shows components and connections of the saturation amplification circuits 32, 34,..., 36 of the saturation amplification unit 20. The saturation amplifier circuit 32 of the first stage is connected so that the input signal 44 is supplied to the gate terminal of the NMOS transistor Mn11 and the gate terminal of the NMOS transistor Mn12 via the (+) and (−) input terminals (not shown). ing. The resistor R10 has one terminal 102 connected to the power supply voltage terminal Vdd and the other terminal 104 connected to the drain terminal of the NMOS transistor Mn11. The terminal 104 is connected to the gate terminals of the NMOS transistors Mn13 and Mn16. Further, the terminal 104 is connected to the gate terminal of the NMOS transistor Mn22 in the saturation amplifier circuit 34 in the second stage.

  The resistor R12 has one terminal 106 connected to the power supply voltage terminal Vdd and the other terminal 108 connected to the drain terminal of the NMOS transistor Mn12. The terminal 108 is connected to the gate terminals of the NMOS transistors Mn14 and Mn15. Further, the terminal 108 is connected to the gate terminal of the NMOS transistor Mn21 in the saturation amplifier circuit 34 in the second stage.

  The source terminals of the NMOS transistors Mn11 and Mn12 are commonly connected to the input terminal of the current source I10, and the output terminal of the current source I10 is grounded. The source terminals of the NMOS transistors Mn13 and Mn14 are commonly connected to the input terminal of the current source I12, and the output terminal of the current source I12 is grounded. Further, the source terminals of the NMOS transistors Mn15 and Mn16 are commonly connected to the input terminal of the current source I14, and the output terminal of the current source I14 is grounded.

  The second stage saturation amplification circuit 34,..., The mth stage saturation amplification circuit 36, and the nth stage saturation amplification circuit 42 shown in FIG. Are connected to the connection relations described above. The number of the second digit of the reference sign in the components in FIGS. 3 and 4 indicates the number of stages of the saturation amplification section.

  The drain terminals of the first to m-th stage NMOS transistors Mn13 to Mnm3 and the NMOS transistors Mn15 to Mnm5 are connected to the drain terminal and the gate terminal of the PMOS transistor Mp5 shown in FIG. The source terminal of the PMOS transistor Mp5 is connected to the power supply voltage terminal Vdd.

  (M + 1) to n-stage NMOS transistors Mn (m + 1) 3 to Mnn3 and the drain terminals of the NMOS transistors Mn (m + 1) 5 to Mnn5 are the drains of the PMOS transistor Mp6 as shown in FIG. Connected to terminal and gate terminal. The source terminal of the PMOS transistor Mp6 is connected to the power supply voltage terminal Vdd.

  The drain terminals of the first to m-th stage NMOS transistors Mn14 to Mnm4 and the NMOS transistors Mn16 to Mnm6 are connected to the drain terminal and gate terminal of the PMOS transistor Mp1 and the gate terminal of the PMOS transistor Mp2, respectively. The source terminals of the PMOS transistors Mp1 and Mp2 are connected to the power supply voltage terminal Vdd. The drain terminal of the PMOS transistor Mp2 is connected to the drain terminal of the PMOS transistor Mp4 and to one terminal 110 of the resistor Rout. The node terminal 110 is connected to the output terminal 112 (out) of the input amplifier unit 12.

  Further, the NMOS transistors Mn (m + 1) 4 to Mnn4 from (m + 1) to n stages, and the drain terminals of the NMOS transistors Mn (m + 1) 6 to Mnn6 are the drain terminal and gate terminal of the PMOS transistor Mp3, respectively. Also connected to the gate terminal of the PMOS transistor Mp4. The source terminal of the PMOS transistor Mp4 is connected to the power supply voltage terminal Vdd. The other terminal of the resistor Rout is grounded.

  When the gate width W and the gate length L of the transistor are set, when the value of the ratio W / L in the transistor is obtained, the ratio of the PMOS transistor Mp1 and the PMOS transistor Mp2 based on the obtained value is set to 1: 1. The ratio of Mp3 to PMOS transistor Mp4 is set to 1: k. The variable k has a relationship of k> 1.

  The ratio from the first stage to the n-th stage, that is, the NMOS transistors Mn13: Mn14 to Mnn3: Mnn4, is set to r: 1. The variable r has a relationship of r> 1. Similarly, the ratio from the first stage to the n-th stage, that is, the NMOS transistors Mn15: Mn16 to Mnn5: Mnn6 are also set to r: 1.

  The first stage rectifier 60 includes NMOS transistors Mn13, Mn14, Mn15 and Mn16, and current sources I12 and I14. The n-th stage rectifier 70 includes NMOS transistors Mnn3, Mnn4, Mnn5 and Mnn6, and current sources In2 and In4.

  Next, the operation of the input amplifier 12 to which the logarithmic amplifier circuit of the present invention is applied will be described. As described above, if the saturation amplification circuits at all stages have the same gain, the gain of the second stage is the square of the output of the first stage, and the gain of the third stage is the cube of the output of the first stage.・ ・ The output will increase with the magnitude of the exponent for the first stage output. When the saturation amplifier circuit is saturated, the DC output of the rectifier is also saturated. When the rectifier simply detects saturation, it is assumed that 1 is output from the rectifier.

  Based on this idea, in the case of input power that is finally saturated at the n-th stage, which is the final stage, 1 is output to the output of the rectifier for the first time after starting amplification with the n-th power gain of the output at the first stage. The weighting circuit 30 multiplies the output by k (k> 1) and finally outputs k. The input power of the magnitude that saturates the second stage from the last stage is saturated through the (n-1) stage amplifier circuit, so 1 is further added to the output 1 of the last stage to add weight. Supplied to circuit 30. The weighting circuit 30 multiplies this output by k and outputs 2k. Considering the same, the weighting circuit 30 outputs (n−m) k until the (m + 1) th stage saturation amplifier circuit 38 is saturated.

  Further, since the saturated input power up to the m-th stage does not pass through the weighting circuit 30 after the output of the rectifier 64, the output becomes (n−m) k + 1. Next, when the (m-1) th stage is saturated, the output becomes (n-m) k + 2. That is, the input amplifying unit 12 increases the output linearly with respect to the logarithm of the input power because a weight is added to the nth power of the gain as the output of the logarithmic amplifier circuit. Decrease and increase output linearly. This input / output relationship is shown in FIG.

  Returning to FIG. 4, the operation will be further described using a detailed circuit. Here, drain-source currents flowing through the PMOS transistors Mp1, Mp2, Mp3 and Mp4 are set as I1, I2, I3 and I4, respectively. The total output current of the first to m-th rectifiers 60 to 64 flows to the drain-source current I1 of the PMOS transistor Mp1. Since the PMOS transistors Mp1 and Mp2 form a current mirror circuit, a current similar to the current I1 flows through the current I2. The total output current of the rectifiers 66 to 70 in the (m + 1) th stage to the nth stage is a current I3 flowing through the PMOS transistor Mp3. Since the PMOS transistors Mp3 and Mp4 form a current mirror circuit, the current I4 multiplied by k flows. A current obtained by adding these currents I2 and I4 flows through the resistor Rout, and the flowing current is converted into a voltage. That is, the output voltage of the input amplifier 12 is R1 * (I1 + kI3).

  Next, the basic operation as the ASK demodulation circuit 10 will be described. The ASK modulated signal is a modulated wave whose amplitude is changed by placing the signal on the amplitude of the carrier wave. An ASK modulation signal 44 is input to the input amplifier 12. When the output of the input amplifying unit 12 is in the linear region based on the input power versus the output voltage in FIG. 5, there is almost no dependence due to the input power. The input amplifying unit 12 substantially determines the output amplitude based on the modulation degree of ASK modulation, and outputs a waveform obtained by applying a logarithmic weight to the sine wave.

  When the input ASK modulation signal 44 changes in the range 112 on the X axis shown in FIG. 5, the input amplifier 12 outputs the output signal 90 having a waveform that changes between the ranges 114 to the input terminals 92 of the integrator 14 and the comparator 16. Output to. The integrator 14 integrates the output signal 90. The integrator 14 outputs the integrated signal 94 to the input terminal 96 of the comparator 16.

  For example, the comparator 16 treats the signal 94 as a reference voltage signal and compares the voltage of the input signal 90 with the signal 94 to determine whether the signal “1” or “0” is output. The comparator 16 processes the data after the output signal is retimed by the bit synchronization circuit 100 of the subsequent data processing circuit 18 and the duty is corrected.

  By the way, as shown in FIG. 5, in the ASK demodulating circuit 10, when the input power of the ASK modulated wave is small and changes within the range 116, the input power in the range 116 originally includes thermal noise generated from elements in the circuit. Such noise components and external noise components are included. The area of noise is indicated by range 118. As described above, when the power of the input signal becomes smaller than a certain level, the output voltage of the input amplifier 12 does not change. The boundary level 120 that does not change is called a noise level.

  When the input power is small, the slope of the output characteristic indicated by the solid line 122 of the input power versus the output voltage of the input amplifier 12 is large, so that a large amplitude 124 is obtained although it is buried to some extent.

  On the other hand, when the slope of the output characteristics of the input amplification unit is small in the conventional ASK demodulation circuit, the output amplitude is small. For this reason, the comparator 16 at the subsequent stage cannot accurately compare the voltages, cannot demodulate, or the error rate is remarkably deteriorated.

  In the conventional ASK demodulation circuit, the output amplitude can be increased by increasing the slope of the output characteristic indicated by the dashed line 126.

  Next, in the ASK demodulating circuit 10, as shown in FIG. 5, the input power of the ASK modulated wave is large and may vary within a range 128. In the conventional ASK demodulator circuit, even when the input power is small, it is easy to demodulate, and when the slope is large like the output characteristic 126, the output voltage of the input amplifier 12 is too close to the power supply voltage Vdd, although not shown. The PMOS transistor cannot operate in the saturation region. For this reason, the conventional ASK demodulation circuit does not operate as a current mirror, and the voltage does not extend linearly. As a result, the conventional ASK demodulator circuit has almost no output amplitude, as apparent from FIG. 5, such that the output amplitude is in the range 130 or lower. As a result, the conventional ASK demodulator circuit cannot demodulate or the error rate is remarkably deteriorated.

  On the other hand, the ASK demodulator circuit 10 of this embodiment reduces the slope of the output characteristic 122 in the region where the input power is larger than the boundary 132. As a result, the input amplifying unit 12 lowers the output voltage from the saturation level and extends it to the range 134. Therefore, even if the input amplifying unit 12 is operated in the range 128, a sufficient amplitude can be obtained for the output voltage and demodulation is possible. When the ASK demodulator circuit 10 is used, the input power range that can be demodulated can be expanded as compared with the conventional demodulator circuit.

  In the conventional ASK demodulating circuit, the output amplitude in the range 128 can be increased by reducing the slope of the output characteristic indicated by the broken line 1136. However, the conventional ASK demodulation circuit is affected by noise in the input range where the input power is low as described above.

  In the ASK demodulator circuit 10 of this embodiment, when demodulating near the point 132 where the slope of the output characteristic of the input amplifier 12 changes, the duty is somewhat degraded in the output of the comparator 16, but the bit synchronization circuit 05 in the subsequent stage There is no problem because the duty can be corrected.

  The logarithmic amplifier circuit of Patent Document 2 is intended to suppress current consumption. The logarithmic amplifier circuit has input / output characteristics shown in FIGS. 5, 8, and 13 in the embodiment. These input / output characteristics are obtained by connecting a plurality of saturation amplifiers in a multistage manner, although the slope changes in the middle. These changes in inclination are changes that can normally occur.

  The linear region of the input / output characteristics in the embodiment of the present invention is also not actually a complete straight line, and the slope changes slightly. However, according to the present invention, it is possible to provide an input / output characteristic inclination that can be applied to a larger input power, except for a slight change in inclination.

  As described above, according to the present embodiment, the logarithmic amplifier circuit in which the slope of the input power versus the output voltage becomes small at a certain level of the input power is used in the ASK demodulator circuit 10, so that the range of input power that can be demodulated is increased. The effect of spreading can be achieved.

  In this embodiment, the differential input ASK demodulator circuit 10 is illustrated, but a single phase input may be used. In this embodiment, the weighting is performed after adding the rectified signals. However, it goes without saying that the embodiment can be applied even if the signals are added after the weighting. Specifically, the output of each differential amplification means cascaded in multiple stages is rectified, and the rectified output signal is divided into at least one group and the other group, and the rectified output in the other divided group It is preferable to include a weighting circuit 30 for weighting each of the signals, and an adder 28 for adding each of the rectified output signals in one divided group and each of the rectified output signals of the weighted group. Instead of weighting by the weighting circuit 30, the rectifiers 60, 62,..., 64 and the rectifiers 66, 68,.

It is a block diagram which shows the schematic structure of the input amplifier in the Example to which the logarithmic amplifier circuit which concerns on this invention is applied. FIG. 2 is a block diagram illustrating a schematic configuration of an ASK demodulator circuit to which the input amplifier of FIG. 1 is applied. FIG. 2 is a circuit diagram illustrating a configuration of a main part in the input amplifying unit of FIG. 1. FIG. 4 is a circuit diagram illustrating a configuration of a main part in the input amplification unit following FIG. 3. It is a graph which shows the input-output characteristic in the input amplification part of FIG.

Explanation of symbols

10 ASK demodulator
12 Input amplifier
20 Saturation amplifier
22 Rectifier
24, 26, 28 adder
30 Weight circuit

Claims (10)

Differential amplification means cascaded in multiple stages;
Rectifying means for rectifying the output or input of each of the differential amplifying means, at least divided into one and the other groups;
First and second adding means for adding the rectified output signals for each of the one and other groups;
Weighting means for weighting the summed output signal of the rectified output signal in the other group;
3. A logarithmic amplifier circuit comprising: a third adding means for adding the sum output of the rectified output signal and the weighted sum output of the rectified output signal in the one group.   2. The logarithmic amplifier circuit according to claim 1, wherein the logarithmic amplifier circuit has different conductances in the rectifying means of the one and other groups for each group.   3. The logarithmic amplifier circuit according to claim 1, wherein the logarithmic amplifier circuit is used for demodulation of ASK (Amplitude Shift-Keying). Differential amplification means cascaded in multiple stages;
Rectifying means for rectifying the output or input of each of the differential amplifying means, at least divided into one and the other groups;
Weighting means for weighting each rectified output signal in the other group;
A logarithmic amplifier circuit comprising: adding means for adding each of the rectified output signals in the one group and each of the rectified output signals in a weighted group.   5. The logarithmic amplifier circuit according to claim 4, wherein in the logarithmic amplifier circuit, conductances in the rectifying means of the one and other groups are different for each group.   6. The logarithmic amplifier circuit according to claim 4, wherein the logarithmic amplifier circuit is used for demodulation of ASK (Amplitude Shift-Keying). In an ASK demodulating circuit that demodulates an input signal modulated by ASK (Amplitude Shift-Keying), the ASK recovery circuit includes:
Input amplifying means for amplifying the modulated input signal;
The input amplification means includes differential amplification means cascaded in multiple stages;
Rectifying means for rectifying the output or input of each of the differential amplifying means, at least divided into one and the other groups;
First and second adding means for adding the rectified output signals for each of the one and other groups;
Weighting means for weighting the summed output signal of the rectified output signal in the other group;
3. An ASK demodulating circuit, comprising: a third adding means for adding the sum output of the rectified output signal and the weighted sum output of the rectified output signal in the one group.   8. The ASK demodulating circuit according to claim 7, wherein the input amplifying means has different conductances in the rectifying means of the one group and the other group for each group. In an ASK demodulating circuit that demodulates an input signal modulated by ASK (Amplitude Shift-Keying), the ASK recovery circuit includes:
Input amplifying means for amplifying the modulated input signal;
The input amplification means includes differential amplification means cascaded in multiple stages;
Rectifying means for rectifying the output or input of each of the differential amplifying means, at least divided into one and the other groups;
Weighting means for weighting each rectified output signal in the other group;
An ASK demodulating circuit comprising: adding means for adding each of the rectified output signals in the one group and each of the rectified output signals in a weighted group.   10. The ASK demodulating circuit according to claim 9, wherein the input amplifying means has different conductances in the rectifying means of the one and other groups for each group.

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