JP2009094100A - Sis element, sis mixer, element for superconducting integrated circuit, and manufacturing method of sis element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SIS element which can actualize SIS bonding of high quality and has high performance. <P>SOLUTION: As one embodiment of the present invention, the SIS element has a substrate, an SIS trilayer film formed on the substrate and having a lower electrode, an upper electrode, and a barrier layer formed while sandwiched between the upper electrode and lower electrode, a ground plane formed on the substrate, electrically connected to the lower electrode, and made of a material different from that of the lower electrode, the SIS trilayer film being formed on a buffer layer formed on the substrate or on the substrate in contact. In this constitution, the SIS trilayer film is formed on the buffer layer formed on the substrate or on the substrate in contact. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a SIS element, a SIS mixer, a superconducting integrated circuit element, and a method for manufacturing the SIS element.

In recent years, radio telescopes that focus radio waves and observe celestial bodies have been developed around the world. One of them, the Atacama Large Millimeter / Submillimeter Array (ALMA), is an international collaboration between Europe, North America, Japan, Taiwan, etc. on a vast plateau at an altitude of 5000 m in northern Chile, South America. It is a large-scale radio wave interferometer in the millimeter wave and submillimeter wave band that is being built by This large radio interferometer consists of 64 large interferometers (main array) consisting of 12m antennas and 4m small interferometers (compact array) consisting of 12m and 12m antennas. The ALMA is under construction with the aim of completion in the second half of 2011. Upon completion, ALMA has the world's highest sensitivity in the millimeter-wave and submillimeter-wave bands with a frequency of 30 to 950 GHz (wavelength 10 to 0.3 mm). A radio telescope with high resolution.

This radio telescope's high-sensitivity receiver has a superconductor-insulator-superconductor tunnel junction (SIS (Superconductor Insulator Superconductor) junction) element (SIS element), a heterodyne mixer (millimeter wave, submillimeter wave band) Hereinafter, it is used simply as a mixer (mixer) element. Since the mid-1980s, research and development of high-quality SIS junctions using Nb as a basic material and low-noise millimeter-wave and submillimeter-wave receivers using them has been conducted mainly by the present inventors at National Astronomical Observatory, etc. It was. In the ALMA plan, based on the technology and experience of low-noise receivers such as SIS mixers that have been accumulated so far, the development of higher-performance millimeter-wave and submillimeter-wave receivers and a large number of them The receiver will be manufactured.

FIG. 20 is a diagram showing an example in which a SIS element is applied to the telescope. Since the SIS element is located at the first stage of the receiver, it is directly linked to the sensitivity of the telescope. The SIS element is a device used for frequency conversion (mixing) of weak signals in the millimeter wave, submillimeter wave, and terahertz wave regions having a frequency of 100 GHz or more. In addition to the above-mentioned ALMA, these elements are widely used including the Nobeyama 45m telescope, NMA (Nobeyama Millimeter Array), and ASTE (Atacama Submillimeter Telescope Experiment).

FIG. 21 is a diagram showing an energy band of the SIS junction. FIG. 22 is a cross-sectional view of SIS bonding. Further, FIG. 23 is a diagram (vertical sectional view) showing the structure of a SIS element for frequencies of 700 GHz or less. Features of the superconducting tunnel junction diode include small gap energy (2Δ = 2.8 meV in the case of Nb), small LO power (about 10 μW to 100 μW) and low shot noise. The superconducting tunnel junction diode is also characterized by the fact that the density of states of electrons diverges above and below the energy gap, there is a very strong nonlinearity that is steeper than the photon energy, and a large conversion efficiency can be obtained.

In particular, SIS junctions that use niobium (Nb) as an electrode and aluminum oxide (AlOx) as a barrier have low leakage and a high gap voltage under the condition that they are produced directly on a specific wafer such as quartz. A technique for stably creating things has already been established. For this reason, at a frequency of 700 GHz or less, a structure as shown in FIG. 23 has been widely adopted in which an Nb / AlOx / Nb SIS three-layer film is directly formed on a wafer and a lower electrode also serves as a ground plane.

24 and 25 are diagrams showing the structure of a SIS element for a frequency of 700 GHz or more (for terahertz).

At frequencies above 700 GHz, the Nb superconducting gap frequency is near 700 GHz, so the loss in the Nb ground plane increases rapidly in proportion to the frequency. Therefore, a ground plane film is formed on the wafer with a material having a higher superconducting gap frequency than niobium (for example, niobium titanium nitride: NbTiN), and an Nb SIS junction similar to the above-described element is formed on the ground plane film as an insulating layer. A general method is to form the surrounding area covered.

Takashi Noguchi, “Radio wave detection technology using superconducting SIS elements”, Applied Physics, Vol. 76, No. 1, p.0039-0043 (2007) BD Jackson, G. de Lange, T. Zijlstra, M. Kroug, TM Klapwijk, and JA Stern, “Niobium titanium nitride-based superconductor-insulator-superconductor mixers for low-noise terahertz re-ceivers”, J. Appl. Phys 97, 113904 (2005) Teruhiko Matsunaga, Hiroyuki Maezawa, and Takashi Noguchi, “Characterization of NbTiN Thin Films Prepared by Reactive DC-Magnetron Sputtering”, IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 13, NO. 2, JUNE 2003 B. Leone, BD Jackson, JRGao, TM Klapwijk, WM Laauwen, G. de Lange, “Anomalous Pumped and Unpumped IV Characteristics of Nb SIS Terahertz Mixers with NbTiN Striplines”, Proc. Of the 11th Int. Symp. On Space THz Tech., Pp. 228.337, 2000. Ariyoshi et al., Applied Superconductivity, IEEE Trans.on Appl.Supercond, 13, 2, 1128-1131 (2003)

The present invention has been made in view of the above-described background art, and an object thereof is to provide a high-performance SIS element and the like.

According to this invention, in order to achieve the above-mentioned object, the configuration as described in the claims is adopted. Hereinafter, the present invention will be described in detail.

The first aspect of the present invention is:
A substrate,
A SIS three-layer film formed on the substrate and having a lower electrode, an upper electrode, and a barrier layer formed between the upper electrode and the lower electrode;
Formed on the substrate, electrically connected to the lower electrode, and a ground plane of a material different from the lower electrode,
The SIS three-layer film is a buffer layer formed on the substrate or an SIS element formed in contact with the substrate.

According to this configuration, the SIS three-layer film is formed on or in contact with the buffer layer formed on the substrate or on the substrate, so high-quality SIS bonding can be realized, and a high-performance SIS element can be obtained. .

The second aspect of the present invention is
The ground plane is in the SIS element described above, wherein the ground plane is electrically connected to the lower electrode at a peripheral edge of the lower electrode.

According to this configuration, since the ground plane is electrically connected to the lower electrode at the periphery of the lower electrode, the Joule heat generated by the SIS junction is released to the substrate, etc. An element is obtained.

The third aspect of the present invention is
The ground plane material is a material having a higher gap frequency than the material of the lower electrode, or a normal metal, in the SIS element described above.

According to this configuration, a SIS element with low noise can be obtained.

The fourth aspect of the present invention is
On the substrate, forming a SIS three-layer film having a lower electrode, an upper electrode, and a barrier layer formed between the upper electrode and the lower electrode;
A step of electrically connecting the lower electrode on the substrate and forming a ground plane with a material different from that of the lower electrode;
The SIS three-layer film is in a method of manufacturing a SIS element, wherein the SIS three-layer film is formed on or in contact with a buffer layer formed on the substrate.

According to this configuration, the SIS three-layer film is formed on or in contact with the buffer layer formed on the substrate or on the substrate, so high-quality SIS bonding can be realized, and a high-performance SIS element can be obtained. .

The fifth aspect of the present invention provides
The buffer layer material is the same material as that of the lower electrode.

According to this configuration, since the flatness of the base of the SIS three-layer film is improved, high-quality SIS bonding can be realized, and a high-performance SIS element can be obtained.

Note that the buffer layer is a layer also called a buffer layer. For example, a layer for providing a function as a base layer having good flatness when a film is formed thereon, or a lattice constant between substances. It is a layer for reducing a difference and a difference in thermal expansion coefficient.

According to the present invention, a high-performance SIS element or the like can be obtained.

Other objects, features, or advantages of the present invention will become apparent from the detailed description based on the embodiments of the present invention described later and the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Background to the idea]

As a result of daily research, the present inventors have found that the structure of the terahertz SIS element has several problems that may cause the following problems.

FIG. 26 is a diagram showing a point that may cause a problem with a terahertz SIS element.

 (1) In this structure, the junction leakage current tends to increase. The ground plane often has a stronger stress (in-film stress) than Nb. For this reason, if the barrier is damaged when the stress is released, it causes a leakage current. In addition, the surface state of the ground plane is different from that of the wafer. For this reason, the physical properties of Nb constituting the SIS junction are affected, and the properties of the junction may change. Furthermore, it is necessary to etch through the barrier. This is a matter that causes a short circuit around the SIS junction and causes a leakage current.

(2) Joule heat generated in the SIS joint tends to spread inside the joint. When there is a superconductor having a different gap energy between the SIS junction and the wafer, which is a low-temperature heat bath, the cooling efficiency (heat dissipation) deteriorates because heat does not easily escape from the SIS junction to the wafer.

(3) The surface of the ground plane is rough, which may adversely affect the high-frequency characteristics. The surface of the ground plane material such as NbTiN becomes particularly rough due to dry etching. The effect of this surface roughness on the high-frequency characteristics is not yet elucidated, but it cannot be denied that it may cause adverse effects.

FIG. 27 is a diagram illustrating an example of dcI-V characteristics when an Nb SIS junction is disposed on an NbTiN ground plane. In addition to a large leakage current, the gap voltage is lowered due to poor heat dissipation.

Because there is a possibility of such a problem, the noise at the junction increases even if the microstrip line (MSL) is reduced by using new materials such as NbTiN. As a whole, the effect was weak.

In other words, in order to realize a low-noise SIS mixer element at a frequency of 700 GHz or higher, the junction quality and thermal injuries are as good as a low-frequency SIS element with Nb as the ground plane, and the loss in the ground plane The inventors have paid attention to the fact that it is important to satisfy the demand for a small size.

[SIS element structure]

FIG. 1 is a diagram showing the structure of the SIS element of this embodiment. This element can also be used for terahertz.

Both the SIS junction trilayer and the ground plane are formed directly on the wafer. Paying attention to the structure in the horizontal direction, the three-layer film is formed in an island shape only around the junction, and is in contact with the ground plane at the periphery.

The characteristics of this structure are as follows.

First, the Nb SIS junction is in direct contact with the wafer (substrate), and most of the ground plane is made of a low-loss material. This suggests that the SIS junction with the same low leakage as the SIS element of the Nb ground plane can be produced by using the technology for producing the Nb SIS junction directly on the wafer. Furthermore, by adopting this structure, the Nb of the lower electrode of the SIS junction is in direct contact with the wafer, which leads to an improvement in the heat dissipation of the junction.

In addition, a barrier layer remains around the SIS junction. This suggests that the leakage current passing around the SIS junction can be suppressed. Note that although the barrier layer is left in the structure shown here, the barrier layer may be etched through the barrier layer or may be completely removed by etching.

Furthermore, the surface state of the ground plane is kept in a smooth state immediately after film formation. This is because according to the present embodiment, a process for performing dry etching on the ground plane is not particularly required. This suggests that the influence of the surface roughness of the ground plane on the high-frequency characteristics is reduced.

In particular, the SIS junction is not “ridden” on the NbTiN film, but has a structure that “contacts” the ground plane film (such as NbTiN) at the periphery of the small island-like SIS three-layer film. Also, both the SIS junction and the ground plane film are formed directly on the wafer.

That is, in this embodiment, the Nb SIS junction is in direct contact with the wafer, and most of the MSL ground plane is a low-loss material. For this reason, a SIS junction having the same characteristics as an all-Nb SIS element can be expected. Moreover, since a low-loss material is used, the loss in MSL is small. Furthermore, there is an advantage that the heat dissipation of the SIS junction is improved.

In addition, since it is not necessary to penetrate the SIS three-layer film, leakage current can be suppressed.

Furthermore, it is expected that the high frequency characteristics will be improved by eliminating the process of roughening the surface of the ground plane.

As described above, this embodiment employs a structure in which the Nb SIS junction does not ride on the MSL made of a low-loss material. Therefore, the present embodiment is extremely superior to the conventional SIS elements in that low-loss MSL and high-quality SIS junction are realized at the same time.

[Process Details]

FIG. 2 is a diagram showing a simplified SIS mixer element. A SIS junction is formed on the wafer, a ground plane is formed to cover the periphery of the SIS junction, and an insulating layer and a wiring layer are sequentially formed thereon. To explain the process, consider the case where only one such simplified SIS mixer element is fabricated in the center of the wafer. The bonding size shall be 1 μm.

There can be a plurality of methods for producing a device having a structure similar to the structure of the SIS mixer element described above. First, the most basic process steps are shown, and later derivative processes are also described.

It is as follows when the outline | summary of a process is shown in order.

A buffer layer made of Nb is formed on the substrate. Next, a barrier made of Al and aluminum oxide is formed between the lower electrode made of Nb, the upper electrode made of Nb, the upper electrode and the lower electrode in contact with the buffer layer. Forming a SIS trilayer film with layers. Next, the upper electrode is etched to such an extent that the upper surface of the barrier layer appears. Next, a ground plane made of NbTiN is formed on the substrate by contacting the lower electrode and the barrier layer by contacting the side surface of the lower electrode and the peripheral edge of the barrier layer. Next, the barrier layer is etched to such an extent that the upper surface of the lower electrode appears. Next, an insulating layer is formed on the upper electrode, the barrier layer, the lower electrode, and the substrate. Finally, a wiring layer electrically connected to the upper electrode is formed on the insulating layer.

Hereinafter, each process will be described in the following order.
(1) Nb deposition on the entire wafer surface (2) Nb / Al-AlOx / Nb SIS tri-layer film is formed in islands (3) SIS junction fabrication
(4) Ground plane deposition
(5) Forming an insulating layer on the entire wafer
(6) Etching holes for conduction
(7) Wiring layer deposition

[(1) Nb deposition on the entire wafer surface]

FIG. 3 is a diagram showing a process of depositing Nb on the entire wafer surface. First, Nb is formed by sputtering on the entire SiO ₂ wafer so as to have a film thickness of 100 nm. This process is performed by (1) improving the flatness of the device, and (2) making the Nb film thickness of this layer and the upper electrode substantially the same, and etching the upper electrode during the bond defining the junction. This is for visually confirming that the etching has been completed and has reached the barrier surface, and is not always necessary and can be omitted.

[(2) Nb / Al-AlOx / Nb SIS tri-layer film is formed into islands]

FIG. 4 is a diagram showing a process of forming an Nb / Al—AlOx / Nb SIS three-layer film in an island shape. By this process, a SIS three-layer film that is slightly larger than the bonding is formed by sputtering. After forming the resist pattern, a SIS three-layer film is formed by lift-off. In the figure, the case of a circle with a diameter of 5 μm is considered as an example.

Here, FIG. 5 is an enlarged view of the SIS three-layer film. In order from the film far from the wafer, the upper electrode Nb film thickness is 100 nm, the barrier layer Al-AlOx (or AlNx) film thickness is 10 nm, the lower electrode Nb film thickness is 100 nm, and the buffer layer Nb film thickness is 100 nm. Is formed.

[(3) Fabrication of SIS junction]

FIG. 6 is a diagram showing a manufacturing process of the SIS junction. In this process, the upper electrode of the SIS junction is defined by photolithography, and the surrounding Nb is removed by etching. Nb deposited on the entire wafer first is also completely removed in the region other than just below the three-layer structure. An Nb film thickness of 100 nm, a barrier layer (Al—AlOx (or AlNx)), and an Nb film thickness of 200 nm are formed in order from a film far from the wafer.

[(4) Ground plane deposition]

FIG. 7 is a diagram showing a resist pattern. First, a resist pattern larger than the junction and smaller than the lower electrode is formed by photolithography. Here, the case of a circle having a diameter of 3 μm is considered. The plane structure of the ground plane is also defined at the same time.

FIG. 8 is a diagram showing a process of removing the Al film. The barrier layer in a region not covered with the resist is removed by physical etching or wet etching so that conduction can be established between the lower electrode and the ground plane.

FIG. 9 is a diagram illustrating a ground plane film forming process and a lift-off process. As shown in the figure, a ground plane (NbTiN or the like) is formed and lifted off.

FIG. 10 is a diagram illustrating a process of forming an insulating layer on the entire wafer. As shown in the figure, the entire surface of the device is covered with an insulating layer (for example, SiO ₂ ).

FIG. 11 is a diagram showing a process of forming a hole for conduction by etching. A hole is formed by etching the insulating layer so that conduction can be established between the upper electrode of the junction and the wiring layer, or between the ground plane and the external circuit.

FIG. 12 is a diagram illustrating a process of forming a wiring layer. As shown in the figure, a wiring layer (such as an Al film thickness of 400 nm) is formed. Here, the planar structure is defined by photolithography.

In this way, a SIS mixer element can be obtained.

[Prototype results]

The device according to the present embodiment was actually prototyped along the above-described process. Here, the actual prototype process is shown using SEM photographs while comparing with the above-described process.

FIG. 13 is a diagram illustrating a process of forming a small island-like SIS three-layer film on a wafer. The right side of the figure is an SEM photograph of the SIS three-layer film that was actually fabricated.

FIG. 14 is a diagram showing an upper electrode cutting-out process. A SIS trilayer and photoresist are observed.

FIG. 15 is a diagram showing an NbTiN layer sputtering step. Photoresist over the SIS junction is observed.

FIG. 16 is a completed drawing of the SIS mixer element. The vicinity of the junction covered with the wiring layer is observed.

[Derivative process]

In the above-described process, the SIS three-layer film, the junction, and the ground plane are manufactured in this order. However, the device can be manufactured even if this order is changed.

For example, in the process shown above, the insulating film was etched to create a continuity between the junction and the wiring layer. However, if the SIS three-layer film, ground plane, and junction were fabricated in this order, the continuity was achieved by lift-off. It becomes possible. According to this method, regardless of the order, the final device structure is such that both the junction and the ground plane are directly on the wafer. For this reason, the SIS element can be made by selecting the optimum order according to the quality of the film on the Nb on the ground plane and the ease of processing.

[Physical properties]

FIG. 17 is a diagram showing a comparison of IV characteristics between the terahertz SIS element and the SIS element of the present embodiment. In the drawing, the SIS element for terahertz is expressed as NbTiN MSL, and the SIS element of this embodiment is expressed as NbTiN MSL. As shown in the figure, the SIS element of this embodiment has a small leakage current and a large gap voltage of about 2.8 mV.

FIG. 18 is a diagram showing a comparison of IV characteristics between the 500 GHz SIS element and the SIS element of the present embodiment. As shown in the figure, the SIS element of this embodiment achieves leakage current and gap voltage characteristics that are not inferior to those of a 500 GHz SIS element (all-Nb device), and is low in high frequency. It can be expected to operate with noise.

[Position relationship between ground plane, lower electrode, and barrier]

For easy understanding, the positional relationship between the ground plane, the lower electrode, and the barrier will be described.

FIG. 19 is a schematic diagram of the SIS element. As shown in the figure, the ground plane is electrically connected to the periphery of the lower electrode and the portion outside the junction. This connection is ensured by bringing a region (upper surface or side surface) of the surface of the lower electrode not covered by the upper electrode or the barrier into contact with the ground plane. The ground plane and the barrier may be in contact with each other. On the other hand, when the ground plane and the upper electrode come into contact with each other, a short circuit occurs.

[Other Embodiments]
Although the description has been focused on a specific form so far, the structure of the present embodiment can be generally applied when the material of the junction and the material of the ground plane are different.

In addition, the material of the electrode is not only when the lower electrode and the upper electrode are both Nb, but also when the lower electrode is Nb and the upper electrode is another superconducting material such as NbTiN, both the upper and lower electrodes are Nb such as NbN. The ground plane may be a superconductive material different from the electrode material such as MgB ₂ or a low loss normal conductive material such as Al.

The material of the tunnel barrier may be not only an AlOx barrier (aluminum oxide) but also an insulator such as AlN or MgO, or a semiconductor.

Many variations of the groundwork are possible. For example, there may be a buffer layer. Examples of the material for the buffer layer include insulators such as SiO _{2 and} Al ₂ O _3, superconductors / normal conductors such as Nb, and the like. The wafer (substrate) is not limited to quartz, but may be a dielectric material having a small dielectric loss in the signal frequency band, such as fused quartz, glass, silicon, and MgO.

Many variations are possible for the way of contact (electrical connection) between the SIS trilayer and the ground plane. For example, not only when the groundplane is riding on the trilayer, but conversely, the trilayer may be riding on the groundplane. In addition, neither of them may ride, and the trilayer and the groundplane may be connected to at least one of another metal and superconducting material. In addition, the Nb upper electrode may remain in a portion other than the trilayer junction (including a portion that conducts with the ground plane).

Many variations of the ground plane material are possible. The material of the ground plane may be a superconducting material having a higher gap frequency than the material of the lower electrode or a normal metal. For example, not only a high gap energy superconducting material such as NbTiN, but also other high gap energy superconducting materials such as NbN, MgB ₂ , and other oxide high temperature superconducting materials may be used. Further, a low-loss normal metal such as Al or Au may be used. Further, a normal metal having a low resistivity in the vicinity of 4K (for example, ρ _{4K to} 0.5 μΩ · cm in the case of aluminum) or a material having a resistivity equal to or lower than that of aluminum may be used as the ground plane material. The same material may be used for both the ground plane and the wiring.

Many variations of the insulating layer are conceivable. Any insulator material having a small dielectric loss in the signal frequency band, such as SiO ₂ , Al ₂ O ₃ , and Nb ₂ O ₅ , can be used in this embodiment.

Many variations of the process (manufacturing method) can be considered.

For example, many modifications can be considered for how to connect the trilayer and the wiring. In addition to the case where a hole is formed in the insulating layer by etching, the hole may be formed by lift-off at the time of forming the insulating layer.

Many variations of the process order are also conceivable.

For example, not only the order of trilayer formation, junction etching, and groundplane formation, but also the order of trilayer formation, groundplane formation, junction etching, and the order of groundplane formation, trilayer formation, junction etching may be changed. Good. In addition, when using these methods, extra Nb or the like may be deposited on the groundplane or around the device in order to suppress the etching of the groundplane.

It is also possible to anodize the periphery of the junction and the surface of the ground plane. The area where the trilayer and groundplane overlap is arbitrary. The entire groundplane may be made on the trilayer (or the lower electrode of the trilayer).

Further, the film formation method in the SIS element manufacturing method may be vapor deposition, a method using an electron beam, epitaxial growth, or the like.

The number of junctions may be one, or a plurality of junctions may be distributed in the form of dots (lumped constant circuit) or spread in a plane (distributed constant circuit).

As a use (application range), not only a SIS mixer for terahertz but also a device using a SIS junction or a tunnel type Josephson junction can be widely applied. For example, a SIS photon detector, a superconducting integrated circuit element, and the like.

[Summary]

As described above, in this embodiment, Nb SIS junction is directly fabricated on a quartz wafer, and low loss material such as NbTiN is used for most of the MSL ground plane. Are made smaller at the same time.

Microstrip line (MSL) materials, such as niobium titanium nitride (NbTiN), which have the characteristic of “low transmission loss even at 1 THz or higher”, have various reasons for `` Nb SIS on the film. Many of them have the difficulty of producing a junction. For this reason, even if the MSL of the SIS element for submillimeter waves and terahertz waves is reduced using these materials, the noise at the junction increases conversely, and the overall effect is weak. In the present embodiment, this problem is avoided, and a low-noise SIS mixer is realized even at 1 THz or more by combining a low-loss MSL material and an Nb SIS junction.

[Interpretation of rights, etc.]

The present invention has been described above with reference to specific embodiments. However, it is obvious that those skilled in the art can make modifications or substitutions of the embodiments without departing from the gist of the present invention. That is, the present invention has been disclosed in the form of exemplification, and the contents described in the present specification should not be interpreted in a limited manner. In order to determine the gist of the present invention, the claims section described at the beginning should be considered.

It will also be appreciated that illustrative embodiments of the invention achieve the above objects, but that many modifications and other examples can be made by those skilled in the art. The elements or components of each embodiment described in the claims, specification, drawings, and description may be employed in combination with one or more other elements. The claims are intended to cover such modifications and other embodiments, which are within the spirit and scope of the present invention.

It is a figure which shows the structure of the SIS element of this embodiment. It is a figure which shows the SIS mixer element simplified. It is a figure which shows the process of forming Nb into a film on the whole wafer surface. It is a figure which shows the process of forming the SIS three-layer film of Nb / Al-AlOx / Nb in island shape. It is an enlarged view of a SIS three-layer film. It is a figure which shows the preparation process of SIS joining. It is a figure which shows a resist pattern. It is a figure which shows the removal process of Al film | membrane. It is a figure which shows the film-forming process and lift-off process of a ground plane. It is a figure which shows the process of forming an insulating layer in the whole wafer. It is a figure which shows the process of forming the hole for conduction | electrical_connection by an etching. It is a figure which shows the process of forming a wiring layer into a film. It is a figure which shows the process of forming a small island-like SIS three-layer film on a wafer. It is a figure which shows an upper electrode cutting-out process. It is a figure which shows a NbTiN layer sputtering process. It is a completed drawing of a SIS mixer element. It is a figure which shows the comparison of the IV characteristic of the SIS element for terahertz, and the SIS element of this embodiment. It is a figure which shows the comparison of the IV characteristic of the SIS element for 500 GHz, and the SIS element of this embodiment. It is a schematic diagram of a SIS element. It is a figure which shows the example by which the SIS element is applied to the telescope. It is a figure which shows the energy band etc. of SIS junction. It is sectional drawing of SIS joining. It is a figure (sectional view of the perpendicular direction) showing the structure of a SIS element for frequencies of 700 GHz or less. It is a figure which shows the structure of the SIS element for 700 GHz or more frequency (for terahertz). It is a figure which shows the structure of the SIS element for 700 GHz or more frequency (for terahertz). It is a figure which shows the point which may become a problem of the SIS element for terahertz. FIG. 6 is a diagram illustrating an example of dcI-V characteristics when an Nb SIS junction is disposed on an NbTiN ground plane.

Claims (11)

A substrate,
A SIS three-layer film formed on the substrate and having a lower electrode, an upper electrode, and a barrier layer formed between the upper electrode and the lower electrode;
Formed on the substrate, electrically connected to the lower electrode, and a ground plane of a material different from the lower electrode,
The SIS three-layer film is a buffer layer formed on the substrate or is formed in contact with the substrate. 2. The SIS element according to claim 1, wherein the ground plane is electrically connected to the lower electrode at a peripheral edge of the lower electrode. 2. The SIS element according to claim 1, wherein the material of the ground plane is a superconducting material having a gap frequency higher than that of the material of the lower electrode or a normal metal. 2. The SIS element according to claim 1, wherein the material of the lower electrode is Nb, and the material of the ground plane is NbTiN. A substrate,
A buffer layer made of Nb and formed on the substrate;
Formed in contact with the buffer layer and formed between the lower electrode made of Nb, the upper electrode made of Nb, the upper electrode and the lower electrode, and made of Al and aluminum oxide. A SIS trilayer film having a barrier layer to be
A ground plane formed on the substrate, electrically connected to the lower electrode by contacting the periphery of the lower electrode, and made of NbTiN;
An insulating layer formed on the upper electrode, the barrier layer, the lower electrode and the substrate;
A SIS element comprising: a wiring layer formed on the insulating layer and electrically connected to the upper electrode. A SIS mixer comprising the SIS element according to any one of claims 1 to 5. 6. A superconducting integrated circuit device comprising the SIS device according to claim 1. Description: On the substrate, forming a SIS three-layer film having a lower electrode, an upper electrode, and a barrier layer formed between the upper electrode and the lower electrode;
A step of electrically connecting the lower electrode on the substrate and forming a ground plane with a material different from that of the lower electrode;
The method of manufacturing a SIS element, wherein the SIS three-layer film is formed in contact with a buffer layer formed on the substrate or the substrate.   9. The method of manufacturing a SIS element according to claim 8, wherein the material of the buffer layer is the same material as that of the lower electrode. Forming a buffer layer made of Nb on the substrate;
A barrier made of Al and aluminum oxide, in contact with the buffer layer, formed between the lower electrode made of Nb, the upper electrode made of Nb, and the upper electrode and the lower electrode. Forming a SIS trilayer film having a layer;
Etching the upper electrode to such an extent that the upper surface of the barrier layer appears;
Forming a ground plane made of NbTiN as a material on the substrate by electrically connecting to the lower electrode by contacting the periphery of the lower electrode;
Etching the barrier layer to such an extent that the upper surface of the lower electrode appears;
Forming an insulating layer on the upper electrode, the barrier layer, the lower electrode and the substrate;
And a step of forming a wiring layer electrically connected to the upper electrode on the insulating layer. Forming a buffer layer made of Nb on the substrate;
A barrier made of Al and aluminum oxide, in contact with the buffer layer, formed between the lower electrode made of Nb, the upper electrode made of Nb, and the upper electrode and the lower electrode. Forming a SIS trilayer film having a layer;
Etching the upper electrode and the barrier layer to an extent that penetrates the barrier layer;
Forming a ground plane made of NbTiN as a material on the substrate by electrically connecting to the lower electrode by contacting the periphery of the lower electrode;
Forming an insulating layer on the upper electrode, the barrier layer, the lower electrode and the substrate;
And a step of forming a wiring layer electrically connected to the upper electrode on the insulating layer.