JP2009093598A - Power supply control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply control circuit for detecting a failure of a power supply circuit without providing an additional external element for detection and a terminal for detection. <P>SOLUTION: An error amplifier 25 included in an IC 2 for control outputs a control signal corresponding to a difference between supply voltage Vcc and reference voltage to a power supply control terminal 11 for applying the control signal to external transistors 15 and 8. A failure detection circuit 26 detects power supply failure when the signal level of the power supply control terminal 11 changes to a GND level different from a normal state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power supply control circuit that generates a power supply voltage of a predetermined level by controlling an external step-down transistor.

In an ECU (Electronic Control Unit) mounted on a vehicle, a transistor is controlled from a battery power supply of about 12V to generate a 5V power supply, which is supplied as an operating power supply for a microcomputer constituting the ECU. In this case, if a short circuit failure occurs with the battery power supply, the generation of the 5V power supply becomes impossible. As a technique for detecting such a short circuit fault, there is a technique for detecting a voltage drop when an overcurrent flows through an external resistance element (Patent Document 1).
Further, in Patent Document 2, as a result of the progress of low power consumption of the ECU, when a current that exceeds the current consumption and flows from the outside to the power output line via the input protection circuit is generated, an excessive current is provided. A power supply circuit provided with a configuration for sinking is disclosed.
JP 2006-254657 A JP-A-2005-71320

  However, the configuration of Patent Document 1 has a problem that an external resistor element and a terminal for monitoring the terminal voltage of the resistor element are required. Further, since Patent Document 2 is not originally configured for the purpose of detecting an abnormal state such as a short circuit fault, even when an excessive current flows as a result of the occurrence of a short circuit fault, the current is absorbed. As a result, failure may not be detected.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a power supply control circuit capable of detecting a failure of a power supply circuit without providing an extra detection element or a detection terminal. It is in.

  According to the power supply control circuit of the first aspect, the error amplifier built in the circuit has a difference between the power supply voltage and the reference voltage at the power supply control terminal for applying the control signal to the external step-down transistor. In the configuration for outputting a control signal corresponding to the power supply, the abnormality detection circuit detects a power supply abnormality when the signal level of the power supply control terminal changes to a state different from the normal state. That is, when a short circuit failure occurs in the step-down transistor, the power supply voltage increases, so that the difference from the reference voltage increases, and the error amplifier changes the control signal in a direction to turn off the step-down transistor. As a result, the output signal level of the error amplifier, that is, the control signal level of the power supply control terminal changes from the level indicated when the control state is normal. Therefore, it is possible to detect a power supply abnormality without requiring extra external elements and terminals for abnormality detection.

  According to the power supply control circuit of the second aspect, the abnormality detection circuit detects a power supply abnormality when the output signal level inside the error amplifier changes to a state different from the normal state. In other words, if the output terminal of the stepped down power supply is grounded, or if a part of the connection between the power supply control circuit and the external circuit including the step-down transistor is disconnected, the power supply voltage decreases, so the error amplifier The control signal is changed in a direction to turn on the step-down transistor. Here, in the case of current control of the step-down transistor, since the voltage level of the power supply control terminal does not change even when the current increases, it is determined whether or not the output signal level inside the error amplifier has changed from the normal state. By monitoring, a power supply abnormality can be detected as in the first aspect.

  According to the power supply control circuit of claim 3, the error amplifier is connected between the operational amplifier that outputs an amplified signal corresponding to the difference between the power supply voltage and the reference voltage, and between the power supply control terminal and the ground, and the output of the operational amplifier The abnormality detection circuit is configured to detect a power supply abnormality when the output signal level of the operational amplifier changes to a state different from the normal state. In this case, when a failure such as that described in claim 2 occurs, the output signal level of the operational amplifier changes so as to become the ground level. Therefore, it is possible to detect a power supply abnormality by capturing the change in the signal.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a power supply circuit used in an electronic control unit (ECU) of a vehicle. The power supply circuit 1 includes a control IC (power supply control circuit) 2 and an external circuit unit 3. The power supply circuit 1 is a series regulator type constant voltage power supply circuit that generates the power supply voltage Vcc (5 V) using the battery voltage VB (12 V) as an input voltage. The power supply voltage Vcc is supplied as power for an I / O portion of a microcomputer (not shown) built in the control IC 2, for example, and a lower power supply voltage (for example, 3.3V) is generated for the CPU core portion. Supplied.

  A diode 5 is inserted into the battery power supply line 4 outside the IC 2. Further, a resistor element 7 and a PNP transistor (step-down transistor) 8 are connected in series between the battery power line 4 (the anode side of the diode 5) and the power terminal 6 of the IC 2, and the power terminal 6 A smoothing capacitor 9 is connected between the ground and the ground. The control current supply terminal 10 and the power supply control terminal 11 of the IC 2 are connected inside the IC 2. Among these, the resistance element 12 is connected between the control current supply terminal 10 and the battery power supply line 4. Resistive elements 13 and 14 and an NPN transistor 15 are connected in series between the battery power line 4 and the ground, and the base of the transistor 15 is connected to the power control terminal 11.

  Note that the control current supply terminal 10 and the power supply terminal 11 are provided separately because the battery power line 4 and the control current supply terminal 10 are disconnected, or the terminals 10 and 11 are connected inside the IC 2. This is because the transistors 15 and 8 are reliably turned off when the power supply control becomes impossible due to the disconnection.

  On the other hand, a voltage dividing circuit composed of a series circuit of resistance elements 16 and 17 is connected between the power supply terminal 6 and the ground inside the IC 2, and a common connection point of the resistance elements 16 and 17 is an operational amplifier 18. Connected to the non-inverting input terminal. The inverting input terminal of the operational amplifier 18 is supplied with a reference voltage Vr from a reference voltage generation circuit (BGR) 19 such as a band gap reference voltage circuit.

  The output terminal of the operational amplifier 18 is connected to the gate of an N-channel MOS transistor (internal transistor) 20, and the drain and source of the transistor 20 are connected to terminals 10 and 11 and the ground, respectively. The drain of the transistor 20 is connected to one input terminal of an AND gate 23 through a low-pass filter (Filter) 21 and a level shift circuit (LSFT) 22 having a logic inversion function. The other input terminal of the AND gate 23 is supplied with a startup signal (startup sig.) From a startup circuit (not shown), and the output terminal of the AND gate 23 is a data input of the register (or flip-flop) 24. Connected to the terminal.

  The filter 21 is for noise removal, and the level shift circuit 22 is arranged to shift the drain potential of the transistor 20 to the logic level (high) of the AND gate 23. The start-up signal is a signal for preventing data indicating abnormality detection from being stored in the register 24 along with the state of each signal becoming unstable when the power source of the IC 2 is activated. The operational amplifier 18 and the transistor 20 constitute an error amplifier 25, and the low-pass filter 21, the level shift circuit 22, the AND gate 23, and the register 24 constitute an abnormality detection circuit 26.

  Next, the operation of the present embodiment will be described with reference to FIG. FIG. 2 is a timing chart showing signal states of the respective parts when the power source + B is turned on to start up the IC 2. When the power supply + B is turned on, a base current is first supplied to the transistor 15 via the terminals 10 and 11 of the IC2, and when the transistor 15 is turned on, the transistor 8 is turned on. Therefore, the potential at the terminals 10 and 11 (point A) is the base-emitter voltage VBE of the transistor 15. Then, the voltage level at the power supply terminal 6 rises.

  Then, the power supply voltage supplied to the internal operational amplifier 18 also rises. However, the operation of the operational amplifier 18 is unstable during the rise process, and the level of the output terminal (point B) fluctuates transiently. As a result, the level of the input terminal (point C) of the AND gate 22 may temporarily become high, but the startup signal remains low during that period and becomes high when the power supply voltage becomes stable after a predetermined time. Change to level. Further, since the clock signal CLK supplied to the register 24 starts an oscillating operation immediately after the power is turned on, the data stored in the register 24 is initially 00h.

  When the power supply voltage is stable <normal time>, the operational amplifier 18 generates a gate signal corresponding to the difference between the power supply voltage detected by the voltage dividing circuit of the resistance elements 16 and 17 and the reference voltage supplied from the reference voltage generating circuit 19. Is output to the gate of the transistor 20. Then, the base current of the transistor 15 is adjusted according to the ON state of the transistor 20 (the base current decreases when the ON state becomes deep), and accordingly, the base and collector currents of the transistor 8 are adjusted. Therefore, the lowered power supply voltage Vcc is determined by the amount of voltage drop generated in the resistance element 7 in accordance with the collector current of the transistor 8.

  If a short-circuit failure occurs between the emitter and collector of the transistor 8 from this state, an abnormal current flows into the power supply terminal 6, and the voltage Vcc depends on the time constant between the capacitance of the capacitor 9 (for example, 100 μF) and the abnormal current. Try to rise. The operational amplifier 18 fully turns on the transistor 20 as the voltage Vcc increases (operation to turn off the transistor 8), so that the power supply control terminal 11 (point A) is at the GND level.

Then, since the level of the input terminal (point C) of the AND gate 23 is inverted to high, the output terminal (point D) of the AND gate 23 changes to high level. Accordingly, data 01h is stored in the register 24. Therefore, for example, if the microcomputer in the IC 2 detects that the data value has changed to 01h by referring to the register 24, it is possible to detect the occurrence of overcurrent due to the short circuit failure of the transistor 8. As a result, it is possible to perform an abnormality process such as turning off a transistor (not shown) that controls the input of the power source + B and shutting off the power source.
What is necessary is just to determine the capacity | capacitance of the capacitor | condenser 9, time constants, such as the low-pass filter 21, the level shift circuit 22, etc. so that the time for performing the above abnormal processes may be secured. For example, when it is assumed that an overvoltage is applied by a load dump, the time constant is determined in consideration of the influence, or a Zener diode for clamping is provided if necessary.

  As described above, according to the present embodiment, the error amplifier 25 built in the control IC 2 is connected to the power supply control terminal 11 for applying the control signal to the external transistors 15 and 8 and the power supply voltage Vcc. In the configuration that outputs a control signal according to the difference from the reference voltage, the abnormality detection circuit 26 detects a power supply abnormality when the control signal level of the power supply control terminal 11 changes to a GND level different from the normal level. . Therefore, it is possible to detect the occurrence of an overcurrent associated with a short-circuit failure of the transistor 8 without requiring extra external elements and terminals for detecting an abnormality.

(Second embodiment)
FIG. 3 shows a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals, the description thereof is omitted, and different parts will be described below. The control IC (power supply control circuit) 31 of the second embodiment is configured by arranging a comparator 32 in place of the level shift circuit 22 and the AND gate 23 of the first embodiment. The inverting input terminal of the comparator 32 is connected to the output terminal of the filter 21, and the reference voltage is given to the non-inverting input terminal by the reference voltage circuit 33. The start-up signal is given as an enable signal (or operation power supply) for the comparator 32. The comparator 32, the reference voltage circuit 33, and the register 24 constitute an abnormality detection circuit 34.

  According to the second embodiment configured as described above, a short circuit failure occurs in the transistor 8 and an abnormal current flows into the power supply terminal 6 as in the first embodiment, so that the power supply control terminal 11 (point A). When becomes the GND level, the output terminal (point D) of the comparator 32 changes to the high level, so that the data 01h is stored in the register 24. Therefore, it is possible to detect a short-circuit fault as in the first embodiment.

(Third embodiment)
FIG. 4 shows a third embodiment of the present invention, and different parts from the first embodiment will be described. The control IC (power supply control circuit) 35 of the third embodiment is provided with a timer 36 in place of the register 24 of the first embodiment, and constitutes an abnormality detection circuit 37. The timer 36 is cleared to zero when the output signal level of the AND gate 23 is low, and counts the number of input pulses of the clock signal CLK when a short circuit failure occurs in the transistor 8 and the output signal level becomes high. When the value exceeds a predetermined value, abnormality detection output is performed. Therefore, a short circuit failure of the transistor 8 can be detected by monitoring the abnormality detection output.

(Fourth embodiment)
FIG. 5 shows a fourth embodiment of the present invention. The control IC (power supply control circuit) 38 of the fourth embodiment is a combination of the comparator 32 of the second embodiment and the timer 36 of the third embodiment, and these constitute an abnormality detection circuit 39. Yes. Accordingly, when a short circuit failure occurs in the transistor 8, the output terminal (point D) of the comparator 32 changes to a high level, and the timer 36 starts counting.

(5th Example)
FIG. 6 shows a fifth embodiment of the present invention. The control IC (power supply control circuit) 40 according to the fifth embodiment is configured to output the output signal of the AND gate 23 according to the first embodiment to a reset detection unit (not shown) inside the IC 40, instead of inputting the output signal to the register 24. These constitute the abnormality detection circuit 26A. Here, the reset detection unit resets a logic circuit for outputting a startup signal, for example.
That is, even when the power supply voltage is normal, it may be assumed that an abnormality is detected because the startup signal has changed to a low level. In such a case, if the logic circuit is reset, the status can be returned to <normal>.

(Sixth embodiment)
FIG. 7 shows a sixth embodiment of the present invention. The control IC (power supply control circuit) 41 of the sixth embodiment is also configured to output the output signal of the comparator 32 of the second embodiment to a reset detection unit (not shown) inside the IC 41, instead of inputting the output signal to the register 24. These constitute an abnormality detection circuit 34A. Therefore, the same effect as that of the sixth embodiment can be obtained with respect to the configuration of the second embodiment.

(Seventh embodiment)
FIG. 8 shows a seventh embodiment of the present invention. The control IC (power supply control circuit) 42 of the seventh embodiment replaces the output signal of the AND gate 23 of the fifth embodiment with the reset detection unit, and detects an overcurrent that is an output terminal of the IC 42 via the filter 43. These are output to the terminals, and these constitute the abnormality detection circuit 26B. In this case, the abnormality process can be performed by transmitting the overcurrent detection in the IC 42 to another IC or the like via the external terminal.

(Eighth embodiment)
FIG. 9 shows an eighth embodiment of the present invention. The control IC (power control circuit) 44 of the eighth embodiment also outputs the output signal of the comparator 32 of the sixth embodiment to the overcurrent detection terminal of the IC 44 via the filter 43 instead of the reset detection unit. These constitute the abnormality detection circuit 34B. Therefore, the same effect as that of the seventh embodiment can be obtained with respect to the configuration of the second embodiment.

(Ninth embodiment)
FIG. 10 shows a ninth embodiment of the present invention, and different portions from the first embodiment will be described. In the control IC (power control circuit) 45 of the ninth embodiment, the output terminal of the OR gate 46 is connected to one input terminal of the AND gate 23. One input terminal of the OR gate 46 is connected to the output terminal of the level shift circuit 22, and the other input terminal is connected to the output terminal of the operational amplifier 18 through the level shift circuit 47 having a logic inversion function and the filter 48. ing. These constitute an abnormality detection circuit 49.

  Next, the operation of the ninth embodiment will be described. Assuming a case where the capacitor 9 connected to the power supply terminal 6 is short-circuited (ground fault) or the connection between the power supply terminal 6 and the external circuit unit 3 is disconnected, the detection voltage of the operational amplifier 18 becomes the GND level. . Then, the error amplifier 25 acts to increase the power supply voltage Vcc. That is, when the output signal of the operational amplifier 18 becomes the GND level, the transistor 20 is completely cut off and the base current of the transistor 15 is increased, but the potential of the power supply control terminal 11 remains VBE.

  However, if the output terminal B point of the operational amplifier 18 is at the ground level, the output signal of the AND gate 23 goes to the high level via the OR gate 46. Therefore, as with the overcurrent in the first embodiment, the voltage abnormality or disconnection occurs. The state can be detected. The transistor 8 is also turned off when the battery power line 4 and the control current supply terminal 10 are disconnected, between the power control terminal 11 and the base of the transistor 15, or between the terminal 10 and the terminal 11 inside the IC 45. Therefore, the charge of the capacitor 9 is discharged through the resistance elements 16 and 17 and the voltage at the power supply terminal 6 is lowered.

  As described above, according to the ninth embodiment, when the abnormality detection circuit 49 changes the output signal level in the error amplifier 25, that is, the output signal level of the operational amplifier 18 to almost the GND level which is different from the normal state. The power supply abnormality was detected. Therefore, it is possible to detect a short circuit failure of the capacitor 9 or disconnection at each terminal portion of the IC 45 without providing an external detection element or a detection terminal.

(Tenth embodiment)
FIG. 11 shows a tenth embodiment of the present invention, and the differences from the ninth embodiment will be described. In the control IC (power supply control circuit) 50 of the tenth embodiment, the AND gate 23 is removed and the output terminal of the OR gate 46 is directly connected to the data input terminal of the register 24. The filter 21 on the power control terminal 11 side is connected to the comparator 32 as in the second embodiment, and the output terminal of the comparator 32 is connected to one input terminal of the OR gate 46.

The inverting input terminal of the comparator 51 is connected to the output side of the filter 48, and the reference voltage circuit 52 is connected to the non-inverting input terminal of the comparator 51. The output terminal of the comparator 51 is connected to the other input terminal of the OR gate 46, and a startup signal is given as an enable signal for the comparator 51. These constitute the abnormality detection circuit 53.
According to the above configuration, when the short circuit failure of the transistor 8 or the short circuit failure of the capacitor 9 occurs as in the ninth embodiment, the output signal levels of the comparators 33 and 51 change to high levels. Is output to the register 24 via the OR gate 46. Therefore, the power supply abnormality can be detected as in the ninth embodiment.

(Eleventh embodiment)
FIG. 12 shows an eleventh embodiment of the present invention, and the differences from the ninth embodiment will be described. The control IC (power supply control circuit) 54 of the eleventh embodiment is provided with a timer 36 instead of the register 24 of the ninth embodiment, and these constitute an abnormality detection circuit 55. According to the eleventh embodiment configured as described above, when the output signal of the OR gate 46 changes to a high level due to a short circuit failure of the transistor 8 or a short circuit failure of the capacitor 9, the timer 36 The count operation is started as in the third embodiment. Therefore, a power supply abnormality can be detected in the same manner as in the third embodiment.

(Twelfth embodiment)
FIG. 13 shows a twelfth embodiment of the present invention. The control IC (power supply control circuit) 56 of the twelfth embodiment is obtained by replacing the register 24 in the abnormality detection circuit 53 of the tenth embodiment with a timer 36, and these constitute an abnormality detection circuit 57. According to the twelfth embodiment configured as described above, when the short-circuit failure of the transistor 8 or the short-circuit failure of the capacitor 9 occurs, the output signal levels of the comparators 33 and 51 change to high level, respectively. The timer 36 starts counting through the gate 46. Therefore, the power supply abnormality can be detected in the same manner as the eleventh embodiment.

(Thirteenth embodiment)
FIG. 14 shows a thirteenth embodiment of the present invention. The control IC (power supply control circuit) 58 of the thirteenth embodiment replaces the output signal of the AND gate 23 in the abnormality detection circuit 49 of the ninth embodiment with the input to the register 24, and detects the reset inside the IC 58 (not shown). These components constitute an abnormality detection circuit 49A. Therefore, as in the fifth embodiment, even if the power supply voltage is normal, if the output logic of the startup signal malfunctions, the logic circuit can be reset to return the status to <normal>. It becomes possible.

(14th embodiment)
FIG. 15 shows a fourteenth embodiment of the present invention. The control IC (power supply control circuit) 59 of the fourteenth embodiment is the same as the thirteenth embodiment in place of inputting the output signal of the OR gate 46 in the abnormality detection circuit 53 of the tenth embodiment to the register 24. This is a configuration for outputting to a reset detection unit (not shown) inside the IC 59, and these constitute an abnormality detection circuit 53A. Therefore, the same effects as in the thirteenth embodiment can be obtained with respect to the configuration of the tenth embodiment.

(15th embodiment)
FIG. 16 shows a fifteenth embodiment of the present invention. The control IC (power supply control circuit) 59 of the fifteenth embodiment outputs the output signal of the AND gate 23 of the thirteenth embodiment to an overcurrent detection terminal which is an external output terminal of the IC 59 in place of the reset detection unit. These are the configurations, and these constitute the abnormality detection circuit 49B. In this case, the abnormal process can be performed by transmitting the overcurrent detection in the IC 59 to another IC or the like via the external terminal as in the seventh embodiment.

(Sixteenth embodiment)
FIG. 17 shows a sixteenth embodiment of the present invention. The control IC (power supply control circuit) 60 of the sixteenth embodiment outputs the output signal of the OR gate 46 of the fourteenth embodiment to an overcurrent detection terminal which is an external output terminal of the IC 60 in place of the reset detection unit. These are the configurations, and these constitute the abnormality detection circuit 53B. In this case, the overcurrent detection in the IC 60 can be transmitted to another IC or the like via the external terminal in the same way as in the fifteenth embodiment, so that the abnormality process can be performed.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The circuit configuration configured outside the power supply control circuit is not limited to the external circuit unit 3.
The error amplifier is not limited to the one composed of the operational amplifier 18 and the transistor 20.
The present invention is not limited to the power supply circuit of the vehicle electronic control unit, and can be widely applied to any step-down power supply circuit.

The figure which is 1st Example of this invention and shows the structure of the power supply circuit used with the electronic control unit of a vehicle Timing chart showing signal states of each part when power supply + B is turned on to control IC FIG. 1 equivalent view showing a second embodiment of the present invention. FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention. FIG. 1 equivalent view showing a fifth embodiment of the present invention. FIG. 1 equivalent view showing a sixth embodiment of the present invention. FIG. 1 equivalent view showing a seventh embodiment of the present invention FIG. 1 equivalent view showing an eighth embodiment of the present invention. FIG. 1 equivalent diagram showing a ninth embodiment of the present invention. FIG. 1 equivalent view showing a tenth embodiment of the present invention. FIG. 1 equivalent diagram showing an eleventh embodiment of the present invention. FIG. 1 equivalent diagram showing a twelfth embodiment of the present invention. FIG. 1 equivalent diagram showing a thirteenth embodiment of the present invention. FIG. 1 equivalent diagram showing a fourteenth embodiment of the present invention. FIG. 1 equivalent diagram showing a fifteenth embodiment of the present invention. FIG. 1 equivalent view showing a sixteenth embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is a power supply circuit, 2 is a control IC (power supply control circuit), 8 is a step-down transistor, 11 is a power supply control terminal, 18 is an operational amplifier, 20 is an N-channel MOS transistor (internal transistor), and 25 is an error. Amplifier, 26 is an abnormality detection circuit, 31 is a control IC (power supply control circuit), 34 is an abnormality detection circuit, 35 is a control IC (power supply control circuit), 37 is an abnormality detection circuit, 38 is a control IC (power supply control) Circuit), 39 is an abnormality detection circuit, 40 to 42, 44, 45 are control ICs (power supply control circuits), 49 is an abnormality detection circuit, 50 is a control IC (power supply control circuit), 53 is an abnormality detection circuit, 54 Denotes a control IC (power supply control circuit), 55 denotes an abnormality detection circuit, 56 denotes a control IC (power supply control circuit), 57 denotes an abnormality detection circuit, and 58 to 61 denote control ICs (power supply control circuit).

Claims (3)

In a power supply control circuit that generates a power supply voltage of a predetermined level by controlling an external step-down transistor,
An error amplifier that outputs a control signal according to a difference between the power supply voltage and a reference voltage to a power supply control terminal for applying a control signal to the step-down transistor;
A power supply control circuit comprising: an abnormality detection circuit that detects a power supply abnormality when a signal level of the power supply control terminal changes to a state different from a normal state.   2. The power supply control circuit according to claim 1, wherein the abnormality detection circuit detects a power supply abnormality when an output signal level inside the error amplifier changes to a state different from a normal state. The error amplifier is
An operational amplifier that outputs an amplified signal according to a difference between the power supply voltage and a reference voltage;
It is connected between the power control terminal and the ground, and is composed of an internal transistor controlled by the output signal of the operational amplifier.
The power supply control circuit according to claim 2, wherein the abnormality detection circuit detects a power supply abnormality when an output signal level of the operational amplifier changes to a state different from a normal state.

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