JP2009089078A - Solid-state image pickup apparatus and image pickup apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup apparatus which can be saved as a finished product without being discarded as a defective product, even if DC failure is caused due to dust in pixels, thereby improving a production yield. <P>SOLUTION: Separating circuit sections 3, 4 and a correction processing system section 9 are used to, for example, separate DC failure portion caused due a short-circuited signal line in a pixel and solve a leak current. First, detection of an address of an inter-wiring short-circuit section is detected by a certain method such as detection of defective column-row in a pixels, etc. Then, the wiring of the address is electrically disconnected and brought into a floating state, resulting in a state where a leak current is not generated. However, if a pixel drive signal line or a vertical signal line is electrically disconnected, the electrical signals of the pixels of the corresponding row or column cannot be read, resulting in poor image quality owing to a line fault. To prevent this, a correction processing system section 9 executes longitudinal-lateral line fault correction. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to various solid-state imaging devices and imaging devices such as CCD image sensors and CMOS image sensors.

In recent years, solid-state imaging devices represented by CCD image sensors and CMOS image sensors have been actively developed, and are used in various camera devices and mobile phones.
For example, in a CCD image sensor, a plurality of pixels including photodiodes (photoelectric conversion units) are arranged in a two-dimensional direction on a semiconductor substrate, a CCD vertical transfer register is provided between each pixel row, and an output of each vertical transfer register is provided. A CCD horizontal transfer register is provided at the end.

A laminated film such as an insulating film, a transfer electrode film, and a light shielding film is sequentially formed on the semiconductor substrate, and a color filter, a microlens, and the like are further formed through a planarization film or the like.
In such a CCD image sensor, a driving pulse is supplied to a transfer electrode provided on a semiconductor substrate to drive each transfer register, and a signal charge generated by a photodiode of each pixel is transferred to a CCD vertical transfer register and a CCD horizontal transfer. The signal charges are sequentially transferred through the registers, and the signal charges are converted into voltage signals or current signals by a conversion unit provided at the output end of the CCD horizontal transfer register, and are output as pixel signals.

On the other hand, a CMOS image sensor is provided with an imaging region in which a plurality of pixels including photodiodes are arranged in a two-dimensional direction and a peripheral circuit region formed outside the imaging region on the same semiconductor substrate. .
In the imaging region, for each pixel, a readout transistor (transfer gate) that reads the signal charge of the photodiode to the FD (floating diffusion), an amplification transistor that generates a pixel signal corresponding to the potential of the FD, and a pixel signal Various pixel transistors such as a selection transistor for selecting a pixel to be output and a reset transistor for resetting the FD are provided, and signal charges detected by a photodiode of each pixel are converted into a pixel signal by driving each pixel transistor. Output from the provided signal line.
Further, in the peripheral circuit region, a drive control circuit that controls reading of pixel signals by supplying various control pulses to the pixel array unit, a signal processing circuit that performs various signal processing on the read pixel signals, A power supply control circuit for generating a drive power supply is provided.
A laminated film such as an insulating film, a transistor driving electrode film, a wiring film, and a light shielding film is sequentially formed on the semiconductor substrate, and a color filter, a microlens, and the like are further formed through a planarization film.
In such a CMOS image sensor, the signal charge accumulated in the photodiode of each pixel is converted into a pixel signal for each pixel by driving each pixel transistor, and this is output for each pixel column and is output to the signal processing circuit in the subsequent stage. Sending, noise removal, signal processing, etc. are performed and output.

By the way, in such a conventional image sensor, a fixed noise defect (so-called DC defect) due to dust in the pixel often occurs, and it is one of the problems to improve it.
Therefore, conventionally, the current value of the pixel power source is measured in the standby state, the defective product is detected, and discarded as a DC defective product. As a method for detecting a DC failure, a method for detecting a leakage current generated in a pixel has been proposed (see, for example, Patent Document 1).
JP-A-9-101347

  However, the above-described conventional technique simply detects and discards a DC failure and is not a solution to the DC failure itself. That is, hitherto, no design technology that can fundamentally remedy DC failures has been provided, and improvement measures centered on improvements on the process side, such as reducing the dust generation rate of manufacturing equipment. For this reason, it has been a major obstacle to improving the yield of image sensors.

  Accordingly, the present invention provides a solid-state imaging device and an imaging device that can be remedied as a finished product and improved in yield without being discarded as a defective product even when a DC failure occurs due to dust or the like in the pixel. The purpose is to do.

  In order to achieve the above object, a solid-state imaging device of the present invention includes a pixel array unit in which a plurality of pixels each having a photoelectric conversion unit are arranged in a two-dimensional direction, and sequentially scanning each pixel in the pixel array unit. A readout transmission unit that reads out a pixel signal of a pixel and transmits the pixel signal outside the pixel array unit; a signal processing unit that performs predetermined signal processing on the pixel signal read out by the readout transmission unit and outputs an image; and A separation circuit unit that electrically separates the readout transmission unit between the pixel array unit and the signal processing unit, and a defective pixel that is detected in advance by a predetermined detection unit at the time of image output is separated from the signal processing unit by the separation circuit unit. And correction control means for correcting the pixel signal of the defective pixel based on the pixel signals of the surrounding normal pixels.

  The imaging device of the present invention includes an imaging unit using a solid-state imaging device, a control unit that controls the imaging unit, and an operation unit that operates the imaging unit. A pixel array unit in which a plurality of pixels having a unit are arranged in a two-dimensional direction, a readout transmission unit that sequentially scans each pixel of the pixel array unit, reads out a pixel signal of each pixel, and transmits the pixel signal to the outside of the pixel array unit; The signal processing unit that performs predetermined signal processing on the pixel signal read by the readout transmission unit and outputs an image is electrically disconnected from the readout transmission unit between the pixel array unit and the signal processing unit. The separation circuit unit separates a defective pixel previously detected by a predetermined detection means from the signal processing unit by the separation circuit unit at the time of image output, and also converts the pixel signal of the defective pixel to a pixel of a surrounding normal pixel And having a correction control means for correcting, based on the item.

  According to the solid-state imaging device and the imaging device of the present invention, when outputting an image, a defective pixel detected in advance by a predetermined detection unit is separated from a signal processing unit by a separation circuit unit, and a pixel signal of the defective pixel is converted to a peripheral normal pixel. Therefore, it is possible to use a solid-state imaging device that has been treated as a defective product as a non-defective product, so even if the improvement in the dust level of the process becomes a limit, It is possible to reduce the yield rate and to achieve a reduction in manufacturing cost and a reduction in product cost.

FIG. 1 is a block diagram showing a first configuration example of the solid-state imaging device according to the embodiment of the present invention, and FIG. 2 is a block diagram showing a second configuration example of the solid-state imaging device according to the embodiment of the present invention. is there. FIG. 3 is a circuit diagram showing a configuration example of the pixel of the CMOS image sensor shown in FIGS.
As shown in the figure, the solid-state imaging device according to the present embodiment is an example of an XY address type column parallel readout type CMOS image sensor that simultaneously reads out pixel signals for one row. In FIG. 2 shows an example of a configuration in which a correction processing system (correction control means) and a DSP block 10 are provided outside a semiconductor substrate provided with a portion, and FIG. 2 shows a configuration in which the DSP block 10 is mounted outside a semiconductor substrate provided with a pixel array portion. An example is shown.
In the following example, the case where the present invention is applied to a column parallel readout type CMOS image sensor will be described. However, the present invention can also be applied to a CCD image sensor.

As shown in FIG. 1, the CMOS image sensor of this example includes a pixel array unit 2, separation circuit units 3 and 4, a pixel driver unit 5, a drive control unit 6, and a column signal readout circuit unit on a semiconductor substrate 1. 7 and a signal processing / control unit 8, and a correction processing system unit (correction control means) 9 and a DSP block 10 are provided outside the semiconductor substrate 1.
The pixel array unit 2 includes a plurality of pixels each having a photoelectric conversion unit arranged in a two-dimensional direction. The pixel array unit 2 receives color component light corresponding to the spectral characteristics of a color filter disposed above the pixel array unit 2 according to the amount of light. Generated pixel signals.

As shown in FIG. 3, the pixel is composed of one photoelectric conversion unit (photodiode) 15 and four MOS transistors 11 to 14, and the signal charge detected by the photodiode 15 is read out by the transistor 11 and FD (floating). And the potential of the FD 16 is detected and amplified by the amplification transistor 12 and converted into a pixel signal. The output pixel signal of the amplification transistor 12 is converted at a predetermined output timing based on the operation of the selection transistor 13. Output to the vertical signal line 17. Further, the potential of the FD 16 is reset to the power supply potential by the reset transistor 14 at a predetermined reset timing.
Such a pixel is controlled by the pixel driver unit 5 and the drive control unit 6 via the pixel drive signal line 21. Specifically, the pixel driver unit 5 outputs a read pulse ROG for driving the read transistor 11, a selection pulse SEL for controlling the selection transistor 13, and a reset pulse RST for controlling the reset transistor 14 to the pixel drive signal line 21. The drive control unit 6 controls these output timings.
The separation circuit unit 3 electrically separates the pixel drive signal line 21 between the pixel array unit 2 and the pixel driver unit 5.

Further, the column signal readout circuit unit 7 inputs pixel signals of each column (column) output by the vertical signal line 17 in units of rows, and performs, for example, CDS processing for removing fixed pattern noise and AD for digital conversion of analog signals. Conversion processing is performed.
The separation circuit unit 4 electrically separates the vertical signal line 17 between the pixel array unit 2 and the column signal readout circuit unit 7.
The signal processing / control unit 8 controls the separation circuit units 3 and 4, the drive control unit 6, the column signal readout circuit unit 7, and the like, and performs an operation for processing the digitized column output signal.
The correction processing system unit 9 corrects the imaging signal output from the signal processing / control unit 8.
The DSP block 10 holds or outputs an output image, or performs image processing, and includes a memory and an output device as necessary in addition to a DSP for signal processing.

In the image sensor having the above configuration, the following processing is mainly performed as a normal imaging operation.
First, in each pixel of the signal output row selected by the column signal readout circuit unit 7, the signal level corresponding to the electrons accumulated in the photodiode 15 and the 0 level after resetting the photodiode 15 are as follows. Digitization and CDS are performed by a column AD converter or the like.
Further, during the shutter operation, the photodiode 15 of each pixel is reset. Immediately after driving the signal output row, it operates with the same drive pulse, performs CDS processing, and takes out the signal.
When the electronic shutter row and the signal output row advance at a constant interval, the signal output from the signal output row becomes a light signal photoelectrically converted from the electronic shutter row to the signal output row. The irradiation time (charge accumulation time) to the photodiode 15 can be changed by adjusting the interval between the electronic shutter row and the signal output row.
In addition, drive pulses for the drive control unit 6 and the column signal reading unit 7 are generated by the control unit 8. The charge accumulation time is adjusted by adjusting the drive pulse generated by the control unit 8.
Further, at the time of reading all pixels, the shutter and the reading operation are sequentially selected from the first row to the last row, and are performed on all rows.

Next, operations that characterize the image sensor according to the present embodiment will be described.
Here, by using the separation circuit units 3 and 4 and the correction processing system unit 9, for example, a DC defective portion caused by a signal line short circuit inside the pixel is separated, a leakage current is eliminated, and it is generated by the separation. A specific method and system for correcting the vertical line and horizontal line defects by the signal processing unit 8 at the subsequent stage will be described.
The configuration shown in FIG. 1 and the configuration shown in FIG. 2 are basically the same operation although the arrangement of elements is different, and will be described together.

First, as a basic principle that causes a DC failure, a short circuit between wirings generated in a pixel will be described as an example.
For example, in a pixel having a 4-transistor (4Tr) configuration, when the RST signal line and the ROG signal line are short-circuited between the wirings, and there is a short-circuited portion between the two wirings, a potential difference is generated between the RST signal line and the ROG signal line. Leakage current is generated. For example, in the case of an image sensor in which the potentials of the RST signal line and the SEL signal line are different during standby, a standby leak current is generated, the standby and specs are over, and the current flows without specs over. If you continue, it becomes a quality problem and cannot be shipped as a product.
Therefore, first, for example, in the inspection process before product shipment, the address detection of the inter-wiring short portion is performed. For example, a test image or the like is read by an image sensor, an output signal is checked to detect a defective pixel (or defective column / defective row unit), and an address is detected. The detected defective pixel address is stored in a memory in the image sensor. The function up to this point is the operation as a detection means. However, this function can be automatically performed by installing it in an external test device or by installing it in a signal processing / control unit in the image sensor. It is possible to select according to the scale and specifications of the sensor.

After that, at the time of actual imaging, first, the address stored in the memory is referred to, the corresponding wiring is electrically disconnected, and the floating state is set so that no leak current is generated.
However, when the pixel drive signal line or the vertical signal line is electrically disconnected, the electric signal of the pixel in the row or column cannot be read out, resulting in a line defect and poor image quality.
Therefore, the above-described problem is solved by performing vertical / horizontal line defect correction by the correction processing system unit 9 in the subsequent stage. In this embodiment, the detailed algorithm of the correction process is not mentioned, but for example, a predetermined calculation is performed on the signal values of m × n normal pixels around the defective pixel (for example, an average value is simply obtained). Or calculating the average value by weighting) to calculate the signal value of the defective pixel and interpolate the omission.

Next, a specific example of the separation circuit unit will be described.
FIG. 3 shows an example in which a decoder is used for a selection circuit for a signal line to be separated in the separation circuit section.
FIG. 4 shows an example in which a shift register is used for a selection circuit for a signal line to be separated by the separation circuit unit.
Further, FIG. 5 shows an application example of a case in which a shift register is used for a selection circuit for a signal line to be separated in the separation circuit unit.
6 and 7 show examples of the separation circuit of the separation circuit unit.
Further, FIG. 8 shows an example in which a nonvolatile memory for holding address information of a signal line to be separated by the separation circuit unit is provided.

  First, the separation circuit unit 3 shown in FIG. 3 is provided with a separation switch unit 31 provided with a separation switch 311 for each pixel drive signal line 21 and a decoder circuit unit 32 for selecting the separation switch 311. By inputting a specific code from the pixel driver unit 5 to the decoder circuit unit 32, a signal for turning off one separation switch 311 is output from the decoder circuit unit 32. Therefore, the decoder circuit unit 32 is controlled by the pixel driver unit 5, and the decoder circuit unit 32 controls the disconnection of an arbitrary signal line by selecting the disconnection location. Such a configuration can be similarly applied to pixels other than the 4Tr configuration.

  3 is obtained by replacing the decoder circuit unit 32 of FIG. 3 with a shift register circuit unit 33. By inputting a specific code from the pixel driver unit 5 to the shift register circuit unit 33, an on / off signal is written to a plurality of stages of latch circuits composed of flip-flops (FF) of the shift register circuit unit 33. The plurality of separation switches 311 are selectively turned on / off by the on / off signal. Therefore, the shift register circuit unit 33 is controlled by the pixel driver unit 5 and the shift register circuit unit 33 selects and disconnects an arbitrary signal line. Note that this configuration can also be applied to a pixel other than a pixel having a 4Tr configuration.

3 and 4 show the separation circuit unit 3 for the pixel drive signal line, the same applies to the separation circuit unit 4 for the vertical signal line.
Here, the circuit configuration of FIG. 4 has a circuit configuration in which a plurality of signal lines are simultaneously efficiently separated and controlled. On the other hand, the circuit configuration of FIG. 3 is an effective method for separating a single signal line. However, when a plurality of arbitrary pixel drive signal lines or a plurality of vertical signal lines are simultaneously separated, the circuit scale and the arrangement area are reduced. In view of this, it is not suitable. Therefore, in order to select a plurality of circuits arbitrarily, it is possible to efficiently select a plurality of rows and columns to be separated by using a shift register and storing information on the separation rows or columns. Of course, the same applies to pixels other than those having a 4Tr configuration.

  FIG. 5 shows an application example of the circuit configuration of FIG. In the circuit configuration of FIG. 4, the required FF of the shift register is the number of pixel columns or the number of pixel rows × the number of signal lines. As the number increases, it takes time to write information into the shift register. Depending on the specifications, it may be a problem if the sensor is disconnected at the time of sensor setup (at power-on or immediately after). As a countermeasure, it is conceivable to increase the operation clock of the shift register, but there is a limit. Therefore, as a means for solving the problem, by having a plurality of shift register circuit portions 34, 35, 36, for example, by having a shift register for each type of wiring, the number of FFs per shift register is reduced, The time for writing information to the shift register can be shortened. Note that the structure of the shift register may be devised in accordance with the setup time and clock.

FIG. 6 shows a specific circuit configuration of the separation switch 311.
The separation switch 311 includes a NAND circuit 41 that receives a pixel drive input signal and a separation input signal, a NOR circuit 43 that receives a pixel drive input signal and an inverted signal of the separation input signal by the inverter 42, and a NAND circuit. The NMOS transistor 44 having the output of 41 as the gate input and the PMOS transistor 45 having the output of the NOR circuit 43 as the gate input, the source-drain connection of the NMOS transistor 44 and the PMOS transistor 45 constituting the final stage driver unit The terminal is connected to the pixel drive signal line.
With such a circuit configuration, a signal line for electrically driving a pixel can be disconnected. Specifically, when the separation input signal is LOW, LOW is input to the NMOS transistor 44 in the driver unit in the final stage and HI is input to the PMOS transistor 45, whereby the pixel drive signal line is electrically floating.

FIG. 7 shows another specific circuit configuration of the separation switch 311, as in FIG. 6.
The separation switch 311 includes a series circuit of an NMOS transistor 51 and a PMOS transistor 52 that have a pixel drive input signal as a gate input, and a parallel circuit of an NMOS transistor 53 and a PMOS transistor 54 that have a separation input signal as a gate input. The source / drain connection terminal of the series circuit is connected to one source / drain connection terminal of the parallel circuit, and the other source / drain connection terminal of the parallel circuit is connected to the pixel drive signal line.
With such a circuit configuration, a signal line for electrically driving a pixel can be disconnected. Specifically, LOW is input to the NMOS transistor 53 and HI is input to the PMOS transistor 54 from the separation input signal, so that the pixel drive signal line is electrically floating.

FIG. 8 shows a configuration having a non-volatile memory inside the solid-state imaging device (semiconductor substrate 1).
As shown in the figure, in this image sensor, column / row address information is written in advance in the non-volatile memory 61 from the outside, and this information is continuously held even when the power is turned off, and used in the imaging operation.
Note that it is possible to have a volatile memory instead of a non-volatile memory and specify the column and row separately from the outside each time the power is turned on. If the configuration is separated, the convenience is remarkably improved.
Also in this example, a non-volatile memory or a volatile memory may be provided outside the semiconductor substrate, and separation columns and rows are not designated from the outside, but from the correction processing system side. It is possible to adopt a configuration in which data is written in an internal process by input.

Next, a defective pixel detection unit that can be used in this embodiment will be described. The configuration of the detection means described here includes a leak current detection circuit for each pixel and a determination circuit that determines a defective pixel based on a detection signal of the leak current detection circuit.
As this type of leakage current detection means, there is one disclosed in the above-mentioned Patent Document 1 (Japanese Patent Laid-Open No. 9-101347). However, since this detection means is measured by an external ammeter, Since it takes time for the value to stabilize, it takes a long time to measure, which affects the measurement cost.
Therefore, the present embodiment provides a configuration for detecting leak current more efficiently.

FIG. 10 is a block diagram showing the configuration of the image sensor provided with the leakage current detection means of this example. Note that. In the configuration common to FIG. 1, the same reference numerals are given and the details are omitted.
In FIG. 10, a pixel array unit 2, a pixel driver unit 5, a drive control unit 6, a column signal readout circuit unit 7, and a signal processing / control unit 8 are common to the image sensor shown in FIG. Separation and correction processing are performed.
Further, in the configuration of FIG. 10, the disconnection circuit units 103 and 104 not only disconnect the pixel array unit 2 but also connect the pixel drive signal line 21 and the vertical signal line 17 from the pixel array unit 2 to the leak current when detecting the leak current. It also has the function of a switching circuit connected to the detection circuit unit 110. That is, in addition to the disconnect switch 311 corresponding to each signal line of the pixel drive signal line 21 and the vertical signal line 17, the connection of each signal line of the pixel drive signal line 21 and the vertical signal line 17 is switched to the leak current detection circuit unit 110. A changeover switch 105 is provided. When detecting the leakage current, the selector switch 105 connects the signal lines of the pixel drive signal line 21 and the vertical signal line 17 to the leakage current detection circuit unit 110 and inputs each pixel signal to the leakage current detection circuit unit 110. As a result, the leakage current is detected.
Then, the detection result is sent to the signal processing / control unit 8, and the defective pixel is determined by the signal processing / control unit 8 according to the detection result. That is, in this example, the signal processing / control unit 8 has a function of a leakage current determination circuit.
With this configuration, defective pixels can be detected by internal processing of the image sensor, and address information (for example, expressed in units of rows or columns) of separated pixels is stored in a subsequent memory or the like based on the detection result. It is used for the correction process at the time of image output described above.

Hereinafter, the leak current detection method in this example will be described in detail.
FIG. 11 is a block diagram showing the state of each switch before detection of the leakage current in the disconnection circuit unit 103. As shown in the drawing, in this state, all the disconnect switches 311 (SWC1, SWC2, SWC3,..., SWCn) are opened, and all the changeover switches 105 (SW1, SW2, SW3,. .
FIG. 12 is a timing chart showing the state of each switch when a leakage current is detected. It is assumed that each switch is turned on and the signal line is turned on when the drive pulse supplied to each switch is Hi (active).
As shown in the figure, when leak current is detected in this example, each signal line is sequentially scanned in accordance with the scanning of the pixel array unit 2, and the switch 311 is turned off at the same time as the switch 311 is turned off at the corresponding signal line. As a result, in accordance with the scanning of the pixel array unit 2, the leakage current value is sequentially taken into the leakage current detection circuit unit 110, and the leakage current value can be collected quickly and efficiently. ing. In particular, since the leak current is detected by a circuit configured in the same semiconductor substrate, synchronization and the like can be easily performed with high accuracy, and processing in a short time is possible.
Here, the switch configuration and timing chart on the separation circuit unit 103 side are shown, but the switch configuration and timing chart on the separation circuit unit 104 side are the same.

Next, a specific example of the leakage current detection circuit unit 110 will be described.
FIG. 13 is a circuit diagram showing a configuration of the leakage current detection circuit unit 110 in this example.
A leak current generation source 201 in the figure indicates each pixel in the pixel array unit 2, and the above-described changeover switch 105 and disconnect switch 311 are provided on the pixel drive signal line 21 connected to the leak current generation source 201. When the changeover switch 105 is turned on, the leakage current is taken into the leakage current detection circuit unit 110.
The leak current detection circuit unit 110 includes a reference current generation circuit unit 202, a voltage generation circuit 203, a leak current detection amplifier unit 204, a comparator circuit unit 205, and a latch circuit unit 206.

The reference current generation circuit unit 202 is a current source for always supplying a reference current for comparison of leak current to the leak current detection amplifier unit 204, and the voltage generation circuit 203 supplies a reference voltage to the leak current detection amplifier unit 204. It is a voltage source. The leakage current detection amplifier unit 204 is provided with a capacitor 207 in a negative feedback loop and is used as an integration circuit.
The comparator circuit unit 205 compares the detection signal from the leak current detection amplifier unit 204 with a reference value, and the latch circuit unit 206 latches the comparison result by the comparator circuit unit 205.
Further, a switch 208 (SWA0) for controlling the detection operation (startup / reset) timing is provided at the negative feedback loop of the leakage current detection amplifier unit 204 and the input terminal of the comparator circuit unit 205, and the latch circuit unit 206 includes A switch 209 (SWSH) is provided for controlling the timing of reading the latched signal to the signal processing / control unit 8.

Next, the operation of such a leakage current detection circuit unit 110 will be described.
FIG. 14 is a timing chart showing the operation of the leakage current detection circuit unit 110.
First, the reference current generation circuit unit 202 and the voltage generation circuit unit 203 for comparing leak currents are operated to stabilize the current output and voltage output. That is, the current value generated from the reference current generation circuit 202 is a current for comparison with the leak current value, and it is recognized that there is a leak when the amount of leak current exceeds the reference current in the reverse direction. Can be variably adjusted by an appropriate circuit configuration and setting according to the application, purpose, specification, and process. Further, the reference voltage by the voltage generation circuit unit 203 is set to an appropriate setting value in consideration of the operating range of the leakage current detection amplifier unit 204.

After that, as shown in the timing chart of FIG. 14, the leak current detection circuit unit 110 and the pixel drive signal line 21 are connected by the nth changeover switch 105 (SWn), and the switch 208 (SWA0) is turned on during this connection period. By making it conductive, the comparator circuit unit 205 and the integration circuit are reset.
When the switch 208 (SWA0) is disconnected, the current flows into or is pulled out from the integration circuit (capacitor 207) due to the difference in the amount of current between the leak current value and the reference current value. The output level of the leakage current detection amplifier unit 204 is determined, and the subsequent amplifier (comparator circuit unit) 205 compares and outputs the voltage level. Is the leakage current amount higher than the reference current value? Is it low? Can be determined.
Depending on the leak destination, there is a possibility that there is a leak path in both potential directions of the power supply side and the ground side. Therefore, the current generated from the comparison current circuit 202 is prepared in two directions: a supply direction and a drawing direction. It is necessary to compare and detect both at the time of detection.
After that, by comparing with the comparator circuit unit 205 and applying the pulse of the switch 209 (SWSH) at a timing when the level can be confirmed, the output level is held and the detection result is transmitted to the signal processing unit 8 in the subsequent stage. By outputting a signal from the semiconductor substrate 1, it is possible to obtain information on whether or not there is a leak portion in any row.
In the above operation example, the scanning in the row direction has been described. However, the leak direction can be detected by scanning in the column direction in the same way.

Is there a leak point in the row / column by using the above configuration? It becomes possible to specify simply. Thereby, for example, it becomes possible to quickly analyze a defective portion.
In addition, by specifying the leak location in this way, it is possible to eliminate the defective pixel by separating the leak location with the configuration described with reference to FIGS. 1 to 8, and by combining with the subsequent correction processing system, If it exists, it becomes possible to handle the product which was treated as a defective product as a non-defective product.
Furthermore, by determining the leak current inside the solid-state imaging device, there is an effect that the measurement time is greatly shortened as compared with the state where the leak has been detected by the measuring machine outside the chip until now.

The specific embodiments of the solid-state imaging device according to the present invention have been described above, but the present invention can be further modified in various ways.
For example, in the above embodiment, the configuration in which four transistors are provided in the pixel has been described. However, the present invention can be widely applied to various other solid-state imaging devices such as a CMOS image sensor and a CCD image sensor having other pixel configurations. .
The solid-state imaging device is not limited to an image sensor or the like configured on one chip, and may be a module in which an imaging unit, a signal processing unit, and an optical system are packaged together. Moreover, the apparatus utilized for a camera system or a mobile telephone device may be used. In the present invention, a configuration having a single image sensor function is called a solid-state imaging device, and the solid-state imaging device and other elements (control circuit, operation unit, display unit, data storage function, communication function, etc.) The integrated configuration is referred to as an imaging device.

Hereinafter, a specific example of an imaging apparatus to which the present invention is applied will be described.
FIG. 9 is a block diagram showing a configuration example of a camera apparatus using the image sensor of the above embodiment.
In FIG. 9, an imaging unit 310 performs imaging of a subject using, for example, the image sensor shown in FIGS. 1 and 2, and outputs an imaging signal to a system control unit 320 mounted on the main board.
That is, the imaging unit 310 performs processing such as AGC (automatic gain control), OB (optical black) clamping, CDS (correlated double sampling), and A / D conversion on the output signal of the image sensor described above, and performs digital imaging. Generate and output a signal.

In this example, an example in which an imaging signal is converted into a digital signal and output to the system control unit 320 in the imaging unit 310 is shown. However, an analog imaging signal is sent from the imaging unit 310 to the system control unit 320, and the system The control unit 320 may convert to a digital signal.
Various methods have been conventionally provided for specific control operations, signal processing, and the like in the imaging unit 310, and it is needless to say that the imaging device of the present invention is not particularly limited.

  The imaging optical system 300 includes a zoom lens 301 and a diaphragm mechanism 302 disposed in a lens barrel, and forms a subject image on the light receiving unit of the image sensor, based on an instruction from the system control unit 320. Under the control of the drive control unit 330, each part is mechanically driven to perform control such as autofocus.

The system control unit 320 includes a CPU 321, a ROM 322, a RAM 323, a DSP 324, an external interface 325, and the like.
The CPU 321 uses the ROM 322 and the RAM 323 to send an instruction to each part of the camera apparatus to control the entire system.
The DSP 324 performs various kinds of signal processing on the imaging signal from the imaging unit 310, thereby generating a still image or moving image video signal (for example, a YUV signal) in a predetermined format.
The external interface 325 is provided with various encoders and D / A converters, and with external elements (in this example, the display 360, the memory medium 340, and the operation panel unit 350) connected to the system control unit 320. Various control signals and data are exchanged.

The display 360 is a small display such as a liquid crystal panel incorporated in the camera apparatus, and displays a captured image. In addition to the small display device incorporated in such a camera device, it is of course possible to transmit the image data to an external large display device for display.
The memory medium 340 can appropriately store images taken on, for example, various memory cards, and can replace the memory medium with the memory medium controller 341, for example. As the memory medium 340, in addition to various memory cards, a disk medium using magnetism or light can be used.
The operation panel unit 350 is provided with input keys for a user to give various instructions when performing a photographing operation with the camera device. The CPU 321 monitors an input signal from the operation panel unit 350, Various operation controls are executed based on the input contents.

  By applying the solid-state imaging device of the present invention to such a camera device, it is possible to provide a high-functional imaging device having an effective window cutout function. In the above configuration, unit devices and unit modules as system components, a combination method, a set size, and the like can be appropriately selected based on the actual state of commercialization and the like. The device shall include a wide variety of variations.

In the solid-state imaging device and imaging device of the present invention, the imaging target (subject) is not limited to a general image such as a person or a landscape, but a special fine image pattern such as a counterfeit bill detector or a fingerprint detector. It can also be applied to.
The apparatus configuration in this case is not the general camera apparatus shown in FIG. 9, but further includes a special image pickup optical system and a signal processing system including pattern analysis. This makes it possible to realize accurate image detection.
Furthermore, when configuring a remote system such as telemedicine, security monitoring, personal authentication, etc., it is also possible to configure the device configuration including a communication module connected to the network as described above, and a wide range of applications can be realized. It is.

It is a block diagram which shows the 1st structural example of the solid-state imaging device by embodiment of this invention. It is a block diagram which shows the 2nd structural example of the solid-state imaging device by embodiment of this invention. FIG. 3 is a circuit diagram illustrating a configuration example of a pixel of the CMOS image sensor illustrated in FIGS. 1 and 2 and a configuration example of a separation circuit unit 3; FIG. 4 is a circuit diagram showing a second specific example of the separation circuit unit shown in FIG. 3. It is a circuit diagram which shows the 3rd specific example of the isolation | separation circuit part shown in FIG. FIG. 4 is a circuit diagram showing a first specific example of a separation circuit in the separation circuit section shown in FIG. 3. It is a circuit diagram which shows the 2nd specific example of the isolation | separation circuit in the isolation | separation circuit part shown in FIG. FIG. 3 is a block diagram showing a configuration example having a nonvolatile memory for holding address information of a signal line to be disconnected in the CMOS image sensor shown in FIGS. 1 and 2. It is a block diagram which shows the structural example of the camera apparatus by the other Example of this invention. It is a block diagram which shows the structural example of the solid-state imaging device provided with the leakage current detection means by other embodiment of this invention. FIG. 11 is a block diagram illustrating a state of each switch before leakage current detection in a separation circuit unit in the CMOS image sensor illustrated in FIG. 10. 12 is a timing chart illustrating a state of each switch when a leakage current in the disconnection circuit unit illustrated in FIG. 11 is detected. It is a circuit diagram which shows the structure of the leakage current detection circuit part shown in FIG. 11 is a timing chart illustrating an operation of the leakage current detection circuit unit illustrated in FIG. 10.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Pixel array part, 3, 4 ... Separation circuit part, 5 ... Pixel driver part, 6 ... Drive control part, 7 ... Column signal read-out circuit part, 8 ... Signal processing Control unit, 9 ... correction processing system unit (correction control means), 10 ... DSP block, 110 ... leak current detection circuit unit.

Claims (20)

A pixel array unit in which a plurality of pixels each having a photoelectric conversion unit are arranged in a two-dimensional direction;
A readout transmission unit that sequentially scans each pixel of the pixel array unit to read out a pixel signal of each pixel and transmits the pixel signal to the outside of the pixel array unit;
A signal processing unit that performs predetermined signal processing on the pixel signal read by the read transmission unit and outputs an image;
A disconnecting circuit unit for electrically disconnecting a readout transmission unit between the pixel array unit and the signal processing unit;
A correction control unit that separates a defective pixel detected in advance by a predetermined detection unit from a signal processing unit by a separation circuit unit at the time of image output, and corrects a pixel signal of the defective pixel based on a pixel signal of a peripheral normal pixel;
A solid-state imaging device.   2. The solid-state imaging according to claim 1, wherein the separation circuit unit electrically separates an output signal line of a pixel signal between the pixel array unit and the signal processing unit and a pixel drive control line for the pixel array unit. apparatus.   The solid-state imaging device according to claim 1, wherein the separation circuit unit and the correction control unit are mounted on the same semiconductor substrate as the pixel array unit.   2. The solid-state imaging device according to claim 1, wherein the separation circuit unit includes means for separating a signal of a pixel designated by an arbitrary address in the pixel array unit.   2. The solid-state imaging device according to claim 1, wherein the separation circuit unit includes means for separating signals of a plurality of pixel columns or a plurality of pixel rows designated by arbitrary addresses in the pixel array unit.   The solid-state imaging device according to claim 1, further comprising a non-volatile memory or a volatile memory that stores information on pixels to be separated by the separation circuit unit.   The solid-state imaging device according to claim 6, wherein the nonvolatile memory or the volatile memory is mounted on the same semiconductor substrate as the pixel array unit.   The solid-state imaging device according to claim 6, wherein the nonvolatile memory or the volatile memory is mounted outside a semiconductor substrate provided with the pixel array unit.   The solid-state imaging device according to claim 1, wherein the detection unit includes a leakage current detection circuit and a determination circuit that determines a defective pixel based on a detection signal of the leakage current detection circuit.   The solid-state imaging device according to claim 9, wherein the leakage current detection circuit includes means for variably adjusting a leakage current amount to be detected. An imaging unit using a solid-state imaging device, a control unit that controls the imaging unit, and an operation unit that operates the imaging unit,
The solid-state imaging device
A pixel array unit in which a plurality of pixels each having a photoelectric conversion unit are arranged in a two-dimensional direction;
A readout transmission unit that sequentially scans each pixel of the pixel array unit to read out a pixel signal of each pixel and transmits the pixel signal to the outside of the pixel array unit;
A signal processing unit that performs predetermined signal processing on the pixel signal read by the read transmission unit and outputs an image;
A disconnecting circuit unit for electrically disconnecting a readout transmission unit between the pixel array unit and the signal processing unit;
A correction control unit that separates a defective pixel detected in advance by a predetermined detection unit from a signal processing unit by a separation circuit unit at the time of image output, and corrects a pixel signal of the defective pixel based on a pixel signal of a peripheral normal pixel;
An imaging device comprising:   12. The imaging apparatus according to claim 11, wherein the separation circuit unit electrically separates an output signal line of a pixel signal between the pixel array unit and the signal processing unit and a pixel driving control line for the pixel array unit. .   12. The imaging apparatus according to claim 11, wherein the separation circuit unit and the correction control unit are mounted on the same semiconductor substrate as the pixel array unit.   12. The imaging apparatus according to claim 11, wherein the separation circuit unit includes means for separating a signal of a pixel designated by an arbitrary address in the pixel array unit.   12. The imaging apparatus according to claim 11, wherein the separation circuit unit includes means for separating signals of a plurality of pixel columns or a plurality of pixel rows designated by arbitrary addresses in the pixel array unit.   The imaging apparatus according to claim 11, further comprising a non-volatile memory or a volatile memory that stores information of pixels to be separated by the separation circuit unit.   The imaging device according to claim 16, wherein the nonvolatile memory or the volatile memory is mounted on the same semiconductor substrate as the pixel array unit.   The imaging apparatus according to claim 16, wherein the nonvolatile memory or the volatile memory is mounted outside a semiconductor substrate provided with the pixel array unit.   12. The imaging apparatus according to claim 11, wherein the detection unit includes a leakage current detection circuit and a determination circuit that determines a defective pixel based on a detection signal of the leakage current detection circuit.   The imaging apparatus according to claim 19, wherein the leakage current detection circuit includes means for variably adjusting a leakage current amount to be detected.

Images