JP2009088004A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that the reduction of resistance value in a current route is limited in a MOSFET with up-drain structure because current is concentrated in a current rising region formed right under a drain electrode. <P>SOLUTION: A heavily doped n-type impurity region is arranged in such a part under a gate pad that is an invalid are as an element area. Thus, drain resistance can be reduced without making the element area small or expanding a chip. In addition, the n-type impurity region and a drain electrode are provided at the outer circumference end of the chip, so that a depleted layer of a substrate can be terminated even if a conventional annular region or a shield metal is not separately provided. Namely, since the n-type impurity region and the drain electrode are commonly used as an annular region or a shield metal, even the MOSFET with up-drain structure having necessary configuration can avoid the reduction of the element region or an increase in chip area. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can reduce concentration of current paths and reduce on-resistance in a structure in which a first electrode and a second electrode that are respectively connected to an input / output unit are provided on the same main surface side.

  Many discrete semiconductor devices (semiconductor chips) are provided with electrodes connected to the input part and the output part respectively on both main surfaces (front and back surfaces) of the chip. A type that is provided on a surface and can be surface-mounted is also known.

  With reference to FIG. 7, a conventional surface mountable semiconductor device will be described by taking a so-called up-drain MOSFET as an example. FIG. 7A is a cross-sectional view, and FIG. 7B is a plan view.

  An n− type semiconductor layer 111 is provided on an n + type semiconductor substrate 110, and a p type impurity layer 112 is provided. A trench 115 reaching from the surface of the p-type impurity layer 112 to the n − -type semiconductor layer 111 is formed, the inner wall of the trench 115 is coated with a gate insulating film 116, and a gate electrode 117 is embedded in the trench 115 to form a large number of MOSFETs. A cell is provided. An n + type source region 114 is formed on the surface of the p type impurity layer 112 adjacent to the trench 115. The trench 115 is covered with an interlayer insulating film 118. The source electrode 120 is provided in connection with the source region 114 of each cell.

  A drain electrode 126 is provided on the n − type semiconductor layer 111. The drain electrode 126 is in contact with a high-concentration n-type impurity region 119 provided in the n − -type semiconductor layer 111. The n-type impurity region 119 reduces drain extraction resistance in an up-drain structure in which a main current path is formed in the horizontal direction of the n + -type semiconductor substrate 110 from the MOSFET cell to the drain electrode 126.

  Further, a metal plate 127 is provided on the back surface of the n + type semiconductor substrate 110. Since the metal plate 127 has a lower resistance than the n + type semiconductor substrate 110, the current path can be further reduced by providing the metal plate 127 on the back surface of the n + type semiconductor substrate 110 (see, for example, Patent Document 1).

  FIG. 7B is an example of a plan view of FIG.

  As described above, the source electrode 120 is provided on the surface of the element region where the MOSFET cell is disposed, and the pad portion 128 connected to the gate electrode 117 is provided, for example, at the corner portion of the chip. Bump electrodes 120b, 128b, and 126b are provided on the source electrode 120, the pad portion 128 of the gate electrode, and the drain electrode 126, respectively.

A polysilicon layer connected to the gate electrode 117 is provided on the surface of the substrate SB below the pad portion 128 connected to the gate electrode 117, and no impurity diffusion region is disposed on the surface of the substrate SB, or p-type. In general, a structure in which an impurity region (for example, a guard ring) is disposed (see, for example, Patent Document 2).
JP 2007-142272 A JP 2002-368218 A

  As shown in FIG. 7A, the current in the case of the conventional up-drain structure flows in the direction perpendicular to the surface of the substrate SB from the MOSFET cell toward the metal plate 127 as indicated by an arrow, for example. It flows in the horizontal direction of the plate 127 and the n + -type semiconductor substrate 110, and further flows in the vertical direction toward the high-concentration n-type impurity region 119 and reaches the drain electrode 126.

  However, since the current is concentrated in the n-type impurity region 119 immediately below the drain electrode 126, the resistance is increased here, and there is a limit to reducing the resistance.

  In the case of the up drain structure, it is necessary to provide the drain electrode 126 on one main surface side of the chip where the source electrode 120 and the pad portion 128 of the gate electrode are arranged, and the chip size cannot be reduced. There is. On the other hand, in the substrate SB below the pad portion 128 of the gate electrode, for example, a MOSFET cell or the like cannot be arranged, and this is an invalid region that does not particularly contribute to the operation.

  The present invention has been made in view of such a problem, and has a high-concentration one-conductivity-type semiconductor substrate, a one-conductivity-type semiconductor layer provided on the semiconductor substrate, and a discrete semiconductor element region provided on one main surface of the semiconductor layer. A high-concentration one-conductivity type impurity region that is exposed from a side surface of the semiconductor layer at an end portion of the semiconductor layer and that is provided at a depth reaching the semiconductor substrate from the one main surface, and provided on the element region A first electrode connected to an input portion or an output portion of the element region; and provided on one main surface of the semiconductor layer and in contact with the one-conductivity type impurity region; and to an output portion or an input portion of the element region. A second electrode to be connected, and a third electrode provided on one main surface of the semiconductor layer and connected to the element region, wherein a part of the one conductivity type impurity region is below the pad portion of the third electrode. It is solved by being placed in It is.

  According to the present invention, first, in a semiconductor device having a structure in which a first electrode, a second electrode, and a third electrode are provided on one main surface side of a substrate, and a current path is formed in a horizontal direction of the substrate. A single conductivity type impurity region (n-type impurity region) that is in contact with the second electrode and serves as a region for raising a current path in the substrate can be secured widely. In other words, it is possible to reduce the current path resistance while avoiding concentration in the current extraction region.

  Further, even if the n-type impurity region is extended to the lower portion of the pad portion of the third electrode, which is an ineffective region as a current path, the chip size and the element region can be increased even if the n-type impurity region is widened. The area can be maintained as before.

  In the case of an up-drain structure, it is necessary to provide a drain electrode on one main surface side of a chip on which a pad portion of a source electrode or a gate electrode is disposed, and there is a problem that the chip size cannot be reduced. On the other hand, on the substrate below the pad portion of the gate electrode, for example, a MOSFET cell or the like cannot be arranged, and this is an invalid region that does not particularly contribute to the operation of the MOSFET.

  For example, in the case of a MOSFET having a conventional structure, a polysilicon layer connected to the gate electrode of the MOSFET in the element region is generally disposed on the substrate SB below the third electrode pad portion (gate electrode pad portion 128). No impurity diffusion region is disposed on the (n − type semiconductor layer surface) (or an impurity region having a conductivity type opposite to that of the substrate (p-type) (for example, a guard ring)) and contributes as a current path. It was an area that did not.

  However, in the present embodiment, an n-type impurity region serving as a current pulling region is disposed below the pad portion of the gate electrode, so that the current path can be reduced without increasing the chip size or reducing the element region. The resistance can be reduced.

  Embodiments of the present invention will be described in detail with reference to FIGS.

  The semiconductor device of the present invention includes a high-concentration one-conductivity type semiconductor substrate, a one-conductivity type semiconductor layer, an element region, a one-conductivity type impurity region, a first electrode, a second electrode, and a third electrode. In the element region, a discrete semiconductor element is formed.

  Here, the discrete semiconductor element of the present embodiment is an individual name, a single function, or a generic name of these composite elements. Examples include MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), junction field effect transistors (J-FETs), bipolar transistors, and diodes. Furthermore, the discrete semiconductor of this embodiment includes a composite element in which element regions of different discrete semiconductors such as MOSFETs and SBDs (Schottky Barrier Diodes) are integrated on the same substrate (chip).

  First, the case of a MOSFET will be described as an embodiment of the present invention with reference to FIGS.

  FIG. 1 is a schematic plan view showing a MOSFET 100 of the present embodiment. 2A to 2C are enlarged views in the vicinity of the aa, bb, and cc lines in FIG. 1, respectively.

  Referring to FIG. 1, on the first main surface Sf1 side of a semiconductor substrate (semiconductor chip) 10, an element region 20 in which a number of MOSFET cells are arranged by diffusing a desired impurity is provided. The element region 20 of the present embodiment is a region for forming a channel layer of a MOSFET that is a p-type impurity region.

  An insulating film (not shown) having an opening is provided on the element region, and an electrode layer is disposed. The electrode layer is connected to the input / output part of the element region 20.

  The electrode layer includes a first electrode 17, a second electrode 18, and a third electrode 19. The first electrode 17 is a source electrode, the second electrode 18 is a drain electrode, and the third electrode 19 is a gate wiring electrode.

  The source electrode 17 is composed of one flat electrode layer (metal layer) covering the element region 20 and is in contact with the source region of the element region 20.

  A drain electrode 18 is constituted by, for example, the outermost electrode layer (metal layer) of the semiconductor substrate 10, and the drain electrode 18 is in contact with an n-type impurity region 22 disposed below the drain electrode 18. For example, the drain electrode 18 extends along the end E of the semiconductor substrate 10 starting from the drain pad portion 18p, continuously surrounds the outside of the source electrode 17, and reaches the drain pad portion 18p.

  The gate wiring electrode 19 is disposed between the source electrode 17 and the drain electrode 18.

  The source electrode 17, the drain electrode 18, and the gate wiring electrode 19 are each provided with an external connection electrode 26 as indicated by a circle, for example. The external connection electrode 26 is, for example, a bump electrode, and the drain electrode 18 and the gate wiring electrode 19 are provided on the drain pad portion 18p and the gate pad portion 19p, respectively. The source terminal S and the drain terminal D are connected through the external connection electrode 26 and the gate terminal G is connected.

  1 shows a total of four bump electrodes, the number and arrangement thereof are not limited to those shown in the figure.

  This will be described in more detail with reference to FIG. In FIG. 2, the external connection electrode 26 is indicated by a one-dot chain line. 2A and 2B and FIG. 2C are different in scale on account of space, but the end E of the semiconductor substrate 10 actually exists on the same side. 2 (A), 2 (B), and 2 (C) are partially extracted diagrams, and the portions connected by a two-dot chain line are actually continuously used as the same constituent elements. (See FIG. 1).

  The gate wiring electrode 19 is connected to a gate electrode (not shown here) in the element region 20, and is patterned into a strip shape having a width W11 of about 10 μm (FIGS. 2A and 2B). The gate wiring electrode 19 partially overlaps with the polysilicon layer 13c extending on the substrate 10 and is provided along this.

  The gate wiring electrode 19 has a pad portion (gate pad portion) 19p having a width W12 of, for example, about 300 μm (FIG. 2C).

  Here, the width refers to the width from the end E of the semiconductor substrate (semiconductor chip) 10 toward the center of the chip, and so on. Further, the end portion E is a side surface of the substrate (semiconductor chip) 10 that is exposed when divided into semiconductor chip sizes by dicing.

  The drain electrode 18 has a pad portion (drain pad portion) 18p having a width W21 of, for example, about 350 μm (FIG. 2B), and is otherwise patterned into a strip shape having a width W22 of about 10 μm (FIG. 2 ( A) (C)).

  A high concentration n-type impurity region 22 is provided at the end E of the semiconductor substrate 10 over the entire circumference of the semiconductor substrate 10.

  The n-type impurity region 22 reaches the end E of the semiconductor substrate 10 from a position separated by a certain distance (width W3) from the outside of the p-type impurity region at the end of the element region 20 and extends along the outermost periphery of the semiconductor substrate 10. It is a continuous area.

  Here, the p-type impurity region at the end of the element region 20 is the guard ring 21. That is, the n-type impurity region 22 is arranged with a width W3 from the outside of the guard ring 21. The width W3 is set according to the withstand voltage required for the MOSFET, and is, for example, about 20 μm here. The guard ring 21 is provided below the gate wiring electrode 19 so as to overlap (FIGS. 2A and 2B), and is also disposed below the source electrode 17 near the gate pad portion 19p. The guard ring 21 is wide in the vicinity of the gate pad portion 19p, and is patterned in a concave shape immediately below the gate pad portion 19p (FIG. 2C). Note that the width W3 from the guard ring 21 to the n-type impurity region 22 is actually the same in FIGS. 2A, 2B, and 2C.

  Note that the guard ring 21 may not be provided. In that case, the n-type impurity region 22 is disposed with a width W3 away from the end of the channel layer which is the p-type impurity region.

  In other words, the n-type impurity region 22 has an outer periphery that coincides with the end E of the rectangular semiconductor substrate 10, and the inner periphery has a pattern along the guard ring 21. The n-type impurity region 22 is in contact with the drain electrode 18 in a partly overlapping manner, is disposed along the drain electrode 18, and is disposed substantially over the entire surface below the drain pad electrode 18p. That is, the n-type impurity region 22 is disposed on at least the entire surface below the fixing region of the external connection electrode 26 (bump electrode) (FIG. 2B).

  A part of the n-type impurity region 22 is disposed below the gate pad portion 19p. That is, the n-type impurity region 22 has an extended portion 22a that protrudes in the chip center direction below the gate pad portion 19p (FIG. 2C). Thereby, the resistance value of the current path can be reduced, which will be described later with reference to a cross-sectional view.

  Below the gate pad portion 19p, a width W4 from the inner periphery of the n-type impurity region 22 including the extended portion 22a to the end portion E of the semiconductor substrate 10 is, for example, 350 μm. The extended portion 22a is also spaced from the end of the guard ring 21 with a certain width W3.

  A polysilicon layer 13c doped with impurities is disposed below the gate wiring electrode 19 including the gate pad portion 19p. A part of the polysilicon layer 13c extends below the source electrode 17 and is connected to a gate electrode (not shown) in the element region 20 (FIGS. 2A and 2B). The polysilicon layer 13c is also disposed below the gate pad portion 19p, but there may be a case where, for example, a MOSFET protection diode is formed.

  The gate wiring electrode 19 and the polysilicon layer 13c, and the drain electrode 18 and the n-type impurity region 22 are in contact with each other through a contact hole CH indicated by a broken line. The extended portion 22 a of the n-type impurity region 22 below the gate pad portion 19 p is insulated from the gate wiring electrode 19.

  3 is a cross-sectional view taken along the line aa in FIG.

The semiconductor substrate 10 has a configuration in which an n− type semiconductor layer (for example, an n− type epitaxial layer having an impurity concentration of about 1 × 10 ¹⁶ cm ⁻³ ) 2 is provided on an n + type silicon semiconductor substrate 1. A channel layer 4 which is a p-type impurity region is provided on the surface of the n − type semiconductor layer 2 which becomes the first main surface Sf1, and the semiconductor substrate 10 below the channel layer 4 becomes a drain region.

  The MOSFET cell is provided in the p-type channel layer 4 provided on the first main surface Sf1 of the n-type semiconductor substrate 10.

  The trench 7 passes through the channel layer 4 and reaches the n − type semiconductor layer 2. The trench 7 is generally patterned in a lattice shape or a stripe shape in the plane pattern of the first main surface Sf1.

  A gate oxide film 11 is provided on the inner wall of the trench 7. The thickness of the gate oxide film 11 is about several hundreds of squares depending on the MOSFET driving voltage. In addition, a conductive material is buried in the trench 7 to provide the gate electrode 13. The conductive material is, for example, polysilicon, and n-type impurities, for example, are introduced into the polysilicon in order to reduce the resistance.

  The source region 15 is a diffusion region in which a high concentration n-type impurity is implanted into the surface of the channel layer 4 adjacent to the trench 7. A body region 14 which is a diffusion region of a high concentration p-type impurity is provided on the surface of the channel layer 4 between the adjacent source regions 15 to stabilize the potential of the substrate. As a result, a portion surrounded by the adjacent trenches 7 becomes one cell of the MOS transistor, and a large number of these cells are collected to constitute the element region 20 of the MOSFET.

  A guard ring 21 in which high-concentration p-type impurities are diffused is provided at the outer peripheral end of the element region 20. The guard ring 21 relaxes the curvature of the end portion of the depletion layer extending from the channel layer 4 to the n − type semiconductor layer 2 when a reverse bias is applied to the element region 20.

  The gate electrode 13 is covered with an interlayer insulating film 16. The source electrode 17 is a metal electrode obtained by patterning a metal layer such as aluminum (Al) into a desired shape. The source electrode 17 is provided on the first main surface Sf1 side of the semiconductor substrate 10 so as to cover the element region 20 and is connected to the source region 15 and the body region 14 through a contact hole between the interlayer insulating films 16.

  The gate electrode 13 is drawn out on the substrate 10 outside the element region 20 as a polysilicon layer 13c, and the polysilicon layer 13c is in contact with the gate wiring electrode 19 provided thereon.

  A drain electrode 18 is disposed on the end E side of the substrate 10 from the gate wiring electrode 19. The drain electrode 18 is a metal layer on the outermost periphery of the semiconductor substrate 10.

Below the drain electrode 18, an n-type impurity region 22 reaching the n + -type semiconductor substrate 1 from the first main surface Sf1 is provided. The n-type impurity region 22 is a diffusion region provided from the end portion of the guard ring 21 to the end portion E of the semiconductor substrate 10 with a certain width W3 and from the side surface of the semiconductor substrate 10 (end portion E). Exposed. The impurity concentration of the n-type impurity region 22 is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

  In the present embodiment, the high-concentration n-type impurity region 22 reaches the end E of the semiconductor substrate 10 and also has an effect of preventing the substrate surface from being inverted.

  The outer periphery of the drain electrode 18 is inside the end E of the semiconductor substrate 10, and a part of the n-type impurity region 22 is disposed so as to be exposed from the drain electrode 18. Although the surface is covered with the insulating film 23 and the solder resist 25, the scribe line at the right end in FIG. 3 is not protected by the solder resist 25 and is not necessarily covered.

  A metal layer 30 is provided on the back surface of the substrate 10 in order to further reduce the resistance of the current flowing through the substrate 10 in the horizontal direction.

  The outermost surface of the first main surface Sf1 of the substrate 10 is covered with a resin layer (for example, solder resist) 25.

  4 is a cross-sectional view taken along line bb of FIG. The same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The gate electrode 13 in the element region 20 is drawn out to the surface of the substrate 10 outside the element region 20 and contacts the gate wiring electrode 19.

  A UBM (Under Bump Metal) 24 is provided as a base electrode in an opening of an insulating film (for example, a nitride film) 23 covering the surface of the drain pad portion 18, and an external connection electrode 26 is provided on the UBM 24. Here, the external connection electrode 26 is a bump electrode made of solder.

  Also in this cross section, the width W3 from the guard ring 21 to the n-type impurity region 22 is constant.

  The n-type impurity region 22 is provided on substantially the entire surface below the drain pad portion 18p, that is, on at least the entire surface below the UBM 24 to which the external connection electrode 26 is fixed. Since the current flowing through the substrate 10 is finally pulled up from the drain pad portion 18p, an n-type impurity region 22 serving as a conductive path is disposed on the entire lower surface of the drain pad portion 18p in order to eliminate current concentration as much as possible.

In order to reduce contact resistance, a contact portion having a higher concentration (impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ ) may be provided on the surface of the n-type impurity region 22. In particular, when the n-type impurity region 22 is deeply diffused, there is a concern that the surface concentration may decrease. In this case, the impurity concentration on the surface of the substrate 10 may be increased in a separate process.

  The outermost surface of the first main surface Sf1 of the substrate 10 is covered with a resin layer (for example, a solder resist) 25 except for the external connection electrode 26 portion and the end portion E (on the rake line).

  In FIG. 4, for convenience of explanation, the external connection electrode 26 is illustrated in the vicinity of the end E of the chip, but in actuality, it is disposed inside the chip from this position.

  5 is a cross-sectional view taken along line cc of FIG. The same components as those in FIG. 3 and FIG.

  A part of the gate wiring electrode 19 becomes a gate pad portion 19 p outside the element region 20. The gate pad portion 19p is provided with an UBM 24 as a base electrode in an opening of an insulating film (for example, a nitride film) 23 covering the surface, and an external connection electrode 26 is provided on the UBM 24. Here, the external connection electrode 26 is a bump electrode made of solder.

  An n-type impurity region 22 reaching the n + -type semiconductor substrate 1 from the first major surface Sf1 is provided below the gate pad portion 19p. The n-type impurity region 22 is provided from the end of the guard ring 21 to the end E of the semiconductor substrate 10 with a certain width W3, and is exposed from the side surface of the semiconductor substrate 10 (end E thereof). In addition, in the cross section of FIG. 5, the width | variety of the guard ring 21 is wider than another area | region (refer FIG. 2).

  The n-type impurity region 22 below the gate pad portion 19p is an extended portion 22a that extends the n-type impurity region 22 provided below the drain electrode 18 to the lower portion of the gate pad portion 19p. The extended portion 22a (n-type impurity region 22) is insulated from the gate pad portion 19p by the insulating film 11 '.

The polysilicon layer 13c connected to the gate electrode 13 of the MOSFET is in contact with the gate wiring electrode 19 (gate pad portion 19p) provided thereon. A protective diode may be formed in the polysilicon layer 13c below the gate pad portion 19p. The drain electrode 18 is disposed on the end E side of the substrate 10 from the gate pad portion 19p. The drain electrode 18 is an outermost metal layer of the semiconductor substrate 10, and a part of the drain electrode 18 is overlapped with the n-type impurity region 22 and is in contact therewith.

  With reference to FIG. 6, the structure of the present embodiment will be described in comparison with a conventional structure as shown in FIG. FIG. 6A is a schematic diagram when the extended portion 22a of the present embodiment is provided. FIG. 6B shows an n-type impurity region only below the drain electrode 126 as shown in FIG. 119 is a schematic diagram when 119 is provided.

  The MOSFET of this embodiment has a so-called up drain structure in which a current path is formed in a horizontal direction with respect to the surface of the substrate 10, and an n-type impurity region connected to the drain electrode 18 as a current drawing region in the substrate 10. 22 is provided.

  The impurity concentration of the n-type impurity region 22 is higher than that of the n − type semiconductor layer 2 and reaches the n + type semiconductor substrate 1. The n-type impurity region 22 becomes a conductive path for pulling up the current flowing through the substrate 10 to the drain electrode 18 with low resistance, and the source electrode 17 -source region 15 -channel layer 4 -n- type semiconductor layer 2 -n + type semiconductor substrate 1- A current path is formed between n-type impurity region 22 and drain electrode 18.

  That is, a wider n-type impurity region 22 can secure a wider low-resistance current path, and can further reduce resistance. Therefore, in this embodiment, the extended portion 22a of the n-type impurity region 22 is provided below the gate pad portion 19p. Thereby, the low resistance region can be widened even inside the substrate 10.

  Conventionally, as shown in FIG. 6B, there is a problem that current concentrates on an n-type impurity region 119 provided just below the drain electrode 126 and the resistance increases immediately before reaching the drain electrode 126. According to the embodiment, as shown in FIG. 6A, the current is dispersed by the extended portion 22a, so that the current concentration before reaching the drain electrode 18 can be alleviated. Thereby, resistance can be reduced.

  The extended portion 22a of the n-type impurity region 22 is provided only below the gate pad portion 19p, and is not provided below the other gate wiring electrodes 19 (see FIGS. 3 and 4). Although the gate pad portion 19p is a wide area below, in the conventional structure, for example, a p-type impurity region such as a guard ring is not disposed, or any impurity region is not disposed, and the current path is an ineffective region. Met.

  In the present embodiment, the extension 22a of the n-type impurity region 22 is arranged in this region, thereby reducing the resistance of the current path without increasing the chip size or reducing the area of the element region 20. be able to.

  In addition, since the extended portion 22a is disposed with the predetermined width W3 secured from the end of the guard ring 21 even below the gate pad portion 19p, there is no problem of deteriorating the breakdown voltage.

  In the present embodiment, the n-type impurity region 22 reaching the end E of the substrate 10 and the drain electrode 18 overlapping with the n-type impurity region 22 can function as an annular region and a shield metal. That is, the n-type impurity region 22 serving as a conductive path is provided at the end E of the substrate 10 so as to be exposed from the side surface of the substrate 10, and the drain electrode 18 is disposed on the n-type impurity region 22. As a result, when a reverse bias is applied to the MOSFET, the depletion layer extending to the n − type semiconductor layer 2 can be terminated by the high concentration n type impurity region 22. That is, the n-type impurity region 22 can also function as an annular region, and the drain electrode 18 can also function as a conventional shield metal.

  Accordingly, in this embodiment, it is not necessary to separately provide an annular region and a shield metal, and the peripheral region of the chip on the outer periphery of the device region can be efficiently used to provide a necessary configuration. Alternatively, the chip can be downsized.

  As described above, in the present embodiment, the MOSFET has been described as an example. However, the present invention is not limited to this, and a diode or a bipolar transistor can be similarly implemented.

It is a top view explaining the semiconductor device of the embodiment of the present invention. It is a top view explaining the semiconductor device of the embodiment of the present invention. It is sectional drawing for demonstrating the semiconductor device of this invention. It is sectional drawing for demonstrating the semiconductor device of this invention. It is sectional drawing for demonstrating the semiconductor device of this invention. 2A and 2B are a cross-sectional view compared with a conventional structure for explaining a semiconductor device of the present invention, (A) a cross-sectional view showing the semiconductor device of the present invention, and (B) a cross-sectional view showing a semiconductor device of the conventional structure. It is (A) sectional drawing and (B) top view explaining the conventional semiconductor device.

Explanation of symbols

1 n + type silicon semiconductor substrate 2 n− type semiconductor layer 4 channel layer 7 trench 10 semiconductor substrate (semiconductor chip)
DESCRIPTION OF SYMBOLS 11 Gate insulating film 13 Gate electrode 13c Polysilicon layer 14 Body region 15 Source region 16 Interlayer insulating film 17 Source electrode 18 Drain electrode 18p Drain pad part 19 Gate wiring electrode 19p Gate pad part 20 Element region 21 Guard ring 22 N-type impurity region 22a extension portion 23 insulating film 24 ground electrode 25 resin layer 26 external connection electrode 110 semiconductor substrate 111 n− type semiconductor layer 112 p type impurity layer 113 body region 114 source region 115 trench 116 gate insulating film 117 gate electrode 118 interlayer insulating film 119 n-type impurity region 120 source electrode 126 drain electrode 128 pad portion E (chip) end S source terminal D drain terminal G gate terminal

Claims (4)

A high concentration one conductivity type semiconductor substrate;
A one-conductivity-type semiconductor layer provided on the semiconductor substrate;
An element region of a discrete semiconductor provided on one main surface of the semiconductor layer;
A high-concentration one-conductivity type impurity region provided at a depth that is exposed from the side surface of the semiconductor layer at an end of the semiconductor layer and reaches the semiconductor substrate from the one main surface;
A first electrode provided on the element region and connected to an input portion or an output portion of the element region;
A second electrode provided on one main surface of the semiconductor layer, connected to the one-conductivity type impurity region, and connected to an output portion or an input portion of the element region;
A third electrode provided on one main surface of the semiconductor layer and connected to the element region,
A part of the one conductivity type impurity region is disposed below the pad portion of the third electrode.   2. The semiconductor device according to claim 1, wherein another part of the one conductivity type impurity region is disposed below a pad portion of the second electrode.   2. The semiconductor device according to claim 1, wherein the one conductivity type impurity region is separated from the opposite conductivity type impurity region at an end portion of the element region while ensuring at least a predetermined distance.   Providing the first external connection electrode, the second external connection electrode, and the third external connection electrode connected to the first electrode and the pad portions of the second electrode and the third electrode, respectively, on the one main surface side; The semiconductor device according to claim 1.

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