JP2009081612A - Controller and method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To change the number of operating taps in an equalizer in response to the quality of a signal after an equalization. <P>SOLUTION: In a demodulating circuit 1, the equalizer 11 equalizes an input signal, an error-rate estimating circuit 12 estimates an error rate from the input signal equalized by the equalizer 11 and a tap-number determining circuit 13 changes the number of the taps operated in a plurality of the taps configuring the equalizer 11 on the basis of the error rate estimated by the error-rate estimating circuit 12. This invention can be applied to the demodulating circuit with the equalizer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a control device, method, and program, and more particularly, to a control device, method, and program that allow the number of operation taps of an equalizer to be changed according to signal quality after equalization, for example.

  In a general demodulation circuit having an equalizer composed of a conventional FIR (Finite Impulse Response) filter, the equalizer is adapted to the environment in which the demodulation circuit is most difficult to equalize. The number of taps is determined (see, for example, Patent Document 1).

For example, in the demodulation circuit of a tuner for BS (Broadcasting Satellite) digital broadcasting, the most difficult environment is assumed to be, for example, indoor wiring in a housing complex where multipath occurs. In order to equalize a delay signal having a delay amount of several tens to several hundreds of meters, an equalizer having a tap number of 20 taps to 30 taps has been mounted. On the other hand, in an indoor wiring of a detached house, the amount of delay generated is relatively small, and an equalizer having a tap number of about several taps to 10 taps is sufficient to equalize the delayed signal. . Therefore, when used in a detached house, the number of taps of the equalizer may be more than necessary.
JP-A-6-276053

  As described above, since there are a wide variety of channel conditions in digital broadcasting, when the number of taps in the demodulation circuit is fixed, the number of taps in the equalizer may increase more than necessary.

  If the number of taps in the equalizer is larger than necessary, the power consumption of the demodulation circuit is increased accordingly. The ratio of the equalizer to the entire demodulation circuit is large, and the power consumption of the equalizer is required to be reduced from the viewpoint of thermal design.

  The present invention has been made in view of such a situation. For example, the number of operation taps of an equalizer can be changed according to the signal quality after equalization.

  The control device according to one aspect of the present invention is a control device that controls an equalizer that equalizes an input signal, an estimation unit that estimates an error rate from the input signal equalized by the equalizer, and the estimation Control means for changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the means.

  A control method or program according to one aspect of the present invention is a program that causes a computer to execute a control method or control process of a control device that controls an equalizer that equalizes an input signal, and is equalized by the equalizer An estimation step for estimating an error rate from the input signal, and a control step for changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the processing of the estimation step. A program for causing a computer to execute a control method or a control process including:

  In one aspect of the present invention, an error rate is estimated from an input signal equalized by an equalizer, and based on the estimated error rate, an operation tap among a plurality of taps constituting the equalizer The number is changed.

  According to one aspect of the present invention, for example, the number of operation taps of the equalizer can be changed according to the signal quality after equalization.

  Embodiments of the present invention will be described below. Correspondences between the constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

The control device according to one aspect of the present invention includes:
In a control device (for example, the demodulator circuit 1 in FIG. 1) for controlling an equalizer (for example, the equalizer 11 in FIG. 1) for equalizing an input signal,
Estimator for estimating an error rate from the input signal equalized by the equalizer (for example, the error rate estimation circuit 12 in FIG. 1);
Control means (for example, the tap number determination circuit 13 in FIG. 1) for changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the estimation means. .

A control method or program according to one aspect of the present invention includes:
A program that causes a computer to execute a control method or a control process of a control device (for example, the demodulator circuit 1 of FIG. 1) that controls an equalizer that equalizes an input signal (for example, the equalizer 11 of FIG. 1).
An estimation step for estimating an error rate from the input signal equalized by the equalizer (eg, steps S3 and S6 in FIG. 3);
A control step (for example, steps S4 and S8 in FIG. 3) for changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the processing of the estimation step; A program that causes a computer to execute a control method or control process.

  Embodiments to which the present invention is applied will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a demodulation circuit 1 having an equalizer.

  The demodulation circuit 1 is supplied with an IF (Intermediate Frequency) signal from an RF (Radio Frequency) circuit (not shown) in the preceding stage.

  The demodulation circuit 1 inputs the IF signal supplied thereto, equalizes distortion and delay with respect to the input signal, and uses the resulting equalized signal as an output signal, for example, as shown in FIG. This is supplied to a demodulation processing circuit (not shown). In this demodulation processing circuit, the signal supplied thereto is demodulated by a predetermined modulation method, error correction, and the like.

  The demodulation circuit 1 estimates an error rate (decoding) such as MER (Modulation Error Rate) or BER (Bit Error Rate) from the equalized signal obtained as a result of equalization with respect to the input signal, and based on the error rate. Then, processing for changing the number of operation taps of the equalizer (hereinafter referred to as operation tap number change processing) is performed.

  A configuration example of the demodulation circuit 1 that realizes the operation tap number changing process will be described.

  The demodulating circuit 1 includes an equalizer 11, an error rate estimating circuit 12, and a tap number determining circuit 13.

  The equalizer 11 is composed of, for example, an FIR filter. The equalizer 11 equalizes the input signal input to the demodulation circuit 1 and supplies the equalized signal obtained as a result to the error rate estimation circuit 12 as an output signal. For example, the above-described demodulation processing circuit To supply.

  Further, the equalizer 11 changes the number of operation taps among a plurality of taps constituting itself based on the tap number information supplied from the tap number determination circuit 13.

  The error rate estimation circuit 12 includes, for example, a MER estimation circuit, a BER estimation circuit, and the like, estimates an error rate such as MER and BER from the output signal output from the equalizer 11, and notifies the tap number determination circuit 13. To do. Note that the MER estimation circuit and the BER estimation circuit are known in the communication field, and for the BER estimation circuit, for example, a method using a block error rate is known.

  The tap number determination circuit 13 determines, for example, to change the number of operation taps by a predetermined number based on the error rate notified from the error rate estimation circuit 12, and equalizes the tap number information indicating that fact. 11 is supplied. Thereby, the tap number determination circuit 13 changes the number of operation taps of the equalizer 11.

  Next, a configuration example of the equalizer 11 will be described with reference to FIG.

The equalizer 11 includes delay elements 41 _{1 to} 41 ₄ (hereinafter referred to as delay elements 41 when not individually distinguished, the same applies in other cases), multipliers 42 _{1 to} 42 ₅ , addition And a clock coefficient output circuit 45. The delay element 41 is configured by, for example, a delay flip-flop, and the multiplier 42, the adder 43, and the tap number determining circuit 44 are configured by, for example, a logic circuit. The clock output circuit 45 is composed of a clock module including, for example, a vibrator and an oscillation circuit.

That is, in the case of this example, the equalizer 11, the tap consists of multipliers 42 ₁ # 0, the tap # 1 consisting of delay elements 41 ₁ and the multiplier 42 _2, consisting of delay elements 41 ₂ and a multiplier 42 ₃ Tap # 2, has five taps of the tap # 4 consisting of tap # 3, and the delay element 41 ₄ and the multiplier 42 ₅ consists delay element 41 ₃ and a multiplier 42 _4.

The multiplier 42 ₁ of the tap # 0 multiplies the input signal supplied thereto by the tap coefficient h ₀ output from the tap coefficient determination circuit 44, and outputs the multiplication result to the adder 43.

Delay element 41 ₁ of tap # 1, and only one clock delay of the clock which is supplied with an input signal input thereto from the clock output circuit 45, the multiplier 42 ₂ and the delay element 41 ₂ of the tap # 2 Supply. The multiplier 42 ₂ multiplies the signal output from the delay element 41 ₁ by the tap coefficient h ₁ output from the tap coefficient determination circuit 44 and supplies the multiplication result to the adder 43.

Delay element 41 ₂ of the tap # 2 is only one clock delay of the clock which is supplied with an input signal inputted from the delay element 41 ₁ of tap # 1 from the clock output circuit 45, a multiplier 42 _3, and tap # 3 to the delay element 41 ₃ . The multiplier 42 ₃ multiplies the signal supplied from the delay element 41 ₂ by the tap coefficient h ₂ output from the tap coefficient determination circuit 44 and supplies the multiplication result to the adder 43.

The delay element 41 ₃ of the tap # ₃ delays the input signal input from the delay element 41 ₂ of the tap # 2 by one clock of the clock supplied from the clock output circuit 45, and the multiplier 424 and the tap # ₄ This is supplied to _four delay elements 41 ₄ . The multiplier 42 ₄ multiplies the signal supplied from the delay element 41 ₃ by the tap coefficient h ₃ output from the tap coefficient determination circuit 44 and supplies the multiplication result to the adder 43.

Delay element 41 ₄ taps # 4 is delayed by one clock of the clock signal supplied to an input signal inputted from the delay element 41 ₃ of tap # 3 from the clock output circuit 45 is supplied to the multiplier 42 ₅ . The multiplier 42 ₅ multiplies the signal supplied from the delay element 41 ₄ by the tap coefficient h ₄ output from the tap coefficient determination circuit 44 and supplies the multiplication result to the adder 43.

The adder 43 adds all the outputs from the respective multipliers 42 ₁ to the multiplier 42 ₅ taps # 0 through tap # 4, and supplies the error rate estimation circuit 12 and the addition result as an output signal, e.g. This is supplied to the demodulation processing circuit described above.

Specifically, in the equalizer 11, Assuming that the input signal x _k of the k clock there at time k is input, as shown in equation (1), the four clocks before (ie 4 clocks past ) Input signal x _k-4 and tap coefficient h ₄ multiplication result (h ₄ · x _k-4 ) 3 clocks past input signal x _k-3 and tap coefficient h ₃ multiplication result (h ₃ · x _k-3 ) Multiplying result of input clock x _{k-2 of} 2 clocks past and tap coefficient h ₂ (h ₂ · x _k-2 ) Input signal x _{k-1 of} past 1 clock and tap coefficient h ₁ Multiplication result (h ₁ · x _k-1 ) and the input signal x _k just input and the multiplication result (h ₀ · x _k ) of the tap coefficient h ₀ are added, and the addition result is the k-th clock. It is outputted as the output signal y _k of.

The tap coefficient determination circuit 44, for example, based on the tap number information supplied from the tap number determination circuit 13, for example, an output signal supplied from the adder 43 to the tap coefficient determination circuit 44 and a predetermined signal determined in advance. differences so smaller, and updates the tap coefficients h ₀ to h _4, starts the process of setting the multiplier 42 ₁ to the multiplier 42 ₅ (referred to as optimization updating process). This optimization update processing is performed when, for example, the transmission side transmits the predetermined signal described above periodically or irregularly via the transmission path, and the reception side (demodulation circuit 1 side) receives the signal. To be started.

The tap coefficient determination circuit 44 changes the tap coefficients h _{0 to} h ₄ (fixed to 0 in this example) based on the tap number information supplied from the tap number determination circuit 13.

  Further, the tap coefficient determination circuit 44 supplies a control signal for controlling the clock supply to each of the taps # 0 to # 4 to the clock output circuit 45 based on the tap number information supplied from the tap number determination circuit 13. To do.

  The clock output circuit 45 generates a clock based on the control signal from the tap coefficient determination circuit 44 and supplies it to the delay elements 41 and the multipliers 42 of the taps # 0 to # 4.

  Next, the operation of the demodulation circuit 1 when the operation tap number changing process is executed will be described with reference to the flowchart of FIG.

  The operation tap number changing process is started when, for example, the tap number determining circuit 13 issues a command for instructing the start of the operation tap number changing process periodically or irregularly.

  In step S1, the tap number determination circuit 13 determines to initialize the number of operation taps to the total number of taps (here, 5), and tap number information for instructing to initialize the number of operation taps. This is supplied to the equalizer 11.

  In step S2, the equalizer 11 initializes the number of operation taps to the total number of taps based on the tap number information supplied from the tap number determination circuit 13 and instructing the initialization of the number of operation taps. To do.

Specifically, the tap coefficient determination circuit 44 of the equalizer 11 supplies a control signal for starting the supply of the clock to each of the taps # 0 to # 4 to the clock output circuit 45 and the tap coefficient h _0. If any one of h ₄ to h ₄ is fixed, the optimization update process for the tap coefficients h _{0 to} h ₄ is started after the fixing is released. As a result, equalization processing is performed using tap coefficients h _{0 to} h ₄ that are appropriately updated by the optimization update processing.

  In step S <b> 3, the error rate estimation circuit 12 estimates the initial error rate from the output signal equalized and output by the equalizer 11, and notifies the tap number determination circuit 13.

  In step S <b> 4, the tap number determination circuit 13 supplies the equalizer 11 with tap number information that instructs to reduce the number of operation taps by one, for example.

  In step S5, the equalizer 11 reduces the number of operating taps by 1 based on the tap number information instructed to reduce the number of operating taps by 1 supplied from the tap number determination circuit 13 in step S4. Equalization.

  Specifically, the tap coefficient determination circuit 44 of the equalizer 11 has the largest tap coefficient subscript number among the operation taps based on the tap number information instructing to reduce the number of operation taps by one. The tap coefficient of the tap is fixed to 0, for example. Note that tap coefficients are fixed in order from taps with a large number of subscripts of tap coefficients, that is, taps used for equalization of a delayed signal with a larger delay amount. Further, for taps with fixed tap coefficients, the tap coefficients are not updated by the optimization update process until the fixing is canceled in step S8 described later.

For example, when all taps # 0 to # 4 is in operation the tap is secured to the tap # 0 to # tap coefficient h ₄ 0 subscript number is the largest tap # 4 of the tap coefficients of the four . In other words, in this case, the output signal y _k is expressed by Expression (2).

  By fixing the tap coefficient of the tap in this way, it is possible to save the power consumed by the tap multiplier 42 with the fixed tap coefficient.

  The tap coefficient determination circuit 44 supplies the clock output unit 45 with a control signal for stopping the supply of the clock to the tap having the fixed tap coefficient, and stops the supply of the clock to the tap.

In the present example, the tap coefficient determining circuit 44 supplies the clock to the tap # 4 by supplying a control signal for stopping the supply of the clock to the tap # 4 corresponding to the tap coefficient h ₄ clock output section 45 Stop.

Since the tap coefficient h ₄ is 0 term of next tap coefficient h ₄ is 0, the output from the tap # 4 is not required. Therefore, the supply of the clock to the tap # 4 can be stopped in this way. If the supply of the clock to the tap whose tap coefficient is fixed to 0 is stopped, the operations of the delay element 41 and the multiplier 42 constituting the tap are stopped, so that the power consumed by these can be saved. .

  In step S6, the error rate estimation circuit 12 estimates the error rate from the output signal equalized and output by the equalizer 11 in which the number of operation taps is reduced by 1 in step S5, and notifies the tap number determination circuit 13 of the error rate. To do.

In step S7, the tap number determination circuit 13 determines whether the difference between the error rate after the reduction in the number of operation taps and the initial error rate is equal to or greater than a predetermined threshold. If it is determined in step S7 that the difference between the error rate after reducing the number of operating taps and the initial error rate is not equal to or greater than a predetermined threshold, that is, the error rate after reducing the number of operating taps is a predetermined error rate (initial error rate). If the error rate is smaller than the error rate obtained by subtracting a predetermined threshold from the rate, the process returns to step S4, and the same process is performed thereafter. That is, equalization is performed by further reducing the number of operation taps by one based on the tap number information instructing to reduce the number of operation taps by one. For example, among the tap # 0 to # 3 are turned operating tap, the tap coefficient h ₃ subscript tap # 3 number is the greatest of the tap coefficients are fixed at 0, as shown in equation (3) Output Signal y _k is output.

  If it is determined in step S7 that the difference between the error rate after reducing the number of operating taps and the initial error rate is smaller than a predetermined threshold, that is, the error rate after reducing the number of operating taps is a predetermined error rate (initial error rate). If the error rate is equal to or greater than the error rate obtained by subtracting a predetermined threshold from the rate, the process proceeds to step S8, and the error rate after the reduction in the number of operation taps determines the allowable lower limit signal quality. Since it exceeds the rate, the tap number determination circuit 13 supplies the equalizer 11 with tap number information for instructing to increase the number of operation taps by 1 (to reduce the number of operation taps to that before reduction). .

  In step S <b> 9, the equalizer 11 increases the number of operation taps by 1 based on the tap number information supplied from the tap number determination circuit 13 and instructing to increase the number of operation taps by 1.

  Specifically, the tap coefficient determination circuit 44 of the equalizer 11 fixes the tap coefficient of the tap with the smallest number of subscripts of the tap coefficient among the non-operating taps whose tap coefficient is fixed to 0. Is released, and the optimization update process for the tap is started.

For example, when the number of operation taps is increased by 1 when there are two operation taps # 0 and # 1, the subscript of the non-operational taps # 2 to # 4 whose tap coefficient is fixed to 0 the number of taps # 2 of the tap coefficients h ₂ fixed smallest is released. The output signal y _k after the tap # 2 is newly set as an operation tap in this way is expressed by Equation (3).

  Further, the tap coefficient determination circuit 44 supplies the clock output unit 45 with a control signal for starting the clock supply to the tap because the supply of the clock to the tap whose tap coefficient is fixed to 0 is stopped. The clock supply to the tap is started.

  In this example, the tap coefficient determination circuit 44 supplies a control signal for starting the supply of the clock to the tap # 2 to the clock output unit 45 to start the supply of the clock to the tap # 2.

As a result, the delay element 41 ₂ and the multiplier 42 ₃ of the tap # 2 start to operate, and the output from the tap # 2 is supplied to the adder 43.

  Thereafter, the operation tap number changing process ends.

  As described above, the demodulation circuit 1 equalizes the input signal by the equalizer 11, estimates the error rate from the input signal equalized by the equalizer 11, and equalizes based on the estimated error rate. Since the number of operation taps among the plurality of taps constituting the equalizer 11 is changed, for example, the number of operation taps of the equalizer can be changed according to the signal quality after equalization. As a result, the effective power consumption of the demodulation circuit can be reduced.

Here, although the total number of taps of the equalizer 11 is five, the total number of taps is not limited to this. For example, when the total number of taps is n + 1 (this equalizer is called FIR of (n + 1) tap) and the operation taps are all taps, the output signal y _k of the k-th clock is given by the formula ( 3).

Here, h _j is a coefficient of the input signal x _kj of the kjth (0 ≦ j ≦ n) clock, and is a tap coefficient of the tap #j.

  Further, the tap number determining circuit 13 can be provided with an externally settable register for holding the predetermined threshold value used in step S7 of FIG. 3, so that the predetermined threshold value is set to an arbitrary value from the outside. It may be.

  The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software executes various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a program recording medium in a general-purpose personal computer or the like.

  FIG. 4 is a block diagram illustrating an example of a hardware configuration of a computer that executes the above-described series of processes using a program.

  In the computer, a CPU 61, a ROM (Read Only Memory) 62, and a RAM (Random Access Memory) 63 are connected to each other by a bus 64.

  An input / output interface 65 is further connected to the bus 64. The input / output interface 65 includes an input unit 66 including a keyboard, a mouse, and a microphone, an output unit 67 including a display and a speaker, a storage unit 68 including a hard disk and a non-volatile memory, and a communication unit 69 including a network interface. A drive 70 for driving a removable medium 71 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is connected.

  In the computer configured as described above, the CPU 61 loads, for example, the program stored in the storage unit 68 to the RAM 63 via the input / output interface 65 and the bus 64 and executes the program, and the series described above. Is performed.

  The program executed by the computer (CPU 61) is, for example, a magnetic disk (including a flexible disk), an optical disk (CD-ROM (Compact Disc-Read Only Memory), DVD (Digital Versatile Disc), etc.), a magneto-optical disk, or a semiconductor. The program is recorded on a removable medium 71 that is a package medium including a memory or the like, or is provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

  The program can be installed in the storage unit 68 via the input / output interface 65 by attaching the removable medium 71 to the drive 70. The program can be received by the communication unit 69 via a wired or wireless transmission medium and installed in the storage unit 68. In addition, the program can be installed in the ROM 62 or the storage unit 68 in advance.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

2 is a diagram illustrating a configuration example of a demodulation circuit 1. FIG. 2 is a diagram illustrating a configuration example of an equalizer 11. FIG. It is a figure which shows operation | movement of the demodulation circuit 1 in an operation tap number change process. It is a block diagram which shows the structural example of the hardware of the computer to which this invention is applied.

Explanation of symbols

1 demodulation circuit 11 equalizer 12 error rate estimation circuit 13 taps decision circuit, 41, 41 ₁ to 41 ₄ delay elements, 42 ₁ to 42 ₅ multipliers, 43 an adder, 44 a tap coefficient determining circuit , 45 clock output circuit, 61 CPU, 62 ROM, 63 RAM, 64 bus, 65 I / O interface, 66 input section, 67 output section, 68 storage section, 69 communication section, 70 drive, 71 removable media

Claims (9)

In a control device that controls an equalizer that equalizes an input signal,
Estimating means for estimating an error rate from the input signal equalized by the equalizer;
A control device comprising: control means for changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the estimation means. The control unit determines whether the error rate estimated by the estimation unit is smaller than a predetermined error rate, and reduces the number of operation taps when determining that the error rate is smaller than a predetermined error rate. Item 2. The control device according to Item 1. The control means determines whether the error rate estimated by the estimation means is smaller than a predetermined error rate from the input signal equalized by the equalizer with the number of operation taps after reduction, and the error The control device according to claim 2, wherein when it is determined that the rate is equal to or higher than a predetermined error rate, the number of operation taps before reduction is set. The control device according to claim 1, wherein the estimation unit is a MER (Modulation Error Rate) estimation circuit or a BER (Bit Error Rate) estimation circuit. The control means includes
When reducing the number of operation taps, the tap coefficient of the tap corresponding to the reduction of the number of operation taps is fixed,
The control device according to claim 1, wherein when the number of operation taps is increased, the tap coefficient of the tap corresponding to the increase in the number of operation taps is released. The control means includes
When reducing the number of operation taps, stop the supply of the clock to the tap corresponding to the reduction of the number of operation taps,
The control device according to claim 1, wherein when the number of operation taps is increased, supply of a clock to a tap corresponding to the increase in the number of operation taps is started. The control device according to claim 1, wherein the equalizer includes an FIR (Finite Impulse Response Filter) filter. In a control method of a control device that controls an equalizer that equalizes an input signal,
An estimation step for estimating an error rate from the input signal equalized by the equalizer;
A control step of changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the processing of the estimation step. In a program that causes a computer to execute control processing of a control device that controls an equalizer that equalizes an input signal,
An estimation step for estimating an error rate from the input signal equalized by the equalizer;
A program for causing a computer to execute a control process including: a control step of changing the number of operation taps among a plurality of taps constituting the equalizer based on the error rate estimated by the process of the estimation step.

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