JP2009081565A - Operational amplifier circuit and sample hold circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operational amplifier circuit capable of operating with a low power consumption, and to provide a sample hold circuit using the operation amplifier. <P>SOLUTION: A level shifting circuit comprises: a first and a second reference voltage formation circuits; a first capacitor; a plurality of first switches arranged between the first capacitor and the first and the second reference voltage formation circuits; a second capacitor of which the one end and the other end are connected to an amplifier circuit; a plurality of second switches arranged between the first capacitor and the second capacitor; a third capacitor; a plurality of third switches arranged between the third capacitor and the first and the second reference voltage formation circuits; a fourth capacitor of which the one end and the other end are connected to the amplifier circuit; a plurality of fourth switches arranged between the third capacitor and the fourth capacitor; and a switch control portion. The switch control portion controls to turn on and off alternatively the plurality of first switches and the plurality of second switches, and controls to turn on and off alternatively the plurality of third switches and the plurality of fourth switches. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an operational amplifier circuit and a sample-and-hold circuit, for example, an operational amplifier circuit that performs a push-pull operation.

Conventionally, a push-pull output stage capable of obtaining a large driving capability with a small bias current has been used as an output stage in an operational amplifier circuit. In order to realize the push-pull operation, a level shift circuit is required to drive the P-channel transistor (PMOS transistor) and the N-channel transistor (NMOS transistor). However, in the case of the conventional method, a configuration is adopted in which a constant current is passed through the level shift circuit. For this reason, there was a problem that power consumption becomes high. Further, in the conventional method, since the current is turned back by the current mirror circuit, there is a problem that more current is required.
CK. Wang, R. Castello and PR Gray, “A Scalable High-Performance Switched-Capacitor Filter,” IEEE Journal of solid-state circuits, vol. Sc-21, No. 1, February 1986

  The present invention provides an operational amplifier circuit with reduced power consumption and a sample-and-hold circuit using the operational amplifier.

An operational amplifier circuit according to one embodiment of the present invention includes:
First and second input terminals;
A first conductivity type first and second transistor having one end connected to a ground terminal and a gate connected to the first and second input terminals;
First and second transistors of the second conductivity type, one end of which is connected to the power supply voltage terminal;
A first output terminal connected between the other end of the first conductivity type first transistor and the other end of the second conductivity type first transistor;
A second output terminal connected between the other end of the first conductivity type second transistor and the other end of the second conductivity type second transistor;
An amplifier circuit having
The first input voltage input to the first input terminal is level-shifted and applied to the gate of the second conductivity type first transistor, and the second input voltage input to the second input terminal is level-shifted. And a level shift circuit for supplying to the gate of the second transistor of the second conductivity type,
The level shift circuit includes:
First and second reference voltage generation circuits for generating and outputting different first and second reference voltages, respectively;
A first capacitor;
A plurality of terminals provided between one end of the first capacitor and the output of the first reference voltage generation circuit, and between the other end of the first capacitor and the output of the second reference voltage generation circuit. A first switch;
A second capacitor having one end connected to the first input terminal and the other end connected to the gate of the second transistor of the second conductivity type;
A plurality of second capacitors provided between the one end of the first capacitor and one end of the second capacitor, and between the other end of the first capacitor and the other end of the second capacitor. A switch,
A third capacitor;
A plurality of terminals provided between one end of the third capacitor and the output of the first reference voltage generation circuit, and between the other end of the third capacitor and the output of the second reference voltage generation circuit. A third switch;
A fourth capacitor having one end connected to the second input terminal and the other end connected to the gate of the second transistor of the second conductivity type;
A plurality of fourth capacitors provided between the one end of the third capacitor and one end of the fourth capacitor, and between the other end of the third capacitor and the other end of the fourth capacitor. A switch,
The plurality of first switches and the plurality of second switches are controlled to be turned on / off alternately, and the plurality of third switches and the plurality of fourth switches are alternately turned on / off. A switch controller for controlling
It is characterized by having.

  A sample-and-hold circuit as one embodiment of the present invention includes the operational amplifier circuit.

  According to the present invention, the power consumption of the operational amplifier circuit and the sample hold circuit using the operational amplifier can be reduced.

  Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a configuration of an operational amplifier circuit according to a first embodiment of the present invention.

  The operational amplifier circuit includes differential input terminals IN + and IN−, an amplifier circuit (amplifier) 31, a level shift unit 11, a switch control unit 34 that controls the level shift unit 11 using a clock source 35, and an output. Terminals OUT− and OUT + are provided.

  The level shift unit has input terminals A and B and output terminals A ′ and B ′, and performs a level shift between A and A ′ and a level shift between B and B ′. The switch control unit 34 and the level shift unit 11 form a level shift circuit 36.

  The amplifier circuit 31 has two sets of differential input terminals 32 and 33. The differential input signals input from the input terminals IN + and IN− are input to one differential input terminal 32 of the amplifier circuit 31 and the input terminals A and B of the level shift unit 11. The differential input signal input to the level shift unit 11 is level-shifted, output from the output terminals A ′ and B ′, and input to the other differential input terminal 33 of the amplifier circuit.

  The differential output signal of the amplifier circuit 31 is output from the differential output terminals OUT− and OUT +. A drive load (see FIG. 4) such as a capacitor is connected to the differential output terminals OUT− and OUT +.

  FIG. 2 shows a configuration of the level shift unit 11 in the level shift circuit 36.

The level shifter 11 has a capacitor _{C 1} for two push-pull operation, a capacitor _{C 2} for the two transfer, the four switches phi _1, and four switches phi _2, buffer Vref, and Vref ' . Two capacitors C ₁ has the same capacitance value, two capacitors C ₂ have the same capacitance value. The four switches phi ₁ is turned on and off at the same timing, the four switches phi ₂ is turned on and off at the same timing.

Capacitance value of the capacitor _{C 1} is greater than the capacitor _{C 2.} Of the two capacitors C _1, One 'is connected to the other is always input terminal of the level shift section B and the output terminal B' always input terminal A and the output terminal A of the level shifter 11 is connected to.

When the switch phi ₁ is turned on, the switch phi ₂ is off, the two capacitors _{C 2,} buffer Vref, Vref 'voltage between (bias voltage) is applied, charges are charged. On the other hand, when the switch phi ₁ is turned off, the switch phi ₂ is on, the two capacitors C ₂ are connected in parallel with the capacitor C _1, the capacitor C ₁ to the charge stored in the capacitor C _2, connected in parallel Forward to. In FIG. 2, two capacitors _{C 2} and the buffer Vref, 'but connects the buffer Vref, Vref' Vref prepared two respectively, capacitors _{C 2} and the buffer Vref, the Vref '1-one You may connect with. However, as will be described later, when the buffers Vref and Vref ′ are shared by the _two capacitors C2 as shown in FIG. 2, the power consumption of the level shift circuit can be reduced.

  The buffers Vref and Vref ′ operate as a reference voltage generation circuit when one end thereof is connected to the reference voltage terminal, and outputs a reference voltage to the capacitor C. By installing a buffer between the reference voltage terminal and the capacitor C, the capacitor C is driven in a state where the output impedance of the reference voltage generation circuit is low.

FIG. 3 is a timing chart showing the control timing of the switches φ ₁ and φ ₂ .

The switches φ ₁ and φ ₂ are alternately turned on / off. On / off control is performed by the switch control unit 34. The switch control unit 34 includes a clock source 35, and switches on and off the switches φ ₁ and φ ₂ alternately at regular time intervals based on the clock supplied from the clock source 35.

As described above, when the switch phi ₁ switch phi ₂ are off, the capacitor C ₂ by applying a bias voltage, when the switch phi ₂ is ON switch phi ₁ is off is accumulated in the capacitor C ₂ the charges transferred to the capacitor C _1. At one of the capacitors C ₁ terminal A-A 'level shift between done, terminals B-B at the other of the capacitor C _1' is the level shift between performed.

Since the value of the capacitance of the capacitor C ₂ is made smaller than the capacitor C _1, it takes time to rise (to charge the capacitor C ₁ is charged), by reducing the capacitance value of the capacitor C _2, The currents of the buffers Vref and Vref ′ can be reduced, and the sizes of the buffers Vref and Vref ′ can be reduced.

Here is turned on and off four switches phi ₂ are all at the same time, four switches phi ₁ is an example where all are turned on and off at the same timing, the switch phi connected for example terminal B, and B ' _2, terminal a, 'and the timing of on and off with the switch phi ₂ to be connected to the contrary, in accordance with this, the terminal B, B' a switch phi ₁ that is connected to the side terminals a, a the timing of on and off with the switch phi ₁ that is connected to the 'side may be reversed.

  As described above, according to the first embodiment, by employing the level shift unit having the configuration as shown in FIG. 2 in the operational amplifier, it is not necessary to flow a bias current through the level shift unit itself, and the operational amplifier can be reduced. Power consumption can be reduced. In addition, by driving the amplifier circuit 31 by a push-pull operation using the level shift circuit, the driving ability of the operational amplifier circuit can be increased with a small bias current.

Here, in the configuration of the level shift unit of FIG. 2, a buffer Vref to supply charges to the capacitor C _2, Vref 'but is required, after power-on, once, once accumulated charge in the capacitor C _1, Almost no charge needs to be supplied from the buffers Vref and Vref ′. For this reason, it is possible to reduce the currents of the buffers Vref and Vref ′ as long as the period until the circuit becomes operable after the power is turned on is allowed. In addition, by making the buffers Vref and Vref ′ differentially common, the difference in differential voltage between the _two capacitors C2 is averaged by charge redistribution during charging, so that the buffer current is further reduced. be able to. This will be described with reference to FIG.

FIG. 4 is a diagram showing a case where the switch φ1 is turned on in FIG. 2 and the capacitor C2 and the buffers Vref and Vref ′ are connected. The capacitor C ₂ transfers charges to the capacitor C ₁ when the switch φ ₁ is off and the switch φ ₂ is on. Therefore, when the switch φ ₁ is on, the average value V (for example, Vref, Vref ′ A differential voltage shift ΔV occurs with respect to the voltage difference. Deviation ΔV of the differential voltage, the switch phi ₁ is turned on, the capacitor C ₂ is connected buffers Vref, the Vref ', (reallocation is performed in the charge) which redistributed the at capacitor C ₂ to each other . Therefore, the driving capability of the buffers Vref and Vref ′ can be small, and the current of the buffers Vref and Vref ′ can be reduced.

  In FIG. 2, buffers Vref and Vref 'correspond to first and second reference voltage generation circuits that generate and output different first and second reference voltages, for example.

The terminal A, A 'capacitor C ₂ provided on the side corresponds to, for example, a first capacitor, the terminal A, A' 2 two switches phi ₁ provided on the side corresponds to the first switch for example, terminals a, a 'capacitor C ₁ connected to correspond to, for example, a second capacitor, terminals a, a' 2 two switches phi ₂ provided on the side corresponding to the first switch, for example.

The terminal B, B 'side two switches phi ₁ provided corresponds to, for example, the third switch, the terminal B, B' capacitor C ₂ provided on the side corresponds to, for example, a third capacitor, terminals The capacitor C ₁ connected to B and B ′ corresponds to, for example, a fourth capacitor, and the two switches φ ₂ provided on the terminals B and B ′ side correspond to, for example, a fourth switch.

FIG. 5 shows a configuration example of a level shift unit using two transfer capacitors for each system (AA ′ and BB ′). Capacitor _{C 2} and _{C 3} is a capacitor for transfer. The advantage of using two transfer capacitors is that the first is that the capacitors C ₂ and C ₃ have the same capacitance, and the phases (the phase in which the switch φ ₁ is on and the phase in which the switch φ ₂ is on) Regardless, the capacity (level shift capacity) between the terminals AA ′ (and terminals BB ′) is the same. That is, 'when taking as an example, when the switch phi ₁ switch phi ₂ are off, the terminal A-A' terminal A-A for the capacitor C ₁ and C ₃ are connected in parallel between terminal A- The capacity of A ′ is C ₁ + C _3. On the other hand, when the switch φ ₁ is off and the switch φ ₂ is on, the capacitors C ₁ and C ₂ are connected in parallel between the terminals AA ′, so the terminal A The capacity between −A ′ is C ₁ + C ₂ . Therefore, when C ₂ = C ₃ , the capacity of the terminal AA ′ is the same in each phase. The same can be said for the terminal BB ′. The second advantage of using two transfer capacitors is that the capacitor C ₁ is charged with the charges accumulated in the _two capacitors C ₂ and C ₃ , so that the rise is quick.

In FIG. 5, a capacitor C ₃ provided on the terminals A and A ′ side corresponds to, for example, a fifth capacitor, and two switches φ ₂ between the capacitor C ₅ and the buffers Vref and Vref ′ are, for example, It corresponds to the fifth switch, the capacitor C ₅ and the terminal a, 2 two switches phi ₁ between a 'corresponds to the example sixth switch.

The capacitor C ₃ provided on the terminals B and B ′ side corresponds to, for example, a sixth capacitor. Two switches φ ₂ between the capacitor C ₃ and the buffers Vref and Vref ′ are, for example, the seventh switch. equivalent to, the capacitor C ₃ and the terminal B, 2 two switches phi ₁ between B 'corresponds to the eighth switch, for example.

  FIG. 6 is a circuit diagram showing an example of a detailed configuration of an amplification arithmetic circuit including the level shift unit of FIG. However, illustration of the switch control unit is omitted for simplicity of the drawing.

  The amplifier (amplifier) 31 shown in FIG. 1 is composed of MOS transistors. If there is a margin in voltage, the one-stage telescopic type as shown in the figure minimizes the current path, so this configuration is useful for low power consumption.

The gates of N-channel transistors (NMOS transistors) M1 and M2 are connected to the input terminals A and B of the level shift unit and the input terminals IN + and IN−. N-channel transistor M1 corresponds to, for example, a first transistor of the first conductivity type, and N-channel transistor M2 corresponds to, for example, a second transistor of the first conductivity type. Output terminals A ′ and B ′ of the level shift unit are connected to the gates of P-channel transistors (PMOS transistors) M3 and M4. P-channel transistor M3 corresponds to, for example, a first transistor of the second conductivity type, and P-channel transistor M4 corresponds to, for example, a second transistor of the second conductivity type. The level shifter operates so as to make the voltage between the gates of the transistors M1 and M3 and the voltage between the gates of the transistors M2 and M4 as constant as possible regardless of variations in the input voltages at the input terminals IN + and IN−. Voltage between the gate corresponds to the voltage of the capacitor C ₁ of the level shifter.

The connection point of the drain of N-channel transistor M1, a drain of the P-channel transistor M3 via the output terminal OUT-, connected to one end of the capacitor C _L as a drive load. The other end of the capacitor C _L is connected to the ground (ground terminal).

Connection point of the drains of P-channel transistor M4 of the N-channel transistor M2 via the output terminal OUT +, is connected to one end of the capacitor C _L as a drive load. The other end of the capacitor C _L is connected to the ground (ground terminal).

  The sources of the P-channel transistors M3 and M4 are connected to the drain of the P-channel transistor M5, and the source of the P-channel transistor M5 is connected to the power supply potential (power supply voltage terminal). The three P-channel transistors M3, M4, and M5 form a so-called differential pair configuration.

  The sources of the N-channel transistors M1 and M2 are connected to the drain of the N-channel transistor M6, and the source of the N-channel transistor M6 is connected to the ground (ground terminal). Three N-channel transistors M1, M2, and M6 form a differential pair configuration.

When the input terminal IN + of the input voltage is raised, the output terminal OUT + to the connected capacitor C _L of the voltage (output voltage) also increases. The arrow in FIG. 6 indicates the location of the current that increases when the input voltage at the input terminal IN + increases. The output terminal OUT + to a capacitor connected (load capacitance) C _L is driven by P-channel transistor M4, the current of the P-channel transistor M4, and more than the bias current at no signal, the push-pull operation . On the other hand, the output voltage of the reverse-phase (the voltage of the capacitor C _L coupled to the output terminal OUT-), since the N-channel transistor M1 draws current from the capacitor C _L, it will be lowered. At this time, the current of the N-channel transistor M1 is larger than the bias current when there is no signal.

  Although FIG. 6 shows an example in which a differential pair configuration is used in each of the P-channel input stage and the N-channel output stage, a differential pair configuration may be used for only one conductivity type. FIG. 7 shows an example of an operational amplifier circuit using a differential pair configuration for only one conductivity type. In this example, a differential pair configuration is used only for the P-channel input stage.

  FIG. 8 is obtained by changing the amplifier circuit (amplifier) shown in FIG. 6 to a cascode configuration.

That is, the source of the N channel transistor M11 is connected to the drain of the N channel transistor M1, the drain of the N channel transistor M11 is connected to the drain of the P channel transistor 12, and the source of the P channel transistor 12 is connected to the drain of the P channel transistor M3. Has been. Connection point of the drains of P-channel transistor 12 of the N-channel transistor M11 is connected to one end of the capacitor C _L as a driving load via the output terminal OUT-.

The source of the N channel transistor M13 is connected to the drain of the N channel transistor M2, the drain of the N channel transistor M13 is connected to the drain of the P channel transistor 14, and the source of the P channel transistor 14 is connected to the drain of the P channel transistor M4. Has been. Connection point of the drain of N-channel transistor M13 of the drain and the P-channel transistor 14 is connected to one end of the capacitor C _L as a driving load via the output terminal OUT +.

  The gates of the N-channel transistors M11 and M13 are connected in common and set to a certain reference potential. The gates of the P-channel transistors M12 and M14 are connected in common and set to another reference potential.

  By adopting such a cascode configuration, the output impedance is increased and a large gain can be obtained.

  In FIG. 8, the differential pair configuration is used in each of the P-channel input stage and the N-channel output stage. However, as in FIG. 7, the differential pair configuration may be used for only one conductivity type. FIG. 9 shows an example of an operational amplifier circuit using a differential pair configuration in only one conductivity type in FIG. In this example, a differential pair configuration is used only for the P-channel input stage.

  FIG. 10 shows a configuration of a sample and hold circuit to which the operational amplifier circuit of FIG. 1 is applied.

The sample hold circuit is a circuit that samples an input signal and holds (holds) the sampled voltage on the output side. Since the sample and hold circuit repeats sampling and holding according to the clock signal, the sample and hold circuit can be easily combined with the operational amplifier circuit of FIG. 1 that requires a clock. FIG. 11 shows on / off control timings of the switches φ ₁₁ and φ ₁₂ . The switches φ ₁₁ and φ ₁₂ are alternately turned on / off. When the switch phi ₁₁ is on, the input signal is sampled each capacitor Cs. When switch phi ₁₂ is turned on, it is connected to an input terminal of the level shift unit with each capacitor Cs is connected to the input terminal and the output terminal of the operational amplifier circuit, and holds the sampled voltage. The capacitor _CL is a load driven by the operational amplifier circuit.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

1 is a circuit diagram showing a configuration of an operational amplifier circuit as a first embodiment of the present invention. The circuit diagram which shows the structure of a level shift part. The timing chart of control of each switch in a level shift part. The figure explaining the reason which can reduce the electric current of the buffer in a level shift part. The figure which shows the structural example of the level shift circuit which increased the capacitor for a transfer. FIG. 2 is a circuit diagram illustrating an example of a detailed configuration of an amplification arithmetic circuit in FIG. FIG. 7 is a diagram showing an example in which only one conductivity type is configured as a differential pair in FIG. 6. The figure which shows what changed the amplifier circuit shown in FIG. 6 into the cascode structure. FIG. 9 is a diagram showing an example in which only one conductivity type is configured as a differential pair in FIG. 8. The figure which shows the structure of the sample hold circuit to which the operational amplifier circuit of FIG. 1 is applied. 11 is a timing chart showing control timing of switches in the sample hold circuit of FIG.

Claims (10)

First and second input terminals;
A first conductivity type first and second transistor having one end connected to a ground terminal and a gate connected to the first and second input terminals;
First and second transistors of the second conductivity type, one end of which is connected to the power supply voltage terminal;
A first output terminal connected between the other end of the first conductivity type first transistor and the other end of the second conductivity type first transistor;
A second output terminal connected between the other end of the first conductivity type second transistor and the other end of the second conductivity type second transistor;
An amplifier circuit having
The first input voltage input to the first input terminal is level-shifted and applied to the gate of the second conductivity type first transistor, and the second input voltage input to the second input terminal is level-shifted. And a level shift circuit for supplying to the gate of the second transistor of the second conductivity type,
The level shift circuit includes:
First and second reference voltage generation circuits for generating and outputting different first and second reference voltages, respectively;
A first capacitor;
A plurality of terminals provided between one end of the first capacitor and the output of the first reference voltage generation circuit, and between the other end of the first capacitor and the output of the second reference voltage generation circuit. A first switch;
A second capacitor having one end connected to the first input terminal and the other end connected to the gate of the second transistor of the second conductivity type;
A plurality of second capacitors provided between the one end of the first capacitor and one end of the second capacitor, and between the other end of the first capacitor and the other end of the second capacitor. A switch,
A third capacitor;
A plurality of terminals provided between one end of the third capacitor and the output of the first reference voltage generation circuit, and between the other end of the third capacitor and the output of the second reference voltage generation circuit. A third switch;
A fourth capacitor having one end connected to the second input terminal and the other end connected to the gate of the second transistor of the second conductivity type;
A plurality of fourth capacitors provided between the one end of the third capacitor and one end of the fourth capacitor, and between the other end of the third capacitor and the other end of the fourth capacitor. A switch,
The plurality of first switches and the plurality of second switches are controlled to be turned on / off alternately, and the plurality of third switches and the plurality of fourth switches are alternately turned on / off. A switch controller for controlling
An operational amplifier circuit comprising:   2. The operational amplification according to claim 1, wherein the capacitance of the second capacitor is larger than the capacitance of the first capacitor, and the capacitance of the fourth capacitor is larger than the capacitance of the third capacitor. circuit. The level shift circuit includes:
A fifth capacitor;
A plurality of terminals provided between one end of the fifth capacitor and the output of the first reference voltage generation circuit, and between the other end of the fifth capacitor and the output of the second reference voltage generation circuit. A fifth switch;
A plurality of sixth capacitors provided between the one end of the fifth capacitor and one end of the second capacitor, and between the other end of the fifth capacitor and the other end of the second capacitor. A switch, and
3. The calculation according to claim 1, wherein the switch control unit alternately turns on and off the plurality of first and sixth switches and the plurality of second and fifth switches. Amplification circuit.   4. The operational amplifier circuit according to claim 3, wherein a capacity of the first capacitor and a capacity of the fifth capacitor are substantially the same. The level shift circuit includes:
A sixth capacitor;
A plurality of terminals provided between one end of the sixth capacitor and the output of the first reference voltage generation circuit, and between the other end of the sixth capacitor and the output of the second reference voltage generation circuit. A seventh switch;
A plurality of eighth capacitors provided between the one end of the sixth capacitor and one end of the fourth capacitor, and between the other end of the sixth capacitor and the other end of the fourth capacitor. A switch, and
5. The switch control unit according to claim 1, wherein the plurality of third and eighth switches and the plurality of fourth and seventh switches are alternately turned on and off. The operational amplifier circuit according to one item.   6. The operational amplifier circuit according to claim 5, wherein a capacity of the third capacitor and a capacity of the sixth capacitor are substantially the same.   7. One end of the first and second transistors of the second conductivity type is connected to the power supply voltage terminal via another transistor of the second conductivity type. The operational amplifier circuit according to one item.   One end of the first and second transistors of the first conductivity type is connected to the ground terminal via another transistor of the first conductivity type. The operational amplifier circuit according to the item. A third transistor of the first conductivity type having one end connected to the other end of the first transistor of the first conductivity type;
A second transistor of the second conductivity type having one end connected to the other end of the first transistor of the second conductivity type;
A fourth transistor of the first conductivity type having one end connected to the other end of the second transistor of the first conductivity type and a gate connected to the gate of the third transistor of the first conductivity type;
The second conductivity type second transistor having one end connected to the other end of the second conductivity type second transistor and a gate connected to the gate of the second conductivity type third transistor;
The first output terminal is connected between the other end of the third transistor of the first conductivity type and the other end of the third transistor of the second conductivity type.
The second output terminal is connected between the other end of the fourth transistor of the first conductivity type and the other end of the fourth transistor of the second conductivity type.
The operational amplifier circuit according to claim 1, wherein:   A sample and hold circuit comprising the operational amplifier circuit according to claim 1.

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