JP2009081440A - Adhesive sheet used in method for manufacturing semiconductor device, and semiconductor device obtained by the same method - Google Patents

Adhesive sheet used in method for manufacturing semiconductor device, and semiconductor device obtained by the same method Download PDF

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JP2009081440A
JP2009081440A JP2008270166A JP2008270166A JP2009081440A JP 2009081440 A JP2009081440 A JP 2009081440A JP 2008270166 A JP2008270166 A JP 2008270166A JP 2008270166 A JP2008270166 A JP 2008270166A JP 2009081440 A JP2009081440 A JP 2009081440A
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semiconductor device
manufacturing
adhesive sheet
semiconductor element
resin
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JP5149121B2 (en
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Sadahito Misumi
貞仁 三隅
Takeshi Matsumura
健 松村
Kazuto Hosokawa
和人 細川
Hiroyuki Kondo
広行 近藤
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Nitto Denko Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of manufacturing a high reliability-semiconductor device without changing a conventional manufacturing process, to provide an adhesive sheet used for the method, and to provide the semiconductor device obtained by the method. <P>SOLUTION: The method for manufacturing a semiconductor device including a temporarily fixing process that temporarily fixes a semiconductor device 13 onto a body to be adhered 11 through an adhesive sheet 12, a wire bonding process that performs wire bonding on the semiconductor device 13, and a process that seals the semiconductor device 13 with a sealant resin 15, wherein loss elastic modulus of the adhesive sheet 12 at 175°C is 2,000 Pa or higher. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置の製造方法、当該方法に用いる接着シート及び当該方法により得られる半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device, an adhesive sheet used in the method, and a semiconductor device obtained by the method.

半導体装置の微細化、高機能化の要求に対応すべく、半導体チップ(半導体素子)主面の全域に配置された電源ラインの配線幅や信号ライン間の間隔が狭くなってきている。この為、インピーダンスの増加や、異種ノードの信号ライン間での信号の干渉が生じ、半導体チップの動作速度、動作電圧余裕度、耐静電破壊強度等に於いて、十分な性能の発揮を阻害する要因となっている。これらの問題を解決する為、半導体素子を積層したパッケージ構造が提案されている(下記、特許文献1及び特許文献2参照)。   In order to meet the demand for miniaturization and higher functionality of semiconductor devices, the wiring width of power supply lines and the interval between signal lines arranged over the entire main surface of a semiconductor chip (semiconductor element) are becoming narrower. For this reason, an increase in impedance and signal interference between signal lines of different types of nodes occur, impairing the performance of semiconductor chips in terms of operating speed, operating voltage margin, resistance to electrostatic breakdown, etc. Is a factor. In order to solve these problems, a package structure in which semiconductor elements are stacked has been proposed (see Patent Document 1 and Patent Document 2 below).

一方、半導体素子を基板等に固着する際に使用されるものとしては、熱硬化性ペースト樹脂を用いる例(例えば、下記特許文献3参照)や、熱可塑性樹脂及び熱硬化性樹脂を併用した接着シートを用いる例(例えば、下記特許文献4参照)が提案されている。   On the other hand, what is used when fixing a semiconductor element to a substrate or the like is an example using a thermosetting paste resin (for example, see Patent Document 3 below), or an adhesion using a thermoplastic resin and a thermosetting resin in combination. An example using a sheet (for example, see Patent Document 4 below) has been proposed.

従来の半導体装置の製造方法に於いては、半導体素子と、基板、リードフレーム又は半導体素子との接着に際し、接着シート又は接着剤を使用する。接着は、半導体素子と基板等との圧着の後(ダイアタッチ)、接着シート等を加熱工程により硬化させて行う。さらに半導体素子と基板とを電気的に接続する為にワイヤーボンディングを行い、その後に封止樹脂でモールドし、後硬化して当該封止樹脂の封止を行う。   In a conventional method for manufacturing a semiconductor device, an adhesive sheet or an adhesive is used for bonding a semiconductor element and a substrate, a lead frame, or the semiconductor element. Adhesion is performed after the semiconductor element is bonded to the substrate or the like (die attach), and then the adhesive sheet or the like is cured by a heating process. Further, wire bonding is performed to electrically connect the semiconductor element and the substrate, and thereafter, molding is performed with a sealing resin, followed by post-curing to seal the sealing resin.

近年、半導体素子の薄型化・小型化に伴い、半導体素子の厚さが従来の200μmからそれ以下へ、更には100μm以下にまで薄層化している現状がある。100μm以下の半導体素子を用いてダイアタッチを行うと、該半導体素子に反りが発生することがある。その結果、ダイアタッチ後の半導体素子と被着体との間に空隙が生じる場合がある。空隙を残したまま半導体装置を製造すると、その信頼性が低下するという問題がある。   In recent years, with the reduction in thickness and size of semiconductor elements, the thickness of semiconductor elements has been reduced from the conventional 200 μm to less than that, and further to 100 μm or less. When die attach is performed using a semiconductor element of 100 μm or less, the semiconductor element may be warped. As a result, a gap may be generated between the semiconductor element after die attachment and the adherend. If a semiconductor device is manufactured with a gap left, there is a problem that the reliability is lowered.

特開昭55−111151号公報JP-A-55-1111151 特開2002−261233号公報JP 2002-261233 A 特開2002−179769号公報JP 2002-179769 A 特開2000−104040号公報JP 2000-104040 A

本発明は、前記問題点に鑑みなされたものであり、その目的は、従来の製造工程を変更することなく、高信頼性の半導体装置を製造することが可能な半導体装置の製造方法、当該方法に使用する接着シート及び当該方法により得られる半導体装置を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of manufacturing a highly reliable semiconductor device without changing the conventional manufacturing process, and the method. It is providing the adhesive sheet used for this, and the semiconductor device obtained by the said method.

本願発明者等は、前記従来の問題点を解決すべく、半導体装置の製造方法、当該方法に使用する接着シート及び当該方法により得られる半導体装置について鋭意検討した。その結果、下記構成とすることにより前記目的を達成できることを見出して、本発明を完成させるに至った。   In order to solve the above-described conventional problems, the inventors of the present application have made extensive studies on a semiconductor device manufacturing method, an adhesive sheet used in the method, and a semiconductor device obtained by the method. As a result, the inventors have found that the object can be achieved by adopting the following configuration, and have completed the present invention.

即ち、前記の課題を解決する為に、本発明に係る半導体装置の製造方法は、半導体素子を被着体上に接着シートを介して仮固着する仮固着工程と、前記半導体素子にワイヤーボンディングをするワイヤーボンディング工程と、前記半導体素子を封止樹脂により封止する工程とを含み、前記接着シートとして175℃での損失弾性率が2000Pa以上のものを使用することを特徴とする。   That is, in order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention includes a temporary fixing step of temporarily fixing a semiconductor element on an adherend via an adhesive sheet, and wire bonding to the semiconductor element. And a step of sealing the semiconductor element with a sealing resin, wherein the adhesive sheet has a loss elastic modulus at 175 ° C. of 2000 Pa or more.

前記の方法に於いては、前記封止工程に於いて加熱により封止樹脂を硬化させると共に、前記接着シートを介して半導体素子と被着体とを固着させることが好ましい。   In the above method, it is preferable that the sealing resin is cured by heating in the sealing step, and the semiconductor element and the adherend are fixed to each other through the adhesive sheet.

また、前記の方法に於いては、前記封止樹脂の後硬化を行う後硬化工程を含み、前記封止工程及び/又は後硬化工程に於いて、加熱により封止樹脂を硬化させると共に、前記接着シートを介して半導体素子と被着体とを固着させることが好ましい。   Further, the method includes a post-curing step of performing post-curing of the sealing resin, and in the sealing step and / or the post-curing step, the sealing resin is cured by heating, It is preferable to fix the semiconductor element and the adherend through an adhesive sheet.

また、前記封止工程は、150℃〜200℃の範囲内で行われるのが好ましい。   Moreover, it is preferable that the said sealing process is performed within the range of 150 to 200 degreeC.

また、前記の方法に於いて、前記封止後の半導体素子と被着体との間の接着面積が90%以上であることが好ましい。   In the above method, the adhesion area between the semiconductor element after sealing and the adherend is preferably 90% or more.

また、前記の方法に於いて、前記被着体は、基板、リードフレーム又は半導体素子であることが好ましい。   In the above method, the adherend is preferably a substrate, a lead frame, or a semiconductor element.

前記の方法に於いて、前記被着体が半導体素子である場合に、半導体素子と半導体素子との間に、前記接着シートを介してスペーサを積層する工程を含むことができる。   In the above method, when the adherend is a semiconductor element, the method may include a step of stacking a spacer between the semiconductor element and the semiconductor element via the adhesive sheet.

前記接着シートとして、熱可塑性樹脂を含むものを使用することができる。   As the adhesive sheet, one containing a thermoplastic resin can be used.

また、前記接着シートとして、熱硬化性樹脂と熱可塑性樹脂の双方を含むものを使用することができる。   Moreover, what contains both a thermosetting resin and a thermoplastic resin can be used as the said adhesive sheet.

ここで、前記熱可塑性樹脂としては、アクリル樹脂を使用するのが好ましい。   Here, it is preferable to use an acrylic resin as the thermoplastic resin.

また、前記熱硬化性樹脂としては、エポキシ樹脂及び/又はフェノール樹脂を使用するのが好ましい。   Moreover, it is preferable to use an epoxy resin and / or a phenol resin as the thermosetting resin.

更に、前記接着シートとしては、架橋剤が添加されているものを使用するのが好ましい。   Furthermore, as the adhesive sheet, it is preferable to use a sheet to which a crosslinking agent is added.

また、前記の課題を解決する為に、本発明に係る接着シートは、前記半導体装置の製造方法に於いて使用されるものであることを特徴とする。   In order to solve the above problems, the adhesive sheet according to the present invention is used in the method for manufacturing a semiconductor device.

また、前記の課題を解決する為に、本発明に係る半導体装置は、前記半導体装置の製造方法により得られたものであることを特徴とする。   In order to solve the above problems, a semiconductor device according to the present invention is obtained by the method for manufacturing a semiconductor device.

本発明は、前記に説明した手段により、以下に述べるような効果を奏する。
即ち、従来の製造方法の様に、半導体素子と被着体との貼り合わせ当初から接着シートを固着させると、半導体素子と被着体との間に空隙が生じた場合には、これを塞ぐことが困難になる。該空隙は、半導体素子の薄型化に伴い、凹状または凸状に反った状態になることに起因して生じるものである。よって本発明に於いては、半導体素子と被着体との貼り合わせは、接着シートを完全固着させずに仮固着の状態に留めておく。そして、半導体素子の封止工程に於いて固着させる。この封止工程に於いては、例えば150℃〜200℃の範囲内で樹脂封止が行われると、接着シートの流動性が除々に低くなり固着の状態に向かう。その過程で封止樹脂から接着シートに加わる圧力が、半導体素子の反りを低減し空隙を塞ぐ力として作用する。この結果、半導体素子が隙間無く被着体に接着固定して、高信頼性の半導体装置を製造することが可能となる。
The present invention has the following effects by the means described above.
That is, when the adhesive sheet is fixed from the beginning of the bonding of the semiconductor element and the adherend as in the conventional manufacturing method, if a gap is generated between the semiconductor element and the adherend, this is blocked. It becomes difficult. The void is generated due to the concave or convex warpage as the semiconductor element becomes thinner. Therefore, in the present invention, the bonding of the semiconductor element and the adherend is kept in a temporarily fixed state without completely fixing the adhesive sheet. And it fixes in the sealing process of a semiconductor element. In this sealing step, when resin sealing is performed within a range of 150 ° C. to 200 ° C., for example, the fluidity of the adhesive sheet is gradually lowered and the state of fixation is reached. In this process, pressure applied from the sealing resin to the adhesive sheet acts as a force for reducing the warp of the semiconductor element and closing the gap. As a result, the semiconductor element can be bonded and fixed to the adherend without a gap, and a highly reliable semiconductor device can be manufactured.

かかる効果は、前記半導体素子の上に1又は2以上の半導体素子を、前記接着シートを介して積層する場合や、必要に応じて、前記半導体素子と半導体素子との間に前記接着シートを介してスペーサを積層する場合にも同様に奏する。また、前記の製造工程の簡略化は、複数の半導体素子等の3次元実装に於いて、製造効率の一層の向上を図ることができる。   Such an effect is obtained by laminating one or more semiconductor elements on the semiconductor element via the adhesive sheet or, if necessary, via the adhesive sheet between the semiconductor element and the semiconductor element. The same applies to the case where the spacers are stacked. The simplification of the manufacturing process can further improve the manufacturing efficiency in the three-dimensional mounting of a plurality of semiconductor elements.

(実施の形態1)
本発明の実施の形態について、図を参照しながら以下に説明する。但し、説明に不要な部分は省略し、また説明を容易にする為に拡大または縮小等して図示した部分がある。
(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. However, parts that are not necessary for the description are omitted, and some parts are illustrated by being enlarged or reduced for easy explanation.

本発明の実施の形態について、図1を参照しながら説明する。図1は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。但し、説明に不要な部分は省略し、また、説明を容易にする為に拡大又は縮小等して図示した部分がある。以上のことは、以下の図面に対しても同様である。   An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a process diagram for explaining a method of manufacturing a semiconductor device according to the present embodiment. However, parts that are not necessary for the description are omitted, and there are parts that are illustrated in an enlarged or reduced manner for ease of explanation. The same applies to the following drawings.

本実施の形態に係る半導体装置の製造方法は、半導体素子13を基板又はリードフレーム(被着体、以下単に基板等と称する)11上に接着シート12で仮固着する仮固着工程と、半導体素子13にワイヤーボンディングをするワイヤーボンディング工程と、半導体素子13を封止樹脂15で封止する封止工程とを含む。   The semiconductor device manufacturing method according to the present embodiment includes a temporary fixing step of temporarily fixing a semiconductor element 13 on a substrate or a lead frame (adhered body, hereinafter simply referred to as a substrate) 11 with an adhesive sheet 12, and a semiconductor element. 13 includes a wire bonding step of wire bonding to 13 and a sealing step of sealing the semiconductor element 13 with the sealing resin 15.

前記仮固着工程は、図1(a)に示すように、半導体素子13を、接着シート12を介して基板等11に仮固着する工程である。半導体素子13を基板等11上に仮固着する方法としては、例えば基板等11上に接着シート12を積層した後、接着シート12上に、ワイヤーボンド面が上側となる様にして半導体素子13を順次積層して仮固着する方法が挙げられる。また、予め接着シート12が仮固着された半導体素子13を基板等11に仮固着して積層してもよい。   The temporary fixing step is a step of temporarily fixing the semiconductor element 13 to the substrate 11 or the like 11 via the adhesive sheet 12 as shown in FIG. As a method of temporarily fixing the semiconductor element 13 on the substrate 11 or the like, for example, after laminating the adhesive sheet 12 on the substrate 11 or the like, the semiconductor element 13 is placed on the adhesive sheet 12 so that the wire bond surface is on the upper side. A method of sequentially laminating and temporarily fixing is mentioned. Further, the semiconductor element 13 to which the adhesive sheet 12 is temporarily fixed in advance may be temporarily fixed to the substrate 11 and laminated.

尚、本発明に於いて、半導体素子13の厚さは特に限定されない。通常、その厚さは200μm以下であるが、本発明に於いては例えば厚さが100μm以下、更には厚さが25から50μmの半導体素子にも対応可能である。薄型化した半導体素子13を基板等11に仮固着すると、半導体素子13が凹状または凸状に反った状態になることがある。その結果、基板等11との間に隙間が生じ、高信頼性の半導体装置が得られないという不具合が生じる。しかし、本発明に於いては、後述の封止工程を行うことにより半導体素子13を基板等11に固着すると共に、当該隙間を塞ぐことが可能となる。その詳細については後述する。   In the present invention, the thickness of the semiconductor element 13 is not particularly limited. Usually, the thickness is 200 μm or less. However, in the present invention, for example, it is possible to cope with a semiconductor element having a thickness of 100 μm or less, and further a thickness of 25 to 50 μm. If the thinned semiconductor element 13 is temporarily fixed to the substrate 11 or the like, the semiconductor element 13 may be warped in a concave or convex shape. As a result, a gap is formed between the substrate 11 and the like, and a problem that a highly reliable semiconductor device cannot be obtained occurs. However, in the present invention, it is possible to fix the semiconductor element 13 to the substrate 11 and the like and to close the gap by performing a sealing process described later. Details thereof will be described later.

前記基板としては、従来公知のものを使用することができる。また、前記リードフレームとしては、Cuリードフレーム、42Alloyリードフレーム等の金属リードフレームやガラスエポキシ、BT(ビスマレイミド−トリアジン)、ポリイミド等からなる有機基板を使用することができる。しかし、本発明はこれに限定されるものではなく、半導体素子をマウントし、半導体素子と電気的に接続して使用可能な回路基板も含まれる。   A conventionally well-known thing can be used as said board | substrate. As the lead frame, a metal lead frame such as a Cu lead frame or a 42 Alloy lead frame, or an organic substrate made of glass epoxy, BT (bismaleimide-triazine), polyimide, or the like can be used. However, the present invention is not limited to this, and includes a circuit board that can be used by mounting a semiconductor element and electrically connecting the semiconductor element.

前記接着シート12としては、175℃に於ける損失弾性率が2000Pa以上のものを使用し、より好ましくは2000〜1×10Paの範囲内のものを使用する。損失弾性率とは粘弾性体に加えられたエネルギーの内で、いったん貯蔵された後、熱として失われるエネルギーの尺度であり、熱として失われたエネルギーを弾性率に換算して表したものである。エネルギー損失は摩擦エネルギーの形で失われ、摩擦が大きければエネルギー損失が大きくなる。損失弾性率は、動的粘度に角周波数を乗じて得られる。一般に樹脂組成物に熱を加えると、損失弾性率はその硬化反応とともに上昇するが、ある程度硬化が進み固体に近づくと、樹脂組成物の粘性成分が減少する結果、動的粘度が減少しはじめる。故に、損失弾性率が減少するということは、ある程度硬化反応が進行し、固体になりつつある状態のことを意味する。本発明に於いて、接着シート12の175℃に於ける損失弾性率は2000Pa以上であるので、後述の封止工程の際には流動性が低くなり固着の状態近づく。その際、樹脂封止に於いて加わる圧力は、一定程度の剛性を有するに至った接着シートを介して空隙を埋める圧力となる。この結果、半導体素子13と基板等11との間に存在する空隙を低減し、高信頼性の半導体装置を製造することが可能となる。また、半導体素子の一層の薄型化にも対応することができる。 The adhesive sheet 12 has a loss elastic modulus at 175 ° C. of 2000 Pa or more, more preferably 2000-1 × 10 6 Pa. Loss elastic modulus is a measure of the energy lost as heat after being stored once in the energy applied to the viscoelastic body, and is expressed by converting the energy lost as heat into elastic modulus. is there. Energy loss is lost in the form of friction energy, and the greater the friction, the greater the energy loss. The loss modulus is obtained by multiplying the dynamic viscosity by the angular frequency. In general, when heat is applied to a resin composition, the loss elastic modulus increases with the curing reaction, but when the curing proceeds to some extent and approaches a solid, the viscosity component of the resin composition decreases, and the dynamic viscosity begins to decrease. Therefore, the decrease in the loss elastic modulus means that the curing reaction has progressed to some extent and is becoming solid. In the present invention, since the loss elastic modulus at 175 ° C. of the adhesive sheet 12 is 2000 Pa or more, the fluidity is lowered during the sealing process described later and approaches the fixed state. At that time, the pressure applied in the resin sealing is a pressure for filling the gap through the adhesive sheet having a certain degree of rigidity. As a result, a gap existing between the semiconductor element 13 and the substrate 11 can be reduced, and a highly reliable semiconductor device can be manufactured. In addition, the semiconductor device can be made thinner.

また接着シート12としては、仮固着時の剪断接着力が基板等11に対して0.2MPa以上であることが好ましく、0.2〜10MPaであることがより好ましい。接着シート12の剪断接着力を0.2MPa以上とすると、加熱工程を経ることなくワイヤーボンディング工程を行っても、当該工程に於ける超音波振動や加熱により、接着シート12と半導体素子13又は基板等11との接着面でのずり変形の発生を抑制できる。即ち、ワイヤーボンディングの際の超音波振動により半導体素子13が動くのを抑制し、これによりワイヤーボンディングの成功率が低下するのを防止する。尚、接着シート12については、後段に於いて更に詳述する。   Moreover, as the adhesive sheet 12, it is preferable that the shear adhesive force at the time of temporary adhering is 0.2 MPa or more with respect to the substrate 11 or the like, and more preferably 0.2 to 10 MPa. When the shearing adhesive force of the adhesive sheet 12 is 0.2 MPa or more, even if the wire bonding process is performed without passing through the heating process, the adhesive sheet 12 and the semiconductor element 13 or the substrate are caused by ultrasonic vibration or heating in the process. It is possible to suppress the occurrence of shear deformation on the adhesive surface with E11 or the like. In other words, the movement of the semiconductor element 13 due to ultrasonic vibration during wire bonding is suppressed, thereby preventing the success rate of wire bonding from being lowered. The adhesive sheet 12 will be described in detail later.

前記ワイヤーボンディング工程は、基板等11の端子部(インナーリード)の先端と半導体素子13上の電極パッド(図示しない)とをボンディングワイヤー16で電気的に接続する工程である(図1(b)参照)。前記ボンディングワイヤー16としては、例えば金線、アルミニウム線又は銅線等が用いられる。ワイヤーボンディングを行う際の温度は、80〜250℃、好ましくは80〜220℃の範囲内で行われる。また、その加熱時間は数秒〜数分間行われる。結線は、前記温度範囲内となる様に加熱された状態で、超音波による振動エネルギーと印加加圧による圧着工ネルギーの併用により行われる。   The wire bonding step is a step of electrically connecting a tip of a terminal portion (inner lead) of the substrate 11 or the like and an electrode pad (not shown) on the semiconductor element 13 with a bonding wire 16 (FIG. 1B). reference). As the bonding wire 16, for example, a gold wire, an aluminum wire, a copper wire or the like is used. The temperature at the time of wire bonding is 80 to 250 ° C, preferably 80 to 220 ° C. The heating time is several seconds to several minutes. The connection is performed by a combination of vibration energy by ultrasonic waves and crimping energy by applying pressure while being heated so as to be within the temperature range.

本工程は、接着シート12による固着を行うことなく実行される。また、本工程の過程で接着シート12により半導体素子13と基板等11とが固着することはない。ここで、接着シート12の剪断接着力は、80〜250℃の温度範囲内であっても、0.2MPa以上であることが好ましい。当該温度範囲内で剪断接着力が0.2MPa未満であると、ワイヤーボンディングの際の超音波振動により半導体素子が動き、ワイヤーボンディングを行うことができず、歩留まりが低下する場合があるからである。   This step is performed without fixing with the adhesive sheet 12. Further, the semiconductor element 13 and the substrate 11 are not fixed by the adhesive sheet 12 in the process of this step. Here, even if it is in the temperature range of 80-250 degreeC, the shearing adhesive force of the adhesive sheet 12 is preferably 0.2 MPa or more. This is because if the shear adhesive force is less than 0.2 MPa within the temperature range, the semiconductor element moves due to ultrasonic vibration during wire bonding, wire bonding cannot be performed, and the yield may decrease. .

前記封止工程は、封止樹脂15により半導体素子13を封止する工程である(図1(c)参照)。本工程は、基板等11に搭載された半導体素子13やボンディングワイヤー16を保護する為に行われる。本工程は、例えば封止用の樹脂を金型で成型することにより行う。封止樹脂15としては、例えばエポキシ系の樹脂を使用する。樹脂封止の際の加熱温度は、通常175℃で60〜90秒間行われるが、本発明はこれに限定されず、例えば150〜200℃で数分間キュアすることができる。また本工程に於いては、樹脂封止の際に加圧してもよい。この場合、加圧する圧力は1〜15MPaであることが好ましく、3〜10MPaであることがより好ましい。当該範囲内で圧力を加えると、半導体素子13と基板等11との間に存在する空隙を確実に塞ぐことができる(他にも効果があれば追記をお願いいたします)。これにより、接着シート12を介して半導体素子13と基板等11とを固着すると共に、両者の間に存在する空隙を塞ぐことができる。即ち、本発明に於いては、後述する後硬化工程が行われない場合に於いても、本工程に於いて接着シート12による固着が可能であり、製造工程数の減少及び半導体装置の製造期間の短縮に寄与することができる。ここで、基板等11と半導体素子13との接着面積は90%以上であることが好ましく、95%以上であることがより好ましい。接着面積が90%未満であると、耐湿信頼性に於いて不具合が生じる場合があるからである。尚、接着面積とは、半導体素子13と基板等11とが接着シート12を介して接している領域を言い、接着シート12が何れか一方にのみ接着している領域は含まない。   The sealing step is a step of sealing the semiconductor element 13 with the sealing resin 15 (see FIG. 1C). This step is performed to protect the semiconductor element 13 and the bonding wire 16 mounted on the substrate 11 or the like. This step is performed, for example, by molding a sealing resin with a mold. For example, an epoxy resin is used as the sealing resin 15. Although the heating temperature at the time of resin sealing is normally performed at 175 degreeC for 60 to 90 second, this invention is not limited to this, For example, it can cure at 150 to 200 degreeC for several minutes. In this step, pressure may be applied during resin sealing. In this case, the pressure to pressurize is preferably 1 to 15 MPa, and more preferably 3 to 10 MPa. If pressure is applied within this range, the gap between the semiconductor element 13 and the substrate 11 can be reliably closed (please add if there are other effects). Thereby, while adhering the semiconductor element 13 and the board | substrate 11 etc. via the adhesive sheet 12, the space | gap which exists between both can be block | closed. That is, in the present invention, even when the post-curing process described later is not performed, the adhesive sheet 12 can be fixed in this process, and the number of manufacturing processes can be reduced and the semiconductor device manufacturing period can be reduced. It can contribute to shortening. Here, the adhesion area between the substrate 11 and the semiconductor element 13 is preferably 90% or more, and more preferably 95% or more. This is because if the adhesion area is less than 90%, a defect may occur in moisture resistance reliability. The bonded area refers to a region where the semiconductor element 13 and the substrate 11 are in contact with each other via the adhesive sheet 12, and does not include a region where the adhesive sheet 12 is bonded to only one of them.

本発明に於いては、封止工程の後に、封止樹脂15をアフターキュアする後硬化工程を行っても良い。本工程に於いては、前記封止工程で硬化不足の封止樹脂15を完全に硬化させる。本工程に於ける加熱温度は、封止樹脂の種類により異なるが、例えば150〜200℃の範囲内であり、加熱時間は0.5〜8時間程度である。   In the present invention, a post-curing step of after-curing the sealing resin 15 may be performed after the sealing step. In this step, the sealing resin 15 that is insufficiently cured in the sealing step is completely cured. Although the heating temperature in this process changes with kinds of sealing resin, it exists in the range of 150-200 degreeC, for example, and heating time is about 0.5 to 8 hours.

次に、接着シート12について詳述する。接着シート12は、175℃での損失弾性率が2000Pa以上であれば、その構成は特に限定されない。具体的には、例えば接着剤層の単層のみからなる接着シートや、コア材料の片面又は両面に接着剤層を形成した多層構造の接着シート等が挙げられる。ここで、前記コア材料としては、フィルム(例えばポリイミドフイルム、ポリエステルフィルム、ポリエチレンテレフタレートフィルム、ポリエチレンナフタレートフィルム、ポリカーボネートフィルム等)、ガラス繊維やプラスチック製不織繊維で強化された樹脂基板、シリコン基板又はガラス基板等が挙げられる。これらのコア材料のうち、175℃での損失弾性率が2000Pa以上とする為には、接着剤層の構成材料との組み合わせにもよるが、例えば架橋された熱可塑性樹脂等を用いるのが好ましい。架橋することにより流動性が低下するからである。また、接着シートとダイシングシートとの一体型のものも使用することができる。   Next, the adhesive sheet 12 will be described in detail. The configuration of the adhesive sheet 12 is not particularly limited as long as the loss elastic modulus at 175 ° C. is 2000 Pa or more. Specifically, for example, an adhesive sheet composed only of a single layer of an adhesive layer, an adhesive sheet having a multilayer structure in which an adhesive layer is formed on one or both sides of a core material, and the like can be given. Here, examples of the core material include a film (for example, a polyimide film, a polyester film, a polyethylene terephthalate film, a polyethylene naphthalate film, a polycarbonate film), a resin substrate reinforced with glass fiber or plastic non-woven fiber, a silicon substrate, A glass substrate etc. are mentioned. Among these core materials, in order to make the loss elastic modulus at 175 ° C. 2000 Pa or more, for example, it is preferable to use a crosslinked thermoplastic resin or the like, although it depends on the combination with the constituent material of the adhesive layer. . It is because fluidity | liquidity falls by bridge | crosslinking. Also, an integrated type of an adhesive sheet and a dicing sheet can be used.

前記接着剤層は接着機能を有する層であり、その構成材料としては、熱可塑性樹脂と熱硬化性樹脂とを併用したものが挙げられる。又、熱可塑性樹脂単独でも使用可能である。   The adhesive layer is a layer having an adhesive function, and examples of the constituent material thereof include a combination of a thermoplastic resin and a thermosetting resin. A thermoplastic resin alone can also be used.

前記熱可塑性樹脂としては、天然ゴム、ブチルゴム、イソプレンゴム、クロロプレンゴム、エチレン−酢酸ビニル共重合体、エチレン−アクリル酸共重合体、エチレン−アクリル酸エステル共重合体、ポリプタジエン樹脂、ポリカーボネート樹脂、熱可塑性ボリイミド樹脂、6−ナイロンや6,6ナイロン等のポリアミド樹脂、フェノキシ樹脂、アクリル樹脂、PETやPBT等の飽和ポリエステル樹脂、ポリアミドイミド樹脂またはフッ素樹脂等が挙げられる。これらの熱可塑性樹脂は単独で、又は2種以上を併用して用いることができる。これらの熱可塑性樹脂のうち、イオン性不純物が少なく耐熱性が高く、半導体素子の信頼性を確保できるアクリル樹脂が特に好ましい。ここで、175℃に於ける損失弾性率を2000Pa以上とする為には、前記材料のうち架橋性官能基を有しているアクリル樹脂等を採用するのが好ましい。   Examples of the thermoplastic resin include natural rubber, butyl rubber, isoprene rubber, chloroprene rubber, ethylene-vinyl acetate copolymer, ethylene-acrylic acid copolymer, ethylene-acrylic acid ester copolymer, polyptadiene resin, polycarbonate resin, heat Examples thereof include plastic polyimide resins, polyamide resins such as 6-nylon and 6,6 nylon, phenoxy resins, acrylic resins, saturated polyester resins such as PET and PBT, polyamideimide resins, and fluorine resins. These thermoplastic resins can be used alone or in combination of two or more. Of these thermoplastic resins, an acrylic resin that has few ionic impurities and high heat resistance and can ensure the reliability of the semiconductor element is particularly preferable. Here, in order to set the loss elastic modulus at 175 ° C. to 2000 Pa or more, it is preferable to employ an acrylic resin having a crosslinkable functional group among the materials.

前記アクリル樹脂としては、特に限定されるものではなく、炭素数30以下、特に炭素数4〜18の直鎖若しくは分岐のアルキル基を有するアクリル酸又はメタクリル酸のエステルの1種又は2種以上を成分とする重合体等が挙げられる。前記アルキル基としては、例えばメチル基、エチル基、プロピル基、イソプロピル基、n−ブチル基、t−ブチル基、イソブチル基、アミル基、イソアミル基、ヘキシル基、ヘプチル基、シクロヘキシル基、2−エチルヘキシル基、オクチル基、イソオクチル基、ノニル基、イソノニル基、デシル基、イソデシル基、ウンデシル基、ラウリル基、トリデシル基、テトラデシル基、ステアリル基、オクタデシル基、又はドデシル基等が挙げられる。   The acrylic resin is not particularly limited, and includes one or more esters of acrylic acid or methacrylic acid having a linear or branched alkyl group having 30 or less carbon atoms, particularly 4 to 18 carbon atoms. Examples thereof include polymers as components. Examples of the alkyl group include a methyl group, an ethyl group, a propyl group, an isopropyl group, an n-butyl group, a t-butyl group, an isobutyl group, an amyl group, an isoamyl group, a hexyl group, a heptyl group, a cyclohexyl group, and 2-ethylhexyl. Group, octyl group, isooctyl group, nonyl group, isononyl group, decyl group, isodecyl group, undecyl group, lauryl group, tridecyl group, tetradecyl group, stearyl group, octadecyl group, or dodecyl group.

また、前記重合体を形成する他のモノマーとしては、特に限定されるものではなく、例えばアクリル酸、メタクリル酸、カルボキシエチルアクリレート、カルボキシペンチルアクリレート、イタコン酸、マレイン酸、フマール酸若しくはクロトン酸等の様なカルボキシル基含有モノマー、無水マレイン酸若しくは無水イタコン酸等の様な酸無水物モノマー、(メタ)アクリル酸2−ヒドロキシエチル、(メタ)アクリル酸2−ヒドロキシプロピル、(メタ)アクリル酸4−ヒドロキシブチル、(メタ)アクリル酸6−ヒドロキシヘキシル、(メタ)アクリル酸8−ヒドロキシオクチル、(メタ)アクリル酸10−ヒドロキシデシル、(メタ)アクリル酸12−ヒドロキシラウリル若しくは(4−ヒドロキシメチルシクロヘキシル)−メチルアクリレート等の様なヒドロキシル基含有モノマー、スチレンスルホン酸、アリルスルホン酸、2−(メタ)アクリルアミド−2−メチルプロパンスルホン酸、(メタ)アクリルアミドプロパンスルホン酸、スルホプロピル(メタ)アクリレート若しくは(メタ)アクリロイルオキシナフタレンスルホン酸等の様なスルホン酸基含有モノマー、又は2−ヒドロキシエチルアクリロイルホスフェート等の様な燐酸基含有モノマーが挙げられる。   In addition, the other monomer forming the polymer is not particularly limited, and examples thereof include acrylic acid, methacrylic acid, carboxyethyl acrylate, carboxypentyl acrylate, itaconic acid, maleic acid, fumaric acid, and crotonic acid. Carboxyl group-containing monomers such as acid anhydride monomers such as maleic anhydride or itaconic anhydride, 2-hydroxyethyl (meth) acrylate, 2-hydroxypropyl (meth) acrylate, 4- (meth) acrylic acid 4- Hydroxybutyl, 6-hydroxyhexyl (meth) acrylate, 8-hydroxyoctyl (meth) acrylate, 10-hydroxydecyl (meth) acrylate, 12-hydroxylauryl (meth) acrylate or (4-hydroxymethylcyclohexyl) -Methyla Hydroxyl group-containing monomers such as relate, styrene sulfonic acid, allyl sulfonic acid, 2- (meth) acrylamide-2-methylpropane sulfonic acid, (meth) acrylamide propane sulfonic acid, sulfopropyl (meth) acrylate or (meth) Examples thereof include sulfonic acid group-containing monomers such as acryloyloxynaphthalene sulfonic acid, and phosphoric acid group-containing monomers such as 2-hydroxyethylacryloyl phosphate.

前記熱硬化性樹脂としては、フェノール樹脂.アミノ樹脂、不飽和ポリエステル樹脂、エポキシ樹脂、ポリウレタン樹脂、シリコーン樹脂、又は熱硬化性ポリイミド樹脂等が挙げられる。これらの樹脂は、単独で又は2種以上併用して用いることができる。特に、半導体素子を腐食させるイオン性不純物等含有が少ないエポキシ樹脂が好ましい。また、エポキシ樹脂の硬化剤としてはフェノール樹脂が好ましい。   Examples of the thermosetting resin include phenol resin. An amino resin, an unsaturated polyester resin, an epoxy resin, a polyurethane resin, a silicone resin, a thermosetting polyimide resin, or the like can be given. These resins can be used alone or in combination of two or more. In particular, an epoxy resin containing a small amount of ionic impurities that corrode semiconductor elements is preferable. Moreover, as a hardening | curing agent of an epoxy resin, a phenol resin is preferable.

前記エポキシ樹脂は、接着剤組成物として一般に用いられるものであれば特に限定は無く、例えばビスフェノールA型、ビスフェノールF型、ビスフェノールS型、臭素化ビスフェノールA型、水添ビスフェノールA型、ビスフェノールAF型,ビフェニル型、ナフタレン型、フルオンレン型、フェノールノボラック型、オルソクレゾールノボラック型、トリスヒドロキシフェニルメタン型、テトラフェニロールエタン型等の二官能エポキシ樹脂や多官能エポキシ樹脂、又はヒダントイン型、トリスグリシジルイソシアヌレート型若しくはグリシジルアミン型等のエポキシ樹脂が用いられる。これらは単独で、又は2種以上を併用して用いることができる。これらのエポキシ樹脂のうちノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、トリスヒドロキシフェニルメタン型樹脂又はテトラフェニロールエタン型エポキシ樹脂が特に好ましい。これらのエポキシ樹脂は、硬化剤としてのフェノール樹脂との反応性に富み、耐熱性等に優れるからである。   The epoxy resin is not particularly limited as long as it is generally used as an adhesive composition, for example, bisphenol A type, bisphenol F type, bisphenol S type, brominated bisphenol A type, hydrogenated bisphenol A type, bisphenol AF type. , Biphenyl type, naphthalene type, fluorene type, phenol novolak type, orthocresol novolak type, trishydroxyphenylmethane type, tetraphenylolethane type, etc. Type or glycidylamine type epoxy resin is used. These can be used alone or in combination of two or more. Of these epoxy resins, novolac type epoxy resins, biphenyl type epoxy resins, trishydroxyphenylmethane type resins or tetraphenylolethane type epoxy resins are particularly preferred. This is because these epoxy resins are rich in reactivity with a phenol resin as a curing agent and are excellent in heat resistance and the like.

さらに前記フェノール樹脂は、前記エポキシ樹脂の硬化剤として作用するものであり、例えば、フェノールノボラック樹脂、フェノールアラルキル樹脂、クレゾールノボラック樹脂、tert−ブチルフェノールノボラック樹脂、ノニルフェノールノボラック樹脂等のノボラック型フェノール樹脂、レゾール型フェノール樹脂、ポリパラオキシスチレン等のポリオキシスチレン等が挙げられる。これらは単独で、又は2種以上を併用して用いることができる。これらのフェノール樹脂のうちフェノールノボラック樹脂、フェノールアラルキル樹脂が特に好ましい。半導体装置の接続信頼性を向上させることができるからである。   Further, the phenol resin acts as a curing agent for the epoxy resin. Examples thereof include polyphenol styrene such as type phenol resin and polyparaoxy styrene. These can be used alone or in combination of two or more. Of these phenol resins, phenol novolac resins and phenol aralkyl resins are particularly preferred. This is because the connection reliability of the semiconductor device can be improved.

前記エポキシ樹脂とフェノール樹脂の配合割合は、例えば、前記エポキシ樹脂成分中のエポキシ基1当量当たりフェノール樹脂中の水酸基が0.5〜2.0当量になるように配合することが好適である。より好適なのは0.8〜1.2当量である。即ち、両者の配合割合が前記範囲を外れると、十分な硬化反応が進まず、エポキシ樹脂硬化物の特性が劣化し易くなるからである。   The mixing ratio of the epoxy resin and the phenol resin is preferably such that, for example, the hydroxyl group in the phenol resin is 0.5 to 2.0 equivalents per equivalent of epoxy group in the epoxy resin component. More preferred is 0.8 to 1.2 equivalents. That is, if the blending ratio of both is out of the above range, sufficient curing reaction does not proceed and the properties of the cured epoxy resin are likely to deteriorate.

なお、本発明に於いては、エポキシ樹脂、フェノール樹脂及びアクリル樹脂を含む接着シートが特に好ましい。これらの樹脂は、イオン性不純物が少なく耐熱性が高いので、半導体素子の信頼性を確保できる。この場合の配合比は、アクリル樹脂成分100重量部に対して、エポキシ樹脂とフェノール樹脂の混合量が10〜200重量部である。   In the present invention, an adhesive sheet containing an epoxy resin, a phenol resin and an acrylic resin is particularly preferable. Since these resins have few ionic impurities and high heat resistance, the reliability of the semiconductor element can be ensured. In this case, the mixing ratio of the epoxy resin and the phenol resin is 10 to 200 parts by weight with respect to 100 parts by weight of the acrylic resin component.

本発明の接着シート12は、予めある程度架橋をさせておく為、作製に際し、重合体の分子鎖末端の官能基等と反応する多官能性化合物を架橋剤として添加させておくのがよい。これにより、高温下での接着特性を向上させ、耐熱性の改善を図る。   Since the adhesive sheet 12 of the present invention is previously crosslinked to some extent, a polyfunctional compound that reacts with a functional group at the molecular chain end of the polymer or the like is preferably added as a crosslinking agent. Thereby, the adhesive property under high temperature is improved and heat resistance is improved.

前記架橋剤としては、従来公知のものを採用することができる。特に、トリレンジイソシアネート、ジフェニルメタンジイソシアネート、p−フェニレンジイソシアネート、1,5−ナフタレンジイソシアネート、多価アルコールとジイソシアネートの付加物等のポリイソシアネート化合物がより好ましい。架橋剤の添加量としては、前記の重合体100重量部に対し、通常0.05〜7重量部とするのが好ましい。架橋剤の量が7重量部より多いと、接着力が低下するので好ましくない。その一方、0.05重量部より少ないと、凝集力が不足するので好ましくない。また、このようなポリイソシアネート化合物と共に、必要に応じて、エポキシ樹脂等の他の多官能性化合物を一緒に含ませるようにしてもよい。   A conventionally well-known thing can be employ | adopted as said crosslinking agent. Particularly preferred are polyisocyanate compounds such as tolylene diisocyanate, diphenylmethane diisocyanate, p-phenylene diisocyanate, 1,5-naphthalene diisocyanate, adducts of polyhydric alcohol and diisocyanate. The addition amount of the crosslinking agent is usually preferably 0.05 to 7 parts by weight with respect to 100 parts by weight of the polymer. When the amount of the cross-linking agent is more than 7 parts by weight, the adhesive force is lowered, which is not preferable. On the other hand, if it is less than 0.05 parts by weight, the cohesive force is insufficient, which is not preferable. Moreover, you may make it contain other polyfunctional compounds, such as an epoxy resin, together with such a polyisocyanate compound as needed.

また、本発明の接着シート12には、その用途に応じて無機充填剤を適宜配合することができる。無機充填剤の配合は、導電性の付与や熱伝導性の向上、弾性率の調節等を可能とする。前記無機重点材としては、例えば、シリカ、クレー、石膏、炭酸カルシウム、硫酸バリウム、酸化アルミナ、酸化ベリリウム、炭化珪素、窒化珪素等のセラミック類、アルミニウム、銅、銀、金、ニッケル、クロム、鈴、錫、亜鉛、パラジウム、半田などの金属、又は合金類、その他カーボンなどからなる種々の無機粉末が挙げられる。これらは単独で又は2種以上を併用して用いることができる。なかでも、シリカ、特に溶融シリ力が好適に用いられる。また、無機充填剤の平均粒径は0.1〜80μmの範囲内であることが好ましい。   In addition, an inorganic filler can be appropriately blended in the adhesive sheet 12 of the present invention according to its use. The blending of the inorganic filler makes it possible to impart conductivity, improve thermal conductivity, adjust the elastic modulus, and the like. Examples of the inorganic material include silica, clay, gypsum, calcium carbonate, barium sulfate, alumina oxide, beryllium oxide, silicon carbide, silicon nitride and other ceramics, aluminum, copper, silver, gold, nickel, chromium, bell And various inorganic powders made of metals such as tin, zinc, palladium, solder, or alloys, and other carbon. These can be used alone or in combination of two or more. Among these, silica, particularly a melting strength is preferably used. Moreover, it is preferable that the average particle diameter of an inorganic filler exists in the range of 0.1-80 micrometers.

前記無機充填剤の配合量は、有機樹脂成分100重量部に対し0〜80重量%に設定することが好ましい。特に好ましくは0〜70重量%である。   The blending amount of the inorganic filler is preferably set to 0 to 80% by weight with respect to 100 parts by weight of the organic resin component. Particularly preferably, it is 0 to 70% by weight.

なお、本発明の接着シート12には、前記無機充填剤以外に、必要に応じて他の添加剤を適宜に配合することができる。他の添加剤としては、例えば灘燃剤、シランカップリング剤又はイオントラップ剤等が挙げられる。   In addition to the said inorganic filler, another additive can be suitably mix | blended with the adhesive sheet 12 of this invention as needed. Examples of other additives include a flame retardant, a silane coupling agent, and an ion trap agent.

前記難燃剤としては、例えば、三酸化アンチモン、五酸化アンチモン、臭素化エポキシ樹脂等が挙げられる。これらは、単独で、又は2種以上を併用して用いることができる。   Examples of the flame retardant include antimony trioxide, antimony pentoxide, brominated epoxy resin, and the like. These can be used alone or in combination of two or more.

前記シランカップリング剤としては、例えば、6‐(3,4‐エポキシシクロヘキシル)エチルトリメトキシシラン、γ‐グリシドキシプロピルトリメトキシシラン、γ‐グリシドキシプロピルメチルジエトキシシラン等が挙げられる。これらの化合物は、単独で、又は2種以上を併用して用いることができる。   Examples of the silane coupling agent include 6- (3,4-epoxycyclohexyl) ethyltrimethoxysilane, γ-glycidoxypropyltrimethoxysilane, γ-glycidoxypropylmethyldiethoxysilane, and the like. These compounds can be used alone or in combination of two or more.

前記イオントラップ剤としては、例えばハイドロタルサイト類、水酸化ビスマス等が挙げられる。これらは、単独で、又は2種以上を併用して用いることができる。   Examples of the ion trapping agent include hydrotalcites and bismuth hydroxide. These can be used alone or in combination of two or more.

(実施の形態2)
本発明に形態2に係る半導体装置の製造方法について、図2を参照しながら説明する。図2は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。
(Embodiment 2)
A method for manufacturing a semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 2 is a process diagram for explaining the semiconductor device manufacturing method according to the present embodiment.

本実施の形態に係る半導体装置は、前記実施の形態1に係る半導体装置と比較して、複数の半導体素子を積層して3次元実装とした点が異なる。より詳細には、半導体素子の上に他の半導体素子を、前記接着シートを介して積層する工程を含む点が異なる。   The semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that a plurality of semiconductor elements are stacked to achieve three-dimensional mounting. More specifically, it differs in that it includes a step of laminating another semiconductor element on the semiconductor element via the adhesive sheet.

先ず、図2(a)に示すように、所定のサイズに切り出した少なくとも1つ以上の接着シート12を被着体である基板等11に貼り付ける。次に、接着シート12上に半導体素子13を、ワイヤーボンド面が上側となる様にして仮固着する。(図2(b)参照)。さらに、半導体素子13上に、その電極パッド部分を避けて接着シート14を貼り付ける(図2(c)参照)。さらに、接着シート14上に、ワイヤーボンド面が上側となる様にして半導体素子13を仮固着する(図2(d)参照)。   First, as shown in FIG. 2A, at least one adhesive sheet 12 cut out to a predetermined size is attached to a substrate 11 or the like as an adherend. Next, the semiconductor element 13 is temporarily fixed on the adhesive sheet 12 so that the wire bond surface is on the upper side. (See FIG. 2 (b)). Further, an adhesive sheet 14 is stuck on the semiconductor element 13 while avoiding the electrode pad portion (see FIG. 2C). Further, the semiconductor element 13 is temporarily fixed on the adhesive sheet 14 so that the wire bond surface is on the upper side (see FIG. 2D).

次に、図2(e)に示すように、ワイヤーボンディング工程を行う。これにより、半導体素子13に於ける電極パッドと基板等11とをボンディングワイヤー16で電気的に接続する。   Next, as shown in FIG. 2E, a wire bonding step is performed. Thereby, the electrode pad in the semiconductor element 13 and the substrate 11 are electrically connected by the bonding wire 16.

続いて、封止樹脂により半導体素子13を封止する封止工程を行い、封止樹脂を硬化させると共に、接着シート12・14により基板等11と半導体素子13との間、及び半導体素子13同士の間に生じている隙間を塞ぐ。当該封止工程の後には、後硬化工程を行ってもよい。   Subsequently, a sealing step of sealing the semiconductor element 13 with the sealing resin is performed to cure the sealing resin, and between the substrate 11 and the semiconductor element 13 and between the semiconductor elements 13 by the adhesive sheets 12 and 14. Close the gap that is created between the two. A post-curing step may be performed after the sealing step.

本実施の形態によれば、半導体素子の3次元実装の場合に於いても、基板等11と半導体素子13等との間の隙間を埋めるので、高信頼性の半導体装置を歩留まり良く製造できる。また、半導体素子13等を基板等11に隙間なく確実に接着固定できるので、半導体素子の一層の薄型化も可能になる。   According to the present embodiment, even in the case of three-dimensional mounting of semiconductor elements, the gap between the substrate 11 and the semiconductor element 13 is filled, so that a highly reliable semiconductor device can be manufactured with a high yield. In addition, since the semiconductor element 13 and the like can be securely bonded and fixed to the substrate 11 and the like without a gap, the semiconductor element can be made thinner.

(実施の形態3)
本実施の形態の3に係る半導体装置の製造方法について、図3を参照しながら説明する。図3は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。
(Embodiment 3)
A method of manufacturing the semiconductor device according to the third embodiment will be described with reference to FIG. FIG. 3 is a process diagram for explaining the method of manufacturing a semiconductor device according to the present embodiment.

本実施の形態に係る半導体装置は、前記実施の形態2に係る半導体装置と比較して、積層した半導体素子間にスペーサを介在させた点が異なる。より詳細には、半導体素子と半導体素子との間に、接着シートを介してスペーサを積層する工程を含む点が異なる。   The semiconductor device according to the present embodiment is different from the semiconductor device according to the second embodiment in that a spacer is interposed between stacked semiconductor elements. More specifically, it differs in that it includes a step of laminating a spacer via an adhesive sheet between the semiconductor elements.

先ず、図3(a)〜(c)に示すように、前記実施の形態2と同様にして、基板等11上に接着シート12、半導体素子13及び接着シート14を順次積層して仮固着する。さらに、接着シート14上に、スペーサ21、接着シート14及び半導体素子13を順次積層して仮固着する(図3(d)〜(f)参照)。   First, as shown in FIGS. 3A to 3C, the adhesive sheet 12, the semiconductor element 13, and the adhesive sheet 14 are sequentially laminated and temporarily fixed onto the substrate 11 or the like as in the second embodiment. . Further, the spacer 21, the adhesive sheet 14, and the semiconductor element 13 are sequentially laminated and temporarily fixed on the adhesive sheet 14 (see FIGS. 3D to 3F).

次に、図3(g)に示すように、ワイヤーボンディング工程を行う。これにより、半導体素子13に於ける電極パッドと基板等11とをボンディングワイヤー16で電気的に接続する。   Next, as shown in FIG. 3G, a wire bonding step is performed. Thereby, the electrode pad in the semiconductor element 13 and the substrate 11 are electrically connected by the bonding wire 16.

次に、封止樹脂により半導体素子13を封止する封止工程を行い、封止樹脂を硬化させると共に、接着シート14により基板等11と半導体素子13との間、及び半導体素子13同士の間に生じている隙間を塞ぐ。また、封止工程の後、後硬化工程を行ってもよい。以上の製造工程を行うことにより、本実施の形態に係る半導体装置を得ることができる。   Next, a sealing step of sealing the semiconductor element 13 with a sealing resin is performed to cure the sealing resin, and between the substrate 11 and the semiconductor element 13 and between the semiconductor elements 13 with the adhesive sheet 14. Close the gaps that occur. Further, a post-curing process may be performed after the sealing process. By performing the manufacturing steps described above, the semiconductor device according to this embodiment can be obtained.

なお、前記スペーサ21としては、特に限定されるものではなく、例えば従来公知のシリコンチップ、ボリイミドフイルム等を用いることができる。   The spacer 21 is not particularly limited. For example, a conventionally known silicon chip, polyimide film, or the like can be used.

(実施の形態4)
本実施の形態4に係る半導体装置の製造方法について、図4を参照しながら説明する。図4は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。
(Embodiment 4)
A method of manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIG. FIG. 4 is a process diagram for explaining the semiconductor device manufacturing method according to the present embodiment.

先ず、図4(a)に示すように、接着シート12’を半導体ウェハ13’の裏面に貼り付けて接着シート付きの半導体ウェハを作製する。次に、半導体ウェハ13’にダイシングテープ33に貼り合わせる(図4(b)参照)。さらに、接着シート付きの半導体ウェハを所定の大きさとなる様にダイシングしてチップ状にし(図4(c)参照)、ダイシングテープ33から接着剤が付いたチップを剥離する。   First, as shown in FIG. 4A, an adhesive sheet 12 'is attached to the back surface of the semiconductor wafer 13' to produce a semiconductor wafer with an adhesive sheet. Next, the semiconductor wafer 13 'is bonded to the dicing tape 33 (see FIG. 4B). Further, the semiconductor wafer with the adhesive sheet is diced to a predetermined size to form a chip (see FIG. 4C), and the chip with the adhesive is peeled from the dicing tape 33.

次に、図4(d)に示すように、接着シート12が付いた半導体素子13を、ワイヤーボンド面が上側となる様にして基板等11上に仮固着する。さらに、接着シート31が付いた大きさの異なる半導体素子32を、ワイヤーボンド面が上側となる様にして半導体素子13上に仮固着する。   Next, as shown in FIG. 4D, the semiconductor element 13 with the adhesive sheet 12 is temporarily fixed onto the substrate 11 or the like so that the wire bond surface is on the upper side. Further, the semiconductor elements 32 of different sizes with the adhesive sheet 31 are temporarily fixed on the semiconductor element 13 so that the wire bond surface is on the upper side.

次に、図4(e)に示すように、ワイヤーボンディング工程を行う。これにより、半導体素子13・32に於ける電極パッドと基板等11とをボンディングワイヤー16で電気的に接続する。   Next, as shown in FIG. 4E, a wire bonding step is performed. As a result, the electrode pads and the substrate 11 in the semiconductor elements 13 and 32 are electrically connected by the bonding wires 16.

次に、封止樹脂により半導体素子13・32を封止する封止工程を行い、封止樹脂を硬化させると共に、接着シート12・31により基板等11と半導体素子13との間、及び半導体素子13と半導体素子32との間を固着させる。また、封止工程の後、後硬化工程を行ってもよい。以上の製造工程を行うことにより、本実施の形態に係る半導体装置を得ることができる。   Next, a sealing step of sealing the semiconductor elements 13 and 32 with a sealing resin is performed to cure the sealing resin, and between the substrate 11 and the semiconductor element 13 and the semiconductor elements with the adhesive sheets 12 and 31. 13 and the semiconductor element 32 are fixed. Further, a post-curing process may be performed after the sealing process. By performing the manufacturing steps described above, the semiconductor device according to this embodiment can be obtained.

(実施の形態5)
本実施の形態5に係る半導体装置の製造方法について、図5を参照しながら説明する。図5は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。
(Embodiment 5)
A method of manufacturing the semiconductor device according to the fifth embodiment will be described with reference to FIG. FIG. 5 is a process diagram for explaining the semiconductor device manufacturing method according to the present embodiment.

本実施の形態に係る半導体装置の製造方法は、前記実施の形態4に係る半導体装置の製造方法と比較して、ダイシングテープ33上に接着シート12’を積層した後、更に接着シート12’上に半導体ウェハ13’を積層した点が異なる。   Compared with the method of manufacturing a semiconductor device according to the fourth embodiment, the method of manufacturing a semiconductor device according to the present embodiment further includes a step of laminating the adhesive sheet 12 ′ on the dicing tape 33 and then further on the adhesive sheet 12 ′. The difference is that the semiconductor wafer 13 ′ is laminated.

先ず、図5(a)に示すように、ダイシングテープ33上に接着シート12’を積層する。さらに、接着シート12’上に半導体ウェハ13’を仮固着する(図5(b)参照)。さらに、接着シート付きの半導体ウェハを所定の大きさとなる様にダイシングしてチップ状にし(図5(c)参照)、ダイシングテープ33から接着剤が付いたチップを剥離する。   First, as shown in FIG. 5A, the adhesive sheet 12 ′ is laminated on the dicing tape 33. Further, the semiconductor wafer 13 ′ is temporarily fixed on the adhesive sheet 12 ′ (see FIG. 5B). Further, the semiconductor wafer with the adhesive sheet is diced to a predetermined size to form a chip (see FIG. 5C), and the chip with the adhesive is peeled from the dicing tape 33.

次に、図5(d)に示すように、接着シート12が付いた半導体素子13を、ワイヤーボンド面が上側となる様にして基板等11上に仮固着する。さらに、接着シート31が付いた大きさの異なる半導体素子32を、ワイヤーボンド面が上側となる様にして半導体素子13上に仮固着する。この際、半導体素子32の固着は、下段の半導体素子13の電極パッド部分を避けて行われる。   Next, as shown in FIG. 5D, the semiconductor element 13 with the adhesive sheet 12 is temporarily fixed on the substrate 11 or the like so that the wire bond surface is on the upper side. Further, the semiconductor elements 32 of different sizes with the adhesive sheet 31 are temporarily fixed on the semiconductor element 13 so that the wire bond surface is on the upper side. At this time, the semiconductor element 32 is fixed while avoiding the electrode pad portion of the lower semiconductor element 13.

次に、図5(e)に示すように、ワイヤーボンディング工程を行う。これにより、半導体素子13・32に於ける電極パッドと基板等11に於ける内部接続用ランドとをボンディングワイヤー16で電気的に接続する。   Next, as shown in FIG.5 (e), a wire bonding process is performed. As a result, the electrode pads in the semiconductor elements 13 and 32 and the internal connection lands in the substrate 11 are electrically connected by the bonding wires 16.

次に、封止樹脂により半導体素子を封止する封止工程を行い、封止樹脂を硬化させると共に、接着シート12・31により基板等11と半導体素子13との間、及び半導体素子13と半導体素子32との間を固着させる。また、封止工程の後、後硬化工程を行ってもよい。以上の製造工程を行うことにより、本実施の形態に係る半導体装置を得ることができる。   Next, a sealing step of sealing the semiconductor element with a sealing resin is performed to cure the sealing resin, and between the substrate 11 and the semiconductor element 13 and between the semiconductor element 13 and the semiconductor with the adhesive sheets 12 and 31. The element 32 is fixed. Further, a post-curing process may be performed after the sealing process. By performing the manufacturing steps described above, the semiconductor device according to this embodiment can be obtained.

(実施の形態6)
本実施の形態6に係る半導体装置の製造方法について、図6及び図7を参照しながら説明する。図6は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。図7は、本実施の形態に係る半導体装置の製造方法により得られた半導体装置の概略を示す断面図である。
(Embodiment 6)
A method for manufacturing a semiconductor device according to the sixth embodiment will be described with reference to FIGS. FIG. 6 is a process diagram for explaining the semiconductor device manufacturing method according to the present embodiment. FIG. 7 is a cross-sectional view schematically showing a semiconductor device obtained by the semiconductor device manufacturing method according to the present embodiment.

本実施の形態に係る半導体装置は、前記実施の形態3に係る半導体装置と比較して、スペーサとしてコア材料を採用した点が異なる。   The semiconductor device according to the present embodiment is different from the semiconductor device according to the third embodiment in that a core material is employed as a spacer.

先ず、前記実施の形態5と同様にして、ダイシングテープ33上に接着シート12’を積層する。さらに、接着シート12’上に半導体ウェハ13’を貼り付ける。さらに、接着シート付きの半導体ウェハを所定の大きさとなる様にダイシングしてチップ状にし、ダイシングテープ33から接着剤が付いたチップを剥離する。これにより、接着シート12を備えた半導体素子13を得る。   First, the adhesive sheet 12 ′ is laminated on the dicing tape 33 as in the fifth embodiment. Further, a semiconductor wafer 13 'is stuck on the adhesive sheet 12'. Further, the semiconductor wafer with the adhesive sheet is diced to a predetermined size to form a chip, and the chip with the adhesive is peeled from the dicing tape 33. Thereby, the semiconductor element 13 provided with the adhesive sheet 12 is obtained.

他方、ダイシングテープ33の上に接着シート41を形成し、該接着シート41上にコア材料42を貼り付ける。さらに、所定のサイズとなる様にダイシングしてチップ状にし、ダイシングテープ33から接着剤が付いたチップを剥離する。これにより、接着シート41’を備えたチップ状のコア材料42’を得る。   On the other hand, the adhesive sheet 41 is formed on the dicing tape 33, and the core material 42 is pasted on the adhesive sheet 41. Further, the chip is diced to have a predetermined size, and the chip with the adhesive is peeled from the dicing tape 33. As a result, a chip-like core material 42 ′ provided with the adhesive sheet 41 ′ is obtained.

次に、前記半導体素子13を、ワイヤーボンド面が上側となる様に、基板等11上に接着シート12を介して仮固着する。さらに、半導体素子13上に接着シート41’を介してコア材料42’を固着する。さらに、コア材料42’上に接着シート12を介して半導体素子13を、ワイヤーボンド面が上側となる様に仮固着する。以上の製造工程を行うことにより、本実施の形態に係る半導体装置を得ることができる。   Next, the semiconductor element 13 is temporarily fixed to the substrate 11 or the like 11 via the adhesive sheet 12 so that the wire bond surface is on the upper side. Further, the core material 42 ′ is fixed onto the semiconductor element 13 via the adhesive sheet 41 ′. Further, the semiconductor element 13 is temporarily fixed on the core material 42 ′ via the adhesive sheet 12 so that the wire bond surface is on the upper side. By performing the manufacturing steps described above, the semiconductor device according to this embodiment can be obtained.

次に、ワイヤーボンディング工程を行う。これにより、半導体素子13に於ける電極パッドと基板等11に於ける内部接続用ランドとをボンディングワイヤー16で電気的に接続する(図7参照)。   Next, a wire bonding process is performed. Thereby, the electrode pads in the semiconductor element 13 and the internal connection lands in the substrate 11 are electrically connected by the bonding wires 16 (see FIG. 7).

次に、封止樹脂により半導体素子を封止する封止工程を行い、封止樹脂を硬化させると共に、接着シート12・41’により基板等11と半導体素子13との間、及び半導体素子13とコア材料42’との間を固着させる。また、封止工程の後、後硬化工程を行ってもよい。以上の製造工程を行うことにより、本実施の形態に係る半導体装置を得ることができる。   Next, a sealing step of sealing the semiconductor element with the sealing resin is performed to cure the sealing resin, and between the substrate 11 and the semiconductor element 13 and the semiconductor element 13 with the adhesive sheets 12 and 41 ′. The core material 42 'is fixed. Further, a post-curing process may be performed after the sealing process. By performing the manufacturing steps described above, the semiconductor device according to this embodiment can be obtained.

なお、前記コア材料としては特に限定されるものではなく、従来公知のものを用いることができる。具体的には、フィルム(例えばポリイミドフイルム、ポリエステルフィルム、ポリエチレンテレフタレートフィルム、ポリエチレンナフタレートフィルム、ポリカーボネートフィルム等)、ガラス繊維やプラスチック製不織繊維で強化された樹脂基板、ミラーシリコンウェハ、シリコン基板又はガラス基板等を使用できる。   In addition, it does not specifically limit as said core material, A conventionally well-known thing can be used. Specifically, a film (for example, a polyimide film, a polyester film, a polyethylene terephthalate film, a polyethylene naphthalate film, a polycarbonate film, etc.), a resin substrate reinforced with glass fibers or plastic non-woven fibers, a mirror silicon wafer, a silicon substrate or A glass substrate or the like can be used.

(実施の形態7)
本実施の形態7に係る半導体装置の製造方法について、図8を参照しながら説明する。図8は、本実施の形態に係る半導体装置の製造方法を説明する為の工程図である。
(Embodiment 7)
A method for manufacturing a semiconductor device according to the seventh embodiment will be described with reference to FIG. FIG. 8 is a process diagram for explaining the method of manufacturing a semiconductor device according to the present embodiment.

本実施の形態に係る半導体装置の製造方法は、前記実施の形態6に係る半導体装置の製造方法と比較して、コア材料のダイシングに替えて、打ち抜き等によりチップ化した点が異なる。   The manufacturing method of the semiconductor device according to the present embodiment is different from the manufacturing method of the semiconductor device according to the sixth embodiment in that a chip is formed by punching or the like instead of dicing the core material.

先ず、前記実施の形態6と同様にして、接着シート12を備えた半導体素子13を得る。他方、接着シート41上にコア材料42を貼り付ける。さらに、所定のサイズとなる様に打ち抜き等によりチップ状にし、接着シート41’を備えたチップ状のコア材料42’を得る。   First, the semiconductor element 13 provided with the adhesive sheet 12 is obtained as in the sixth embodiment. On the other hand, the core material 42 is stuck on the adhesive sheet 41. Further, it is formed into a chip shape by punching or the like so as to obtain a predetermined size, and a chip-shaped core material 42 ′ having an adhesive sheet 41 ′ is obtained.

次に、前記実施の形態6と同様にして、接着シート12・41’を介してコア材料42’及び半導体素子13を順次積層して仮固着する。   Next, in the same manner as in the sixth embodiment, the core material 42 ′ and the semiconductor element 13 are sequentially stacked and temporarily fixed via the adhesive sheets 12 and 41 ′.

さらに、ワイヤーボンディング工程、封止工程、必要に応じて後硬化工程を行い、本実施の形態に係る半導体装置を得ることができる。   Furthermore, a wire bonding step, a sealing step, and a post-curing step as necessary can be performed to obtain the semiconductor device according to the present embodiment.

(その他の事項)
前記基板等上に半導体素子を3次元実装する場合、半導体素子の回路が形成される面側には、バッファーコート膜が形成されている。当該バッファーコート膜としては、例えば窒化珪素膜やポリイミド樹脂等の耐熱樹脂からなるものが挙げられる。
(Other matters)
When a semiconductor element is three-dimensionally mounted on the substrate or the like, a buffer coat film is formed on the surface side where the circuit of the semiconductor element is formed. Examples of the buffer coat film include those made of a heat resistant resin such as a silicon nitride film or a polyimide resin.

また、半導体素子の3次元実装の際に、各段で使用される接着シートは同一組成からなるものに限定されず、製造条件や用途等に応じて適宜変更可能である。   In addition, the adhesive sheet used at each stage when the semiconductor element is three-dimensionally mounted is not limited to the one having the same composition, and can be appropriately changed according to the manufacturing conditions and applications.

また、前記実施の形態に於いて述べた積層方法は例示的に述べたものであって、必要に応じて適宜変更が可能である。例えば、前記実施の形態2に係る半導体装置の製造方法に於いては、2段目以降の半導体素子を前記実施の形態3に於いて述べた積層方法で積層することも可能である。   In addition, the lamination method described in the above embodiment has been described by way of example, and can be appropriately changed as necessary. For example, in the method for manufacturing a semiconductor device according to the second embodiment, the semiconductor elements in the second and subsequent stages can be stacked by the stacking method described in the third embodiment.

また、前記実施の形態に於いては、基板等に複数の半導体素子を積層させた後に、一括してワイヤーボンディング工程を行う態様について述べたが、本発明はこれに限定されるものではない。例えば、半導体素子を基板等の上に積層する度にワイヤーボンディング工程を行うことも可能である。   Further, in the above-described embodiment, the mode in which the wire bonding process is performed collectively after laminating a plurality of semiconductor elements on a substrate or the like has been described, but the present invention is not limited to this. For example, it is possible to perform a wire bonding process every time a semiconductor element is stacked on a substrate or the like.

以下に、この発明の好適な実施例を例示的に詳しく説明する。但し、この実施例に記載されている材料や配合量等は、特に限定的な記載がない限りは、この発明の範囲をそれらのみに限定する趣旨のものではなく、単なる説明例に過ぎない。   Hereinafter, preferred embodiments of the present invention will be described in detail by way of example. However, the materials, blending amounts, and the like described in the examples are not intended to limit the scope of the present invention only to them, but are merely illustrative examples, unless otherwise specified.

(実施例1)
アクリル酸エチル−メチルメタクリレートを主成分とするアクリル酸エステル系ポリマー(根上工業(株)製、パラクロンW−197CM)100部に対して、多官能イソシアネート系架橋剤3部、エポキシ樹脂(ジャパンエポキシレジン(株)製、エビコート1004)23部、フェノール樹脂(三井化学(株)製、ミレックスXLC‐LL)6部、をメチルエチルケトンに溶解させ、濃度20重量%の接着剤組成物の溶液を調整した。
Example 1
3 parts of a polyfunctional isocyanate-based crosslinking agent and 100 parts of an epoxy resin (Japan Epoxy Resin) with respect to 100 parts of an acrylate-based polymer (manufactured by Negami Kogyo Co., Ltd., Paracron W-197CM) mainly composed of ethyl acrylate-methyl methacrylate Co., Ltd., Shrimp Coat 1004) 23 parts and phenol resin (Mitsui Chemicals Co., Ltd., Mirex XLC-LL) 6 parts were dissolved in methyl ethyl ketone to prepare a solution of an adhesive composition having a concentration of 20% by weight.

この接着剤組成物の溶液を、剥離ライナーとしてシリコーン離型処理したポリエチレンテレフタレートフィルム(厚さ50μm)からなる離型処理フィルム上に塗布した。さらに、120℃で3分間乾燥させたことにより、厚さ25μmの本実施例1に係る接着シートを作製した。   This adhesive composition solution was applied onto a release-treated film composed of a polyethylene terephthalate film (thickness 50 μm) subjected to silicone release treatment as a release liner. Furthermore, the adhesive sheet which concerns on this Example 1 with a thickness of 25 micrometers was produced by making it dry at 120 degreeC for 3 minute (s).

(実施例2)
本実施例2に於いては、実施例1にて使用したアクリル酸エステル系ポリマーに替えて、ブチルアクリレートを主成分としたポリマー(根上工業(株)製、パラクロンSN−710)を用いた以外は、前記実施例1と同様にして、本実施例2に係る接着シート(厚さ25μm)を作製した。
(Example 2)
In Example 2, instead of the acrylic ester polymer used in Example 1, a polymer mainly composed of butyl acrylate (manufactured by Negami Industrial Co., Ltd., Paracron SN-710) was used. In the same manner as in Example 1, an adhesive sheet (thickness 25 μm) according to Example 2 was produced.

(比較例1)
アクリル酸エチル−メチルメタクリレートを主成分とするアクリル酸エステル系ポリマー(根上工業(株)製、パラクロンW−197CM)100部に対して、エポキシ樹脂(ジャパンエポキシレジン(株)製、エビコート1004)23部、フェノール樹脂(三井化学(株)製、ミレックスXLC‐LL)6部をメチルエチルケトンに溶解させ、濃度20重量%の接着剤組成物の溶液を調整した。
(Comparative Example 1)
Epoxy resin (Japan Epoxy Resin Co., Ltd., Shrimp Coat 1004) 23 with respect to 100 parts of an acrylic ester polymer (Paracron W-197CM, manufactured by Negami Kogyo Co., Ltd.) mainly composed of ethyl acrylate-methyl methacrylate. Part of a phenol resin (Milex Chemical Co., Ltd., Milex XLC-LL) was dissolved in methyl ethyl ketone to prepare a solution of an adhesive composition having a concentration of 20% by weight.

この接着剤組成物の溶液を、剥離ライナーとしてシリコーン離型処理したポリエチレンテレフタレートフィルム(厚さ50μm)からなる離型処理フィルム上に塗布した。さらに、120℃で3分間乾燥させたことにより、比較例1に係る接着シート(厚さ25μm)を作製した。   This adhesive composition solution was applied onto a release-treated film composed of a polyethylene terephthalate film (thickness 50 μm) subjected to silicone release treatment as a release liner. Furthermore, the adhesive sheet (thickness 25 micrometers) which concerns on the comparative example 1 was produced by making it dry at 120 degreeC for 3 minute (s).

(比較例2)
比較例2に於いては、前記比較例1にて使用したアクリル酸エステル系ポリマーに替えて、ブチルアクリレートを主成分としたポリマー(根上工業(株)製、パラクロンSN−710)を用いた以外は、比較例1と同様にして、比較例2に係る接着シート(厚さ25μm)作製した。
(Comparative Example 2)
In Comparative Example 2, in place of the acrylic ester polymer used in Comparative Example 1, a polymer mainly composed of butyl acrylate (manufactured by Negami Industrial Co., Ltd., Paracron SN-710) was used. Was produced in the same manner as in Comparative Example 1, and an adhesive sheet (thickness 25 μm) according to Comparative Example 2 was produced.

〔損失弾性率測定〕
前記実施例及び比較例に於いて作製した接着シートについて、損失弾性率を以下の通り測定した。
(Measurement of loss modulus)
About the adhesive sheet produced in the said Example and a comparative example, the loss elastic modulus was measured as follows.

測定装置は、動的粘弾性測定装置(RSAII、Reometric Scientif社製)を用いて測定される。測定条件は、シートを縦10mm×横5mmに切断し、引張りモードで、一定の周波数(10Hz)で、温度を5℃/分で昇温させ、30℃〜250℃での測定を行い、その175℃での損失弾性率を決定した。次に、基板、リードフレーム及び半導体素子について接着面積評価用各種試料を作製した。   The measuring device is measured using a dynamic viscoelasticity measuring device (RSAII, manufactured by Reometric Scientific). The measurement condition is that the sheet is cut into 10 mm length × 5 mm width, the temperature is raised at a constant frequency (10 Hz) at 5 ° C./min in the tension mode, and the measurement is performed at 30 ° C. to 250 ° C. The loss modulus at 175 ° C. was determined. Next, various samples for evaluating the adhesion area of the substrate, the lead frame, and the semiconductor element were produced.

即ち、基板(UniMicron Technorogy Corporations製 、商品名TFBGA16×16(2216−001A01))の場合に於いては、得られた接着フィルムをセパレーターから剥離した後、5mm□に切断したものを用いた。一方、シリコンウェハをダイシングして、縦5mm×横5mm×厚さ100μmのチップを作製した。このチップを、基板に仮固着して試験片を作製した。仮固着は、120℃の温度下で荷重(0.25MPa)をかけ、1秒間加熱するという条件下で、ダイボンダー((株)新川製SPA−300)を用いて行った。   That is, in the case of a substrate (trade name TFBGA16 × 16 (2216-001A01) manufactured by UniMicron Technology Corporation), the obtained adhesive film was peeled off from the separator and then cut into 5 mm □. On the other hand, the silicon wafer was diced to produce a chip of 5 mm length × 5 mm width × 100 μm thickness. This chip was temporarily fixed to the substrate to prepare a test piece. Temporary fixing was performed using a die bonder (SPA-300 manufactured by Shinkawa Co., Ltd.) under the condition of applying a load (0.25 MPa) at a temperature of 120 ° C. and heating for 1 second.

また、リードフレーム(新光電気株式会社製、品名CA−F313(MF202))の場合に於いても、前記基板の場合と同様にして試験片を作製した。   In the case of a lead frame (product name: CA-F313 (MF202) manufactured by Shinko Electric Co., Ltd.), a test piece was prepared in the same manner as in the case of the substrate.

また、半導体素子の場合に於いては、得られた接着シートをセパレーターから剥離した後、6mm□に切断したものを用いた。リードフレーム(新光電気株式会社製、品名CA−F313(MF202))のダイパッドに、シリコンウェハを縦6mm×横6mm×厚さ300μmにダイシングしたものをダイアタッチした。その後、前記接着シートを5mm□に切断したものを用い、アルミ蒸着ウェハから縦5mm×横5mm×厚さ100μmにダイシングしたチップを前記評価用素子の上にダイアタッチした試験片を作製した。ダイアタッチは、基板及びリードフレームの場合と同様の条件で行った。   In the case of a semiconductor element, the obtained adhesive sheet was peeled from the separator and then cut into 6 mm □. A die pad of a lead frame (product name: CA-F313 (MF202), manufactured by Shinko Electric Co., Ltd.) was diced with a silicon wafer diced into a length of 6 mm × width of 6 mm × thickness of 300 μm. Thereafter, a test piece was prepared by die-attaching a chip diced from an aluminum vapor-deposited wafer to a length of 5 mm, a width of 5 mm, and a thickness of 100 μm on the evaluation element. The die attach was performed under the same conditions as those for the substrate and the lead frame.

次に封止工程は、TOWA TEC(株)製オートモールドプレスCPS‐401にて行った。封止条件は、金型温度175℃、プレヒート3秒、キュアタイム120秒、クランプ圧 200kN、トランスファー圧力5kNにて行った。封止樹脂は日東電工(株)製GE−100を使用した。   Next, the sealing step was performed with an auto mold press CPS-401 manufactured by TOWA TEC Co., Ltd. The sealing conditions were as follows: mold temperature 175 ° C., preheating 3 seconds, cure time 120 seconds, clamping pressure 200 kN, and transfer pressure 5 kN. As the sealing resin, GE-100 manufactured by Nitto Denko Corporation was used.

接着面積の測定は、超音波深傷装置(日本バーンズ社製、Sono−Scan D−6000)にて、仮固着後、および封止後のそれぞれについて接着面積を測定した。それらの結果を下記表1に示す。   The adhesion area was measured with an ultrasonic deep wound device (Nihon Burns Co., Ltd., Sono-Scan D-6000) after temporary fixing and after sealing. The results are shown in Table 1 below.

Figure 2009081440
Figure 2009081440

表1に示す様に、実施例1及び2に係る接着シートは、何れも2000Pa以上の損失蝉性率を有し、何れの被着体に対しても、封止後の接着面積が90%以上であった。その一方、比較例1及び2に係る接着シートは、何れも2000Pa以下であり、何れの接着面積ともダイアタッチ後と封止後とで変化が無かった。   As shown in Table 1, the adhesive sheets according to Examples 1 and 2 both have a loss inertia ratio of 2000 Pa or more, and the adhesion area after sealing is 90% for any adherend. That was all. On the other hand, the adhesive sheets according to Comparative Examples 1 and 2 were both 2000 Pa or less, and any adhesive area did not change after die attach and after sealing.

本発明の実施の形態1に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態2に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態3に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態4に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態5に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. 本発明の実施の形態6に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. 前記実施の形態6に係る半導体装置の製造方法により得られた半導体装置の概略を示す断面図である。It is sectional drawing which shows the outline of the semiconductor device obtained by the manufacturing method of the semiconductor device which concerns on the said Embodiment 6. FIG. 本発明の実施の形態7に係る半導体装置の製造方法を説明する為の工程図である。It is process drawing for demonstrating the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention.

符号の説明Explanation of symbols

11 基板等(被着体)
12、14、31、41 接着シート
13 半導体素子
15 封止樹脂
16 ボンディングワイヤー
21 スペーサ
32 半導体素子
33 ダイシングテープ
42、42’ コア材料(スペーサ)
11 Substrate etc. (Adherent)
12, 14, 31, 41 Adhesive sheet 13 Semiconductor element 15 Sealing resin 16 Bonding wire 21 Spacer 32 Semiconductor element 33 Dicing tape 42, 42 'Core material (spacer)

Claims (14)

半導体素子を被着体上に接着シートを介して仮固着する仮固着工程と、
前記半導体素子にワイヤーボンディングをするワイヤーボンディング工程と、
前記半導体素子を封止樹脂により封止する工程とを含み、
前記接着シートとして175℃での損失弾性率が2000Pa以上のものを使用することを特徴とする半導体装置の製造方法。
A temporary fixing step of temporarily fixing the semiconductor element on the adherend via an adhesive sheet;
A wire bonding step of wire bonding to the semiconductor element;
Sealing the semiconductor element with a sealing resin,
A method for manufacturing a semiconductor device, wherein the adhesive sheet has a loss elastic modulus at 175 ° C. of 2000 Pa or more.
前記請求項1に記載の半導体装置の製造方法であって、
前記封止工程に於いて加熱により封止樹脂を硬化させると共に、前記接着シートを介して半導体素子と被着体とを固着させることを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to claim 1,
In the sealing step, the sealing resin is cured by heating, and the semiconductor element and the adherend are fixed through the adhesive sheet.
前記請求項1に記載の半導体装置の製造方法であって、
前記封止樹脂の後硬化を行う後硬化工程を含み、
前記封止工程及び/又は後硬化工程に於いて、加熱により封止樹脂を硬化させると共に、前記接着シートを介して半導体素子と被着体とを固着させることを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to claim 1,
A post-curing step of performing post-curing of the sealing resin,
In the sealing step and / or the post-curing step, the sealing resin is cured by heating, and the semiconductor element and the adherend are fixed via the adhesive sheet. .
前記請求項1〜3の何れか1項に記載の半導体装置の製造方法であって、
前記封止工程は、150℃〜200℃の範囲内で行われることを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device according to any one of claims 1 to 3,
The said sealing process is performed within the range of 150 degreeC-200 degreeC, The manufacturing method of the semiconductor device characterized by the above-mentioned.
前記請求項1〜4の何れか1項に記載の半導体装置の製造方法であって、
前記封止後の半導体素子と被着体との間の接着面積が90%以上であることを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to any one of claims 1 to 4,
A method of manufacturing a semiconductor device, wherein an adhesion area between the semiconductor element after sealing and the adherend is 90% or more.
前記請求項1〜5の何れか1項に記載の半導体装置の製造方法であって、
前記被着体は、基板、リードフレーム又は半導体素子であることを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to any one of claims 1 to 5,
The method of manufacturing a semiconductor device, wherein the adherend is a substrate, a lead frame, or a semiconductor element.
前記請求項6に記載の半導体装置の製造方法であって、
前記被着体が半導体素子である場合に、半導体素子と半導体素子との間に、前記接着シートを介してスペーサを積層する工程を含むことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to claim 6,
When the adherend is a semiconductor element, the semiconductor device manufacturing method includes a step of stacking a spacer between the semiconductor elements via the adhesive sheet.
前記請求項1〜7の何れか1項に記載の半導体装置の製造方法であって、
前記接着シートとして、熱可塑性樹脂を含むものを使用することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device according to any one of claims 1 to 7,
A method for manufacturing a semiconductor device, comprising using a thermoplastic resin as the adhesive sheet.
前記請求項1〜7の何れか1項に記載の半導体装置の製造方法であって、
前記接着シートとして、熱硬化性樹脂と熱可塑性樹脂の双方を含むものを使用することを特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device according to any one of claims 1 to 7,
A method of manufacturing a semiconductor device, wherein the adhesive sheet includes a sheet containing both a thermosetting resin and a thermoplastic resin.
前記請求項8又は9に記載の半導体装置の製造方法であって、
前記熱可塑性樹脂として、アクリル樹脂を使用することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to claim 8 or 9,
A method for manufacturing a semiconductor device, wherein an acrylic resin is used as the thermoplastic resin.
前記請求項9に記載の半導体装置の製造方法であって、
前記熱硬化性樹脂として、エポキシ樹脂及び/又はフェノール樹脂を使用することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to claim 9,
An epoxy resin and / or a phenol resin is used as the thermosetting resin.
前記請求項8〜11の何れか1項に記載の半導体装置の製造方法であって、
前記接着シートとして、架橋剤が添加されているものを使用することを特徴とする半導体装置の製造方法。
It is a manufacturing method of the semiconductor device according to any one of claims 8 to 11,
A manufacturing method of a semiconductor device, wherein a bonding agent is added as the adhesive sheet.
前記請求項1〜12の何れか1項に記載の半導体装置の製造方法に於いて使用される接着シート。   The adhesive sheet used in the manufacturing method of the semiconductor device of any one of the said Claims 1-12. 前記請求項1〜12の何れか1項に記載の半導体装置の製造方法により得られたものであることを特徴とする半導体装置。
A semiconductor device obtained by the method for manufacturing a semiconductor device according to claim 1.
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JP2011116897A (en) * 2009-12-04 2011-06-16 Nitto Denko Corp Thermosetting die bond film, dicing die bond film, and semiconductor device

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