JP2009080926A - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device which can flexibly determine data to be prefetched. <P>SOLUTION: The storage device has a nonvolatile memory (2), a buffer memory (4) having higher access speed than that of the nonvolatile memory and a control circuit (5). When a prefetch command is input from the outside, the control circuit generates a prefetch data management table where a logic address of prefetch data designated by the prefetch command is made to correspond to the address of the buffer memory storing the prefetch data, reads data designated by the command from the nonvolatile memory and stores the read data into the buffer memory as the prefetch data, when a read command is input from the outside and the logic address designated by the read command coincides with the logic address made to corresponded to the buffer memory address by the prefetch data management table, the control circuit outputs the corresponding prefetch data from the buffer memory. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage device such as a hard disk device or a flash memory card, and more particularly to an invention that is effective when applied to a technique for prefetching storage information of a nonvolatile memory as a storage medium into a buffer memory.

  In a storage device composed of a controller, a buffer memory, a storage medium, and the like, when a read request is received from the host device, the controller reads data expected to be used thereafter from the storage medium before the read request is received from the host device. There is a look-ahead technique for storing data in the buffer memory. For example, a hard disk drive (HDD) device described in Patent Document 1 has a disk cache, and caches predicted data in the disk cache in advance, thereby minimizing time-consuming access to the magnetic disk. Is done. The hard disk controller performs control for prefetching a part of data stored in the magnetic disk and holding it in the disk cache.

JP 2001-1225829 A (paragraphs 24 to 27)

  Since the data read performance for a storage medium such as a magnetic disk or a flash memory has not been able to follow the speeding up of the host interface, it is necessary to reduce the read processing from the storage medium at the time of a read request from the host device. For this purpose, it is considered effective to pre-read data from the storage medium as described above and store it in the buffer memory in advance. However, the data to be prefetched is determined by the controller of the storage device, and the user cannot use the prefetch function. In short, if the controller determines prefetched data according to a predetermined algorithm, it is not easy to prefetch data that is expected to be used frequently into the buffer memory in advance, and the effect of shortening access time by prefetching is maximized. It is difficult to let it show to the limit.

  An object of the present invention is to provide a storage device that can flexibly determine data to be prefetched.

  Another object of the present invention is to provide a storage device that can easily maximize the effect of shortening access time by prefetching.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A storage device according to the present invention includes a nonvolatile memory (2), a buffer memory (4) having a higher access speed than the nonvolatile memory, and a control circuit (5), and the control circuit is externally input. A pre-read data management table (Ti) that associates the logical address of the pre-read data specified by the pre-read command and the buffer memory address for storing the pre-read data, and reads the data specified by the command from the nonvolatile memory When the logical address specified by the read command input from the outside matches the logical address associated in the prefetch data management table, the corresponding prefetch data is output from the buffer memory.

  According to the above means, the prefetch data can be designated from the outside of the storage device by the prefetch command. Therefore, the data to be prefetched can be determined flexibly so that the effect of shortening the access time by prefetching can be maximized. The read performance of the storage device is the bottleneck of the read performance of the non-volatile memory itself, which is the storage medium. Therefore, prefetch data is output from the buffer memory in place of the read processing from the storage medium when an external read request is made. System performance can be improved by increasing processing. A plurality of prefetching commands can be designated by a plurality of prefetching commands within the range allowed by the capacity of the buffer memory.

  As a specific form of the present invention, the prefetch command designates prefetch data by a logical address. As represented by the master boot record or FAT (file allocation table), the user can easily grasp the logical address, so it is convenient because the pre-read data can be specified directly. is there.

  The prefetch command may designate prefetch data by a file name. In general, a storage device user may not be able to grasp a logical address on a storage device managed by an OS (operating system), and it is easy for a storage device user to grasp data by a file name. Realizes good operability for prefetching.

  The transfer of the prefetch data by the control circuit may be performed when the prefetch command is executed. Alternatively, the prefetch data management table may be generated first, and then the prefetch data may be transferred to the buffer memory at a predetermined timing. Then, the control circuit can transfer the prefetch data to the buffer memory in the command waiting state after the execution of the prefetch command. It is possible to prevent the occurrence of a situation in which processing such as read access is awaited by prefetch data transfer processing.

  As a specific form of the present invention, the prefetch data management table includes a top logical address (30) of prefetch data, a top memory address (31) of a prefetch data storage area, and an area for storing the number of prefetch data. (32) etc.

  The prefetch data management table may hold a flag (33) indicating the validity of the corresponding prefetch data.

  The prefetch data management table may have an area (35) for holding a file name including prefetch data. For example, when file fragmentation occurs in the FAT file system, one file data is managed by a plurality of divided prefetch data management tables, and at this time, processing for responding to the access specified by the file name Convenient to. That is, the corresponding prefetch data management table can be searched by the file name, and access to required prefetch data on the buffer memory is further accelerated.

  The prefetch data management table may have an area (34) for holding the number of times of prefetch data access. The control circuit searches for a buffer memory address with a low access frequency based on the number of accesses held in the prefetch data management table when there is no unused area for storing the prefetch data in the buffer memory. An area can be allocated to a storage area for new prefetch data. It is possible to guarantee effective use of prefetched data that is frequently accessed.

  The control circuit may save the prefetch data management table in a prefetch data management table storage area of the nonvolatile memory at a predetermined timing. When the prefetch data management table is operated in the buffer memory or in the memory inside the control circuit, the prefetch data on the buffer memory can be saved by shutting off the power supply by saving the prefetch data management table of the functioning prefetch data. If lost, it can be reproduced later. For example, the control circuit reads the prefetch data management table from the nonvolatile memory in response to power-on, and transfers the prefetch data whose location is defined by the read prefetch data management table from the nonvolatile memory to the buffer memory.

  [2] A storage device according to another aspect of the present invention includes a nonvolatile memory, a buffer memory having a higher access speed than the nonvolatile memory, and a control circuit, and the control circuit receives a read command input from the outside. In response, the rewritable prefetch data management table that associates the logical address of the prefetch data with the buffer memory address that stores the prefetch data is referenced to determine whether the buffer memory holds the data specified by the command. If the data is held, the data read from the buffer memory is output to the outside. If not, the data read from the nonvolatile memory is output to the outside.

  According to the above means, by using the rewritable prefetch data management table, it is possible to flexibly determine data to be prefetched so that the effect of shortening the access time by prefetching can be maximized. Since the number of processes for outputting pre-read data from the buffer memory instead of the process for reading from the nonvolatile memory in response to the read command increases, the system performance can be improved.

  As a specific form of the present invention, the control circuit reads the prefetch data management table from the non-volatile memory in response to power-on, and reads the prefetch data whose location is defined by the read prefetch data management table. To the buffer memory. The prefetched data that was functioning before the power was shut off can be easily reproduced on the buffer memory later.

  [3] A storage device according to still another aspect of the present invention includes a nonvolatile memory, a buffer memory having a higher access speed than the nonvolatile memory, and a control circuit, and the control circuit includes a prefetch command input from the outside. In response to the logical address of the pre-read data specified by it and the buffer memory address for storing the pre-read data, a pre-read data management table is generated, and the data specified by the command is read from the nonvolatile memory and buffered. The data is stored in the memory as prefetched data, and the prefetched data stored in the buffer memory can be read out to the outside. Prefetch data can be designated from outside the storage device by a prefetch command. Therefore, the data to be prefetched can be determined flexibly so that the effect of shortening the access time by prefetching can be maximized.

  As a specific form of the present invention, the control circuit, as a process when there is no unused area for storing the pre-read data in the buffer memory, permits overwriting to the area that already holds the pre-read data, or already holds the pre-read data. The overwriting prohibition to the area to be performed may be selectable. Selecting the former is convenient for dynamic replacement of prefetched data. By selecting the latter, it is easy to guarantee effective use of frequently read-ahead data. When the latter is selected, if there is no unused area, an error response may be returned to the prefetch command issuer to alert the user. The overwriting permission may be a full permission to an area that already holds prefetched data or a partial permission to an area with low access frequency. The partial permission is convenient to achieve both the dynamic interchangeability of the prefetched data and the effective utilization of the prefetched data that is frequently accessed.

  As a response process to a read command, the control circuit refers to the prefetch data management table in response to a read command input from the outside, and determines whether or not the buffer memory holds the data specified by the command If the data is held, the data read from the buffer memory is output to the outside. If not, the data read from the nonvolatile memory is output to the outside.

  In response to a write command, the control circuit refers to the prefetch data management table in response to a write command input from the outside, and determines whether or not the buffer memory holds data at a write address according to the command. If the data is held, the data in the buffer memory is updated with the write data together with the data in the nonvolatile memory. If not, the data in the nonvolatile memory is updated with the write data.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, prefetch data can be designated from the outside of the storage device by a prefetch command. Therefore, the data to be prefetched can be determined flexibly so that the effect of shortening the access time by prefetching can be maximized. Data processing performance of a system using a storage device can be improved by increasing processing for outputting prefetched data from the buffer memory instead of processing for reading from the storage medium when an external read request is made.

<Flash memory card>
FIG. 1 shows a flash memory card which is an example of a storage device according to the present invention. The flash memory card 1 shown in FIG. 1 includes a nonvolatile memory such as an electrically erasable and writable memory flash memory 2 and a buffer memory 4 composed of DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). And a card controller (control circuit) 5 for performing memory control and external interface control on the mounting board. The flash memory card 1 is controlled as a file memory device by the host computer 6. That is, when performing file access, the host computer 6 refers to the FAT (File Allocation Table) formed in the flash memory card 1 to obtain the logical address of the sector constituting the file and uses this logical address. The access command is issued to the flash memory card 1. The flash memory card 1 controls access to the flash memory 2 and the buffer memory 4 in response to the access command.

  The card controller 5 controls access to the buffer memory 4 and the flash memory 2 in accordance with an instruction by a read command, a write command, a pre-read command or the like given from the host computer 6. The read command is an instruction to read data by designating the start logical address and the number of sectors of the read sector, for example. The write command is an instruction to write data by designating the start logical address and the number of sectors, for example. The prefetch command generates a prefetch data management table in which the logical address of the data to be prefetched is associated with the buffer memory address for storing the prefetch data, reads the data to be prefetched from the flash memory 2 and prefetches it into the buffer memory 4 This is an instruction to store as data. Details of processing for each command will be described later.

  The storage area of the buffer memory 4 is a primary storage area (write data storage area) 10 for write data supplied from the host computer 6 and an area for temporarily storing data read from the flash memory 2 and output to the host computer 6. A read data storage area 11, a work area 12, and an area (prefetch data storage area) 13 for storing data read from the flash memory 2 in response to the prefetch command as prefetch data. FIG. 2 illustrates details of the address map of the buffer memory 4. Since the pre-read data is always read on the buffer memory and occupies the storage area of the buffer memory, it can be managed separately from the buffer areas 10 and 11 for normal use of writing and reading.

  The storage areas of the flash memory 2 are a data unit 14, an internal information storage unit 15, and a prefetch data management table storage unit 16, each having a management unit added thereto. The internal information storage unit 15 stores the ID, RD (root directory), FAT (file allocation table), and the like of the memory card 1 and can be referred to by the OS (operating system) of the host computer 6. The prefetch data management table storage unit 16 stores the prefetch data management table generated in response to the prefetch command.

  The flash memory 2 has a memory array ARY in which a large number of electrically erasable and writable nonvolatile memory cell transistors are arranged in a matrix, although not shown. A memory cell transistor (also referred to as a flash memory cell) is formed through a tunnel oxide film in a channel region between a source and a drain formed in a semiconductor substrate or well, and between the source and drain, although not particularly shown. A stacked gate structure including a floating gate and a control gate superimposed on the floating gate with an interlayer insulating film interposed therebetween. The control gate is connected to the corresponding word line, the drain is connected to the corresponding bit line, and the source is connected to the source line. The threshold voltage of the memory cell transistor increases when electrons are injected into the floating gate, and the threshold voltage decreases when electrons are extracted from the floating gate. The memory cell transistor stores information corresponding to the level of the threshold voltage with respect to the word line voltage (control gate applied voltage) for reading data. Although not particularly limited, in this specification, a state in which the threshold voltage of the memory cell transistor is low is referred to as an erased state, and a state in which the threshold voltage is high is referred to as a written state.

  In FIG. 1, the card controller 5 includes a host interface circuit 20, a microprocessor (MPU) 21 as operation control means, a flash controller 22, and a buffer controller 23. The flash controller 22 includes an ECC circuit (not shown).

  The MPU 21 includes a CPU (Central Processing Unit) 25, a program memory (PGM) 26, a work RAM (WRAM) 27, and the like, and controls the card controller 5 as a whole. The program memory 26 holds an operation program for the CPU 25 and the like.

  The host interface circuit 20 is in accordance with a predetermined protocol such as ATA (ATAttachment), IDE (Integrated Device Electronics), SCSI (Small Computer System Interface), MMC (MultiMediaCard: registered trademark), PCMCIA (Personal Computer Memory Card International Association). Interface with a host computer 6 such as a personal computer or workstation.

  The buffer controller 23 controls access to the buffer memory 4 in accordance with an access instruction given from the MPU 21.

  The flash controller 22 controls a read operation, an erase operation, and a write operation with respect to the flash memory 2 in accordance with an access instruction given from the MPU 21. An ECC circuit (not shown) generates an error correction code (error correction code) for data to be written to the flash memory 2 in accordance with an instruction given from the MPU 21, and adds the error correction code to the write data. Further, error detection / correction processing is performed on the read data read from the flash memory 2 by using an error correction code added to the read data, and error correction is performed for errors occurring within the error correction capability range. .

  FIG. 3 illustrates the configuration of the flash memory 2 storage area and details of the prefetch data management table. The storage area (memory array) of the flash memory 2 includes, for example, memory blocks numbered 0 to number 4n + 3 in the figure and n blocks constituted by M0 to Mn management units as storage areas. Each memory sector and each management unit has a physical address, and a logical address is assigned to each memory sector. The logical address is, for example, a file sector number (file sector number). In the following description, the address of the memory sector is simply referred to as a physical address or a physical sector address. The logical address can be grasped as an address instructed from the outside, and the physical address can be grasped as an address for accessing the inside by the logical address. The memory sector corresponds to a storage sector capacity 512B (bytes) as a rewrite unit in a storage such as an HDD (hard disk drive). The management area stores a block validity flag, a substitution flag, and the like. The ECC code is arranged for each memory sector. Non-volatile memory cells constituting one block are selected by one word line or one type of word line selection signal, and are used as a unit for erasing processing and writing processing. For example, a high voltage necessary for erasing processing and writing processing is a word. Applied in line units.

  The memory sectors 4n to 4n + 3 are used as the prefetch data management table storage unit 16. A plurality of prefetch data management tables Ti (T0, T1, T2,...) And ECC codes are stored in each memory sector of the prefetch data management table storage unit 16. Since the prefetch data management table can be added by performing a process in response to the prefetch command, a plurality of prefetch data management tables are allowed.

  The prefetch data management table Ti includes, for example, a head logical address area 30, a head memory address area 31, a sector number area 32, a valid flag area 33, an access count area 34, and a file name area 35. The leading logical address area 30 stores the leading logical address (logical sector address) of the prefetched data. The start memory address area 31 stores the start memory address of an area holding prefetched data on the buffer memory. The sector number area 32 stores the number of sectors of the pre-read data. The valid flag area 33 stores a flag indicating whether or not the prefetch data management table is valid. The access count area 34 is an area for storing the number of accesses by the host computer 6 for the pre-read data managed by the write management table. The file name area 35 is an area for holding a file name to which prefetched data belongs.

  The prefetch data management table may be managed either on the flash memory 2 or on the buffer memory 4. In the case of management on the flash memory 2, the erasure and write processing for the prefetch data management table storage unit 16 is performed every time the prefetch data management table is generated and extinguished. In the case of management on the buffer memory 4, the operation of creating and extinguishing the management table becomes faster. However, it is necessary to save the prefetch data management table in the flash memory 2 when the power is shut off. In response to power-on, it is desirable to read the prefetch data management table from the flash memory 2 and transfer prefetch data whose location is defined by the read prefetch data management table from the flash memory to the buffer memory 4.

<< Read-ahead command response processing >>
FIG. 4 shows the main specifications of the prefetch command. The pre-read data can be specified by an address or a file name. The address designation means that a user (user) of the memory card 1 designates a prefetch data area by a logical address. The file designation is that the user designates a file name having prefetched data. If the absolute path of the location is included in the file name, duplication of the file name can be easily dealt with, and the file search becomes easy.

  In general, the user of the storage device may not be able to grasp the logical address on the flash memory card 1 managed by the OS. It is easy for the user of the flash memory card 1 to grasp the data by the file name, and by considering this, it is possible to guarantee good operability for the data prefetching. In some cases, the logical address on the flash memory cannot be managed on the OS. Even in such a case, the prefetch data can be specified.

  The operation timing for storing the pre-read data from the flash memory 2 to the buffer memory 4 is performed in the background when the pre-read command is issued or in the command waiting state after the pre-read data management table is generated first. By performing the process while waiting for a command, it is possible to prevent the occurrence of a situation in which a process such as a read access is awaited by a process of transferring prefetched data from the flash memory 2 to the buffer memory 4.

  FIG. 5 illustrates a control procedure for the prefetch command response process. When a prefetch command issued from the host computer 6 is received (S1), the physical address of the prefetch data designated by the logical address or file name is acquired by the command (S2). A prefetch data management table is created based on the logical address of the prefetch data designated by the prefetch command and the corresponding physical address (S3). The creation location is, for example, the work area 12 of the buffer memory 4. It is determined whether or not the prefetched data specified by the created prefetched data management table is actually readable (S4). This is to detect the case where the file does not exist or the logical address is not associated with the block of the flash memory. If the file is not readable, an error code is returned to the host computer 6. If it can be read, it is determined whether the next command can be received. If it cannot be received, in other words, if no other access command is issued from the host computer 6, the prefetched data is read from the flash memory 2 and the buffer memory 4 is read. (S6), and a valid flag is set in the valid flag area 33 of the corresponding prefetch data management table (S7). When the number of sectors of the pre-read data is 2 or more, the process returns to steps S6 and S7 for the subsequent sector data and the same processing is repeated (S8). The pre-read data read address of the flash memory 2 and the pre-read data write address of the buffer memory necessary for pre-reading the subsequent sector data may be obtained sequentially by the address calculation of the microprocessor 11. When the prefetching of all the sector data defined in the prefetch data management table created in step S3 is completed, the busy state by the current prefetch command reception is canceled (S9), and the process is terminated. In step S5, if the next command can be received, the busy state by receiving the prefetch command is canceled (S9), and the next command is received and executed.

  Needless to say, it is possible to adopt a processing procedure in which the determination processing in step S5 is invalidated and the processing in step S6 and subsequent steps is automatically continued. In this case, the switching of processing (switching whether or not to perform step S5) may be performed by the card controller 5 itself, or the pre-read command may have control information for function switching. .

  When an access command is supplied from the host computer 6, the valid flag 33 of the prefetch data management table is checked, and only the prefetch data management table having the valid flag 33 set acquires the location of the prefetch data to be used. To be searched.

  FIG. 6 shows a specific example of the host designation address acquisition process (S2). The process shown in the figure is a response process when the prefetch data is designated by a file name by a prefetch command supplied from the host computer 6. First, the name of the file that holds the prefetch data is acquired from the prefetch command (S21). Next, the partition ID of the master boot record area (MBR) of the flash memory 2 is read to recognize the file system used (S22). It is determined whether the file system can be recognized according to the used file system (S23). If possible, the file system is analyzed using FAT on the flash memory 2 to obtain the logical address where the file is stored. To do. Similarly, when the file is fragmented, the logical address where the file is stored is acquired. Then, after confirming that the corresponding data exists on the file system (Yes in S25), the memory address of the flash memory is calculated. In a system in which the correspondence between the logical address and the physical address of the flash memory 2 is variable, the calculation is performed with reference to an address conversion table that defines the mutual relationship. The address translation table is stored in a predetermined area in the flash memory 2.

  A user cannot manage logical addresses on the file system. For this reason, by making it possible to specify the file name, it becomes possible to manage the prefetched data of the user.

  When the file is fragmented, the prefetch data management table has the configuration shown in FIG. 3, so that it is necessary to create a prefetch data management table for each fragmented portion where logical addresses are continuous. Even if there are a plurality of prefetch data management tables for one data file, each prefetch data management table has a file name in its file name area 35. Therefore, there is a problem in search processing when responding to an access command. It will not be.

  Since it is assumed that there are a plurality of the same file names on the flash memory 2, it is desirable to save the file names to be saved in the prefetch data management table including the absolute path. Alternatively, since the logical addresses on the file system are different even for the same file name, the file name stored in the prefetch data management table may be stored including the logical address.

  FIG. 7 illustrates a processing form (prefetch data update form) when there is no unused area for storing the prefetch data in the buffer memory 4.

  As a processing mode when there is no unused area for storing the prefetched data in the buffer memory 4, there is an overwriting permission to an area that already holds the prefetched data or an overwriting prohibition to an area that already holds the prefetched data.

  By adopting overwriting prohibition, it is easy to guarantee effective use of frequently read-ahead data. When overwriting prohibition is adopted, if there is no unused area, an error response may be returned to the prefetch command issuer to alert the user. Adopting overwrite permission is convenient for dynamic replacement of prefetched data.

  As a form of overwriting permission, there are full permission to an area that already holds prefetched data, or partial permission to an area with low access frequency. In the case of permitting overwriting all over, the card controller 5 may perform control to permit overwriting to the pre-read data storage area 13 in order from the oldest one by FIFO (first-in first-out).

  When partial permission according to the access frequency is adopted, whether or not the access frequency is low may be determined based on the value of the access frequency area 34 held in the prefetched data management table. For example, when the access count 1 is adopted as the determination criterion, the prefetch data management table having the access count 1 is searched, and the buffer memory address used in the prefetch data management table after the search is used. Alternatively, a buffer memory address managed by a prefetch data management table having a minimum access count obtained by searching an arbitrary plurality of prefetch data management tables may be used.

  The partial permission is advantageous for achieving both dynamic exchangeability of prefetched data and effective utilization of prefetched data that is frequently accessed.

  The prefetch data update form may be set in the card controller 5 by control data or a mode signal. Or you may make it designate each time with a prefetch command.

<Read command response processing>
FIG. 8 illustrates a control procedure for the read command response process. When the card controller 5 receives the read command issued from the host computer 6 (S30), the card controller 5 determines whether or not a pre-read data management table corresponding to the logical address specified by the read command exists (S31). If there is no pre-read data management table for all of the specified logical addresses, the physical sector address of the flash memory corresponding to the read target logical address is calculated (S32), and the data is read from the physical sector address to store the read data in the buffer memory. The data is transferred to the area (S33), and the data transferred to the read data storage area is output to the host computer 6 (S34).

  When it is determined in the process of step S31 that there is a prefetch data management table for the specified logical address, it is determined whether or not all data has been prefetched (S35). In short, it is determined whether or not all of the logical addresses specified by the read command match the logical addresses associated in the prefetch data management table. If the result of the determination is that there is no partial prefetched data, the physical sector address of the flash memory corresponding to the logical address without the prefetched data is calculated (S36), the data is read from the physical sector address and the read data of the buffer memory 4 is read. Transfer to the storage area (S33). For a logical address with partial prefetched data, the access count of the corresponding prefetched data management table is incremented by +1 (S37). In step S33, the data transferred to the read data storage area and the remaining prefetch data in the prefetch data storage area 13 are output to the host computer 6 (S34). If there is prefetch data for all logical addresses, the access count of the prefetch data management table corresponding to the logical address is incremented by +1 (S37), and the corresponding prefetch data in the prefetch data storage area 13 is stored in the host computer 6. (S34).

  In the process of FIG. 8, when pre-read data is not prepared, data transfer to the host computer 6 is performed after the insufficient data is transferred from the flash memory 2 to the buffer memory 4. The preread data may be transferred to the host computer 6 before the missing data is read from the flash memory 2 to the buffer memory 4.

<Write command response processing>
FIG. 9 illustrates a control procedure of the write command response process. When the card controller 5 receives the write command issued from the host computer 6 (S40), the card controller 5 temporarily stores the write data supplied from the host computer 6 in the write data storage area 10 (S41). The card controller 5 calculates the physical sector address on the flash memory 2 corresponding to the logical address specified by the write command (S42), gives the flash write command to the flash memory 2, and instructs the write process to the flash memory 2. (S34). In parallel with the write operation of the flash memory 2, the card controller 5 determines whether or not there is a pre-read data management table related to the write data (S44). If there is valid prefetch data related to the write data, the prefetch data is updated with the write data on the buffer memory 4 (S47), and the contents of the corresponding prefetch data management table are updated (S48). For example, the access count is incremented by +1. After the process of step S48 is completed, or if there is no corresponding prefetch data in the determination of step S44, the process waits for the flash memory writing process started in step S43 to end, and then releases the busy flag by the write command ( S46), the process ends.

  When updating the preread data, it is necessary to update the data in the preread data storage area on the buffer simultaneously with the data on the storage medium. For this reason, it is necessary to always monitor the address at the time of a write request. However, since the update process of the buffer memory 4 is very fast compared to the storage time in the storage medium, no significant performance degradation occurs.

<< Saving the prefetch data management table >>
When the prefetch data management table is operated on a volatile memory such as the work area 12 of the buffer memory 4, the card controller 5 stores the prefetch data management table in the prefetch data management table storage area of the flash memory 2 at a predetermined timing. Evacuate to. The predetermined timing is, for example, when the power is shut off or when waiting for a command after a predetermined period. By storing the pre-read data management table of functioning pre-read data, even if the pre-read data on the buffer memory 4 is lost due to power interruption or the like, it can be reproduced later. The card controller 5 reads the prefetch data management table from the flash memory 2 in response to power-on, and transfers the prefetch data whose location is defined in the read prefetch data management table from the flash memory 2 to the buffer memory 4. Good.

  According to the flash memory card 1 described above, the following operational effects can be obtained.

  [1] Prefetch data can be designated from the host computer 6 to the flash memory card 1 by a prefetch command. Therefore, the data to be prefetched can be determined flexibly so that the effect of shortening the access time by prefetching can be maximized. The read performance of the flash memory card 1 is the bottleneck of the read performance of the flash memory 2 itself, which is a storage medium. The system performance can be improved by increasing the number of processes for outputting the prefetched data.

  [2] The pre-read command can specify pre-read data by either a logical address or a file name. For example, in the prefetch command, the logical address designation field and the file name designation field are different. As shown by the master boot record or FAT (file allocation table), the user can easily understand the logical address. Therefore, the pre-read data can be specified directly by specifying the logical address. Convenient.

  The user of the flash memory card 1 may not be able to grasp the logical address on the flash memory 2 managed by the OS, and the user of the flash memory card 1 can easily grasp the data by the file name. Good operability can be realized.

  [3] As a transfer form of the prefetch data by the card controller 5, a prefetch data management table is first generated in addition to when the prefetch command is executed, and then the prefetch data is transferred to the buffer memory 4 at a predetermined timing. can do. Thereby, the card controller 5 can transfer the prefetch data to the buffer memory 4 in the command waiting state after the execution of the prefetch command is completed. It is possible to prevent the data processing efficiency from being lowered by waiting for processing such as read access by the prefetch processing.

  [4] The prefetch data management table includes an area for holding the file name including the prefetch data, as well as an area for holding the top logical address of the prefetch data, the top memory address of the area for storing the prefetch data, and the number of prefetch data. Have. As a result, when file fragmentation occurs in the file system, one file data is managed by a plurality of divided pre-read data management tables. The pre-read data management table to be searched can be retrieved, and access to required pre-read data on the buffer memory is further accelerated.

  [5] The prefetch data management table has an area 34 for holding the number of times the prefetch data is accessed by the host computer 6, so that the card controller 5 has no unused area for storing the prefetch data in the buffer memory 4. Based on the number of accesses held in the prefetch data management table, a buffer memory address with a low access frequency can be retrieved, and the area of the retrieved buffer memory address can be allocated to a new prefetch data storage area. It is possible to guarantee effective use of prefetched data that is frequently accessed.

  [6] When the card controller 5 operates the prefetch data management table on the buffer memory 4 or the work RAM 26 by saving the prefetch data management table to the prefetch data management table storage area of the flash memory 2 at a predetermined timing. By storing a prefetch data management table of functioning prefetch data, even if prefetch data on the buffer memory is lost due to power interruption or the like, it can be reproduced later.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, although the FAT file system is used as the file system in the above description, other file systems such as NTFS may be used. Although the nonvolatile memory is a flash memory, it may be another semiconductor memory such as a high dielectric memory. Further, the nonvolatile memory is not limited to a semiconductor memory, and may be a recording disk such as a hard disk. The present invention is not limited to a memory card such as a flash memory card, and can also be applied to a hard disk device. At this time, the storage device is not limited to being removable, and may be of a usage form that is fixedly arranged in the mounting system.

  The flash memory is not limited to a stacked gate structure, and may have a split gate structure formed in series without providing a diffusion layer between the selection MOS transistor portion and the memory MOS transistor portion. Further, a memory cell structure that locally accumulates charges in a trap region such as a silicon nitride film may be employed. The semiconductor nonvolatile memory is not limited to the configuration in which the storage information held in one memory cell is 1 bit, and may be a storage format in which 2 or more bits are stored.

  In addition, when the present invention is applied to a memory card, a control circuit such as a card controller may not include a host interface circuit such as IDE, and the memory card is standardized so that the function is borne by the host computer. Is also applicable.

  Further, the logical address of the pre-read data specified by the pre-read command may substantially match the physical address of the nonvolatile memory depending on the configuration of the file system.

1 is a block diagram of a flash memory card that is an example of a storage device according to the present invention. FIG. It is explanatory drawing which shows the detail of the address map of a buffer memory. It is explanatory drawing which illustrates the detail of the structure of the storage area of a flash memory, and the prefetch data management table. It is explanatory drawing which shows the main specifications of a prefetch command. It is a flowchart which illustrates the control procedure of prefetch command response processing. It is a flowchart which shows the specific example of a host designation | designated address acquisition process (S2). It is explanatory drawing which illustrates the processing form (prefetch data update form) when there is no unused area | region which stores prefetch data in a buffer memory. It is a flowchart which illustrates the control procedure of a read command response process. It is a flowchart which illustrates the control procedure of a write command response process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory card 2 Flash memory 4 Buffer memory 5 Card controller 6 Host computer 10 Write data storage area 11 Read data storage area 12 Work area 13 Prefetch data storage area 14 Data section 15 Internal information storage section 16 Prefetch data management table storage section 20 Host Interface circuit 21 Microprocessor 22 Flash controller 33 Buffer controller 25 CPU
26 Work RAM
27 Program memory Ti Prefetched data management table 30 First logical address area 31 First memory address area 32 Sector number area 33 Valid flag area 34 Access count area 35 File name area

Claims (15)

A nonvolatile memory, a buffer memory having a faster access speed than the nonvolatile memory, and a control circuit;
When a prefetch command is input from the outside, the control circuit generates a prefetch data management table in which a logical address of prefetch data designated by the prefetch command and a buffer memory address for storing the prefetch data are associated with each other. Reads data specified by the command from the non-volatile memory and stores it in the buffer memory as pre-read data,
When a read command is input from the outside, when the logical address specified by the read command matches the logical address associated with the prefetch data management table, the corresponding prefetch data is output from the buffer memory. Storage device.   The storage device according to claim 1, wherein the prefetch command designates prefetch data by a logical address.   2. The storage device according to claim 1, wherein the prefetch command designates prefetch data by a file name.   The storage device according to claim 1, wherein the control circuit transfers prefetch data to a buffer memory when a prefetch command is executed.   The storage device according to claim 1, wherein the control circuit transfers the prefetch data to the buffer memory after generating the prefetch data management table.   6. The storage device according to claim 5, wherein the control circuit transfers the prefetch data to the buffer memory in a command waiting state after the execution of the prefetch command is completed.   2. The storage device according to claim 1, wherein the prefetch data management table includes a head logical address of the prefetch data, a head memory address of an area for storing the prefetch data, and an area for holding the number of data of the prefetch data.   7. The storage device according to claim 6, wherein the prefetch data management table has an area for holding a flag indicating validity of corresponding prefetch data.   4. The storage device according to claim 3, wherein the prefetch data management table has an area for holding a file name including prefetch data.   The storage device according to claim 1, wherein the prefetch data management table has an area for holding the number of accesses of prefetch data.   The control circuit searches for a buffer memory address with a low access frequency based on the number of accesses held in the prefetch data management table when there is no unused area for storing the prefetch data in the buffer memory. 11. The storage device according to claim 10, wherein the area is allocated to a storage area for new prefetch data.   2. The storage device according to claim 1, wherein the control circuit saves the prefetch data management table in a prefetch data management table storage area of the nonvolatile memory at a predetermined timing.   The control circuit reads the prefetch data management table from the nonvolatile memory in response to power-on, and transfers the prefetch data whose location is defined by the read prefetch data management table from the nonvolatile memory to the buffer memory. The storage device according to claim 12. A non-volatile memory, a buffer memory having a higher access speed than the non-volatile memory, and a control circuit;
In response to a read command input from the outside, the control circuit refers to a rewritable prefetch data management table that associates a logical address of the prefetch data with a buffer memory address that stores the prefetch data, and the command specifies Determine whether or not the buffer memory holds the data to be read, and if so, output the data read from the buffer memory to the outside, otherwise output the data read from the non-volatile memory to the outside A storage device.   The storage device according to claim 1, wherein the prefetch data management table is provided in the buffer memory.

Images