JP2009080638A - Integrated circuit manufacturing device, its method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an integrated circuit manufacturing device and its method and program, for easily executing the change of wiring connection in manufacturing an integrated circuit by arranging cells configured of the combination of a plurality of logic circuits with prescribed array configurations, and integrating them into multi-layer wiring. <P>SOLUTION: This integrated circuit manufacturing device is provided with: a replacement part for replacing a first sequential circuit in which an initial logical value is predicted to change among a plurality of logic circuits with a second sequential circuit; a wiring inhibition region setting part by which after arranging the second sequential circuit replaced by the replacing part, a wiring inhibition region is set in any one wiring layer among a plurality of wiring layers whose wiring can be connected to the prescribed terminal of the sequential circuit; and a wiring part for wiring-connecting the prescribed terminal of the sequential circuit in the wiring layer of the wiring inhibition region in changing the initial logical value of the replaced second sequential circuit in the middle of the setting of an integrated circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit manufacturing apparatus for manufacturing an integrated circuit in which a plurality of logic circuit groups are arranged in a predetermined arrangement form based on circuit information to form a multilayer wiring.

  Cell-based layout production is widely performed in which integrated circuits such as LSI (Large Scale Integration) and the like are arranged in a matrix in a plurality of logic circuits, for example, to form a multilayer wiring. Yes.

On the other hand, for example, in the imaging apparatus 400 illustrated in FIG. 11, the register 440 performs communication with the outside of the imaging apparatus 400 and timing of the timing generator 410, the pixel unit 420, the image processing unit 430, and the like. In such an imaging apparatus 400, the register of the analog characteristic value is changed according to the characteristic evaluation result and the usage situation.
JP 9-129738 A

Cell-based integrated circuit layout fabrication does not assume the use of registers. Therefore, in the imaging device 400 or the like that employs the register 440 described above, the initial logical value of the asynchronous register 440 cannot be easily changed during layout creation. As a result, when the initial logical value of the register 440 is not preferable during layout production, it is difficult to correct the value to reduce register communication.
Further, the cited document 1 does not disclose a process around the wiring to be pulled up to the uppermost layer, and there is a possibility that the layout is not surely produced when the degree of wiring congestion is high.
In addition, a circuit change by a focused ion beam (FIB) has a disadvantage that it cannot cope with a change in wiring connection other than the uppermost wiring layer as well as a layout change and a mask change.

  The present invention relates to an integrated circuit manufacturing apparatus and method for easily changing a wiring connection in manufacturing an integrated circuit in which cells each having a set of a plurality of logic circuits are arranged in a predetermined arrangement form to form a multilayer wiring. To provide a program.

  An integrated circuit manufacturing apparatus according to a first aspect of the present invention is an integrated circuit manufacturing apparatus that arranges cells having a set of a plurality of logic circuits based on circuit information in a predetermined arrangement form, and manufactures an integrated circuit that forms a multilayer wiring. A replacement unit that replaces the first sequential circuit, in which the change of the initial logical value is predicted, among the plurality of logic circuits, with a second sequential circuit; and the second sequence replaced by the replacement unit. After the sequential circuit is arranged, a wiring prohibited area setting unit that sets a wiring prohibited area in any one of the plurality of wiring layers to which a predetermined terminal of the sequential circuit can be connected by wiring, and the replaced second above A wiring portion for wiring-connecting the predetermined terminal of the sequential circuit in a wiring layer of the wiring-prohibited region when the initial logical value of the sequential circuit is changed.

  Preferably, the replacement unit replaces the first sequential circuit with the second sequential circuit having a set terminal for asynchronously setting a predetermined logical value and a reset terminal for resetting the logical value.

  Preferably, the replacement unit selects the cell having the same driving capability as that of the second sequential circuit.

  Preferably, the wiring unit reversely connects the wirings of the set terminal and the reset terminal of the second sequential circuit only when changing the initial logical value.

  Preferably, when the cell includes a plurality of the first sequential circuits, the wiring prohibition region setting unit is configured to prohibit the wiring by adjoining the second sequential circuits each replaced by the replacement unit. Set the area.

  Preferably, in the case where the cell includes a plurality of the first sequential circuits, the wiring unit includes an input terminal and an output terminal of the second sequential circuit, each of which is replaced by the replacement unit. Replace the wires and connect them.

  Preferably, the wiring prohibition area setting unit sets the wiring prohibition area only for the first sequential circuit having a high priority.

  Preferably, the wiring prohibited area setting unit sets the wiring prohibited area even when the cell does not include the second sequential circuit.

  Preferably, the first and second sequential circuits include registers.

  Preferably, the first sequential circuit includes a register, and the second sequential circuit includes a flip-flop.

  An integrated circuit manufacturing apparatus according to a second aspect of the present invention is an integrated circuit manufacturing apparatus that manufactures an integrated circuit in which a plurality of logic circuits are grouped in a predetermined arrangement based on circuit information and arranged in a multilayered manner. And an arithmetic unit that performs an operation based on the circuit information, and at least one storage unit that stores processing data of the arithmetic unit, wherein the arithmetic unit includes the plurality of logic circuits, After the arrangement of the replacement unit that replaces the first sequential circuit whose change in the initial logical value is predicted with the second sequential circuit, and the second sequential circuit replaced by the replacement unit, the predetermined terminal of the sequential circuit A wiring prohibited area setting unit that sets a wiring prohibited area in any one of the plurality of wiring layers that can be connected by wiring, and the initial logical value of the replaced second sequential circuit is changed The predetermined end of the sequential circuit. The and a wiring section for wiring connection with the wiring layer of the wiring prohibited area.

  An integrated circuit manufacturing method according to a third aspect of the present invention is an integrated circuit manufacturing method for manufacturing an integrated circuit in which cells each having a plurality of logic circuits are arranged in a predetermined arrangement form based on circuit information to form a multilayer wiring. A step of replacing a first sequential circuit in which a change of an initial logical value is predicted among the plurality of logic circuits with a second sequential circuit, and the second sequential circuit replaced by the step After the arrangement, the step of setting a wiring prohibition region in any one of the plurality of wiring layers to which the predetermined terminal of the sequential circuit can be connected, and the initial of the replaced second sequential circuit Connecting the predetermined terminal of the sequential circuit in the wiring layer of the wiring prohibition region when changing the logical value.

  A program according to a fourth aspect of the present invention is a process for producing an integrated circuit in which a plurality of logic circuit sets are arranged in a predetermined arrangement form based on circuit information, and a multilayer wiring is formed. Among the logic circuits, the process of replacing the first sequential circuit in which the change of the initial logic value is predicted with the second sequential circuit, and the placement of the second sequential circuit replaced by the replacement unit, A process of setting a wiring prohibited area in any one of the plurality of wiring layers connectable to a predetermined terminal of the sequential circuit, and the initial logical value of the replaced second sequential circuit is changed. In this case, the computer is caused to execute a process of wiring-connecting the predetermined terminal of the sequential circuit in the wiring layer of the wiring-prohibited area.

  According to the present invention, the first sequential circuit whose change in the initial logical value is predicted is replaced with the second sequential circuit, and after the replacement of the replaced second sequential circuit, the predetermined terminal of the sequential circuit is wired When a wiring prohibition area is provided in any one of the connectable wiring layers and the initial logical value of the replaced second sequential circuit is changed, the predetermined terminals of the sequential circuit are prohibited from wiring. Connect the wiring in the wiring layer of the area.

  According to the present invention, an integrated circuit manufacturing apparatus and method for easily changing wiring connection in manufacturing an integrated circuit in which a plurality of logic circuit sets are arranged in a predetermined arrangement form to form a multilayer wiring As well as programs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
An embodiment of an integrated circuit manufacturing method and an integrated circuit manufacturing apparatus employing a program according to the present embodiment will be described with reference to FIGS.
FIG. 1 is a schematic diagram showing a configuration example of an integrated circuit manufacturing apparatus according to this embodiment.
FIG. 2 is a block diagram showing a configuration example of the integrated circuit manufacturing apparatus shown in FIG.

  As illustrated in FIG. 1, the integrated circuit manufacturing apparatus 1 includes an arithmetic device 10, an operation unit 11, and a display unit 12.

  The integrated circuit manufacturing apparatus 1 arranges cells having a plurality of logic circuits as a set based on the circuit information 2 in a predetermined arrangement form, and manufactures an integrated circuit that forms a multilayer wiring. Then, the integrated circuit manufacturing apparatus 1 outputs the result as layout data 3.

  The circuit information 2 is set by a user or the like, and includes, for example, information RTL (Register Transfer Level) related to a logic level expressed by a register, a combinational circuit, or the like, information related to a constraint condition specified by the user when creating a layout, and the like.

  The layout data 3 is data output from the integrated circuit manufacturing apparatus 1.

  The operation unit 11 includes an input device such as a keyboard and a pointing device such as a mouse, and inputs input information such as circuit information 2 by the user to the arithmetic device 10. The configuration of the operation unit 11 is not particularly limited.

  The display unit 12 is composed of a CRT, a liquid crystal display, or the like, and displays various data output from the arithmetic unit 10, such as circuit information 2 and layout data 3. The configuration of the display unit 12 is not particularly limited.

Next, the configuration of the arithmetic unit 10 in FIG. 1 will be mainly described with reference to FIG. The arithmetic device 10 includes a CPU 100, a hard disk (HD) 110, a ROM 120, a RAM 130, and a control unit 140.
Further, the CPU 100 includes a synthesis unit 1001, a replacement unit 1002, an arrangement unit 1003, a wiring prohibited area setting unit 1004, and a wiring unit 1005.
In addition, the hard disk 110 includes a synthesis storage unit 1101, a replacement storage unit 1102, an arrangement storage unit 1103, a wiring prohibited area setting storage unit 1104, and a wiring storage unit 1105.
The CPU 100 corresponds to the calculation unit of the present invention, and the hard disk 110 corresponds to one of the storage units of the present invention.

The CPU 100 performs calculations based on the circuit information 2 and records the calculation results and the like in a predetermined area while sequentially accessing the hard disk 110. Details of each component of the CPU 100 will be described later.
Note that the processing content executed by the CPU 100 can execute various numerical calculations and information processing in addition to those described above, and the processing content is not particularly limited.

  The hard disk 110 is, for example, a magnetic disk device, and records circuit information 2, layout data 3, calculation results output from the CPU 100, programs, and various other data. The data recording period is not particularly limited and can be stored for a long time. Details of each component of the hard disk 110 will be described later.

  The ROM 120 is, for example, a read-only non-volatile semiconductor memory, in which data such as programs necessary for processing executed by the CPU 100 is recorded in advance, and necessary data is received from the CPU 100 and the like under the control of the control unit 140. Read out.

  The RAM 130 is, for example, a readable / writable DRAM (Dynamic Random Access Memory), and temporarily records data while accessing the CPU 100 and the hard disk 110 under the control of the control unit 140.

  The control unit 140 controls the overall integrated circuit manufacturing apparatus 1 including the operation unit 11, the display unit 12, the CPU 100, the hard disk 110, the ROM 120, and the RAM 130.

  Hereinafter, each component of the CPU 100 will be described in detail. FIG. 3 is a diagram for explaining an example of each component included in the arithmetic unit according to the present embodiment. Hereinafter, when each component is described, FIG. 3 will be referred to as appropriate.

“200” in FIG. 3 is a register having an asynchronous reset terminal 201, for example, and has an initial logical value of 0. Note that the register 200 resets the initial logical value to 0 when a low level (L level) signal is supplied to the reset signal line RSTL connected to the reset terminal 201.
“200a” in FIG. 3 is a register having an asynchronous set terminal 202, for example, and has an initial logical value of 1. Note that the register 200a sets the initial logical value to 1 when an L level signal is supplied to the set signal line SETL connected to the set terminal 202.
“210” in FIG. 3 is a flip-flop having an asynchronous set terminal 212 and reset terminal 211, for example, and has an initial logical value of 0. Note that the flip-flop 210 resets the initial logic value to 0 when an L level signal is supplied to the reset signal line RSTL connected to the reset terminal 211.
Further, “210a” in FIG. 3 is a flip-flop having the same configuration as that of the flip-flop 210, but has an initial logical value of 1. The flip-flop 210a sets the initial logical value to 0 when an L level signal is supplied to the set signal line SETL connected to the set terminal 212.

In the present embodiment, the registers 200 and 200a described above correspond to the first sequential circuit according to the present invention, and the flip-flops 210 and 210a correspond to the second sequential circuit, respectively.
The flip-flops 210 and 210a may be registers having asynchronous set terminals and reset terminals.
The registers 200 and 200a may be flip-flops each having an asynchronous reset terminal and set terminal.
The first and second sequential circuits according to the present invention are not particularly limited as long as the first and second sequential circuits can store a logical value state and have sequential set terminals and reset terminals.

The synthesizing unit 1001 performs logic synthesis based on a net list including circuit information 2 and cell connection relationships.
Specifically, in the logic synthesis of the register, the synthesis unit 1001 selects the register 200 illustrated in FIG. 3 when the initial logical value of the register is 0, and selects the register 200a when the initial logical value of the register is 1. To do.
Further, the synthesis unit 1001 may not select the flip-flop 210 shown in FIG.

Therefore, the present embodiment has a replacement unit 1002, and the replacement unit 1002 is a flip-flop having an asynchronous set terminal and a reset terminal as a register in which a change in the initial logical value is predicted, particularly for a sequential circuit among a plurality of logic circuits. Replace with a group.
Here, “the change of the initial logical value is predicted” means that the initial logical value of the register (register 200 or 200a in FIG. 3) may be changed by the user during or after the production of the layout, for example. The initial logical value is not necessarily changed.

Specifically, as shown in FIG. 3, the replacement unit 1002 has an initial logical value of 0 for the register 200 having an initial logical value of 0, depending on the netlist and constraint conditions after the synthesis unit 1001 performs logical synthesis. In the flip-flop 210, the register 200a whose initial logical value is 1 is replaced with the flip-flop 210a whose initial logical value is 1.
The constraint condition used in the replacement unit 1002 here includes designation of a cell to be replaced in the register 200 (200a).
Replacement unit 1002 connects constant 1-b1 to set terminal 212 of flip-flop 210 after replacement, and constant 1-b1 to reset terminal 211 of flip-flop 210a after replacement. The value of the constant 1-b1 is, for example, the power supply voltage VDD and is not particularly limited.

  Further, the replacement unit 1002 selects cells having the same driving capability of the flip-flop 210 (210a) to be replaced in order to minimize the timing change after the logic synthesis by the synthesis unit 1001.

When the user changes the initial logical value of the replaced flip-flop 210 from 0 to 1 during or after the creation of the layout, the replacement unit 1002 replaces the flip-flop 210 whose initial logical value is 0 with an initial logical value of 1. Replace with flip-flop 210a.
When the initial logical value of the replaced flip-flop 210a is changed from 1 to 0, the replacement unit 1002 replaces the flip-flop 210a having the initial logical value of 1 with the flip-flop 210 having the initial logical value of 0.

  The placement unit 1003 suitably places the flip-flop 210 (210a) replaced by the replacement unit 1002 on a predetermined cell.

When the change of the initial logical value of the register 200 (200a) is predicted later according to the restriction condition by the user (see the circuit information 2 in FIG. 1), the wiring prohibited area setting unit 1004 A wiring prohibited area is set in any one of the plurality of wiring layers to which the reset terminal 211 and the set terminal 212 of 210 (210a) can be connected by wiring.
Here, the constraint condition regarding the wiring prohibited area includes designation of a wiring layer to be prohibited from wiring and designation of a cell to be prohibited from wiring in an upper layer.
The wiring prohibited area is set for an area of about one cell.

The wiring prohibited area will be described with reference to FIGS.
FIG. 4 is an inclined view of an example of a multi-layered layout for explaining the wiring prohibited area according to the present embodiment, and FIG. 5 is a multi-layered layout for explaining the wiring prohibited area. It is sectional drawing of an example.
5A and 5B are diagrams in which the layout layers are combined, and FIG. 5C is a diagram illustrating only the top layer of the layout. 4 and 5 will be appropriately referred to in the following description.

The layout shown in FIG. 4 includes an underlayer 300, an intermediate layer 310, and an uppermost layer 320, and wiring is provided in the intermediate layer 310 and the uppermost layer 320.
Each layer shown is an area of about one cell. In the base layer 300, flip-flops 210 (210a) replaced by the replacement unit 1002 are arranged by the arrangement unit 1003 as shown in FIG.
In the present embodiment, the layout is composed of three layers, but may be four layers, for example, and is not particularly limited.

The wiring prohibited area setting unit 1004 sets the wiring prohibited area ARE in the intermediate layer 310 shown in FIG. 4A or the uppermost layer 320 shown in FIG. Further, FIG. 5A shows the wiring prohibited area ARE provided by the wiring prohibited area setting unit 1004.
Note that the layer in which the wiring prohibited area ARE is set is preferably set by the user.

When changing the initial logical value of the replaced flip-flop, the wiring unit 1005 wire-connects the set terminal and the reset terminal of the flip-flop in the wiring layer of the wiring prohibited area.
Specifically, as illustrated in FIG. 3, when the initial logical value of the flip-flop 210 replaced by the replacement unit 1002 is changed from 0 to 1, the wiring unit 1005 is the flip-flop having the replaced initial logical value of 1. The wiring of the reset terminal 211 and the set terminal 212 is reversed and connected to any of the layers (the intermediate layer 310 or the uppermost layer 320 in FIG. 4) in which the wiring prohibition area ARE is provided. .
On the other hand, when the initial logical value of the flip-flop 210a replaced by the replacement unit 1002 is changed from 1 to 0, the wiring unit 1005 performs the wiring prohibited area ARE for the flip-flop 210 with the replaced initial logical value 0. The wiring of the reset terminal 211 and the set terminal 212 is reversed and connected in any one of the layers provided with.

  For the sake of explanation, it is assumed that the wiring unit 1005 changes the initial logical value of the flip-flop 210 from 0 to 1 and that the wiring prohibited area ARE is provided in the intermediate layer 310 of FIG.

As shown in FIG. 4A, the wiring unit 1005 reverses the wiring between the reset terminal 211 and the set terminal 212 of the flip-flop 210a arranged in the base layer 300 of the cell, and the wiring prohibited area of the intermediate layer 310 Wire connection is made at ARE.
Here, “wiring connection” means that the reset terminal 211 and the set terminal 212 are connected by the wiring 311 on the intermediate layer 310 in FIG.
Of course, the same applies to the case where the flip-flop disposed in the base layer 300 of the cell is the flip-flop 210 having an initial logical value of 0.

  FIG. 6 is a diagram illustrating an example of the wiring connection performed by the wiring unit 1005 according to the present embodiment in the intermediate layer 310 of FIG. 6A is a cross-sectional view of a layout when the initial logical value of the flip-flop 210 is not changed, and FIG. 6B is a cross-sectional view of the layout when the initial logical value is changed.

When the initial logical value of the flip-flop 210 is changed, the wiring unit 1005 changes the wirings 311a and 311b illustrated in FIG. 6A to the wirings 311c and 311d illustrated in FIG. .
On the other hand, when the wiring prohibition area ARE is provided in the uppermost layer 320, as shown in FIG. 4B, the wiring portion 1005 is provided with a contact hole 312 in the intermediate layer 310, and a reset terminal 211 and a set terminal 212. Are pulled up to the uppermost layer 320 and connected to the wiring in reverse.

Finally, the wiring unit 1005 is connected by wiring as shown in FIGS. As shown in FIGS. 5B and 5C, after the wiring connection by the wiring unit 1005, wiring relating to other logic circuits (other than the flip-flop 210) is not provided in the wiring prohibited area ARE, and these other logics are not provided. The wiring of the circuit is preferably wired and bypassed the wiring prohibited area ARE.
Note that the wiring connection by the wiring unit 1005 is made to an area of about one cell.

  Even when the wiring unit 1005 changes the initial logical value of the flip-flop 210a from 1 to 0, the wiring of the reset terminal 211 and the set terminal 212 is reversely connected in the layer where the wiring prohibition area ARE is provided. That is no different.

Next, each component of the hard disk 110 illustrated in FIG. 2 will be described.
The synthesis storage unit 1101 appropriately stores the processing result of the synthesis unit 1001 of the CPU 100 under the control of the control unit 140.
Regarding the hard disk 110, similarly to the components other than the composite storage unit 1101, the replacement storage unit 1102 displays the processing result of the replacement unit 1002 and the placement storage unit 1103 processes the processing result of the placement unit 1003 according to the control of the control unit 140. The wiring prohibition area setting storage unit 1104 appropriately records the processing result of the wiring prohibition area setting unit 1004, and the wiring storage unit 1105 appropriately records the processing result of the wiring part 1005.

  The operation of the integrated circuit manufacturing apparatus 1 will be described below. FIG. 7 is a flowchart showing an example of the operation of the integrated circuit manufacturing apparatus according to this embodiment.

(Step ST1)
Logic synthesis is performed based on a net list including circuit information 2 and cell connection relationships. Specifically, in the logic synthesis of the register, the synthesis unit 1001 selects the register 200 illustrated in FIG. 3 when the initial logical value of the register is 0, and selects the register 200a when the initial logical value of the register is 1. To do.

(Step ST2)
The replacement unit 1002 replaces a register whose initial logical value is predicted to be changed to a flip-flop having an asynchronous set terminal and reset terminal.
In step ST1 described above, the replacement unit 1002 causes the register 200 having an initial logical value of 0 to be replaced with the flip-flop 210 having an initial logical value of 0 by the netlist and constraint conditions after the synthesis unit 1001 performs logical synthesis. The registers 200a whose initial logical value is 1 are replaced with flip-flops 210a whose initial logical value is 1, respectively.
Replacement unit 1002 connects constant 1-b1 to set terminal 212 of flip-flop 210 after replacement, and constant 1-b1 to reset terminal 211 of flip-flop 210a after replacement.
Furthermore, the replacement unit 1002 selects a cell having the same driving capability of the flip-flop 210 (210a) to be replaced in order to minimize the timing change after the logic synthesis by the synthesis unit 1001 (see FIG. 3).

(Step ST3)
The placement unit 1003 suitably places the flip-flop 210 (210a) replaced by the replacement unit 1002 on a predetermined cell (see FIG. 3).

(Step ST4)
When the change of the initial logical value of the register 200 (200a) is predicted due to the restriction condition by the user, the wiring prohibited area setting unit 1004 resets the reset terminal 211 and the set terminal 212 of the flip-flop 210 (210a) replaced by the replacement unit 1002. A wiring prohibition area ARE is set in any one of the plurality of wiring layers connectable to each other. Here, the constraint condition regarding the wiring prohibition area ARE includes designation of a wiring layer for which wiring is prohibited and designation of a cell for which wiring prohibition is performed in an upper layer (see FIGS. 3 and 4).

(Step ST5)
The wiring unit 1005 wire-connects the set terminal and the reset terminal of the flip-flop in the wiring layer of the wiring prohibition region when changing the initial logical value of the replaced flip-flop during the setting of the layout.

(Step ST6)
When the initial logical value of the flip-flop 210 (210a) replaced in step ST2 is changed from 0 (1) to 1 (0) (Yes), the replacement unit 1002 is a flip-flop whose initial logical value is 0 (1). The flip-flop 210a (210) having the initial logical value of 1 (0) is replaced with the flip-flop 210 (210a), and the process proceeds to step ST7.
On the other hand, when the initial logical value of the flip-flop 210 (210a) replaced in step ST2 is not changed (No), no processing is performed on the flip-flop 210 (210a), and the integrated circuit manufacturing apparatus 1 The process ends.

(Step ST7)
The wiring unit 1005 has one of the layers (the intermediate layer 310 or the uppermost layer in FIG. 4) in which the wiring prohibited area ARE is provided for the flip-flop 210a (210) whose initial logical value is 1 (0). 320), the wiring between the reset terminal 211 and the set terminal 212 is reversed and connected.

As described above, in the present embodiment, with respect to the register 200 (200a) in which the change of the initial logical value is predicted later, the replacement unit 1002 converts the register into the flip-flop 210 (210a) having the asynchronous set terminal 212 and reset terminal 211. The wiring prohibited area setting unit 1004 suitably sets the wiring prohibited area ARE.
Therefore, as shown in FIGS. 4, 5B, and 5C, wirings 311 and 321 relating to logic circuits other than the flip-flop 210 (210a) are not formed in the wiring prohibited area ARE.
When the user later changes the initial logical value of the flip-flop 210 (210a), the wiring unit 1005 wire-connects the flip-flop 210 (210a) in the wiring prohibited area ARE.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described with reference to FIGS.
FIG. 8 is a diagram illustrating an example of a wiring prohibited region when a plurality of first sequential circuits according to the present invention are arranged on a cell.
FIG. 9 is a diagram illustrating an example of a wiring portion when the first sequential circuit according to the present invention is multi-bit.
FIG. 10 is a diagram illustrating an example of a wiring prohibited area when the first sequential circuit according to the present invention is multi-bit.

  In the present embodiment, the cell includes a plurality of registers 200 (200a), each of which is replaced with a flip-flop 210 (210a) by a replacement unit 1002, and is a multi-bit case.

  In the following description, the four flip-flops 210-1 to 210-4 whose initial logical values are 0 replaced by the replacement unit 1002 will be described as an example. The flip-flops 210-1 to 210-4 each have an input terminal 213 to which data (logical value 0 or 1) is input and an output terminal 214.

In this embodiment, the user makes a multi-bit declaration in advance in the circuit information 2 in order to recognize that the integrated circuit manufacturing apparatus 1 handles a multi-bit register.
As illustrated in FIG. 8A, the replacement unit 1002 replaces four registers having an initial logical value of 0 with flip-flops 210-1 to 210-4 having an initial logical value of 0, respectively.
At this time, the replacement unit 1002 connects the constant 4-b 1001 to each set terminal 212.
Then, the flip-flops 210-1 to 210-4 in which the arrangement unit 1003 is replaced are arranged adjacently, for example, on one cell.
Thereafter, the wiring prohibited area setting unit 1004 sets the wiring prohibited area ARE for the flip-flops 210-1 to 210-4 arranged adjacent to each other.
In which layer the wiring prohibition area ARE is provided is preferably set by the user, but in this embodiment, the wiring prohibition area ARE is provided in the intermediate layer 310 (see FIG. 4A).

As shown in FIG. 8B, the wiring of logic circuits other than the flip-flops 210-1 to 210-4 (for example, the wirings 311 and 321) is the wiring prohibited area ARE in which the wiring part 1005 is provided in the intermediate layer 310. Make a wiring connection bypassing.
The wirings 313 to 316 of the flip-flops 210-1 to 210-4 illustrated in FIG. 9A are wired by the wiring unit 1005 as illustrated in FIG. 10A when the initial logical value is changed. Wire connection is made in the prohibited area ARE.

In the present embodiment, the wiring portion 1005 can be connected to each other by exchanging wirings between the input terminals 213 of the flip-flops and between the output terminals 214.
As shown in FIG. 9B, for example, the wirings of the input terminal 213 of the flip-flop 210-1 and the input terminal 213 of the flip-flop 210-2 are exchanged and connected. Similarly, the output terminals 214 are connected by exchanging their wirings.
The wiring unit 1005 wire-connects the flip-flops 210-1 to 210-4 in the wiring prohibited area ARE as shown in FIG.
In the above example, the wiring connection between the flip-flops 210-1 and 210-2 has been described. However, the flip-flops 210-3 and 210-4 or other combinations may be used.

  In the present embodiment, when a multi-bit register is handled, the user makes a multi-bit declaration in the circuit information 2. However, even in a combination of registers (flip-flops) that are not multi-bit declared as the same register, the circuit information 2 Multi-bit wiring prohibition can be specified by adding restrictions or the like.

As another embodiment, the wiring prohibited area setting unit 1004 can set the wiring prohibited area ARE only for the register having a high priority.
Thereby, it can be set so that the wiring prohibition area ARE is not provided only for a part of the flip-flop 210 (210a) replaced by the replacement unit 1002. As a result, the wiring unit 1005 can execute wiring connection without bypassing the wiring prohibited area ARE, and can efficiently secure the wiring area even when the wiring congestion degree is high.

As another embodiment, the wiring prohibited area setting unit 1004 can set the wiring prohibited area ARE even in a cell that does not include the register 200 (200a).
As a result, the logic circuit can be changed only by modifying the wiring layer even at the end of the layout production.

In another embodiment, for example, in an integrated circuit having substantially the same digital unit and different analog characteristics, such as an imaging device, or in a small number of other types of integrated circuits having a small circuit difference, the wiring unit 1005 has a part of wiring. Only the layer can be suitably changed.
This makes it possible to manufacture and manufacture different integrated circuits while the other layers are common.

  According to the present invention, even when the initial logical value of a register or the like is changed during or after the layout is created, by setting a wiring prohibited area in any wiring layer. A region for correcting wiring such as a register is secured, and wiring can be easily and reliably corrected even in an integrated circuit having a high wiring congestion degree.

  When the present invention is not adopted, it is difficult to change the initial logical value only by changing the wiring for a flip-flop having only an asynchronous reset terminal, for example, during or after the production of the layout. According to the invention, it is easy to change the initial logical values of registers and the like during the production of the layout.

Further, according to the present invention, the wiring can be corrected even in a lower layer where it is difficult to change the wiring by FIB.
Further, if the switching of the terminals on the cell is made, there is an advantage that the influence of the timing on the wiring correction is negligibly small.

  As described above, the present invention is particularly effective for a cell-based logic circuit, and the same effect can be obtained even when wiring is modified across a plurality of cells by devising the cell arrangement.

An example of the use of a register is an image pickup apparatus. However, if the present invention is applied to such an image pickup apparatus or the like, there is an advantage that an analog characteristic value can be changed even before mask creation.
For this reason, it is easy to adapt to a product in which the analog characteristics are changed with the base layer as it is, or a product of a small amount of other varieties, etc. only by preparing a mask whose wiring is changed so as to change the analog characteristics.

  The method described in detail above can be configured as a program corresponding to the above procedure and executed by a computer such as a CPU. Further, such a program can be configured to be accessed by a recording medium such as a semiconductor memory, a magnetic disk, an optical disk, a floppy (registered trademark) disk, or a computer in which the recording medium is set, and to execute the program.

It is the schematic which shows the example of 1 structure of the integrated circuit manufacturing apparatus concerning this embodiment. FIG. 2 is a block diagram illustrating a configuration example of an integrated circuit manufacturing apparatus illustrated in FIG. 1. It is a figure for demonstrating the synthetic | combination part which concerns on this embodiment. It is an inclined view of an example of a layout in a multilayer wiring for explaining a wiring prohibited area according to the present embodiment. It is sectional drawing of an example of the layout made into the multilayer wiring for demonstrating the wiring prohibition area | region which concerns on this embodiment. It is a figure which shows an example of the wiring connection which the wiring part which concerns on this embodiment performed in the intermediate | middle layer of FIG. It is a flowchart which shows an example of operation | movement of the integrated circuit manufacturing apparatus which concerns on this embodiment. It is an example for demonstrating the wiring prohibition area | region in case the 1st sequential circuit which concerns on this invention is multiply arranged on the cell. It is a figure for demonstrating operation | movement of the wiring part in case the 1st sequential circuit based on this invention is multi-bit. It is an example for demonstrating the wiring prohibition area | region in case the 1st sequential circuit which concerns on this invention is multi-bit. It is a figure showing an example of 1 composition of an imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Integrated circuit manufacturing apparatus, 2 ... Circuit information, 3 ... Layout data, 10 ... Arithmetic unit, 11 ... Operation part, 12 ... Display part, 100 ... CPU, 110 ... Hard disk (HD), 120 ... ROM, 130 ... RAM , 140 ... control unit, 1001 ... synthesis unit, 1002 ... replacement unit, 1003 ... placement unit, 1004 ... wiring prohibited area setting unit, 1005 ... wiring unit, 1101 ... synthesis storage unit, 1102 ... replacement storage unit, 1103 ... placement memory , 1104... Wiring prohibition area setting storage unit, 1105... Wiring storage unit, 200, 200a register, 201, 211... Reset terminal, 202, 212... Set terminal, 210, 210a. Output terminal 300 ... underlying layer 310 ... intermediate layer 311 311a-311c, 313-316 ... wiring 312 Contact hole, 320 ... the top layer, ARE ... wiring prohibited area.

Claims (13)

An integrated circuit manufacturing apparatus for manufacturing an integrated circuit for arranging a plurality of logic circuits based on circuit information in a predetermined arrangement form and forming a multilayer wiring,
A replacement unit that replaces the first sequential circuit, of which the initial logical value is predicted to be changed, with the second sequential circuit among the plurality of logic circuits;
After the placement of the second sequential circuit replaced by the replacement unit, wiring prohibition for setting a wiring prohibition region in any one of the plurality of wiring layers to which a predetermined terminal of the sequential circuit can be connected by wiring An area setting section;
An integrated circuit manufacturing apparatus comprising: a wiring unit that wire-connects the predetermined terminal of the sequential circuit in a wiring layer of the wiring-prohibited region when the initial logical value of the replaced second sequential circuit is changed. The replacement part is
The integrated circuit manufacturing apparatus according to claim 1, wherein the first sequential circuit is replaced with the second sequential circuit having a set terminal for asynchronously setting a predetermined logical value and a reset terminal for resetting the logical value. The replacement part is
The integrated circuit manufacturing apparatus according to claim 2, wherein the second sequential circuit has the same driving capability as that of the second sequential circuit. The wiring part is
2. The integrated circuit manufacturing apparatus according to claim 1, wherein only when the initial logical value is changed, wirings of the set terminal and the reset terminal of the second sequential circuit are reversely connected. The wiring prohibition area setting section
2. The integrated circuit fabrication according to claim 1, wherein when the cell includes a plurality of the first sequential circuits, the wiring prohibited region is set by adjoining the second sequential circuits, each replaced by the replacement unit. apparatus. The wiring part is
When the cell includes a plurality of the first sequential circuits, the respective wirings are exchanged and connected between the input terminals and between the output terminals of the second sequential circuit each replaced by the replacement unit. The integrated circuit manufacturing apparatus according to claim 1. The wiring prohibition area setting section
The integrated circuit manufacturing apparatus according to claim 1, wherein the wiring prohibition region is set only for the first sequential circuit having a high priority. The wiring prohibition area setting section
The integrated circuit manufacturing apparatus according to claim 1, wherein the wiring prohibited area is set even when the cell does not include the second sequential circuit. The integrated circuit manufacturing apparatus according to claim 1, wherein the first and second sequential circuits include a register. The first sequential circuit includes a register,
The integrated circuit manufacturing apparatus according to claim 1, wherein the second sequential circuit includes a flip-flop. An integrated circuit manufacturing apparatus for manufacturing an integrated circuit for arranging a plurality of logic circuits based on circuit information in a predetermined arrangement form and forming a multilayer wiring,
An arithmetic unit that performs an operation based on the circuit information;
At least one storage unit for storing processing data of the arithmetic unit;
Have
The arithmetic unit is
A replacement unit that replaces the first sequential circuit, of which the initial logical value is predicted to be changed, with the second sequential circuit among the plurality of logic circuits;
After the placement of the second sequential circuit replaced by the replacement unit, wiring prohibition for setting a wiring prohibition region in any one of the plurality of wiring layers to which a predetermined terminal of the sequential circuit can be connected by wiring An area setting section;
An integrated circuit manufacturing apparatus, comprising: a wiring unit that wire-connects the predetermined terminal of the sequential circuit in a wiring layer of the wiring-prohibited region when changing the initial logical value of the replaced second sequential circuit. An integrated circuit manufacturing method for manufacturing an integrated circuit in which cells having a plurality of logic circuits set based on circuit information are arranged in a predetermined arrangement form to form a multilayer wiring,
Replacing the first sequential circuit, of which the initial logical value is predicted to be changed, among the plurality of logic circuits, with a second sequential circuit;
After the placement of the second sequential circuit replaced by the step, a step of setting a wiring prohibited area in any one of the plurality of wiring layers to which a predetermined terminal of the sequential circuit can be wire-connected;
Connecting the predetermined terminal of the sequential circuit with a wiring layer in the wiring-prohibited region when changing the initial logical value of the replaced second sequential circuit. A process for producing an integrated circuit in which cells having a plurality of logic circuits set based on circuit information are arranged in a predetermined arrangement form to form a multilayer wiring,
A process of replacing the first sequential circuit, in which the initial logical value is predicted to be changed, among the plurality of logic circuits, with a second sequential circuit;
After setting the second sequential circuit replaced by the replacement unit, a process of setting a wiring prohibited area in any one of the plurality of wiring layers to which a predetermined terminal of the sequential circuit can be connected by wiring; ,
When changing the initial logical value of the replaced second sequential circuit, the program causes the computer to execute a process of wiring connecting the predetermined terminal of the sequential circuit with a wiring layer in the wiring prohibited area.

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