JP2009077538A - Signal processing circuit for step-up type dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processing circuit for a step-up type DC-DC converter improving switching efficiency in a step-up-down operating mode by using the same switching frequency even in all operating modes of a step-up operation, a step-down operation and the step-up-down operations. <P>SOLUTION: The signal processing circuit is composed of a voltage-level shift appliance 11 generating a first comparison voltage and a second comparison voltage from an error voltage and a waveform generator 12 generating a first waveform signal and a second waveform signal whose phase is an inverted phase of the first waveform signal. The signal processing circuit is further composed of a plurality of comparators 21 to 24 comparing the first and second waveform signals and the first and second comparison voltages respectively and outputting comparison signals and a logical circuit 30 makes an intermediate logical output on the basis of these comparison signals. A switch unit 4 is controlled on the basis of the intermediate logical output from the logical circuit 30, and any of the step-up operation, the step-down operation and the step-up-down operations is conducted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  When the output voltage is lower than the input voltage, it functions as a step-down type. Conversely, when the output voltage is higher than the input voltage, it functions as a step-up type. The present invention relates to a signal processing circuit for a step-up / step-down DC / DC converter that automatically functions as a type.

  17 and 18 show an overall system diagram of a conventional step-up / step-down DC / DC converter. FIG. 17 is a system diagram of a buck-boost DC / DC converter having a voltage feedback loop, and FIG. 18 is a system diagram of a buck-boost DC / DC converter having a current feedback loop in addition to the voltage feedback loop.

  In FIG. 17, after the output voltage is divided at a certain ratio and the error voltage, which is the result of comparing the voltage with the reference voltage, is determined in the mode determination circuit 3 as the boost mode or the step-down mode, A voltage feedback loop for obtaining a target output voltage by feedback is configured. As the reference voltage, a band gap voltage having a flat temperature-voltage characteristic using a band gap characteristic in a semiconductor is used.

  The conventional step-up / step-down DC / DC converter in FIG. 17 includes a signal processing circuit 1, a driver 2, a mode determination circuit 3, a switch unit 4, a voltage divider 40, and an error amplification circuit 50, and the input voltage Vin is switched by the switch unit 4. Thus, the voltage stepped up and down is output as the output voltage Vout.

  The driver 2 converts the four switches in the switch unit 4 into driver signals Va, Vb, Vc, and Vd that turn on / off the four switches in the switch unit 4 in accordance with the mode information signals Vgb and Vgc output from the signal processing circuit 1. Below, the relationship between Vgb and Vgc (intermediate logic output) which are the outputs of the signal processing circuit 1 and the switches A, B, C and D (described in detail in FIG. 19) in the signal processing circuit 1 will be described. Here, Va, Vb, Vc, and Vd are driver signals for ON / OFF control of these four switches, and control the buck-boost mode and at the same time control the amount of charge to be charged according to the control time. In this document, it is assumed that when Va, Vb, Vc, and Vd are at the H level, the switches A, B, C, and D are turned on, respectively.

  In the step-down mode, the intermediate logic outputs Vgb and Vgc function as a toggle switch that selects either the switch A or the switch B while the switch D is in the ON state. When the switch A is ON and the switch B is OFF, the charge is charged to the inductance in the direction from Vin to Vout. From this state, when the switch B is turned on and the switch A is turned off, the charge stored in the inductance flows in the Vout direction.

  In the step-up mode, Vgb and Vgc function as toggle switches for selecting one of the switches C and D while the switch A is in the ON state. When the switch C is ON and the switch D is OFF, a charge is charged from the Vin toward the ground in the inductance. From this state, when the switch D is turned ON and the switch C is turned OFF, the charge stored in the inductance flows in the Vout direction. Note that these signal processing circuit 1 and driver 2 are commonly used in the prior art and the present invention.

  18 is different from the voltage feedback loop of FIG. 17 in that a feedback loop including a current detection circuit 55 and an adder 56 is added. The output voltage terminal Vout is connected to a large-capacitance capacitor (not shown) for smoothing the charge charged by switching of inductance or capacitance as a voltage regulator. For this reason, the voltage feedback loop that performs feedback by detecting the output voltage as a voltage has a drawback that the response speed of the feedback becomes slow in exchange for the stability of the voltage detection point Vout.

  When the load connected to the output Vout fluctuates transiently, the voltage feedback loop with a large time constant may not be able to follow. In such a case, a feedback characteristic having a high response speed that is not affected by the time constant of the output load capacitor can be realized by equivalently detecting the current flowing through the switch element and applying feedback.

  In the conventional step-up / step-down DC / DC converter in FIG. 18, a current detection circuit 55 and an adder 56 are added to the circuit in FIG. The input voltage Vin is switched by the switch unit 4 and the voltage obtained by step-up / step-down is output as the output voltage Vout. However, in addition to the signal from the error amplification circuit 50, the signal from the current detection circuit 55 is added to the adder 56. Are different from each other in that they are added and supplied to the signal processing circuit 1. The operational relationship between the driver 2 and the signal processing circuit 1 is the same as that in FIG.

  FIG. 19 shows a synchronous prior art step-up / step-down DC / DC converter switch unit. This switch unit 4 is similarly used in the present invention. In the present invention, the point of controlling the switch unit 4 is a new idea, and the switch unit 4 itself is not new. In the step-down mode, the switch A and the switch B function as a toggle switch for selecting one of them while the switch D is kept in the ON state. When the switch A is ON and the switch B is OFF, the charge is charged to the inductance in the direction from Vin to Vout. From this state, when the switch B is turned on and the switch A is turned off, the charge stored in the inductance flows in the Vout direction.

In the step-up mode, the switch C and the switch D function as a toggle switch for selecting one of them while the switch A is in the ON state. When the switch C is ON and the switch D is OFF, a charge is charged from the Vin toward the ground in the inductance. From this state, when the switch D is turned ON and the switch C is turned OFF, the charge stored in the inductance flows in the Vout direction.
Va, Vb, Vc, and Vd are control voltages for ON / OFF control of the four switches, and control the buck-boost mode and at the same time control the amount of charge to be charged according to the control time.

  FIG. 20 is a diagram illustrating a conventional signal processing circuit that controls a switch. First, in the signal generation circuit, an error voltage Verror which is an input signal is generated through a voltage level shift circuit 11 to generate a boosting comparison voltage Error_boost and a bucking comparison voltage Error_book. The waveform generator 12 is a signal generator for comparing with the boosting comparison voltage or the bucking comparison voltage, and a triangular wave, a sawtooth wave, or the like is used.

  In the comparison circuit 20, the signal Vx generated by the waveform generator 12 is compared by two comparators with the boosting comparison voltage “Error_boost” and the step-down comparison voltage “Error_book” generated by the voltage shift circuit. Vb is a step-down comparison result voltage, and Vc is a step-up comparison result voltage.

FIG. 21 is a diagram showing the relationship between the output signals Vgb and Vgc of the signal processing circuit and the control signals Va, Vb, Vc and Vd for controlling the switches A, B, C and D. Both the switch A and the switch B are not turned on at the same time, and when one is turned on, the other is turned off. Similarly, both the switch C and the switch D are not turned on, and when one is turned on, the other is turned off.
When the switch drive signal Va is H level, the switch A is ON, when the switch drive signal Vb is H level, the switch B is ON, when the switch drive signal Vc is H level, the switch C is ON, the switch drive signal When Vd is at the H level, the switch D is turned on. As described above, Va and Vb are in an inverse logic relationship, and Vc and Vd are also in an inverse logic relationship.

  Next, the intermediate logic output Vgb is a source logic signal for generating the drive signal Va of the switch A and the drive signal Vb of the switch B. Since the logic (H level or L level) matches Vb, it is expressed as Vgb. is doing. The meaning of the signal Vgb means a logic signal for generating drive signals for the switches A and B. Similarly, the intermediate logic output Vgc is a logic signal that is a source for generating the drive signal Vc of the switch C and the drive signal Vd of the switch D, and is expressed as Vgc because the logic (H level or L level) matches Vc. ing. The meaning of the signal of the intermediate logic output Vgc means a logic signal for generating drive signals for the switches C and D.

  FIG. 22 is a diagram showing a conventional step-down mode waveform when the waveform of the signal generator 10 is a triangular wave. When the triangular wave signal Vx is always higher than the boosting comparison voltage Verror_boost and has an intersection with the lowering comparison voltage Verror_book, it functions as a buck mode.

  The comparison voltage Verr_back and the triangular wave Vx cross to invert the step-down comparator output Vb. On the other hand, since the comparison voltage Verror_boost and the triangular wave Vx do not cross each other, the boost comparator output Vc maintains the L level. Signals Va, Vb, Vc, and Vd for controlling the four switches A, B, C, and D are generated by logic processing of the step-down comparator output and the step-up comparator output.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  The relationship between Vgb and Vgc and switches A, B, C, and D in FIG. 22 will be described below. In FIG. 20, the comparison circuit 20 and the logic circuit 30 are expressed separately, but the outputs Vb and Vc of the comparison circuit 20 and the outputs Vgb and Vgc of the comparison circuit 20 are always matched. ing. In FIG. 22, an intermediate logic output Vgb is a logic signal for generating a drive signal Va for switch A and a drive signal Vb for switch B. The drive signal Va for switch A and the drive signal Vb for switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  FIG. 23 is a diagram showing a boost mode waveform of the prior art when the waveform of the signal generator 10 is a triangular wave. When the step-down comparison voltage Verror_book is always higher than the triangular wave Vx and the step-up comparison voltage Verror_boost and the triangular wave Vx have an intersection, the step-up comparison function functions as a step-up mode.

  When the comparison voltage Verror_boost and the triangular wave Vx cross, the boost comparator output Vc is inverted. On the other hand, since the comparison voltage Verror_back and the triangular wave Vx do not cross, the boost comparator output Vb maintains the L level. Signals Va, Vb, Vc, and Vd for controlling the four switches A, B, C, and D, respectively, are generated by logic processing of the step-down comparator output and the step-up comparator output.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

  FIG. 24 is a diagram showing a conventional step-up / step-down mode waveform when the waveform of the signal generator 10 is a triangular wave. When both the step-down comparison voltage Verror_book and the step-up comparison voltage Verror_boost have an intersection with the triangular wave Vx, the step-up / step-down mode functions.

  The comparison voltage Verr_back and the triangular wave Vx cross to invert the step-down comparator output Vb. On the other hand, since the comparison voltage Verror_boost and the triangular wave Vx do not cross, the boost comparator output Vc maintains the L level. Signals Va, Vb, Vc, and Vd for controlling the four switches A, B, C, and D are generated by logic processing of the step-down comparator output and the step-up comparator output.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly, when Vb, Vc, and Vd are each at the H level, the switches B, C, and D are in the ON state. Conversely, when Vb, Vc, and Vd are each at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  Next, when the comparison voltage Verror_boost and the triangular wave Vx cross, the boost comparator output Vc is inverted. On the other hand, since the comparison voltage Verror_back and the triangular wave Vx do not cross, the boost comparator output Vb maintains the L level. Signals Va, Vb, Vc, and Vd for controlling the four switches A, B, C, and D, respectively, are generated by logic processing of the step-down comparator output and the step-up comparator output.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

As a DC / DC converter that feedback-controls the output voltage by feeding back the output voltage Vout, for example, an invention as disclosed in Patent Document 1 is disclosed.
JP-A-9-215314

  As is apparent from FIG. 24, the conventional technology realizes the step-up / step-down mode by simply combining the step-up mode and the step-down mode. Usually, when the required output voltage is higher than the input voltage, the boost mode is used. Conversely, when the required output voltage is lower than the input voltage, the step-down mode is functioned. However, even in the step-up mode, when the electromotive force of the battery voltage or the like that is the input voltage decreases due to battery consumption, a condition for shifting to the step-up / step-down mode in which the input voltage and the output request voltage antagonize is satisfied. Further, when the input voltage and the output required voltage are close in voltage, it always functions as a step-up / down mode.

  In order to minimize the power loss of the signal processing circuit, it is necessary to minimize the operation of the switch. In addition, considering the frequency characteristics of the feedback loop, etc., the boost mode, the buck mode, and the buck-boost mode It is desirable that the switching frequency is constant in any mode.

  In the step-down mode of FIG. 22 and the step-up mode of FIG. 23, the switching operation is performed once in one cycle. However, in the step-up / step-down mode of FIG. 24, the switching operation in the step-down mode and the step-up mode is performed twice in one cycle. In the signal processing circuit, power loss occurs with the switching operation. Therefore, an increase in the number of times of switching means that the power efficiency in the step-up / step-down mode is lowered.

  In the present invention, in any of the operation modes of step-up operation, step-down operation, and step-up / step-down operation, when one switch performs ON / OFF switching operation, the other switch also performs OFF / ON switching operation synchronously. Do. When one switch continues to be in the ON state, the other switch is also synchronized with the OFF state. Thus, it aims at reducing the power consumption by switching and performing efficient control by using it as 2 sets of 2 switches, and a total of 4 switches.

  Another object of the present invention is to increase the switching efficiency in the step-up / step-down operation mode by making the switching frequency the same in any of the operation modes of the step-up operation, the step-down operation and the step-up / step-down operation.

  A signal processing circuit for a step-up / step-down DC / DC converter according to the first aspect of the present invention includes a voltage level shift circuit that generates a first comparison voltage and a second comparison voltage from an error voltage, a first signal, and a first waveform. A waveform generator that generates a second waveform signal whose phase is inverted from that of the signal, a first comparator that compares the first waveform signal with a first comparison voltage and outputs a first comparison signal; A second comparator that compares the second waveform signal and the first comparison voltage and outputs a second comparison signal, and compares the first waveform signal and the second comparison voltage to obtain a third comparison signal. A third comparator that outputs, a fourth comparator that compares the second waveform signal with the second comparison voltage and outputs a fourth comparison signal, and first through fourth comparison signals; A logic circuit that generates an intermediate logic output based on the switch and a switch based on the intermediate logic output from the logic circuit And controlling the knit.

  A signal processing circuit for a step-up / step-down DC / DC converter according to a second aspect of the present invention includes a voltage level shift circuit that generates a first comparison voltage and a second comparison voltage from an error voltage, a first signal, and a first waveform. A waveform generator that generates a second waveform signal whose phase is inverted from that of the signal, a first comparator that compares the first waveform signal with a first comparison voltage and outputs a first comparison signal; A second comparator that compares the second waveform signal with the second comparison voltage and outputs a second comparison signal; and a logic that generates an intermediate logic output based on the first comparison signal and the second comparison signal The switch unit is controlled based on a circuit and an intermediate logic output from the logic circuit.

  A signal processing circuit for a step-up / step-down DC / DC converter according to a third aspect of the present invention includes a voltage level shift circuit that generates a first comparison voltage and a second comparison voltage from an error voltage, a first signal, and a first waveform. A waveform generator that generates a second waveform signal whose phase is inverted from that of the signal, a first voltage level shift circuit that shifts a voltage level of the first waveform signal, an output of the first voltage level shift circuit, A first comparator that compares the first comparison voltage and outputs a first comparison signal; a second voltage level shift circuit that shifts the voltage level of the second waveform signal; and a second voltage level shift circuit A second comparator that compares the output of the first and the second comparison voltage and outputs a second comparison signal; and a logic circuit that generates an intermediate logic output based on the first comparison signal and the second comparison signal; Based on intermediate logic output from logic circuit And controlling the switch unit Te.

  The waveform generator in the signal processing circuit for the step-up / step-down DC / DC converter according to the fourth aspect of the present invention generates a triangular wave or a sawtooth wave.

  The signal processing circuit for the step-up / step-down DC / DC converter according to the fifth aspect of the present invention further includes an error amplification circuit, and the error amplification circuit compares the voltage divided by the resistance voltage divider with the reference voltage. And a current error amplifier that detects a current from each switching element of the switch unit and adds the current detection level and the output of the voltage error amplifier.

  According to the first aspect of the present invention, a signal processing circuit for a step-up / step-down DC / DC converter includes a voltage level shift circuit that generates a first comparison voltage and a second comparison voltage from an error voltage, a first signal, A waveform generator that generates a second waveform signal whose phase is inverted from that of the first waveform signal, and a first comparator that compares the first waveform signal with a first comparison voltage and outputs a first comparison signal A second comparator that compares the second waveform signal with the first comparison voltage and outputs a second comparison signal, and compares the first waveform signal with the second comparison voltage to obtain a third A third comparator that outputs a comparison signal, a fourth comparator that compares the second waveform signal with the second comparison voltage and outputs a fourth comparison signal, and first to fourth comparison signals. And a logic circuit for generating an intermediate logic output based on the comparison signal. Therefore, the signal processing circuit for the step-up / step-down DC / DC converter according to the first aspect of the present invention is a step-down type when the output voltage Vout is lower than the unstabilized input voltage Vin, and the input is not stabilized. When the output voltage Vout is higher than the voltage Vin, it automatically operates as a boost type, and when the input voltage Vin and the output voltage Vout are equal, it automatically operates as a step-up / down type. Therefore, regardless of whether the output voltage is higher, lower, or the same as the input voltage, when one switch performs the ON / OFF switching operation, the other switch also synchronizes OFF / ON. By performing the operation, a highly efficient buck-boost signal processing circuit can be realized. In any of the operation modes of the step-up operation, the step-down operation, and the step-up / step-down operation, by performing the switching operation once in one cycle, it is possible to reduce power consumption due to switching and to perform efficient control.

  According to the second aspect of the present invention, the signal processing circuit for the step-up / step-down DC / DC converter includes the voltage level shift circuit that generates the first comparison voltage and the second comparison voltage from the error voltage, the first signal, and the second signal. A waveform generator that generates a second waveform signal whose phase is inverted from that of the first waveform signal, and a first comparison that compares the first waveform signal with the first comparison voltage and outputs a first comparison signal A second comparator that compares the second waveform signal with a second comparison voltage and outputs a second comparison signal; and intermediate logic based on the first comparison signal and the second comparison signal. And a logic circuit for generating an output. Therefore, it has the same effect as that of the first invention and is constituted by a small number of comparison circuits, so that a further economic effect can be obtained. That is, according to the second aspect of the present invention, the number of required comparators can be reduced from four to two as compared with the first aspect of the invention, so that the scale of the logic circuit can be reduced.

  According to the third aspect of the present invention, a signal processing circuit for a step-up / step-down DC / DC converter includes a voltage level shift circuit that generates a first comparison voltage and a second comparison voltage from an error voltage, a first signal, A waveform generator that generates a second waveform signal whose phase is inverted from that of the first waveform signal, a first voltage level shift circuit that shifts a voltage level of the first waveform signal, and a first voltage level shift circuit A first comparator that compares the output with the first comparison voltage and outputs a first comparison signal; a second voltage level shift circuit that shifts the voltage level of the second waveform signal; and a second voltage A second comparator that compares the output of the level shift circuit with a second comparison voltage and outputs a second comparison signal, and generates an intermediate logic output based on the first comparison signal and the second comparison signal And a logic circuit. Therefore, since the voltage level shift circuit is added while having the same effect as the second invention, the levels of the first waveform signal and the second waveform signal generated by the waveform generator can be arbitrarily adjusted. , Va, Vb, Vc, Vd can be freely set, so that precise voltage setting is possible. Similarly, according to the third aspect of the present invention, the number of required comparators can be reduced from four to two as compared with the first aspect of the invention, so that the scale of the logic circuit can be reduced.

  According to the fourth aspect of the present invention, the waveform generator in the signal processing circuit for the step-up / step-down DC / DC converter can generate a triangular wave or a sawtooth wave. Therefore, by changing the output waveform of the waveform generator, the pulse widths of Va, Vb, Vc, and Vd can be freely set, so that precise voltage setting is possible.

  According to the fifth aspect of the present invention, the signal processing circuit for the step-up / step-down DC / DC converter further includes an error amplification circuit, and the error amplification circuit compares the voltage divided by the resistance voltage divider with the reference voltage. The voltage error amplifier includes a current error amplifier that detects current from each switching element of the switch unit and adds the current detection level and the output of the voltage error amplifier. Therefore, it is possible to construct an interrupt system without a large time constant, and as a result, it is possible to provide an error amplification circuit with a small time constant and quick response.

Embodiment 1. FIG.
FIG. 1 is a diagram illustrating an example of a signal processing circuit that controls a switch according to the first embodiment of the present invention. In this example, an example is shown in which a total of four comparators 21, 22, 23, and 24 are used as the step-down comparator and the step-up comparator.

  The error voltage Verror is passed through the voltage level shift circuit 11 to generate a boosting comparison voltage Verror_boost (second comparison voltage) and a step-down comparison voltage Verror_book (first comparison voltage). On the other hand, the waveform generator 12 is a circuit for comparing with the comparison voltage for step-up or the comparison voltage for step-down, and generates a triangular wave, a sawtooth wave, or the like. The outputs Vx and Vy of the waveform generator 12 are differential output signals that are 180 degrees out of phase.

  The comparison circuit 20 includes signals Vx and Vy generated by the waveform generator 12 and four comparators 21 to 24 that respectively compare the boosting comparison voltage Verr_boost and the bucking comparison voltage Verr_back generated by the voltage shift circuit. Composed. Vbx is a comparison signal obtained as a result of comparing the step-down comparison voltage Verror_back and the waveform signal Vx, Vby is a comparison signal obtained as a result of comparing the step-down comparison voltage Verror_back and the waveform signal Vy, and Vcx is a step-up comparison voltage Verror_boost. A comparison signal Vcy obtained as a result of comparison with the waveform signal Vx is a comparison signal obtained as a result of comparison between the boosting comparison voltage Verror_boost and the waveform signal Vy.

  The logic circuit 30 performs a logic process in which either Vgb or Vgc becomes H level at the timing of switching. Further, the state of Hg or Lg of Vgb or Vgc is determined at the rising edge of the clock signal Vclk.

  The intermediate logic outputs Vgb and Vgc of the logic circuit 30 are as follows depending on the combination of Vcy and Vbx and Vby and Vcx, which are outputs of the comparison circuit 20. Here, the intermediate logic output Vgb is an intermediate logic output that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is an intermediate logic output that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  FIG. 2 is a diagram illustrating the relationship between the outputs Vbx, Vby, Vcy, Vcx of the comparison circuit 20 and the outputs Vgb, Vgc of the logic circuit 30. In FIG. 2, a clock signal Vclk is a timing signal for generating Vgb and Vgc. The clock signal Vclk performs timing and logic determination for generating the logic signal Vgb for generating the drive signals for the switches A and B and the logic signal Vgc for generating the drive signals for the switches C and D. Control. Note that the mode selection signal Vclk does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching the step-down mode and the step-up mode in the step-up / step-down mode, and performs logical determination of Vgb and Vgc alternately.

  Explaining this procedure in detail, Vbx and Vcy are checked at the rising timing of the first clock signal Vclk. When both or Vbx is at H level, Vgb is at H level. When Vbx is L level and Vcy is H level, Vgc is set to H level (see Table 1). Vcx and Vby are checked at the rising timing of the next clock signal Vclk. When both or Vcx is at H level, Vgc is at H level. When Vby is H level and Vcx is L level, Vgb is H level (see Table 1).

The clock signal Vclk gives priority to Vgb over Vgc in the (2n + 1) period (where n is a natural number), which is the first period and the odd period, and the (2n + 2) period (here, the second period and the even period). And n is a natural number), Vgc is given priority over Vgb.
Here, the clock signal Vclk is a timing signal (clock signal) for generating Vgb and Vgc. When Vbx is H level at the rising timing of the clock signal Vclk, Vgb is set to H level. However, when Vbx is at L level, Vgb is at L level.

  In Table 1, NA indicates a case where Vcy or Vbx, or Vby or Vcx becomes H level at the rising edge timing of the clock signal Vclk, and becomes invalid due to a combination condition that does not exist.

  For example, in the combination of Vcy and Vbx in the first period, when Vbx is at H level, Vgb is at H level regardless of the value of Vcy. When Vbx is L level and Vcy is H level, Vgc is set to H level. Further, there is no condition that both Vbx and Vcy are at the L level (however, at the rise timing of Vclk).

  Next, in the combination of Vcx and Vby in the second period, when Vcx is at H level, Vgc is set at H level regardless of the value of Vby. When Vcx is at L level and Vby is at H level, Vgb is at H level. Further, there is no condition that both Vby and Vcx become L level (however, at the rise timing of Vclk).

Table 1 is a truth table showing the relationship between the four comparator output voltages Vbx, Vby, Vcx, Vcy and the two intermediate logic outputs Vgb, Vgc in FIGS. As a basic idea, Vbx and Vby are logical information for setting Vgb to H level when either is at H level. Vcx and Vcy are logical information for setting Vgc to H level when either is at H level.

  FIG. 3 is a diagram showing a step-down mode waveform when the waveform of the signal generator 10 is a triangular wave. In FIG. 3, the triangular wave signal Vx has the same function as Vx in the prior art. Further, Vbx and Vcx respectively correspond to the comparison circuit outputs Vb and Vc in the prior art. The triangular wave signal Vy is another triangular wave signal added according to the present invention, and has a phase relationship opposite to that of the triangular wave signal Vx. Although the comparison circuit outputs of the triangular wave signal Vy are Vby and Vcy, as shown in FIG. 3, the relationship between Vbx and Vby, and Vcx and Vcy is not necessarily in reverse phase. When the triangular wave signals Vx and Vy always exceed the boosting comparison voltage Verror_boost, and the triangular wave signal Vx or Vy has an intersection with the step-down comparison voltage Verror_back, it functions as a step-down mode.

  When the comparison voltage Verror_back and the triangular waves Vx and Vy cross, the step-down comparator outputs Vbx and Vby are inverted. On the other hand, since the boosting comparison voltage Verror_boost and the triangular waves Vx and Vy do not intersect, the boosting comparator outputs Vcx and Vcy maintain the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 3, an intermediate logic output Vgb is a logic signal that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  Vclk is a timing signal (clock signal) for generating Vgb and Vgc. When Vbx or Vby is at H level at the rise timing of Vclk, Vgb is set to H level. However, when Vbx and Vby are at L level, Vgb is at L level. FIG. 3 shows two periods. In the first period, Vgb is at the H level due to Vbx. In the second period, Vgb is at H level due to Vby.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  FIG. 4 is a diagram showing a boost mode waveform when the waveform of the signal generator 10 is a triangular wave. Vbx and Vcx respectively correspond to the comparison circuit outputs Vb and Vc in the prior art. The triangular wave signal Vy is another triangular wave signal added according to the present invention, and has a phase relationship opposite to that of the triangular wave signal Vx. Although the comparison circuit outputs of the triangular wave signal Vy are Vby and Vcy, as shown in FIG. 4, the relationship between Vbx and Vby, and Vcx and Vcy is not necessarily in reverse phase. When the triangular wave signals Vx and Vy are always lower than the step-down comparison voltage Verror_back and the triangular wave signal Vx or Vy has an intersection with the step-up comparison voltage Verror_boost, it functions as a step-up mode.

  When the comparison voltage Verror_boost and the triangular waves Vx, Vy cross, the boost comparator outputs Vcx, Vcy are inverted. On the other hand, since the step-down comparison voltage Verror_back and the triangular waves Vx and Vy do not intersect, the step-down comparator outputs Vbx and Vby maintain the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 4, an intermediate logic output Vgb is a logic signal that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  Similarly, when Vcx or Vcy is at H level at the rise timing of Vclk, Vgc is set to H level. However, when Vcx and Vcy are at L level, Vgc is at L level. FIG. 4 shows two periods. In the first period, Vgc is at H level due to Vcy. In the second period, Vgc is at the H level due to Vcx.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly, when Vb, Vc, and Vd are each at the H level, the switches B, C, and D are in the ON state. Conversely, when Vb, Vc, and Vd are each at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

  FIG. 5 is a diagram showing a step-up / down mode waveform when the waveform of the signal generator 10 is a triangular wave. In FIG. 5, the triangular wave signal Vx has the same function as Vx in the prior art. Further, Vbx and Vcx respectively correspond to the comparison circuit outputs Vb and Vc in the prior art. The triangular wave signal Vy is another triangular wave signal added according to the present invention, and has a phase relationship opposite to that of the triangular wave signal Vx. Although the comparison circuit outputs of the triangular wave signal Vy are Vby and Vcy, as shown in FIG. 3, the relationship between Vbx and Vby, and Vcx and Vcy is not necessarily in reverse phase. When the triangular wave signals Vx and Vy have intersections with both the boosting comparison voltage Verr_boost and the bucking comparison voltage Verror_back, they function as the step-up / step-down mode.

  In the first period in the step-down mode, the comparison voltage Verror_back and the triangular waves Vx and Vy cross to invert the step-down comparator outputs Vbx and Vby. On the other hand, since the boosting comparison voltage Verror_boost and the triangular waves Vx and Vy do not intersect, the boosting comparator outputs Vcx and Vcy maintain the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 5, an intermediate logic output Vgb is a logic signal that is a source for generating the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  Vclk is a timing signal (clock signal) for generating Vgb and Vgc. In the first period in the step-down mode, Vgb is set to H level when Vbx or Vby is at H level at the rising timing of Vclk. However, when Vbx and Vby are at L level, Vgb is at L level. In the first period, both Vbx and Vcy are at the H level, but Vclb gives priority to Vgb over Vgc. Similarly, in the second period in the boost mode, when Vcx or Vcy is H level at the rising timing of Vclk, Vgc is set to H level. However, when Vcx and Vcy are at L level, Vgc is at L level. In the second period, both Vby and Vcx are at the H level, but Vgc is prioritized over Vgb by Vclk. As described above, when the condition that both Vgb and Vgc become H level is satisfied, Vgb and Vgc are alternately set to H level.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly, when Vb, Vc, and Vd are each at the H level, the switches B, C, and D are in the ON state. Conversely, when Vb, Vc, and Vd are each at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  Next, in the second period in the boost mode, the comparison voltage Verror_boost and the triangular waves Vx and Vy cross to invert the boost comparator outputs Vcx and Vcy. On the other hand, since the step-down comparison voltage Verror_back and the triangular waves Vx and Vy do not intersect, the step-down comparator outputs Vbx and Vby maintain the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

In both the conventional invention and the present invention, two triangular waves or sawtooth waves are used. In the conventional invention, since two threshold values are compared with one triangular wave or sawtooth wave in the step-up / step-down mode, one triangular wave or sawtooth wave is compared with the step-down mode or boost mode. Compared with the case where one threshold value is compared, the number of times of switching is clearly doubled as follows.
Fig. 22 Step-down mode Switching frequency 1 cycle / cycle Fig. 23 Boosting mode Switching frequency 1 cycle / cycle Fig. 24 Buck-boost mode Switching frequency 2 times / cycle

However, in the present invention, since two triangular waves or sawtooth waves having a period twice as much as the phase are used, the number of switching is not changed in the step-down mode or the step-up mode compared to the conventional invention when compared in one period. In the step-up / step-down mode, the number of switching operations is halved, and can be the same as the step-down mode or the step-up mode single condition as follows.
3, 8, 13 Step-down mode 1 switching / cycle 1 FIG. 4, 9, 14 Step-up mode 1 switching / cycle 1 FIG. 5, 10, 15 Buck-boost mode 1 switching / cycle 1

Embodiment 2. FIG.
FIG. 6 is a diagram showing an example of a signal processing circuit for controlling the switch in the present invention.
In this example, a case where a total of two comparators 21 and 22 are used as a step-down comparator and a step-up comparator and a mode selection signal Vselect is used is shown.

  The error voltage Verror is generated through the voltage level shift circuit 11 to generate a boosting comparison voltage Verror_boost and a bucking comparison voltage Verror_book. On the other hand, the waveform generator 12 generates a signal for comparison with the step-up comparison voltage or the step-down comparison voltage. Here, a sawtooth wave is shown as an example. The outputs Vx and Vy of the waveform generator 12 are differential output signals that are 180 degrees out of phase.

  The comparator circuit 20 compares the signals Vx and Vy generated by the waveform generator 12 with the two comparators 21 that respectively compare the step-up comparison voltage Verror_boost and the step-down comparison voltage Verror_book generated by the voltage level shift circuit 11. , 22. Vbx is a step-down comparison result voltage, and Vcy is a step-up comparison result voltage.

  Vbx is a comparison output between the step-down comparison voltage Verror_back and the waveform signal Vx, and Vcy is a comparison output between the step-up comparison voltage Verror_boost and the waveform signal Vy. The Vselect signal is a signal for selecting Vgb or Vgc when both Vcy and Vbx are turned on in the step-up / step-down mode.

  The logic circuit 30 performs a logic process in which either Vgb or Vgc becomes H level at the timing of switching. Further, the state of the H level or L level of Vgb or Vgc is determined at the rising edge of the mode selection signal Vselect.

  The outputs Vgb and Vgc of the logic circuit 30 are as follows according to the combination of Vcy and Vbx and Vby and Vcx, which are outputs of the comparison circuit 20. Here, the intermediate logic output Vgb is a logic signal that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical (H or L) reverses. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  The mode selection signal Vselect alternately repeats whether Vgb is set to H level or Vgc is set to H level when both of the comparator output voltages Vbx and Vcy are at H level. In the combination of Vcy and Vbx in Table 2, when Vcy is at H level and Vbx is at L level, Vgc is at H level. Similarly, when Vcy is at L level and Vbx is at H level, Vgb is at H level.

  Here, the function of the mode selection signal Vselect is basically the same as Vclk. The basic difference between the clock signal Vclk and the mode selection signal Vselect is that the clock signal Vclk is positioned as a start pulse within one cycle, whereas the mode selection signal Vselect is a state output that is inverted every cycle. It is. However, the purpose is the same in that both the clock signal Vclk and the mode selection signal Vselect determine Vgb and Vgc at the rising timing.

  When both Vcy and Vbx are at the H level, whether the Vgb is set to the H level or the Vgc is set to the H level is determined by the mode selection signal Vselect. In Table 2, the mode selection signal Vselect is defined as H level, that is, Vselect = 1, Vselect ′ = 0 in the first period of FIGS.

  As described above, according to the mode selection signal Vselect, Vgb becomes H level when both Vcy and Vbx are H level in the first period and the (2n + 1) period (where n is a natural number) which is an odd period. Further, in the (2n + 2) period (where n is a natural number) that is the second period and the even period, Vgc is at the H level when both Vcy and Vbx are at the H level. In Table 2, there is no condition that both Vcy and Vbx are at L level (rising timing of Vselect).

  The intermediate logic outputs Vgb and Vgc based on the combination of Vcy and Vbx and Vby and Vcx are shown in the logic table of Table 2. In Table 2, NA indicates a case where Vcy or Vbx becomes H level at the rising edge timing of the mode selection signal, and becomes invalid due to a combination condition that does not exist.

Table 2 is a truth table representing the relationship between the two comparison circuit output voltages Vbx and Vcy in FIGS. 8, 9, and 10 and the two intermediate logic outputs Vgb and Vgc that are the basis of the switch drive signal. The basic concept is logical information for setting Vgb to H level when Vbx is at H level. Further, when Vcy is at H level, this is logical information for setting Vgc to H level.

  FIG. 8 is a diagram showing a step-down mode waveform when the signal generator 10 has a sawtooth waveform. The second embodiment in FIG. 8 differs from the first embodiment in that a sawtooth wave is used in place of the triangular wave, the comparator outputs Vby and Vcx are omitted, and a mode selection signal Vselect is used instead. These are two points. The mode selection signal Vselect does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching between the step-down mode and the step-up mode in the step-up / step-down mode. The sawtooth signal Vx has the same function as the triangular wave signal Vx in the prior art. Also, Vbx and Vcy correspond to the comparison circuit outputs Vb and Vc in the prior art, respectively. The sawtooth wave signal Vy is another sawtooth wave signal added according to the present invention, and has a phase relationship opposite to that of the sawtooth wave signal Vx.

  When the sawtooth wave signals Vx and Vy always exceed the boosting comparison voltage Verror_boost, and the sawtooth wave signal Vx or Vy has an intersection with the bucking comparison voltage Verr_back, it functions as a buck mode.

  The comparison voltage Verr_back and the sawtooth waves Vx and Vy cross to invert the step-down comparator output Vbx. On the other hand, the boosting comparison voltage Verror_boost and the sawtooth waves Vx and Vy do not cross each other, so that the boosting comparator output Vcy maintains the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 8, an intermediate logic output Vgb is a logic signal that is a source for generating the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In the step-down mode, Vcy is always at the L level, so there is no influence on Vgb and Vgc by the Vselect signal.
As described above, in FIG. 8, Vbx and Vgb are equal, Vgb is equal to Vb, and Va is in opposite phase to Vgb. Similarly, Vcy and Vgc are equal, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  FIG. 9 is a diagram showing a boost mode waveform when the waveform of the signal generator 10 is a sawtooth wave. The second embodiment in FIG. 9 differs from the first embodiment in that a sawtooth wave is used in place of the triangular wave, the comparator outputs Vby and Vcx are omitted, and a mode selection signal Vselect is used instead. These are two points. The mode selection signal Vselect does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching between the step-down mode and the step-up mode in the step-up / step-down mode. The sawtooth signal Vx has the same function as the triangular wave signal Vx in the prior art. Further, Vbx and Vcy correspond to the comparator outputs Vb and Vc in the prior art, respectively. The sawtooth wave signal Vy is another sawtooth wave signal added according to the present invention, and has a phase relationship opposite to that of the sawtooth wave signal Vx.

  When the sawtooth wave signals Vx and Vy are always lower than the step-down comparison voltage Verror_back and the sawtooth wave signal Vx or Vy has an intersection with the step-up comparison voltage Verror_boost, it functions as a step-up mode.

  When the comparison voltage Verror_boost and the sawtooth waves Vx and Vy cross, the boost comparator output Vcy is inverted. On the other hand, the step-down comparison voltage Verror_back and the sawtooth waves Vx and Vy do not cross each other, so that the step-down comparator output Vbx maintains the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 9, an intermediate logic output Vgb is a logic signal used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. However, in the step-up mode of FIG. 9, Vbx is always at L level, so that there is no influence on Vgb and Vgc by the Vselect signal.
As described above, in FIG. 9, Vbx and Vgb are equal, Vgb is equal to Vb, and Va has an opposite phase to Vgb. Similarly, Vcy and Vgc are equal, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

  FIG. 10 is a diagram showing a step-up / down mode waveform when the waveform of the signal generator 10 is a sawtooth wave. The second embodiment in FIG. 10 differs from the first embodiment in that a sawtooth wave is used instead of a triangular wave, and that the comparator outputs Vby and Vcx are omitted, and a mode selection signal Vselect is used instead. It is two points. The mode selection signal Vselect does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching between the step-down mode and the step-up mode in the step-up / step-down mode. The sawtooth signal Vx has the same function as the triangular wave signal Vx in the prior art. Further, Vbx and Vcy correspond to the comparator outputs Vb and Vc in the prior art, respectively. The sawtooth wave signal Vy is another sawtooth wave signal added according to the present invention, and has a phase relationship opposite to that of the sawtooth wave signal Vx.

  When the sawtooth wave signals Vx and Vy have intersections with both the boosting comparison voltage Verr_boost and the bucking comparison voltage Verror_back, it functions as a step-up / step-down mode.

  In the first period which is the step-down mode, the comparison voltage Verror_back and the sawtooth waves Vx and Vy cross to invert the step-down comparator output Vbx. On the other hand, the boosting comparison voltage Verror_boost and the sawtooth waves Vx and Vy do not cross each other, so that the boosting comparator output Vcy maintains the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 10, an intermediate logic output Vgb is a logic signal that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In FIG. 10, since both Vbx and Vcy are at the H level in the first cycle, when the Vselect signal is at the H level, Vgb is at the H level and Vgc is at the L level.
As described above, in FIG. 10, in the first period, Vbx and Vgb are equal, Vgb is equal to Vb, and Va has a phase opposite to Vgb. Conversely, Vcy and Vgc are different, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  Next, in the second period, which is the boost mode, the comparison voltage Verror_boost and the sawtooth waves Vx and Vy cross to invert the boost comparator output Vcy. On the other hand, the step-down comparison voltage Verror_back and the sawtooth waves Vx and Vy do not cross each other, so that the step-down comparator output Vbx maintains the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 10, an intermediate logic output Vgb is a logic signal that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In FIG. 10, since both Vbx and Vcy are at the H level in the second period, when the Vselect signal is at the L level, Vgc is at the H level and Vgb is at the L level.
As described above, in FIG. 10, in the second period, Vbx and Vgb are different, Vgb is equal to Vb, and Va has a phase opposite to Vgb. Conversely, Vcy and Vgc are equal, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

Embodiment 3. FIG.
FIG. 11 is a diagram illustrating an example of a signal processing circuit that controls a switch according to the third embodiment of the present invention. In this example, the error voltage Verror is used as it is as the comparison voltage of the step-down comparator and the step-up comparator, and the waveform signal is subjected to voltage shift.

  From the error voltage Verror, it becomes a comparison voltage for step-up and a comparison voltage for step-down. On the other hand, the waveform generator 12 is a signal generator for generating a signal to be compared with the comparison voltage for step-up or the comparison voltage for step-down. As an example of the signal generated by the waveform generator 12, a voltage level shift is performed. Shows the sawtooth wave. The outputs Vx and Vy of the waveform generator 12 are differential output signals that are 180 degrees out of phase. The outputs Vx and Vy of the waveform generator 12 are supplied to the comparison circuit 20 after the voltage levels are shifted by the voltage level shift circuits 13 and 14, respectively. In the comparison circuit 20, the signals Vx and Vy generated by the waveform generator 12 and voltage-shifted by the voltage level shift circuits 13 and 14 are compared with the error voltage Verror by two comparators. Vbx is a step-down comparison result voltage, and Vcy is a step-up comparison result voltage.

  Vbx is a comparison output between the step-down comparison voltage Verror and the waveform signal Vx, and Vcy is a comparison output between the step-up comparison voltage Verror and the waveform signal Vy. The Vselect signal is a signal for selecting Vgb or Vgc when both Vcy and Vbx are turned on in the step-up / step-down mode.

Table 3 is a diagram illustrating the logic of the logic circuit 30 according to the third embodiment. Table 3 is a truth table showing the relationship between the two comparison circuit output voltages Vbx and Vcy and the two intermediate logic outputs Vgb and Vgc that are the basis of the switch drive signal in FIGS. . The basic concept is logical information for setting Vgb to H level when Vbx is at H level. Further, when Vcy is at H level, this is logical information for setting Vgc to H level.

  The logic circuit 30 performs a logic process in which either Vgb or Vgc becomes H level at the timing of switching. Further, the state of the H level or L level of Vgb or Vgc is determined at the rising edge of the mode selection signal Vselect.

  The outputs Vgb and Vgc of the logic circuit 30 are as follows according to the combination of Vcy and Vbx and Vby and Vcx, which are outputs of the comparison circuit 20. Here, the intermediate logic output Vgb is a logic signal that is used to generate the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical (H or L) reverses. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  The mode selection signal Vselect alternately repeats whether Vgb is set to H level or Vgc is set to H level when both of the comparator output voltages Vbx and Vcy are at H level. In the combination of Vcy and Vbx in Table 2, when Vcy is at H level and Vbx is at L level, Vgc is at H level. Similarly, when Vcy is at L level and Vbx is at H level, Vgb is at H level.

  When both Vcy and Vbx are at the H level, whether the Vgb is set to the H level or the Vgc is set to the H level is determined by the mode selection signal Vselect. In the example of FIG. 15, when Vselect is at the H level, the logic has priority over Vgb over Vgc. In Table 3, when both Vcy and Vbx are at the H level, Vgb is at the H level or Vgc is at the H level depending on the value of Vselect. The mode selection signal Vselect is defined as H level in the first period of FIGS. 13, 14, and 15, that is, Vselect = 1 in Table 3.

  As described above, according to the mode selection signal Vselect, Vgb becomes H level when both Vcy and Vbx are H level in the first period and the (2n + 1) period (where n is a natural number) which is an odd period. Further, in the (2n + 2) period (where n is a natural number) that is the second period and the even period, Vgc is at the H level when both Vcy and Vbx are at the H level. In Table 3, there is no condition that both Vcy and Vbx are at the L level (the rise timing of Vselect). In other words, at the rising edge timing of the mode selection signal Vselect, either Vcy or Vbx is at the H level, and therefore, it becomes invalid due to a combination condition that does not exist.

  FIG. 12 is a diagram illustrating the relationship between the outputs Vbx and Vcy of the comparison circuit 20 in FIG. 11 and the outputs Vgb and Vgc of the logic circuit 30. In FIG. 12, a mode selection signal Vselect is a timing signal for generating Vgb and Vgc. The mode selection signal Vselect is a timing and logic determination for generating a logic signal Vgb for generating the drive signals for the switches A and B and a logic signal Vgc for generating the drive signals for the switches C and D. To manage. Further, the mode selection signal Vselect performs the logical determination of Vgb and Vgc alternately.

  This procedure will be described in detail. When Vbx is H level in the state of the first mode selection signal Vselect (H level in the figure), Vgb is set to H level. However, when Vbx is at L level, Vgb is at L level. When Vcy is H level in the state of the next mode selection signal Vselect (L level in the figure), Vgc is set to H level. However, when Vcy is at L level, Vgc is at L level.

  The function of the mode selection signal Vselect is basically the same as Vclk described above. The basic difference between the clock signal Vclk and the mode selection signal Vselect is that the clock signal Vclk is positioned as a start pulse within one cycle, whereas the mode selection signal Vselect is a state output that is inverted every cycle. It is. However, the purpose is the same in that both the clock signal Vclk and the mode selection signal Vselect determine Vgb and Vgc at the rising timing.

  FIG. 13 is a diagram showing a step-down mode waveform when the signal generator 10 has a sawtooth waveform. The third embodiment in FIG. 13 is different from the second embodiment in that the sawtooth wave itself is subjected to a voltage level shift, and the comparison voltage is reduced to one Error. Note that the comparator outputs Vby and Vcx are omitted, and the mode selection signal Vselect is used instead, as in FIG. 8 of the second embodiment. The mode selection signal Vselect does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching between the step-down mode and the step-up mode in the step-up / step-down mode. The sawtooth signal Vx has the same function as the triangular wave signal Vx in the prior art. Further, Vbx and Vcy correspond to the comparator outputs Vb and Vc in the prior art, respectively. The sawtooth wave signal Vy is another sawtooth wave signal added according to the present invention, and has a phase relationship opposite to that of the sawtooth wave signal Vx.

  When the sawtooth wave signal Vy always exceeds the comparison voltage Verror and the sawtooth wave signal Vy has an intersection with the comparison voltage Verror, it functions as a step-down mode.

  When the comparison voltage Verror and the sawtooth wave Vx cross, the step-down comparator output Vbx is inverted. On the other hand, since the comparison voltage Verror and the sawtooth wave Vy do not intersect, the boost comparator output Vcy maintains the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 13, an intermediate logic output Vgb is a logic signal that is a source for generating the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In the step-down mode, Vcy is always at the L level, so there is no influence on Vgb and Vgc by the Vselect signal.
As described above, in FIG. 17, Vbx and Vgb are equal, Vgb is equal to Vb, and Va is in opposite phase to Vgb. Similarly, Vcy and Vgc are equal, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON.
As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  FIG. 14 is a diagram showing a boost mode waveform when the waveform of the signal generator 10 is a sawtooth wave. The third embodiment in FIG. 14 is different from the second embodiment in that the sawtooth wave itself is subjected to a voltage level shift, and the comparison voltage is reduced to one Error. The comparator outputs Vby and Vcx are omitted, and the mode selection signal Vselect is used instead, as in FIG. 9 in the second embodiment. The mode selection signal Vselect does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching between the step-down mode and the step-up mode in the step-up / step-down mode. The sawtooth signal Vx has the same function as the triangular wave signal Vx in the prior art. Further, Vbx and Vcy correspond to the comparator outputs Vb and Vc in the prior art, respectively. The sawtooth wave signal Vy is another sawtooth wave signal added according to the present invention, and has a phase relationship opposite to that of the sawtooth wave signal Vx.

  When the sawtooth wave signal Vx is always below the comparison voltage Verror and the sawtooth wave signal Vy has an intersection with the comparison voltage Verror, it functions as a boost mode.

  When the comparison voltage Verror and the sawtooth wave Vy cross, the boost comparator output Vcy is inverted. On the other hand, since the comparison voltage Verror and the sawtooth wave Vx do not cross, the step-down comparator output Vbx maintains the L level. Signals Va, Vb, Vc for controlling the four switches A, B, C, D via the intermediate logic outputs Vgb, Vgc are obtained by performing logic processing on these step-down comparator outputs and step-up comparator outputs. , Vd is generated.

  In FIG. 14, an intermediate logic output Vgb is a logic signal that is a source for generating the drive signal Va of the switch A and the drive signal Vb of the switch B. The drive signal Va of the switch A and the drive signal Vb of the switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

  Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In the step-down mode, Vcy is always at the L level, so there is no influence on Vgb and Vgc by the Vselect signal. Thus, in FIG. 14, Vbx and Vgb are equal, Vgb is equal to Vb, and Va has a phase opposite to Vgb. Similarly, Vcy and Vgc are equal, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly for Vb, Vc, and Vd, switches B, C, and D are in the ON state when they are at the H level, respectively, and conversely, when Vb, Vc, and Vd are at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

  FIG. 15 is a diagram illustrating a step-up / down mode waveform when the waveform of the signal generator 10 is a sawtooth wave. The third embodiment in FIG. 15 differs from the second embodiment in that the sawtooth wave itself is subjected to a voltage level shift and the comparison voltage is reduced to one error. The comparator outputs Vby and Vcx are omitted, and the mode selection signal Vselect is used instead, as in FIG. 10 in the second embodiment. The mode selection signal Vselect does not substantially function in the step-down mode and the step-up mode, but is used as information for alternately switching between the step-down mode and the step-up mode in the step-up / step-down mode. The sawtooth signal Vx has the same function as the triangular wave signal Vx in the prior art. Further, Vbx and Vcy correspond to the comparator outputs Vb and Vc in the prior art, respectively. The sawtooth wave signal Vy is another sawtooth wave signal added according to the present invention, and has a phase relationship opposite to that of the sawtooth wave signal Vx.

  When the sawtooth wave signals Vx and Vy have an intersection with the comparison voltage Verror, it functions as a step-up / step-down mode. In the first cycle, which is the step-down mode, the comparison voltage Verr and the sawtooth waves Vx and Vy cross to invert the step-down comparator outputs Vbx and Vcy. Signals for controlling the four switches A, B, C, and D via the intermediate logic outputs Vgb and Vgc by logically processing these step-down comparator outputs, step-up comparator outputs, and mode selection signal Vselect. Va, Vb, Vc, and Vd are generated.

  In FIG. 15, an intermediate logic output Vgb is a logic signal for generating a drive signal Va for switch A and a drive signal Vb for switch B. The drive signal Va for switch A and the drive signal Vb for switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In FIG. 15, since both Vbx and Vcy are at the H level in the first period, when the Vselect signal is at the H level, Vgb is at the H level and Vgc is at the L level.
Thus, in FIG. 15, in the first period, Vbx and Vgb are equal, Vgb is equal to Vb, and Va is in the opposite phase to Vgb. Conversely, Vcy and Vgc are different, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly, when Vb, Vc, and Vd are each at the H level, the switches B, C, and D are in the ON state, and conversely, when Vb, Vc, and Vd are each at the L level, the switches B, C, and D are in the OFF state. It becomes.

  In the logic processing in the step-down mode, when Va is at H level, Vb is at L level, so that switch A is ON and switch B is OFF. Conversely, when Va is at L level, Vb is at H level, so switch A is OFF and switch B is ON. Since Vc is always L level and Vd is always H level, the switch C is always OFF and the switch D is always ON. As described above, the switch A and the switch B are alternately turned ON / OFF while the switch D of the switch unit of FIG.

  Next, the comparator outputs Vbx and Vcy are inverted by crossing the comparison voltage Verror and the sawtooth waves Vx and Vy in the second period in the boost mode. Signals for controlling the four switches A, B, C, and D via the intermediate logic outputs Vgb and Vgc by logically processing these step-down comparator outputs, step-up comparator outputs, and mode selection signal Vselect. Va, Vb, Vc, and Vd are generated.

  In FIG. 15, an intermediate logic output Vgb is a logic signal for generating a drive signal Va for switch A and a drive signal Vb for switch B. The drive signal Va for switch A and the drive signal Vb for switch B are logical ( H or L) is reversed. Similarly, the intermediate logic output Vgc is a logic signal that is used to generate the drive signal Vc of the switch C and the drive signal Vd of the switch D. The drive signal Vc of the switch C and the drive signal Vd of the switch D are logical (H or L) reverses.

Vselect is a mode selection signal for alternately setting Vgb and Vgc to H level when both Vbx and Vcy are at H level. In FIG. 15, since both Vbx and Vcy are at the H level in the second period, when the Vselect signal is at the L level, Vgc is at the H level and Vgb is at the L level.
As described above, in FIG. 15, Vbx and Vgb are different in the second period, Vgb is equal to Vb, and Va has a phase opposite to Vgb. Conversely, Vcy and Vgc are equal, Vgc is equal to Vc, and Vd is in opposite phase to Vgc.

  When Va is at the H level, the switch A is in the ON state. Conversely, when Va is at the L level, the switch A is in the OFF state. Similarly, when Vb, Vc, and Vd are each at the H level, the switches B, C, and D are in the ON state. Conversely, when Vb, Vc, and Vd are each at the L level, the switches B, C, and D are in the OFF state. It becomes.

In the boost mode logic processing, when Vc is at H level, Vd is at L level, so that switch C is ON and switch D is OFF. Conversely, when Vc is at L level, Vd is at H level, so that switch C is OFF and switch D is ON. Since Va is always at H level and Vb is always at L level, switch A is always ON and switch B is always OFF.
As described above, the switch C and the switch D are alternately turned ON / OFF while the switch A of the switch unit of FIG.

Embodiment 4 FIG.
FIG. 16 is a diagram illustrating an example of an error amplifying circuit that generates the error voltage Verror supplied to the signal processing circuits according to the first to third embodiments of the present invention. In the prior art, an error amplifying circuit 50 using an operational amplifier as shown in FIGS. 17 and 18 is often used. However, the present invention can provide an error amplifying circuit 50 having a small time constant and quick response. . The error amplifier circuit 50 includes a voltage error amplifier 51 and a current error amplifier 52. The voltage error amplifier 51 includes an active filter circuit that amplifies the error voltage.

As shown in FIG. 17, the voltage Vout extracted from the output of the switch unit 4 is divided by the resistance voltage divider 40 and supplied to the error amplification circuit 50 in FIG. 16. In the resistor voltage divider 40, system feedback as a voltage works so that the voltage Vfb obtained by dividing the output voltage Vout of the switch unit 4 by the resistors R1 and R2 is equal to the reference voltage Vref. That is, the output voltage Vout of the switch unit 4 can be set by the relationship between the resistance values R1 and R2 with reference to the reference voltage Vref as shown in Equation 1.

When Expression 1 is modified, the output voltage Vout of the switch unit 4 is expressed by Expression 2.
The reference voltage Vref is often a bandgap voltage having a flat temperature characteristic.

The voltage error amplifier 51 functions as an inverting active filter that provides a filter and an amplifying function for the divided voltage signal Vout by resistors R3, R4 and capacitors C1, C2. The frequency characteristic of the voltage error amplifier 51 as an active filter with respect to the voltage signal Vout can be expressed by Equation 3.

  The voltage error amplifier 52 is an amplifier that adds an error voltage and a current signal. Usually, a large capacitor is connected to Vout in order to smooth the output voltage. Therefore, this capacity is responsible for the time constant as the voltage feedback system, and the voltage feedback system having a large time constant may not be able to follow the transient demand of the current load. Therefore, in the current detector 55, if current is detected from each switching element of the switch unit shown in FIG. A pressure type DC / DC converter can be constructed. The voltage error amplifier 52 can generate an error voltage Verror by adding the current detection level and the error voltage of the voltage error amplifier 51. With such a configuration, it is possible to provide the error amplifying circuit 50 having a small time constant and quick response.

The current error amplifier 52 functions as a non-inverting active filter that provides a filter and an amplifying function to the output voltage Vamp1 of the voltage error amplifier 51 by resistors R5, R6, and a capacitor C3. Similarly, the current detection signal Vsense functions as an inverting active filter that provides a filter and an amplification function by the resistors R5, R6, and the capacitor C3. The frequency characteristic of the current error amplifier 52 with respect to the output voltage Vamp1 of the voltage error amplifier 51 can be expressed by Equation 4.
The frequency characteristic of the current error amplifier 52 with respect to the current detection signal Vsense can be expressed by Equation 5.

  As described above, the combined signal Verror can be obtained from the voltage signal obtained by dividing the output voltage and the current detection signal by the operation of the voltage error amplifier 51 and the current error amplifier 52.

  The above embodiment is an example of a preferred embodiment of the present invention, but the present invention is not limited to this, and various modifications and changes can be made without departing from the scope of the invention.

  The present invention can be applied as a signal processing circuit for a step-up / step-down DC / DC converter that can operate in any operation mode of a step-up operation and a step-down operation.

It is a figure which shows the signal processing circuit of Embodiment 1 of this invention. It is a figure which shows the relationship between Vbx, Vby, Vcx, Vcy and Vgb, Vgc in Embodiment 1 of this invention. It is a figure which shows the pressure | voltage fall mode waveform of Embodiment 1 of this invention. It is a figure which shows the pressure | voltage rise mode waveform of Embodiment 1 of this invention. It is a figure which shows the buck-boost mode waveform of Embodiment 1 of this invention. It is a figure which shows the signal processing circuit of Embodiment 2 of this invention. It is a figure which shows the relationship between Vbx and Vcy and Vgb and Vgc in Embodiment 2 of this invention. It is a figure which shows the pressure | voltage fall mode waveform of Embodiment 2 of this invention. It is a figure which shows the pressure | voltage rise mode waveform of Embodiment 2 of this invention. It is a figure which shows the buck-boost mode waveform of Embodiment 2 of this invention. It is a figure which shows the signal processing circuit of Embodiment 3 of this invention. It is a figure which shows the relationship between Vbx and Vcy and Vgb and Vgc in Embodiment 3 of this invention. It is a figure which shows the pressure | voltage fall mode waveform of Embodiment 3 of this invention. It is a figure which shows the pressure | voltage rise mode waveform of Embodiment 3 of this invention. It is a figure which shows the buck-boost mode waveform of Embodiment 3 of this invention. It is a figure which shows an example of the error amplifier circuit of Embodiment 4 of this invention. It is a figure which shows the whole system of the step-up / step-down type signal processing circuit by a prior art. It is a figure which shows the whole system of the step-up / step-down type signal processing circuit by a prior art. It is a figure which shows the switch unit of the synchronous buck-boost signal processing circuit by a prior art. It is a figure which shows the signal processing circuit by a prior art. It is a figure which shows the relationship between the output signals Vgb and Vgc of the signal processing circuit and the control signals Va, Vb, Vc and Vd for controlling the switches A, B, C and D. It is a figure which shows the pressure | voltage fall mode waveform by a prior art. It is a figure which shows the pressure | voltage rise mode waveform by a prior art. It is a buck-boost mode waveform according to the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal processing circuit 4 Switch unit 10 Signal generation circuit 11 Voltage level shift circuit 12 Waveform generator 20 Comparison circuit 21, 22, 23, 24 Comparator 30 Logic circuit 40 Voltage divider 41 Capacitor 42 Inductance 43 Capacitor 44 Load resistance 50 Error amplifier 51 Voltage Error Amplifier 52 Current Error Amplifier 55 Current Detector 56 Adder

Claims (5)

In a signal processing circuit for a step-up / step-down DC / DC converter,
A voltage level shift circuit for generating a first comparison voltage and a second comparison voltage from an error voltage;
A waveform generator for generating a first waveform and a second waveform signal having a phase reversed from that of the first waveform signal;
A first comparator that compares the first waveform signal with the first comparison voltage and outputs a first comparison signal;
A second comparator that compares the second waveform signal with the first comparison voltage and outputs a second comparison signal;
A third comparator for comparing the first waveform signal with the second comparison voltage and outputting a third comparison signal;
A fourth comparator for comparing the second waveform signal with the second comparison voltage and outputting a fourth comparison signal;
A logic circuit for generating an intermediate logic output based on the first comparison signal to the fourth comparison signal;
A signal processing circuit for a step-up / step-down DC / DC converter, wherein the switch unit is controlled based on an intermediate logic output from the logic circuit. In a signal processing circuit for a step-up / step-down DC / DC converter,
A voltage level shift circuit for generating a first comparison voltage and a second comparison voltage from an error voltage;
A waveform generator for generating a first waveform and a second waveform signal having a phase reversed from that of the first waveform signal;
A first comparator that compares the first waveform signal with the first comparison voltage and outputs a first comparison signal;
A second comparator that compares the second waveform signal with the second comparison voltage and outputs a second comparison signal;
A logic circuit for generating an intermediate logic output based on the first comparison signal and the second comparison signal;
A signal processing circuit for a step-up / step-down DC / DC converter, wherein the switch unit is controlled based on an intermediate logic output from the logic circuit. In a signal processing circuit for a step-up / step-down DC / DC converter,
A voltage level shift circuit for generating a first comparison voltage and a second comparison voltage from an error voltage;
A waveform generator for generating a first waveform and a second waveform signal having a phase reversed from that of the first waveform signal;
A first voltage level shift circuit for shifting the voltage level of the first waveform signal;
A first comparator that compares an output of the first voltage level shift circuit with the first comparison voltage and outputs a first comparison signal;
A second voltage level shift circuit for shifting the voltage level of the second waveform signal;
A second comparator that compares the output of the second voltage level shift circuit with the second comparison voltage and outputs a second comparison signal;
A logic circuit for generating an intermediate logic output based on the first comparison signal and the second comparison signal;
A signal processing circuit for a step-up / step-down DC / DC converter, wherein the switch unit is controlled based on an intermediate logic output from the logic circuit.   4. The signal processing circuit for a step-up / step-down DC / DC converter according to claim 1, wherein the waveform generator generates a triangular wave or a sawtooth wave. In addition, an error amplification circuit is provided,
The error amplifier circuit compares a voltage divided by the resistor voltage divider with a reference voltage, detects a current from each switching element of the switch unit, and detects the current detection level and the output of the voltage error amplifier. 5. A signal processing circuit for a step-up / step-down DC / DC converter according to any one of claims 1 to 4, characterized in that the signal processing circuit comprises a current error amplifier for summing the two.