JP2009077042A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2009077042A5 JP2009077042A5 JP2007242553A JP2007242553A JP2009077042A5 JP 2009077042 A5 JP2009077042 A5 JP 2009077042A5 JP 2007242553 A JP2007242553 A JP 2007242553A JP 2007242553 A JP2007242553 A JP 2007242553A JP 2009077042 A5 JP2009077042 A5 JP 2009077042A5
- Authority
- JP
- Japan
- Prior art keywords
- synchronization signal
- signal
- video
- switching
- delayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 15
- 230000003111 delayed Effects 0.000 claims 13
- 230000000875 corresponding Effects 0.000 claims 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 6
- 238000005259 measurement Methods 0.000 claims 2
Claims (6)
第１の映像信号に対応する第１の同期信号と、前記第１の映像信号とフレームレートの異なる第２の映像信号に対応する第２の同期信号とを、ユーザによる前記第１の映像信号から前記第２の映像信号への切り換え操作に応じて切り換えて出力する第１の切り換え手段と、
前記第１の切り換え手段から出力された同期信号の間隔をクロック数により計測する計測手段と、
前記計測手段により計測されたクロック数を用いて、前記第１の切り換え手段から出力された同期信号よりも少なくとも１周期分遅延した遅延同期信号を生成する遅延同期信号生成部と、
前記第１の同期信号および前記第２の同期信号のいずれよりも間隔の長い同期信号である内部同期信号を生成する内部同期信号生成部と、
前記計測手段により計測されたクロック数が予め決められた範囲に含まれるか否かを判別する判別手段と、
前記計測されたクロック数が予め決められた範囲に含まれないと判別された場合、前記第１の同期信号から少なくとも１周期分遅延された遅延同期信号と、前記第２の同期信号から少なくとも１周期分遅延された遅延同期信号との間に前記内部同期信号が挿入されるように前記遅延同期信号と前記内部同期信号とを切り換えて出力する第２の切り換え手段とを有する
ことを特徴とする映像処理装置。 In a video processing apparatus that processes and outputs a video signal and a synchronization signal,
A first synchronization signal corresponding to a first video signal and a second synchronization signal corresponding to a second video signal having a frame rate different from that of the first video signal are used as the first video signal by a user. a first switching means you output is switched in response to the switching operation to the second video signal from,
Measuring means for measuring the interval of the synchronization signal output from the first switching means by the number of clocks;
A delay synchronization signal generation unit that generates a delay synchronization signal delayed by at least one cycle from the synchronization signal output from the first switching unit, using the number of clocks measured by the measurement unit ;
An internal synchronization signal generating unit that generates an internal synchronization signal that is a synchronization signal having a longer interval than either of the first synchronization signal and the second synchronization signal ;
Determining means for determining whether or not the number of clocks measured by the measuring means is included in a predetermined range;
When it is determined that the measured number of clocks is not included in a predetermined range, a delay synchronization signal delayed by at least one cycle from the first synchronization signal and at least one from the second synchronization signal And a second switching means for switching and outputting the delayed synchronization signal and the internal synchronization signal so that the internal synchronization signal is inserted between the delayed synchronization signal delayed by a period. Video processing device.
ことを特徴とする請求項１に記載の映像処理装置。 The range of the predetermined number of clocks used for determination by the determination means is at least from the smaller value of the number of clocks required for the interval between the first synchronization signal and the second synchronization signal. The video processing apparatus according to claim 1, comprising a range up to a larger value .
ことを特徴とする請求項１または２に記載の映像処理装置。 To obtain the number of clocks of the synchronization signal outputted from said second switching means, the image processing apparatus according to claim 1 or 2, characterized in <br/> further have a holding means for holding a predetermined period .
第１の映像信号に対応する第１の同期信号と、第２の映像信号に対応し、前記第１の同期信号と位相の異なる第２の同期信号とを、ユーザによる前記第１の映像信号から前記第２の映像信号への切り換え操作に応じて切り換えて出力する第１の切り換え手段と、
遅延同期信号を生成する遅延同期信号生成部と、
予め決められた周期の内部同期信号を生成する内部同期信号生成部と、
前記第１の同期信号に基づく同期信号と、前記第２の同期信号に基づく同期信号との間に前記内部同期信号が挿入されるように前記遅延同期信号と前記内部同期信号とを切り換えて出力する第２の切り換え手段と、
前記第１の切り換え手段から出力される同期信号と前記第２の切り換え手段から出力される同期信号との位相を比較して位相差情報を出力する位相比較部とを有し、
前記遅延同期信号生成部は、前記位相比較部による位相差情報に基づいて、前記第１の切り換え手段から出力される同期信号との位相差を徐々に減少させるように遅延同期信号の生成を行う
ことを特徴とする映像処理装置。 In a video processing apparatus that processes and outputs a video signal and a synchronization signal,
A first synchronization signal corresponding to a first video signal, and a second synchronization signal corresponding to a second video signal and having a phase different from that of the first synchronization signal are used as the first video signal by a user. a first switching means you output is switched in response to the switching operation to the second video signal from,
A delay synchronization signal generator for generating a delay synchronization signal;
An internal synchronization signal generator for generating an internal synchronization signal having a predetermined period;
The delayed synchronization signal and the internal synchronization signal are switched and output so that the internal synchronization signal is inserted between the synchronization signal based on the first synchronization signal and the synchronization signal based on the second synchronization signal. Second switching means for
A phase comparison unit that compares the phases of the synchronization signal output from the first switching unit and the synchronization signal output from the second switching unit and outputs phase difference information;
The delay locked signal generation unit, based on the phase difference information by the phase comparison unit, the generation of pre-Symbol gradually delayed sync signal to reduce the phase difference between the synchronizing signal output from the first switching means An image processing apparatus characterized in that:
第１の切り換え手段が、第１の映像信号に対応する第１の同期信号と、前記第１の映像信号とフレームレートの異なる第２の映像信号に対応する第２の同期信号とを、ユーザによる前記第１の映像信号から前記第２の映像信号への切り換え操作に応じて切り換えて出力するプロセスと、 The first switching means selects a first synchronization signal corresponding to the first video signal and a second synchronization signal corresponding to a second video signal having a frame rate different from that of the first video signal. A process of switching and outputting in accordance with a switching operation from the first video signal to the second video signal by:
計測手段が、前記第１の切り換え手段から出力された同期信号の間隔をクロック数により計測するプロセスと、 A process in which the measuring means measures the interval of the synchronization signal output from the first switching means by the number of clocks;
遅延同期信号生成部が、前記計測手段により計測されたクロック数を用いて、前記第１の切り換え手段から出力された同期信号よりも少なくとも１周期分遅延した遅延同期信号を生成するプロセスと、 A process in which a delay synchronization signal generation unit generates a delay synchronization signal delayed by at least one cycle from the synchronization signal output from the first switching unit using the number of clocks measured by the measurement unit;
内部同期信号生成部が、前記第１の同期信号および前記第２の同期信号のいずれよりも間隔の長い同期信号である内部同期信号を生成するプロセスと、 A process in which an internal synchronization signal generation unit generates an internal synchronization signal that is a synchronization signal having a longer interval than either of the first synchronization signal and the second synchronization signal;
判別手段が、前記計測手段により計測されたクロック数が予め決められた範囲に含まれるか否かを判別するプロセスと、 A process of determining whether or not the determining unit includes a clock number measured by the measuring unit within a predetermined range;
前記計測されたクロック数が予め決められた範囲に含まれないと判別された場合、第２の切り換え手段が、前記第１の同期信号から少なくとも１周期分遅延された遅延同期信号と、前記第２の同期信号から少なくとも１周期分遅延された遅延同期信号との間に前記内部同期信号が挿入されるように前記遅延同期信号と前記内部同期信号とを切り換えて出力するプロセスとを有する When it is determined that the measured number of clocks is not included in a predetermined range, the second switching unit includes a delay synchronization signal delayed by at least one period from the first synchronization signal, A process of switching and outputting the delayed synchronization signal and the internal synchronization signal so that the internal synchronization signal is inserted between the two synchronization signals and a delayed synchronization signal delayed by at least one cycle.
ことを特徴とする映像処理装置の制御方法。A control method for a video processing apparatus.
第１の切り換え手段が、第１の映像信号に対応する第１の同期信号と、第２の映像信号に対応し、前記第１の同期信号と位相の異なる第２の同期信号とを、ユーザによる前記第１の映像信号から前記第２の映像信号への切り換え操作に応じて切り換えて出力するプロセスと、 The first switching means selects a first synchronization signal corresponding to the first video signal and a second synchronization signal corresponding to the second video signal and having a phase different from that of the first synchronization signal. A process of switching and outputting in accordance with a switching operation from the first video signal to the second video signal by:
遅延同期信号生成部が、遅延同期信号を生成するプロセスと、 A process in which the delay synchronization signal generation unit generates the delay synchronization signal;
内部同期信号生成部が、予め決められた周期の内部同期信号を生成するプロセスと、 A process in which the internal synchronization signal generator generates an internal synchronization signal having a predetermined period;
第２の切り換え手段が、前記第１の同期信号に基づく同期信号と、前記第２の同期信号に基づく同期信号との間に前記内部同期信号が挿入されるように前記遅延同期信号と前記内部同期信号とを切り換えて出力するプロセスと、 A second switching unit configured to insert the internal synchronization signal between the synchronization signal based on the first synchronization signal and the synchronization signal based on the second synchronization signal; A process of switching and outputting the synchronization signal;
位相比較部が、前記第１の切り換え手段から出力される同期信号と前記第２の切り換え手段から出力される同期信号との位相を比較して位相差情報を出力するプロセスとを有し、 A phase comparison unit that compares the phase of the synchronization signal output from the first switching unit and the phase of the synchronization signal output from the second switching unit and outputs phase difference information;
前記遅延同期信号を生成するプロセスにおいて、前記遅延同期信号生成部は、前記位相比較部による位相差情報に基づいて、前記第１の切り換え手段から出力される同期信号との位相差を徐々に減少させるように遅延同期信号の生成を行う In the process of generating the delay synchronization signal, the delay synchronization signal generation unit gradually reduces the phase difference from the synchronization signal output from the first switching unit based on the phase difference information from the phase comparison unit. To generate a delayed synchronization signal
ことを特徴とする映像処理装置の制御方法。A control method for a video processing apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007242553A JP5020754B2 (en) | 2007-09-19 | 2007-09-19 | Video processing apparatus and control method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007242553A JP5020754B2 (en) | 2007-09-19 | 2007-09-19 | Video processing apparatus and control method thereof |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009077042A JP2009077042A (en) | 2009-04-09 |
| JP2009077042A5 true JP2009077042A5 (en) | 2010-11-04 |
| JP5020754B2 JP5020754B2 (en) | 2012-09-05 |
Family
ID=40611620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007242553A Expired - Fee Related JP5020754B2 (en) | 2007-09-19 | 2007-09-19 | Video processing apparatus and control method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5020754B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5375492B2 (en) * | 2009-09-29 | 2013-12-25 | セイコーエプソン株式会社 | Display controller and electronic device |
| JP5614977B2 (en) * | 2009-11-27 | 2014-10-29 | 三菱電機株式会社 | Video display device |
| JP5768383B2 (en) * | 2011-01-24 | 2015-08-26 | セイコーエプソン株式会社 | Image display device and image display method |
| WO2012111064A1 (en) * | 2011-02-14 | 2012-08-23 | Ｎｅｃディスプレイソリューションズ株式会社 | Video signal monitoring device and video display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3676258B2 (en) * | 2001-05-22 | 2005-07-27 | 松下電器産業株式会社 | Synchronous control circuit |
| JP2004235715A (en) * | 2003-01-28 | 2004-08-19 | Matsushita Electric Ind Co Ltd | Image signal switching device |
| JP4508583B2 (en) * | 2003-09-05 | 2010-07-21 | 三洋電機株式会社 | Liquid crystal display controller |
-
2007
- 2007-09-19 JP JP2007242553A patent/JP5020754B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008157971A5 (en) | ||
| JP2018191226A5 (en) | Synchronous signal output device, adjustment method, and program | |
| JP4032421B2 (en) | Measurement data synchronization system | |
| JP6799369B2 (en) | How to synchronize a test measurement system and multiple oscilloscopes | |
| JP2011055048A5 (en) | ||
| JP6170311B2 (en) | Imaging apparatus and control method thereof | |
| JP2008541619A5 (en) | ||
| TW200736642A (en) | Test equipment, test method and recording media | |
| JP5207748B2 (en) | Measuring apparatus, measuring method and test apparatus | |
| JP2009077042A5 (en) | ||
| TW200736639A (en) | Measuring apparatus, measuring method, testing apparatus, testing method, and electronics device | |
| JP2006041818A5 (en) | ||
| JP2014165755A5 (en) | ||
| US7535982B2 (en) | Method and apparatus for adjusting phase of sampling frequency of ADC | |
| JP2010244399A (en) | Data transfer device and image capturing apparatus | |
| JP2010061458A5 (en) | ||
| US10057524B2 (en) | Image capturing apparatus | |
| JP2017163449A5 (en) | ||
| JP4504714B2 (en) | External synchronization signal generation circuit and phase difference measurement circuit | |
| JP2009175053A (en) | Device and method for detecting change point of measured signal, and testing device | |
| JP2009216617A (en) | Sampling clock generation circuit and alternating current signal measuring device | |
| TW201347413A (en) | Delay-locked loop and method for a delay-locked loop generating an application clock | |
| TWI400596B (en) | Synchronized receiving circuit and method thereof | |
| JP4675992B2 (en) | Synchronous signal generator for video signal | |
| JP2005278088A5 (en) |