JP2009076810A - Method of manufacturing semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor apparatus, which forms a compact film pattern without forming a constriction even when using a Levenson-type mask. <P>SOLUTION: The method of manufacturing a semiconductor apparatus includes: a step (S104) of forming a film to be processed on a substrate; a step (S114) of forming a non-finest film pattern on the film to be processed; a step (S116) of exposing a finest pattern by using a Levenson-type mask so that the edge of the finest pattern overlaps with the edge of the non-finest film pattern, after the non-finest film pattern is formed; steps (S118-S122) of forming a finest film pattern having the finest pattern width, after the finest pattern is exposed; and a step (S126) of etching the film to be processed so that the non-finest film pattern and the finest film pattern are transferred. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, for example, a method for manufacturing a semiconductor device including a step of forming a gate film.

  In recent years, further miniaturization has been demanded along with higher integration and higher performance of semiconductor integrated circuits (LSIs). In particular, it is required to make the gate electrode formed in the element region and the contact portion formed outside the element isolation boundary compact with the miniaturization of the semiconductor element. For this reason, shape control particularly at the edge of the gate pattern has become a problem.

  Conventionally, a gate electrode and a contact part are formed as follows, for example. First, a film that becomes a mask material is deposited on a film to be processed that becomes a gate electrode material. Then, the gate pattern is exposed on the mask material using a Levenson type mask, and a resist pattern is formed by development. Then, the mask material is etched using this resist pattern as an etching mask. Then, the resist is peeled off, and this time, the pattern covering the contact pattern and the gate pattern to be left is exposed. Then, using the obtained resist pattern as a mask, excess mask material is etched. Thereafter, the resist is removed to obtain a mask for etching the gate electrode material. The gate electrode material is etched using the mask thus obtained to form a gate electrode and a contact portion connected to the end of the gate electrode.

  Here, in the exposure of the gate pattern that is the finest pattern in the layer of the gate electrode material, a Levenson type mask that can be phase-shifted to increase the resolution is used to obtain a fine pattern. However, when a Levenson-type mask is used, for example, a rectangular closed pattern is exposed due to its characteristics. Then, when etching is performed using the obtained resist pattern as a mask, the corner or curved portion located at the end of the closed pattern swells and the size of the portion increases. When the space between adjacent closed patterns is used as the gate pattern, there is a problem that the end of the gate pattern is constricted due to the swelling from both sides, and the size is reduced. This constriction becomes a serious problem in device characteristics even if it is several nanometers, and degrades transistor characteristics. Therefore, in order to obtain a highly accurate gate electrode, this constricted portion cannot be formed in the element region. Therefore, in the conventional method, it has been necessary to lay out so that the constricted portion is located outside the element isolation boundary. As a result, the element isolation region must be made larger by the constricted portion, which has been a factor that hinders downsizing.

In addition, after exposing and etching the gate pattern with a Levenson-type mask, the region including the end of the gate pattern of the obtained hard mask is cut, and then the rectangular resist pattern for contact orthogonal to the gate pattern is cut. A method of forming a connection with a portion is also disclosed in the literature (see, for example, Patent Document 1). Thereafter, the polysilicon (Si) film as the gate electrode material is etched using the gate pattern of the hard mask and the rectangular resist pattern as a mask. However, in the method of Patent Document 1, since the gate pattern is exposed and etched with a Levenson-type mask, the above-described constriction or swelling occurs at the end of the gate pattern. Therefore, a step of cutting this dimensional error portion is required before connecting with the rectangular pattern. Further, in the method of Patent Document 1, the poly Si film must be etched in a state where a hard mask and a resist pattern mask are mixed, and it becomes difficult to adjust process conditions during etching.
JP 2007-123342 A (FIGS. 4 to 9)

  An object of the present invention is to provide a method for manufacturing a semiconductor device that overcomes the above-described conventional problems and forms a compact film pattern without forming a constricted portion even when a Levenson-type mask is used. To do.

A method for manufacturing a semiconductor device of one embodiment of the present invention includes:
Forming a film to be processed on the substrate;
Forming a non-thinnest film pattern on the film to be processed;
After forming the non-thinnest film pattern, exposing the thinnest pattern using a Levenson-type mask so that the position of the end portion overlaps the non-thinnest film pattern;
Forming the thinnest film pattern of the finest pattern width outside the region where the non-thinnest film pattern is formed after the thinnest pattern is exposed;
Etching the film to be processed so that the thinnest film pattern and the thinnest film pattern are transferred;
It is provided with.

  According to the present invention, a compact film pattern can be formed without forming a constricted portion.

Embodiment 1 FIG.
The first embodiment will be described below with reference to the drawings.
FIG. 1 is a flowchart showing the main part of the semiconductor device manufacturing method according to the first embodiment.
1, in the method of manufacturing the semiconductor device of the first embodiment, a gate oxide film forming step (S102), a poly Si film forming step (S104), a silicon oxide (SiO ₂ ) film forming step (S106), Amorphous silicon (α-Si) film forming step (S108), SiO ₂ film forming step (S110), exposure / development step (S112), SiO ₂ film etching step (S114), and exposure / development step (S116) ), Α-Si film etching step (S118), exposure / development step (S120), α-Si film etching step (S122), SiO ₂ film etching step (S124), and poly Si film etching step ( A series of steps of S126) and SiO ₂ film etching step (S128) are performed.

FIG. 2 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 2 shows from the gate oxide film forming step (S102) to the α-Si film forming step (S108) in FIG.

In FIG. 2A, as a gate oxide film formation step (S102), by supplying a raw material such as dry oxygen (O ₂ ) gas to the surface of the substrate 200 after forming the element isolation region and heating it, for example, A gate insulating film 202 is formed by depositing a thin film of SiO ₂ film having a thickness of 1.8 nm. Here, the film is formed by dry O ₂ gas, but other methods may be used. As the substrate 200, for example, a silicon wafer having a diameter of 300 mm is used. Here, illustration and description of steps such as element isolation are omitted.

  In FIG. 2B, as a poly-Si film formation step (S104), for example, poly-Si serving as a gate electrode material with a film thickness of 100 nm is deposited on the gate insulating film 202 by a CVD (chemical vapor deposition) method. Then, a poly-Si film 204 (film to be processed) is formed. Here, the film is formed by the CVD method, but other methods may be used.

In FIG. 2 (c), as the SiO ₂ film forming step (S106), on the poly-Si film 204 by the CVD method, for example, SiO ₂ is deposited as the first mask material film thickness 50 nm, SiO ₂ film 206 (first film) is formed. Here, the film is formed by the CVD method, but other methods may be used. As the SiO ₂ film 206, for example, a tetraethoxysilane (TEOS) film is preferably used. In addition to SiO ₂ , silicon nitride (Si ₃ N ₄ ), borosilicate glass (BSG), or phosphosilicate glass (PSG) is preferably used as the first mask material.

In FIG. 2D, as the α-Si film forming step (S108), α-Si serving as a second mask material having a film thickness of, for example, 30 nm is deposited on the SiO ₂ film 206 by the CVD method. A Si film 208 (second film) is formed. Here, the film is formed by the CVD method, but other methods may be used. In addition to α-Si, poly Si may be preferably used as the second mask material. Further, it is preferable that the film thickness of the α-Si film 208 is smaller than the film thickness of the poly-Si film 204.

FIG. 3 is a process sectional view showing a process performed corresponding to the flowchart of FIG.
FIG. 3 shows the SiO ₂ film formation step (S110) of FIG.

3, the SiO ₂ film forming step (S110), on the alpha-Si film 208 by the CVD method, for example, SiO ₂ is deposited as a third mask material film thickness 30 nm, SiO ₂ film 210 ( A third film) is formed. Here, the film is formed by the CVD method, but other methods may be used. As the SiO ₂ film 210, for example, a TEOS film is preferably used similarly to the SiO ₂ film 206. Further, as a third mask material, in addition to SiO _2, similarly to the SiO ₂ film _206, Si ₃ N 4, BSG, or it is also preferable using PSG.

  As described above, in the first embodiment, the first to third mask material films are stacked. By laminating these films, it is possible to use only a hard mask as a mask used for etching a poly-Si film 204 described later. Therefore, it is possible to avoid a mixture of a hard mask and a resist pattern mask. As a result, the etching process conditions can be easily adjusted.

FIG. 4 is a process top view showing an exposure / development process performed corresponding to the flowchart of FIG. The following description will be made with reference to the top view for easy understanding of the technical contents to be described.
In FIG. 4, as an exposure / development step (S112), a contact pattern is exposed by a lithography technique on the SiO ₂ film 210 coated with a resist film (not shown). Then, development is performed to form a resist pattern 212 for a contact region that finally becomes a lead-out portion from the gate electrode.

FIG. 5 is a process top view showing the SiO ₂ film etching process performed corresponding to the flowchart of FIG.
In FIG. 5, as the SiO ₂ film etching step (S114), the SiO ₂ film 210 is etched using the resist pattern 212 as a mask. By removing the exposed SiO ₂ film 210 by an anisotropic etching method, etching can be performed substantially perpendicular to the surface of the substrate 200. For example, as an example, it is preferable to use a reactive ion etching method. Then, the resist pattern 212 is peeled off by ashing or the like, thereby forming a contact pattern SiO ₂ film 210 on the α-Si film 208 as shown in FIG. In this way, a non-thinnest film pattern is formed on the poly-Si film 204.

FIG. 6 is a process top view showing an exposure / development process performed corresponding to the flowchart of FIG.
In FIG. 6, as the exposure / development step (S116), after applying a resist on the substrate 200, using the Levenson mask, the finest pattern is formed so that the position of the end portion overlaps the SiO ₂ film 210 of the contact pattern. The resulting gate pattern is exposed by lithography. The longitudinal direction of the gate pattern is arranged in a direction orthogonal to the longitudinal direction of the contact pattern. By using a Levenson mask, the resolution can be improved. This is particularly effective when exposing the finest pattern in a desired layer such as a gate pattern. Here, a space between the closed patterns peculiar to the Levenson-type mask is used as the gate pattern. In FIG. 6, a plurality of gate patterns including a pattern in which the end portion overlaps with the contact pattern are exposed. Thereafter, development is performed to form a resist pattern 214 including a gate pattern portion.

FIG. 7 is a process top view showing an α-Si film etching process performed corresponding to the flowchart of FIG. 1.
7, in the α-Si film etching step (S118), the α-Si film 208 is etched outside the region where the non-thinned film pattern of the SiO ₂ film 210 is formed using the resist pattern 214 as a mask. By removing the exposed α-Si film 208 by anisotropic etching, etching can be performed substantially perpendicularly to the surface of the substrate 200. Here, for example, it is preferable to use a reactive ion etching method as an example. When the α-Si film 208 is etched, it is desirable to perform the etching under conditions such that the selection ratio with the SiO ₂ films 206 and 210 is sufficient. For example, mixed as an etching ^gas, and oxygen gas _{(O 2)} of 0.25Pa · m 3 / s hydrogen bromide (HBr) gas (150 sccm) and ^{5 × 10 -3 Pa · m 3} / s (3sccm) Use gas. Further, for example, using an ICP type dry etching apparatus, it is preferable that the pressure in the reaction vessel is 2 Pa (15 mTorr), the source power is 400 W, and the bias power is 50 W. Then, after etching, the resist pattern 214 is removed by ashing or the like, thereby forming an α-Si film 208 including a gate pattern portion connected to the contact pattern as shown in FIG.

FIG. 8 is a diagram showing an example comparing the gate pattern shape after etching and the conventional gate pattern shape after etching in the first embodiment.
If the gate pattern is exposed and etched first as in the prior art, a recess 30 is formed at the end of the gate pattern 20. Therefore, the recess 30 must be arranged outside the element isolation boundary. As a result, the contact pattern 24 is arranged on the outer side by the amount of the recess 30. On the other hand, in the first embodiment, after the contact pattern 14 is formed, the gate pattern 10 is exposed so that the tip portion of the gate pattern 10 overlaps with the contact pattern 14, so that a dent that should be caused by etching does not occur. Therefore, the contact pattern 14 can be brought close to the element isolation boundary. As a result, the semiconductor device can be made compact by the dimension L.

FIG. 9 is a process top view showing an exposure / development process performed corresponding to the flowchart of FIG.
In FIG. 9, as an exposure / development step (S <b> 120), after applying a resist on the substrate 200, a pattern is exposed by a lithography technique so as to cover a portion to be left using a phase shift mask. At that time, pattern exposure (second exposure) is performed so as to select a part to be actually used from a plurality of gate patterns. FIG. 9 shows an example in which exposure is performed so that two of the three gate patterns are selected. Thereafter, development is performed to form a resist pattern 216 of a set of a gate pattern and a contact pattern to be left as a pattern. That is, in FIG. 9, the resist pattern 216 is formed so as to leave two sets of gate patterns and contact patterns. Here, in order to select the finest pattern, it is preferable to use a high-resolution phase shift mask as a photomask. For example, a halftone mask that does not have a closed pattern such as a Levenson-type mask is desirable.

FIG. 10 is a process top view showing an α-Si film etching process performed corresponding to the flowchart of FIG.
In FIG. 10, as the α-Si film etching step (S122), the α-Si film 208 is etched using the resist pattern 216 as a mask. By removing the exposed α-Si film 208 by anisotropic etching, etching can be performed substantially perpendicularly to the surface of the substrate 200. Here, for example, it is preferable to use a reactive ion etching method as an example. Then, after etching, the resist pattern 216 is peeled off by ashing or the like, thereby forming a desired contact pattern SiO ₂ film 210 and a gate pattern α-Si film 208 as shown in FIG. By this etching, an unnecessary gate pattern portion can be removed. Further, as shown in FIG. 10, an α-Si film 208 may be partially used for the contact pattern.

FIG. 11 is a process top view showing the SiO ₂ film etching process performed corresponding to the flowchart of FIG.
In FIG. 11, as the SiO ₂ film etching step (S124), the SiO ₂ film 206 is etched using the contact pattern SiO ₂ film 210 and the gate pattern α-Si film 208 obtained in the previous step as a hard mask. . By removing the exposed SiO ₂ film 206 by anisotropic etching, etching can be performed substantially perpendicularly to the surface of the substrate 200. Here, for example, it is preferable to use a reactive ion etching method as an example. Further, the SiO ₂ film 210 was formed on the surface of the contact pattern, so had been thinner than SiO ₂ film 206 can be etched together when etching the SiO ₂ film 206. As a result, as shown in FIG. 11, an α-Si film 208 in which the desired contact pattern and the gate pattern are connected can be formed on the poly-Si film 204 as the gate electrode material.

FIG. 12 is a process top view showing a poly-Si film etching process performed corresponding to the flowchart of FIG.
In FIG. 12, as the poly-Si film etching step (S126), the film pattern of the contact α-Si film 208 and the film pattern of the gate α-Si film 208 obtained in the previous step are used as a hard mask. The poly Si film 204 to be a film is etched. By removing the exposed poly-Si film 204 by an anisotropic etching method, etching can be performed substantially perpendicular to the surface of the substrate 200. Here, for example, it is preferable to use a reactive ion etching method as an example. Further, since the α-Si film 208 formed on the surface of the contact pattern is formed thinner than the poly-Si film 204, it can be etched together when the poly-Si film 204 is etched. As a result, as shown in FIG. 12, the gate pattern of the thinnest film pattern and the contact pattern of the non-thinnest film pattern are transferred in the poly-Si film 204 as the gate electrode material, and the gate electrode region and the upper layer (not shown) are transferred. A contact region for connecting to the conductor can be formed. Here, since etching is performed using only a hard mask, a resist pattern mask is not mixed. Etching process conditions can be easily adjusted by not mixing the resist pattern mask.

FIG. 13 is a process sectional view showing a SiO ₂ film etching process performed corresponding to the flowchart of FIG.
In FIG. 13, as the SiO ₂ film etching step (S128), the SiO ₂ film 206 on the poly Si film 204 is removed by wet etching as necessary to expose the poly Si film 204 as shown in FIG. be able to. At this time, unnecessary gate insulating film material is removed together with the SiO ₂ film 206.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  Further, the size, shape, number, etc. of the thinnest film pattern and the non-thinnest film pattern can be appropriately selected and used for those required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, all semiconductor devices and methods of manufacturing a semiconductor device that include elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention.

  Further, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques may be included.

3 is a flowchart showing a main part of a method for manufacturing a semiconductor device in the first embodiment. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. It is process sectional drawing showing the process implemented corresponding to the flowchart of FIG. FIG. 2 is a process top view illustrating an exposure / development process performed in accordance with the flowchart of FIG. 1. FIG. ₂ is a process top view showing a SiO ₂ film etching process performed corresponding to the flowchart of FIG. 1. FIG. 2 is a process top view illustrating an exposure / development process performed in accordance with the flowchart of FIG. 1. FIG. 6 is a process top view illustrating an α-Si film etching process performed corresponding to the flowchart of FIG. 1. It is a figure which shows an example which compared the gate pattern shape after the etching in Embodiment 1, and the gate pattern shape after the conventional etching. FIG. 2 is a process top view illustrating an exposure / development process performed in accordance with the flowchart of FIG. 1. FIG. 6 is a process top view illustrating an α-Si film etching process performed corresponding to the flowchart of FIG. 1. FIG. ₂ is a process top view showing a SiO ₂ film etching process performed corresponding to the flowchart of FIG. 1. FIG. 7 is a process top view showing a poly-Si film etching process performed corresponding to the flowchart of FIG. 1. It is a process cross-sectional views showing the SiO ₂ film etching processes performed corresponding to the flow chart of FIG.

Explanation of symbols

10, 20 Gate pattern 14, 24 Contact pattern 200 Substrate 204 Poly Si film 206, 210 SiO ₂ film 208 α-Si film

Claims (5)

Forming a film to be processed on the substrate;
Forming a non-thinnest film pattern on the film to be processed;
After forming the non-thinnest film pattern, exposing the thinnest pattern using a Levenson-type mask so that the position of the end portion overlaps the non-thinnest film pattern;
Forming the thinnest film pattern of the finest pattern width outside the region where the non-thinnest film pattern is formed after the thinnest pattern is exposed;
Etching the film to be processed so that the thinnest film pattern and the thinnest film pattern are transferred;
A method for manufacturing a semiconductor device, comprising:   2. The method of claim 1, further comprising: forming a laminated film used for the non-thinnest film pattern and the thinnest film pattern on the substrate before the non-thinnest film pattern is formed. The manufacturing method of the semiconductor device of description. The laminated film is composed of first, second, and third films in order from the lower layer side,
The non-thinnest film pattern is formed on the third film, the thinnest film pattern is formed on the second film,
The third film used for the non-thinnest film pattern is etched together with the first film, and the second film used for the thinnest film pattern is etched together with the film to be processed. The method of manufacturing a semiconductor device according to claim 2. A plurality of finest patterns including the finest pattern are exposed,
4. The manufacturing of a semiconductor device according to claim 1, wherein when forming the thinnest film pattern, second exposure is performed to select a part of the plurality of thinnest patterns. 5. Method. The thinnest film pattern is used as a mask for forming a gate electrode region,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the non-thinnest film pattern is used as a mask for forming a contact region connected to an upper conductor.

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