JP2009076596A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent separation between an interlayer insulating film and a phase transformation film which constituts a memory layer of a phase transformation memory, and to prevent such a malfunction as the diffusion of constituent atoms of an adhesive layer interposed between the interlayer insulating film, and the diffusion of the phase transformation film in the phase transformation film to fluctuate characteristics of the phase transformation film. <P>SOLUTION: Resistive elements RM1 and RM2 are formed on an interlayer insulating film 20. Each of the resistive elements RM1 and RM2 is constituted of a plug 23 (lower electrode) and an adhesive layer 24, a memory layer 25, and an upper electrode 26 stacked on it. The adhesive layer 24 is formed to prevent interfacial delamination between the memory layer 25 and the interlayer insulating film 20, but the adhesive layer 24 is not formed on the upper surface of the plug 23 (lower electrode). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to a semiconductor device including a nonvolatile phase change memory.

  In recent years, a phase-change random access memory (PRAM) using a phase change material such as chalcogenide has been proposed as a next-generation nonvolatile semiconductor memory. Although this phase change memory is non-volatile, writing and reading operations are expected to be as fast as DRAM (Dynamic Random Access Memory), and the cell area can be reduced to the same extent as flash memory. Therefore, it is regarded as the most promising next-generation nonvolatile memory.

Phase change materials used for phase change memories are already used in optical disc media such as DVDs (Digital Versatile Discs). In the case of DVDs, the phase change materials have different light reflectivities depending on whether they are in an amorphous state or in a crystalline state. Utilizes characteristics. For example, in US Pat. No. 5,254,382 (Patent Document 1), [(Ge _y Te _1-y ) _a (Sb _z Te _1-z ) _1-a ] _1-b (In _1-x Te _x ) is used as a recording layer. _b (where 0.4 ≦ y ≦ 0.6, 0.3 ≦ z ≦ 0.6, 0.4 ≦ z ≦ 0.6, 0.1 ≦ a ≦ 0.5, 0.01 ≦ b An optical disc medium using a phase change material represented by ≦ 0.3) is disclosed. The purpose of this is to improve the stability of the amorphous state and improve the long-term storage of data while maintaining the property that crystallization is possible at high speed. Ge (germanium) -Sb (antimony) -In (indium) added to Te (tellurium).

  On the other hand, in the case of a phase change memory, the phase change material is operated as a memory element by utilizing the characteristic that the electric resistance is different by several orders of magnitude between the amorphous state and the crystalline state. The phase change memory switching, that is, the phase change from the amorphous state to the crystalline state of the phase change material and vice versa uses Joule heat generated when a pulse voltage is applied to the phase change material. That is, in the phase change from the amorphous state to the crystalline state, a voltage that is higher than the crystallization temperature and lower than the melting point is applied, and in the phase change from the crystalline state to the amorphous state, a short pulse voltage that is higher than the melting point is applied to rapidly cool. To do.

Phase change materials for phase change memory have been studied mainly with Ge ₂ Sb ₂ Te _5. For example, Japanese Patent Application Laid-Open No. 2002-109797 (Patent Document 2) discloses a recording element using GeSbTe. Has been.

  For the general structure of phase change memory, see “Next Generation Optical Recording Technology and Materials” (Electronic Materials and Technology Series, CMC Publishing, 2004) (Non-Patent Document 1), page 99, FIG. There is a description. In the case of a phase change memory, the electrode film in contact with the phase change film needs to withstand the heat generated during switching of the phase change film. Therefore, in Non-Patent Document 1, tungsten or an alloy containing tungsten is studied. Yes. Further, in order to enable the phase change film to be switched at a low current, the lower electrode is configured by a plug having a smaller area than the phase change film.

  In general, chalcogenides such as GeSbTe described above have poor adhesion to silicon oxide, which is an interlayer insulating film material. Therefore, when a phase change film is peeled off from an interlayer insulating film during the manufacture of a phase change memory, the manufacturing yield is reduced. Causes a drop. Therefore, as a method for preventing the phase change film from peeling off, a structure in which an adhesive layer is provided between the phase change film and the interlayer insulating film is disclosed in Japanese Patent Laid-Open No. 2003-174144 (Patent Document 3) and Japanese Patent Laid-Open No. 2006-352082. (Patent Document 4).

  In Patent Document 3, a conductive material such as Ti (titanium) or doped polysilicon is used as the adhesive layer. In Patent Document 4, as an adhesive layer, TiO (titanium oxide), NbO (niobium oxide), ZrO (zirconium oxide), HfO (hafnium oxide), TaO (tantalum oxide), CrO (chromium oxide), MoO (oxidation). At least one insulating material selected from any of molybdenum), WO (tungsten oxide), and AlO (aluminum oxide) is used.

A phase change memory described in Japanese Patent Laying-Open No. 2006-351992 (Patent Document 5) includes a plug-shaped first electrode, a phase change film on the first electrode, and a second electrode on the phase change film. By having a resistive element and making the cross-sectional shape of the phase change film and the second electrode in the vicinity of the portion facing the first electrode convex or concave, current concentration near the upper end and outer edge of the first electrode is suppressed. is doing.
US Pat. No. 5,254,382 JP 2002-109797 A JP 2003-174144 A JP 2006-352082 A JP 2006-351992 A "Next-generation optical recording technology and materials" (Electronic Materials and Technology Series, CM Publishing, 2004), page 99, Fig. 6

  As described above, in the phase change memory, as a method for preventing peeling between the phase change film and the interlayer insulating film, as in Patent Document 3 and Patent Document 4, adhesion between the phase change film and the interlayer insulating film is performed. It has been proposed to provide a layer.

  However, as in Patent Document 3, when the adhesive layer is made of a conductive material, the current flowing in the surface of the adhesive layer increases when the phase change memory is rewritten, so that a large amount of energy is required for rewriting. Occurs. On the other hand, as in Patent Document 4, when the adhesive layer is made of an insulating material, a large current does not flow in the surface of the adhesive layer during rewriting.

  However, according to the structure described in Patent Document 4, since the adhesive layer is formed on the entire interface between the plug constituting the lower electrode of the phase change memory and the phase change film, a certain amount of current is applied to the adhesive layer during rewriting. Flows. For this reason, when rewriting is repeated, current repeatedly flows in the adhesive layer, and metal atoms or oxygen atoms constituting the adhesive layer may diffuse into the phase change film, thereby changing the electrical resistivity of the phase change material. In some cases, reliability may be impaired.

  An object of the present invention is to prevent peeling between the phase change film and the interlayer insulating film constituting the storage layer of the phase change memory, and the constituent atoms of the adhesive layer interposed between the interlayer insulating film and the phase change film are the phases. It is to prevent a problem that the characteristics of the phase change film are changed by diffusing into the change film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

A semiconductor device according to the present invention includes a phase change memory including a transistor and a resistance element including a phase change material on a main surface of a semiconductor substrate.
The resistance element is formed on the adhesive layer, a lower electrode made of a conductive plug in an interlayer insulating film formed on the transistor, an adhesive layer made of an insulating material formed on the interlayer insulating film, and A storage layer made of the phase change material formed, and an upper electrode formed on the storage layer,
At least a part of the conductive plug and the memory layer are in direct contact with each other without the adhesive layer.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a phase change memory including a transistor and a resistance element including a phase change material on a main surface of a semiconductor substrate,
(A) forming the transistor on a main surface of the semiconductor substrate;
(B) forming an insulating film on the interlayer insulating film after forming an interlayer insulating film on the transistor;
(C) a step of etching the insulating film and the interlayer insulating film to form a connection hole, and then forming a conductive plug in the connection hole to electrically connect the transistor and the conductive plug. ,
(D) forming a conductive film on the thin film after forming a thin film made of a phase change material so as to cover the insulating film and the conductive plug;
(E) By patterning the conductive film and the thin film, the conductive plug serves as a lower electrode, the thin film made of the phase change material serves as a memory layer, and is interposed between the interlayer insulating film and the memory layer. Forming the resistance element using the insulating film as an adhesive layer and the conductive film as an upper electrode.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, since the adhesive layer is provided at the interface between the memory layer and the interlayer insulating film, the memory layer and the interlayer insulating film can be prevented from being peeled off. Further, the provision of the adhesive layer on the interlayer insulating film increases the number of dissimilar material interfaces, thereby increasing the interface thermal resistance. As a result, the temperature around the plug (lower electrode) is likely to rise during rewriting, so that rewriting can be performed with low power, and low power consumption of the phase change memory can be promoted.

  Further, according to the present invention, since the plug (lower electrode) and the memory layer are in direct contact with each other, current can be passed through the adhesive layer without rewriting. Thereby, since the diffusion of the atoms constituting the adhesive layer into the memory layer due to rewriting can be prevented, the secular change of the electrical resistivity of the memory layer can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a principal circuit diagram showing a memory array configuration of a semiconductor device according to an embodiment of the present invention. Note that FIG. 1 shows only a part of the memory array (four word lines WL1 to WL4 and four bit lines BL1 to BL4) in order to prevent the explanation from becoming complicated.

  Four memory cells (MC11 to MC14) are connected to the word line WL1. Similarly, memory cells MC21 to MC24, MC31 to MC34, and MC41 to MC44 are connected to the word lines WL2 to WL4, respectively. The word drivers WL1 to WD4 drive the word lines WL1 to WL4. Which one of the word drivers WD1 to WD4 is selected is determined by a signal from a row decoder (X address decoder) XDEC. On the other hand, four memory cells (MC11 to MC41) are connected to the bit line BL1. Similarly, memory cells MC12 to MC42, MC13 to MC43, and MC14 to MC44 are connected to the bit lines BL2, BL3, and BL4, respectively.

  Each of bit lines BL1 to BL4 is connected to the source side of select transistors QD1 to QD4 arranged on the outer periphery of the memory array. The selection transistors QD1 and QD2 share a drain region with each other, and the selection transistors QD3 and QD4 share a drain region with each other. These selection transistors (QD1 to QD4) have a function of precharging the bit lines (BL1 to BL4). Also, it has a function of receiving a signal from the bit decoder YDEC1 or the bit decoder YDEC2 and selecting a predetermined bit line BL. In this example, the bit decoder YDEC1 and the bit decoder YDEC2 alternately handle the selected bit line BL every two bit lines. The output by reading is detected by the sense amplifier SA.

  Each of the memory cells (MC11 to MC44) is composed of a memory cell transistor QM composed of one n-channel MOS transistor and one resistance element RM connected in series to the memory cell transistor QM. Yes. A word line WL is connected to the gate electrode of the memory cell transistor QM, and a bit line BL is connected to one electrode of the resistance element RM.

  The semiconductor elements constituting the circuit blocks other than the memory array are not particularly limited, but typically include CMOS (Complementary MOS, complementary MOS transistors) transistors, which are formed on a semiconductor substrate (chip) by a known LSI manufacturing technique. It is formed.

  In the figure, VPL is a power supply line to each word driver WD, and Vdd is a power supply voltage. VGL is a potential lead line of each word driver WD, and is fixed to the ground potential here. SL is a source line.

  Next, a specific structure of the memory cell of this embodiment will be described with reference to FIG. This figure is a fragmentary cross-sectional view of a semiconductor substrate showing a part of the memory array (memory cells MC11, MC21) shown in FIG.

  The memory cell MC11 includes a memory cell transistor QM1 and a resistance element RM1, and the memory cell MC21 includes a memory cell transistor QM2 and a resistance element RM2. Each of the memory cell transistors QM1 and QM2 is an n-channel MOS transistor formed in a p-type well 2 of a semiconductor substrate 1 made of, for example, p-type single crystal silicon, and includes a gate insulating film 3, a gate electrode 4, an LDD (Lightly And an n-type semiconductor region (source / drain) 6 having a Doped Drain) structure. One (source) of the n-type semiconductor region 6 is shared by the two memory cell transistors QM1 and QM2. Memory cell transistors QM1 and QM2 are separated from adjacent memory cells by an element isolation trench 9 formed in the semiconductor substrate 1.

  The gate electrode 4 of the memory cell transistor QM1 forms a word line WL1, and the gate electrode 4 of the memory cell transistor QM2 forms a word line WL2. A Co silicide layer 7 is formed on the surface of the gate electrode 4 (word lines WL1, WL2), and sidewall spacers 8 are formed on the sidewalls. A Co silicide layer 7 is formed on the surface of the n-type semiconductor region (source, drain) 6.

  An interlayer insulating film 10 is formed on the memory cell transistors QM 1 and QM 2, and the upper surface thereof is flattened so that the heights of the semiconductor substrate 1 substantially coincide with each other. In the interlayer insulating film 10, connection holes 11 and 12 exposing the surfaces of the n-type semiconductor regions (source and drain) 6 of the memory cell transistors QM1 and QM2 are formed. The plug 13 connected to is embedded.

  An interlayer insulating film 14 is formed on the interlayer insulating film 10. Wiring grooves 15 and 16 are formed in the interlayer insulating film 14, and first layer wirings 17 and 18 are formed therein. The first layer wiring 18 formed inside the wiring groove 16 is connected to the n-type semiconductor regions (drains) 6 of the memory cell transistors QM1 and QM2 via the plug 13 inside the connection hole 12, and the wiring groove The first layer wiring 17 formed inside 15 is connected to the n-type semiconductor region (source) 6 common to the memory cell transistors QM1 and QM2 via the plug 13 inside the connection hole 11. The first layer wiring 17 corresponds to the source line SL shown in FIG.

  An interlayer insulating film 20 is formed on the interlayer insulating film 14. In the interlayer insulating film 20, connection holes 21 and 22 exposing the first layer wiring 18 are formed, and plugs 23 are embedded in these connection holes 21 and 22. The plug 23 inside the connection hole 21 constitutes a lower electrode of a resistance element RM1 described later, and the n-type semiconductor region (drain) of the memory cell transistor QM1 via the first layer wiring 18 and the plug 13 below the first layer wiring 18. 6 is connected. The plug 23 inside the connection hole 22 constitutes the lower electrode of the resistance element RM2, and the n-type semiconductor region (drain) of the memory cell transistor QM2 via the first layer wiring 18 and the plug 13 below the first layer wiring 18. 6 is connected.

  Resistive elements RM1 and RM2 are formed on the interlayer insulating film 20. Each of the resistance elements RM1 and RM2 includes a plug 23 (lower electrode) and an adhesive layer 24, a memory layer 25, and an upper electrode 26 stacked on the plug 23, and a cap insulation is provided on the upper electrode 26. A film 27 is formed. The adhesive layer 24 is provided in order to prevent interface peeling between the memory layer 25 and the interlayer insulating film 20, but in the present embodiment, the adhesive layer 24 is provided on the upper surface of the plug 23 (lower electrode). It is not done.

  An interlayer insulating film 28 is formed on the resistance elements RM1 and RM2. Connection holes 30 and 31 are formed in the interlayer insulating film 28 and the cap insulating film 27 so as to expose the upper electrodes 26 of the resistance elements RM1 and RM2, and plugs 32 are embedded therein.

  A second layer wiring 33 is formed on the interlayer insulating film 28. The second layer wiring 33 corresponds to the bit line BL1 shown in FIG. The second layer wiring 33 (bit line BL1) is connected to the upper electrode 26 of the resistance elements RM1 and RM2 via the plugs 32 inside the connection holes 30 and 31. Although an interlayer insulating film is formed on the second layer wiring 33, its illustration is omitted. Further, a third layer wiring may be formed on the interlayer insulating film as needed.

  Next, an example of a method for manufacturing the memory cell shown in FIG. 2 will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 3, a semiconductor substrate 1 made of p-type single crystal silicon is prepared, and a p-type well 2 and an element isolation trench 9 are formed on the main surface thereof using a known method. Next, memory cell transistors QM 1 and QM 2 are formed in the p-type well 2.

  In order to form the memory cell transistors QM1 and QM2, first, the surface of the p-type well 2 is heat-treated and nitrided to form the gate insulating film 3 made of a silicon oxynitride film and having a thickness of about 1.5 to 10 nm. To do. Subsequently, after depositing an n-type polycrystalline silicon film having a thickness of about 150 to 200 nm on the semiconductor substrate 1 by a CVD method, the polycrystalline silicon film is dry-etched to thereby form the gate electrode 4 (word lines WL1, WL2). ). The gate electrode 4 (word lines WL1, WL2) can be replaced by a laminated film of a polycrystalline silicon film and a W silicide film, for example.

Next, P − (phosphorus) ions are implanted into the p-type well 2, thereby forming n ⁻ -type semiconductor regions (not shown) under the side walls of the gate electrode 4. Subsequently, after depositing a silicon oxide film on the semiconductor substrate 1 by a CVD method, the silicon oxide film is dry-etched to form side wall spacers 8 on both side walls of the gate electrode 4.

  Next, P-type wells 2 are ion-implanted to form n-type semiconductor regions (sources and drains) 6 below the side walls of the gate electrode 4. Subsequently, a Co silicide layer 7 is formed on the surface of the gate electrode 4 and the surface of the n-type semiconductor region (source, drain) 6 using a known silicide technique. The Co silicide layer 7 can be replaced with another metal silicide such as Ni (nickel) silicide, Ti silicide, W silicide, or Pt (platinum) silicide.

  Next, as shown in FIG. 4, after an interlayer insulating film 10 made of a silicon oxide film is deposited on the semiconductor substrate 1 using a CVD method, the interlayer is formed using a chemical mechanical polishing (CMP) method. The surface of the insulating film 10 is planarized. The interlayer insulating film 10 can be replaced by, for example, a BPSG (Boron-Doped Phospho Silicate Glass) film or an SOG (Spin On Glass) film. Next, the interlayer insulating film 10 is dry-etched using the photoresist film as a mask, thereby forming connection holes 11 and 12 exposing the surface of the n-type semiconductor region (source, drain) 6. Subsequently, a plug 13 made of a main conductor film such as W and a conductive barrier film such as Ti / TiN is formed inside the connection holes 11 and 12 using a known method.

  Next, as shown in FIG. 5, an interlayer insulating film 14 made of a silicon oxide film is deposited on the interlayer insulating film 10 using the CVD method, and then the interlayer insulating film 14 is dry-etched using the photoresist film as a mask. As a result, the wiring groove 15 is formed above the connection hole 11, and the wiring groove 16 is formed above the connection hole 12. Next, first layer wirings 17 and 18 are formed by embedding a main conductor film such as W and a conductive barrier film such as Ti / TiN in the wiring grooves 15 and 16 using a known method.

Next, as shown in FIG. 6, an interlayer insulating film 20 made of a silicon oxide film is deposited on the interlayer insulating film 14 using a CVD method, and then, for example, tantalum pentoxide (Ta ₂ O) is formed on the interlayer insulating film 20. ₅ ) The adhesive layer 24 made of a film is formed. In order to form the adhesive layer 24, first, a Ta film is deposited on the interlayer insulating film 20 by sputtering, and then the Ta film is radical-oxidized to form a Ta ₂ O ₅ film. Alternatively, a Ta ₂ O ₅ film may be directly deposited on the interlayer insulating film 20 by sputtering a Ta target in an oxidizing atmosphere. The adhesive layer 24 may be formed of a dielectric film such as a TiO film, an NbO film, a ZrO film, an HfO film, a CrO film, a MoO film, a WO film, or an AlO film instead of the Ta ₂ O ₅ film. Further, the adhesive layer 24 can be formed by laminating two or more of these dielectric films.

  Subsequently, the contact holes 21 and 22 exposing the first layer wiring 18 are formed by dry etching the adhesive layer 24 and the interlayer insulating film 20 using the photoresist film as a mask. Next, a plug 23 made of a main conductor film such as W and a conductive barrier film such as Ti / TiN is formed inside the connection holes 21 and 22 using a known method. The plug 23 inside the connection hole 21 constitutes the lower electrode of the resistance element RM1, and the plug 23 inside the connection hole 22 constitutes the lower electrode of the resistance element RM2.

  Next, as shown in FIG. 7, resistance elements RM <b> 1 and RM <b> 2 are formed on the adhesive layer 24. In order to form the resistance elements RM1 and RM2, first, a multi-system chalcogenide film such as a GeSbTe film or an InGeSbTe film is deposited on the adhesive layer 24 by sputtering, and then a W film is deposited on the chalcogenide film by sputtering. After that, a cap insulating film 27 made of a silicon oxide film is deposited on the W film by a CVD method. Next, the cap insulating film 27, the W film and the chalcogenide film are dry etched by dry etching using the photoresist film as a mask, thereby forming the upper electrode 26 made of the W film and the memory layer 25 made of the chalcogenide film. Note that when this dry etching is performed, all of the adhesive layer 24 in a region other than the lower portion of the memory layer 25 may be removed.

  Next, as shown in FIG. 8, an interlayer insulating film 28 made of a silicon oxide film is deposited on the resistance elements RM1 and RM2 using a CVD method, and then the surface of the interlayer insulating film 28 is flattened using a CMP method. Turn into. Next, the interlayer insulating film 28 and the cap insulating film 27 are dry-etched using the photoresist film as a mask, thereby forming connection holes 30 and 31 that expose the upper electrodes 26 of the resistance elements RM1 and RM2. Next, a plug 32 made of a main conductor film such as W and a conductive barrier film such as Ti / TiN is formed inside the connection holes 30 and 31 using a known method. Thereafter, a metal film (not shown) having Al as the main conductor film is deposited on the interlayer insulating film 28 by sputtering or the like, and then this metal film is dry-etched using the photoresist film as a mask. By forming the two-layer wiring 33, the memory cell shown in FIG. 2 is completed.

In the memory cells MC11 and MC21 configured as described above, since the adhesive layer 24 is formed between the memory layer 25 of the resistance elements RM1 and RM2 and the interlayer insulating film 20, the memory layer 25 and the interlayer insulating film 20 The adhesion between the two is improved, and interfacial peeling between the two can be prevented. Further, since the adhesive layer 24 is composed of an insulating material (Ta ₂ O ₅ film or the like), no current flows in the lateral direction of the adhesive layer 24 (the direction horizontal to the main surface of the semiconductor substrate 1). Therefore, a large current is not required for rewriting.

  The plug 23 and the memory layer 25 inside the connection holes 21 and 22 constituting the lower electrodes of the resistance elements RM1 and RM2 are in direct contact with each other without the adhesive layer 24 interposed therebetween. For this reason, since a current flows directly between the plug 23 (lower electrode) and the memory layer 25, the phenomenon that the elements constituting the adhesive layer 24 diffuse into the memory layer 25 by rewriting can be prevented. Thereby, since the secular change of the electrical resistivity of the memory layer 25 is suppressed, a highly reliable phase change memory can be provided.

  When performing a reset rewrite to pass a current through a memory cell in a low resistance state (set state) to set it to a high resistance state (reset state), the resistance in the reset state is about 100 to 1000 times that in the set state. It is desirable to make it higher. This is to prevent erroneous reading when a resistance value is read by passing a current through the memory cell. In order to obtain the above resistance ratio by reset rewriting, the entire surface of the plug 23 (lower electrode) is covered with the memory layer 25 as in the present embodiment. This is because if even a part of the surface of the plug 23 (lower electrode) is not covered with the memory layer 25, that part becomes a current path, and the resistance in the reset state is reduced.

  FIG. 9 shows the temperature distribution near the interface between the memory layer 25 and the plug 23 (lower electrode) at the time of reset rewriting. An example of the calculation result of the temperature distribution on the straight line along the X direction in FIG. Show. FIG. 9 also shows the temperature distribution when the same current is passed through a memory cell without the adhesive layer 24.

  In any case, in the vicinity of the interface between the memory layer 25 and the plug 23 (lower electrode), the temperature is highest immediately above the center portion of the plug 23, and the temperature decreases as it approaches the peripheral portion from the center portion of the plug 23. . In the case of the present invention having the adhesive layer 24, the temperature of the memory layer 25 exceeds its melting point in a range wider than the diameter of the plug 23. On the other hand, when the adhesive layer 24 is not present, there is a region where the temperature of the memory layer 25 is equal to or lower than the melting point in the peripheral portion of the plug 23. This is presumably because the thermal resistance of the peripheral portion of the plug 23 increased due to the adhesive layer 24 in the present invention. As the increase in thermal resistance, in addition to the thermal resistance of the adhesive layer 24, the thermal resistance of the interface between the memory layer 25 and the plug 23 and the thermal resistance of the interface between the adhesive layer 24 and the interlayer insulating film 20 are conceivable.

  As an example of the magnitude of the thermal resistance of the interface, for example, when a silicon oxide film is formed on Mo, there is a thermal resistance of about several tens of nanometers in terms of the thickness of the silicon oxide film at the interface between the two. ("Metal" Vol. 70, No. 10, page 92-97 Agne Technology Center Co., Ltd., published in 2000). That is, for example, it is known that the thermal resistance can be increased more than the increased film thickness by forming a thin film with a thickness of about several nm and increasing the number of interfaces.

  In the phase change memory according to the present invention, the adhesive layer 24 is added to the interface between the storage layer 25 and the plug 23. As a result, the thermal resistance of the interface is added in addition to the thermal resistance of the adhesive layer 24 itself. It is considered that the temperature in the peripheral portion of the plug 23 has increased compared to the case.

  FIG. 11 is a cross-sectional view showing a phase distribution diagram after rewriting a phase change memory in which an adhesive layer is provided between the memory layer and the plug (lower electrode). On the other hand, FIG. 12 shows a phase distribution diagram when no adhesive layer is provided between the memory layer and the plug (lower electrode).

  As shown in FIG. 11, when the adhesive layer 24 is provided, since the entire upper surface of the plug 23 is covered with the high-resistance amorphous phase 25a, a large resistance value can be obtained before and after reset rewriting. However, when the adhesive layer 24 is not provided, the peripheral portion of the plug 23 is in contact with the crystal layer as shown in FIG. 12, so that this crystal layer becomes a current path and the resistance value decreases. That is, in order to obtain a large resistance ratio in the absence of the adhesive layer 24, it is necessary to form the amorphous phase 25a also in the peripheral portion of the plug 23, so that a larger current is required.

  Considering from the thermal viewpoint as described above, an effective material for the adhesive layer 24 is an insulating material having a large interface thermal resistance with the interlayer insulating film 20 or an insulating material having a lower thermal conductivity than the interlayer insulating film 20. It is. Specifically, it is effective to use at least one insulating material selected from any of TiO, NbO, ZrO, HfO, TaO, CrO, MoO, WO, and AlO.

  Next, the operation principle of the memory cell of this embodiment will be described. A phase change memory is a device in which a phase change material used in a DVD recording medium is applied to a semiconductor memory. A DVD recording medium changes information of a phase change material to an amorphous state or a crystalline state by a laser pulse, and records information according to a difference in refractive index between the amorphous state and the crystalline state. On the other hand, the phase change memory applies a pulse voltage to a memory cell and adjusts the voltage and pulse time to select an amorphous state or a crystalline state. At that time, since the electric resistance differs by about 1000 times or more between the amorphous state and the crystalline state, information is recorded by the difference in electric resistance.

  As shown in FIG. 13, in switching (reset) from the crystalline state to the amorphous state of the memory cell, a short pulse (reset pulse) with a relatively large current is passed. On the other hand, in switching (setting) from the amorphous state to the crystalline state, a long pulse (set pulse) with a relatively small current is passed.

  At the time of reading, a small current / short-time pulse (read pulse) is supplied to the memory cell to read information from the resistance value of the memory cell. In the reset pulse, a large current flows to melt the memory cell, and since the pulse width is short, the memory cell becomes amorphous because cooling is performed sharply. On the other hand, in the set pulse, a current that causes the temperature of the memory cell to exceed the crystallization temperature is passed. As a result, the memory cell changes from an amorphous state to a crystalline state (FIG. 14).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the adhesive layer 24 is not provided on the entire upper surface of the plug 23 (lower electrode). However, the adhesive layer 24 may remain on a part of the upper surface of the plug 23 (lower electrode).

  In the above embodiment, the phase change memory composed of the MOS transistor and the resistance element has been described. However, the present invention can also be applied to a phase change memory composed of the bipolar transistor and the resistance element.

  The present invention can be used for a phase change memory including a transistor and a resistance element.

1 is a main part circuit diagram showing a memory array configuration of a semiconductor device according to an embodiment of the present invention; 1 is a main-portion cross-sectional view of a semiconductor substrate showing a memory cell configuration of a semiconductor device according to an embodiment of the present invention; It is principal part sectional drawing of the semiconductor substrate explaining the manufacturing method of the semiconductor device which is one embodiment of this invention. FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate for describing the method for manufacturing the semiconductor device following FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate for describing the method for manufacturing the semiconductor device following FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, for explaining the method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is an essential part cross-sectional view of the semiconductor substrate, for explaining the method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate for describing the manufacturing method of the semiconductor device following FIG. 7; It is a graph which shows the temperature distribution near the interface of a memory layer and a plug (lower electrode) at the time of reset rewriting. FIG. 10 is a cross-sectional view of a memory cell for explaining the position of the temperature distribution shown in FIG. 9. It is sectional drawing which shows the phase distribution figure after rewriting of the memory cell of this invention which provided the contact bonding layer between the memory | storage layer and the plug (lower electrode). It is sectional drawing which shows the phase distribution diagram after rewriting of the memory cell which does not provide an adhesive layer between a memory layer and a plug (lower electrode). It is a graph explaining the operation pulse of the memory cell of this invention. It is a graph explaining the temperature history at the time of operation | movement of the memory cell of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 P-type well 3 Gate insulating film 4 Gate electrode 5 n ^- type semiconductor region 6 n-type semiconductor region (source, drain)
7 Co silicide layer 8 Side wall spacer 9 Element isolation groove 10 Interlayer insulating film 11, 12 Connection hole 13 Plug 14 Interlayer insulating film 15, 16 Wiring groove 17, 18 First layer wiring 20 Interlayer insulating film 21, 22 Connection hole 23 Plug 24 Adhesive layer 25 Memory layer 25a Amorphous phase 26 Upper electrode 27 Cap insulating film 28 Interlayer insulating film 30, 31 Connection hole 32 Plug 33 Second layer wiring BL Bit line MC Memory cell QD Select transistor QM Memory cell transistor RM Resistive element SA sense Amplifier SL Source line Vdd Power supply voltage VGL Potential extraction line VPL Power supply line WD Word driver WL Word line XDEC Row decoder (X address decoder)
YDEC bit decoder

Claims (11)

A semiconductor device comprising a phase change memory composed of a transistor and a resistance element including a phase change material on a main surface of a semiconductor substrate,
The resistance element is formed on the adhesive layer, a lower electrode made of a conductive plug in an interlayer insulating film formed on the transistor, an adhesive layer made of an insulating material formed on the interlayer insulating film, and A storage layer made of the phase change material formed, and an upper electrode formed on the storage layer,
The semiconductor device, wherein the conductive plug and the memory layer are in direct contact with each other without the adhesive layer interposed therebetween.   2. The semiconductor device according to claim 1, wherein the insulating material constituting the adhesive layer is made of a dielectric film.   The semiconductor device according to claim 1, wherein a thermal conductivity of an insulating material constituting the adhesive layer is lower than a thermal conductivity of the interlayer insulating film.   The insulating material constituting the adhesive layer is at least one insulating material selected from titanium oxide, niobium oxide, zirconium oxide, hafnium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and aluminum oxide. The semiconductor device according to claim 1.   5. The semiconductor device according to claim 4, wherein the insulating material constituting the adhesive layer is tantalum oxide.   2. The semiconductor device according to claim 1, wherein the phase change material constituting the memory layer is germanium / antimony / tellurium or indium / germanium / antimony / tellurium. A method of manufacturing a semiconductor device including a phase change memory including a transistor and a resistance element including a phase change material on a main surface of a semiconductor substrate,
(A) forming the transistor on a main surface of the semiconductor substrate;
(B) forming an insulating film on the interlayer insulating film after forming an interlayer insulating film on the transistor;
(C) a step of etching the insulating film and the interlayer insulating film to form a connection hole, and then forming a conductive plug in the connection hole to electrically connect the transistor and the conductive plug. ,
(D) forming a conductive film on the thin film after forming a thin film made of a phase change material so as to cover the insulating film and the conductive plug;
(E) By patterning the conductive film and the thin film, the conductive plug serves as a lower electrode, the thin film made of the phase change material serves as a memory layer, and is interposed between the interlayer insulating film and the memory layer. Forming the resistance element using the insulating film as an adhesive layer and the conductive film as an upper electrode;   8. The method of manufacturing a semiconductor device according to claim 7, wherein the insulating film constituting the adhesive layer has a thermal conductivity lower than that of the interlayer insulating film.   The insulating film constituting the adhesive layer is made of at least one insulating material selected from titanium oxide, niobium oxide, zirconium oxide, hafnium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and aluminum oxide. The method of manufacturing a semiconductor device according to claim 7.   The method for manufacturing a semiconductor device according to claim 9, wherein the insulating film constituting the adhesive layer is made of tantalum oxide.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the phase change material constituting the memory layer is germanium / antimony / tellurium or indium / germanium / antimony / tellurium.

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