JP5420436B2 - Nonvolatile memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nonvolatile memory device and a method for manufacturing the same, and more particularly to an electrically rewritable phase change memory and a technique effective when applied to the manufacturing thereof.

  In recent years, a phase-change random access memory (PRAM) using a phase-change material such as chalcogenide has been proposed as a next-generation nonvolatile semiconductor memory. Although this phase change memory is non-volatile, writing and reading operations are expected to be as fast as DRAM (Dynamic Random Access Memory), and the cell area can be reduced to the same extent as flash memory. Therefore, it is regarded as the most promising next-generation nonvolatile memory.

  Phase change materials used for phase change memories are already used in optical disc media such as DVDs (Digital Versatile Discs), but in the case of DVDs, the phase change material has a light reflectivity between an amorphous state and a crystalline state. Utilizing different characteristics.

  On the other hand, in the case of a phase change memory, it is a memory element that rewrites electrically by passing a current through the phase change material film by utilizing the property that the phase change material has an electric resistance different by several orders of magnitude between the amorphous state and the crystalline state. is there. The basic memory cell structure of the phase change memory is a structure in which a storage element (phase change material film) and a selection element are combined. The phase change memory stores and retains information by bringing a memory element into a crystalline state or an amorphous state by Joule heat generated in the memory element by applying a current from a selection element. The phase change memory switching, that is, the phase change of the phase change material from the amorphous state to the crystalline state and vice versa utilizes Joule heat generated when a pulse voltage is applied to the phase change material film. That is, in the phase change from the amorphous state to the crystalline state, a voltage that is higher than the crystallization temperature and lower than the melting point is applied, and in the phase change from the crystalline state to the amorphous state, a short pulse voltage that is higher than the melting point is applied to rapidly cool. To do.

  In general, the resistance value of the memory element changes by two to three digits due to a phase change. For this reason, the phase change memory has a read signal that varies greatly depending on whether it is crystalline or amorphous, so that the sensing operation is easy.

  For example, Patent Document 1 (Japanese Patent Laid-Open No. 2003-100085) is known as a known document regarding the phase change memory related to the electrical information storage. Patent Document 1 discloses a technique for providing a phase change memory that operates reliably and easily as a storage device by reading a recording state of the storage cell before recording information in the storage cell.

  Patent Document 2 (Japanese Patent Application Laid-Open No. 2003-303941) discloses a self-aligned memory cell that requires only two array-related masks that define a bit line and a word line, and an intersection of the bit line and the word line. A technology for realizing miniaturization of a memory cell by adopting a cross-point type arranged perpendicularly to the memory cell is disclosed. A phase change memory having a cross-point type memory cell structure can be manufactured at low cost.

  Patent Document 3 (Japanese Patent Laid-Open No. 2001-127263) discloses a phase change thin film having two phases (a high temperature phase and a low temperature phase) stable at room temperature, and a pn junction connected in series to the phase change thin film. A technology for realizing a highly integrated and high-density non-volatile memory by providing a plurality of memory cells each including a switch element and configuring a non-volatile memory is disclosed. Patent Document 3 proposes a method of minimizing the diffusion of heat generated in the phase change material film by providing a conductive heat insulating film between the electrode and the phase change material film.

JP 2003-100085 A JP 2003-303941 A JP 2001-127263 A

  As described above, in order to rewrite the phase change memory, current flows from the diode to the phase change material film to generate heat, and the temperature of the phase change material film is set to the crystallization temperature or melting point of the phase change material. It is necessary to raise to the above temperature. For this reason, there is a problem that a relatively large voltage is required for the phase change and the power consumption becomes large.

  In the techniques shown in Patent Document 1 and Patent Document 2, the space between adjacent memory cells is filled with an insulating film, and heat is dissipated from the heated phase change material film through the insulating film. There is a problem that large power consumption is required for the temperature rise.

  On the other hand, in the technique shown in Patent Document 3, a method is proposed in which a conductive heat insulating film is provided between the electrode and the phase change material film to minimize the diffusion of heat generated in the phase change material film. . However, the conductive heat insulating film described in Patent Document 3 does not have a very large thermal resistance, and an effect of reducing power consumption cannot be expected.

  An object of the present invention is to provide a nonvolatile memory device having a phase change memory with reduced power consumption during writing / erasing.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A non-volatile memory device according to an invention of the present application includes a plurality of first metal wirings extending along a first direction of a main surface of a semiconductor substrate, and a plurality of second metal wires extending along a second direction orthogonal to the first direction. A nonvolatile memory having a metal wiring, a phase change material film that is a memory element driven by current, and a diode that is a selection element at each intersection of the plurality of first metal wirings and the plurality of second metal wirings It is a sex memory device.

  Each memory cell of the nonvolatile memory device includes the diode formed on the first metal wiring, the first metal electrode formed on the diode, and the first metal electrode formed on the first metal electrode. A phase change material film; and a second metal electrode formed on the phase change material film and below the second metal wiring.

  In the nonvolatile memory device according to one aspect of the present application, a gap is formed between at least one of the adjacent first metal electrodes or between the adjacent second metal electrodes.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the phase change memory, power consumption during rewriting and reading of stored information can be reduced.

1 is a main part plan view of a memory matrix of a nonvolatile memory device according to Embodiment 1 of the present invention; FIG. FIG. 2 is a main part cross-sectional view taken along line AA of the memory matrix of FIG. 1. FIG. 3 is a cross-sectional view of a main part taken along line BB of the memory matrix of FIG. 1. FIG. 2 is a main part cross-sectional view taken along line CC of the memory matrix of FIG. 1. FIG. 2 is a cross-sectional view of main parts taken along line DD of the memory matrix of FIG. 1. It is a graph which shows the relationship between melting | fusing point of a phase change material, and an electric current. FIG. 3 is an equivalent circuit diagram of a memory matrix of the nonvolatile memory device according to Embodiment 1 of the present invention. It is principal part sectional drawing explaining the manufacturing process of the non-volatile memory device which is Embodiment 1 of this invention. FIG. 9 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 8. FIG. 9 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 8. FIG. 9 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 8. FIG. 9 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 8. FIG. 10 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 9. FIG. 11 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 10. 12 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 11. FIG. FIG. 13 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 12. FIG. 14 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 13. FIG. 15 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 14. FIG. 16 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 15. FIG. 17 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 16. FIG. 18 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 17. FIG. 19 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 18. FIG. 20 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 19. FIG. 21 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 20. FIG. 22 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 21. FIG. 23 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 22. FIG. 24 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 23. FIG. 25 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 24. FIG. 26 is an essential part cross-sectional view illustrating the manufacturing method of the nonvolatile memory device following FIG. 25. FIG. 27 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 26. FIG. 28 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 27. FIG. 29 is an essential part cross-sectional view illustrating the manufacturing method of the nonvolatile memory device following FIG. 28. FIG. 30 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 29. FIG. 31 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 30. FIG. 32 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 31. FIG. 33 is an essential part cross sectional view for explaining the manufacturing method of the nonvolatile memory device following FIG. 32. FIG. 34 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 33. FIG. 35 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 34. FIG. 36 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 35. FIG. 37 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 36. FIG. 38 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 37. FIG. 39 is an essential part cross sectional view illustrating the method of manufacturing the nonvolatile memory device following FIG. 38. FIG. 40 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 39. FIG. 41 is an essential part cross sectional view illustrating the method of manufacturing the nonvolatile memory device following FIG. 40. FIG. 42 is an essential part cross-sectional view illustrating the manufacturing method of the nonvolatile memory device following FIG. 41. FIG. 43 is a fragmentary cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 42. FIG. 44 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 43. FIG. 45 is an essential part cross-sectional view illustrating the method for manufacturing the nonvolatile memory device following FIG. 44. It is principal part sectional drawing of the memory matrix of the non-volatile memory device which is Embodiment 2 of this invention. It is principal part sectional drawing of the memory matrix of the non-volatile memory device which is Embodiment 3 of this invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. In addition, in the embodiment and the like, when “consisting of A” or “consisting of A” is used, the other elements are not excluded unless specifically stated that only the elements are included. Needless to say.

  Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  In addition, when referring to materials, etc., unless specified otherwise, or in principle or not in principle, the specified material is the main material, and includes secondary elements, additives It does not exclude additional elements. For example, unless otherwise specified, the silicon member includes not only pure silicon but also an additive impurity, a binary or ternary alloy (eg, SiGe) having silicon as a main element, and the like.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment mode, a cross-point memory matrix in which a plurality of self-aligned memory cells are arranged perpendicularly to the intersection of a bit line and a word line is provided, a diode is provided as a selection element, and a phase is provided as a storage element. A non-volatile storage device having a change memory will be described.

  First, FIG. 1 shows a part of a planar layout of a phase change memory according to the present embodiment, and FIGS. 2, FIG. 3, FIG. 4 and FIG. 5 are cross-sectional views taken along lines AA, BB, CC and DD in FIG. 1, respectively.

  As shown in the plan view of FIG. 1, the nonvolatile memory device according to the present embodiment selects a memory element at an intersection 23 between a plurality of first metal wires 2 and a plurality of second metal wires 7 orthogonal to each other in the plane. A memory matrix including cross-point memory cells having elements. In FIG. 1, only the first metal wiring 2 and the second metal wiring 7 are shown for easy understanding of the configuration of the memory matrix. A plurality of first metal wirings 2 are arranged in stripes in a direction along the first direction shown in FIG. 1, and the second metal wirings 7 are along a second direction perpendicular to the first direction as shown in FIG. A plurality of stripes are arranged in the direction.

  The nonvolatile memory device in the present embodiment has a semiconductor substrate 1 as shown in FIGS. On the semiconductor substrate 1, there are formed a plurality of first metal wirings 2 extending in a stripe shape in a direction along the first direction in FIG. On the first metal wiring 2, a plurality of p-type semiconductor films 3a are intermittently formed in a direction along the first direction, and an n-type semiconductor film 3b is formed on the p-type semiconductor film 3a. . The p-type semiconductor film 3 a and the n-type semiconductor film 3 b constitute a diode 3 having a pn junction, and a lower electrode film 4 is formed on the diode 3. A phase change material film 5 is formed on the lower electrode film 4. An upper electrode film 6 is formed on the phase change material film 5. On the upper electrode film 6, a second metal wiring 7 is formed in a stripe shape. As shown in FIG. 1, the first metal wiring 2 extending in the first direction and the second metal wiring 7 extending in the second direction are formed. A plurality of two metal wirings 7 are formed in directions orthogonal to each other on a plane. Each memory cell formed at each intersection of the plurality of first metal wires 2 and the plurality of second metal wires 7 includes a p-type semiconductor film 3a, an n-type semiconductor film 3b, a lower electrode film 4, and a phase change material film 5. And the upper electrode film 6.

  The nonvolatile memory device according to the present embodiment includes a diode 3, a lower electrode film 4, a phase change material film 5, and an upper portion formed at intersections of a plurality of first metal wires 2 and a plurality of second metal wires 7 that are orthogonal to each other. This is a cross-point type memory matrix having a plurality of memory cells made of an electrode film 6. In addition, the nonvolatile memory device according to the present embodiment changes the phase change material film 5 to a crystalline state or an amorphous state by passing a current through the phase change material film 5 in the memory cell, and the phase change material film 5 is crystallized. This is a phase change memory that records information by utilizing the difference in resistance value between the state and the amorphous state. The memory cell has a columnar shape formed perpendicular to the first metal wiring 2 and the second metal wiring 7, and is arranged in a matrix in a planar shape, and an interlayer formed between the memory cells. The insulating films 9, 10, 11, 12 electrically isolate each memory cell.

  Here, as shown in FIG. 2 and FIG. 3, the interlayer insulating films 9 and 10 fill the gaps between the adjacent phase change material films 5, but at least the gaps 13 between the adjacent lower electrode films 4. , 14 are provided. That is, the interlayer insulating films 9 and 10 cover the upper surface of the semiconductor substrate 1 in a region where no memory cell is formed, and the p-type semiconductor film 3a, the n-type semiconductor film 3b, the lower electrode film 4 and the phase change of each memory cell. The side wall of the material film 5 is covered but is not filled between the adjacent p-type semiconductor film 3a, n-type semiconductor film 3b, and lower electrode film 4, and voids are formed in the interlayer insulating films 9 and 10. Has been.

  Thereby, the thermal resistance between the adjacent lower electrode films 4 is increased as compared with the case where there are no gaps 13 and 14 between the lower electrode films 4 and the interlayer insulating films 9 and 10 are filled. . In addition, gaps 15 and 16 are provided between at least the plurality of upper electrode films 6 of the interlayer insulating films 11 and 12, and the thermal resistance between the adjacent upper electrode films 6 is eliminated. Compared to the case where the interlayer insulating films 11 and 12 are filled, the number is increased.

  This is because the voids 13, 14, 15 and 16 have a lower thermal conductivity than the interlayer insulating films 9, 10, 11 and 12. The voids 13, 14, 15 and 16 are formed by confining the atmosphere in the apparatus to the interlayer insulating films 9, 10, 11 and 12 in the step of forming the interlayer insulating film by the CVD (Chemical Vapor Deposition) method. Therefore, the air pressure in the air gaps 13, 14, 15 and 16 has the same air pressure as that in the CVD apparatus in the process of depositing the interlayer insulating films 9, 10, 11 and 12.

  Further, in the present embodiment, like the interlayer insulating films 9 and 10, voids 15 and 16 are also formed in the interlayer insulating films 11 and 12. The interlayer insulating film 11 covers the upper surface of the interlayer insulating film 10 and covers the side wall of the upper electrode film 6. The interlayer insulating film 12 covers the upper surface of the interlayer insulating film 10, the side walls and the upper surface of the upper electrode film 6. However, like the interlayer insulating films 9 and 10, the interlayer insulating films 11 and 12 are not filled between the upper electrode films 6 and have voids 15 and 16 inside.

  The first metal wiring 2 and the second metal wiring 7 are made of, for example, Al (aluminum), Cu (copper), or W (tungsten). The p-type semiconductor film 3a and the n-type semiconductor film 3b are each made of a polycrystalline silicon film, and impurities having different conductivity types are introduced thereinto. For example, the p-type semiconductor film 3a is made of a polycrystalline silicon film containing B (boron), and the n-type semiconductor film 3b is made of a polycrystalline silicon film containing P (phosphorus).

  The upper electrode film 6 and the lower electrode film 4 are made of a refractory metal material such as W (tungsten). By using a refractory metal material for the members of the upper electrode film 6 and the lower electrode film 4, the upper electrode film 6 and the lower electrode film 4 can be heated even when a current is passed through the memory cell during writing and erasing of the phase change memory. Therefore, the reliability of the nonvolatile memory device is improved. In addition, the material of the upper electrode film 6 and the lower electrode film 4 is preferably a material having low thermal conductivity such as TiN because the driving voltage of the phase change memory can be reduced.

The phase change material film 5 is made of, for example, Ge ₂ Sb ₂ Te ₅ (germanium-antimony-tellurium: GST). The material of the interlayer insulating films 9 to 12 is, for example, TEOS (ethyl silicate).

  4 and 5 are cross-sectional views of main parts taken along lines CC and DD in FIG. 1, respectively. FIG. 4 does not show the memory cell and the first metal wiring 2, the interlayer insulating film 10 is intermittently formed on the semiconductor substrate 1, and the gap 14 is formed on the semiconductor substrate 1 and the interlayer insulating film 10. Interlayer insulating films 9 and 10 are formed with a gap therebetween. Interlayer insulating film 10 is intermittently formed in a direction along the main surface of semiconductor substrate 1, and interlayer insulating film 9 fills between adjacent interlayer insulating films 10 in a direction along the main surface of semiconductor substrate 1. The upper surfaces of the interlayer insulating film 9 and the interlayer insulating film 10 are uniformly formed. On the interlayer insulating film 9 and the interlayer insulating film 10, the interlayer insulating film 11 is intermittently formed in the direction along the main surface of the semiconductor substrate 1, with the gap 16 interposed therebetween. A plurality of second metal wirings 7 are formed on the interlayer insulating film 11, and an interlayer insulating film 12 is formed so as to fill between the interlayer insulating film 11 and the second metal wiring 7 formed in a stripe shape. Yes. The upper surface of the interlayer insulating film 12 is formed higher than the second metal wiring 7, and the interlayer insulating film 12 is formed so as to cover the second metal wiring 7.

  Further, FIG. 5 does not show the memory cell and the second metal wiring 7, and the first metal wiring 2 is intermittently formed on the semiconductor substrate 1, and between the first metal wirings 2. An interlayer insulating film 10 is formed. An interlayer insulating film 9 is formed on the semiconductor substrate 1, the interlayer insulating film 10 and the first metal wiring 2 with a gap 13 interposed therebetween. The interlayer insulating film 9 is intermittently formed in the direction along the main surface of the semiconductor substrate 1, and the height of the upper surface of the interlayer insulating film 9 is formed uniformly. An interlayer insulating film 12 is formed on the interlayer insulating film 9 with a gap 15 interposed therebetween.

  Next, the basic operation of the phase change memory according to the present embodiment will be described.

  In the case of rewriting the phase change memory, in FIG. 2, the current flows from the first metal wiring 2 to the p-type semiconductor film 3a, the n-type semiconductor film 3b, the lower electrode film 4, the phase change material film 5, the upper electrode film 6, and the first The two metal wires 7 flow in order. In these systems, Joule heat is mainly a portion having high resistance, that is, the interface between the upper electrode film 6 and the phase change material film 5, the interface between the phase change material film 5 and the lower electrode film 4, the diode 3 and the lower electrode film 4 Or at the interface between the diode 3 and the first metal wiring 2. The generated heat diffuses into the surrounding material. For example, the heat generated in the phase change material film 5 is diffused to the first metal wiring 2, the lower electrode film 4, the upper electrode film 6, the second metal wiring 7 and the interlayer insulating film existing around the phase change material film 5.

  The phase change nonvolatile memory records information using the fact that the phase change material film 5 in the memory cell has different resistance values between the crystalline state and the amorphous state. For example, a memory cell capable of switching between two values can be obtained by turning off a crystalline state with a small resistance value and turning on an amorphous state with a large resistance value. Switching from ON to OFF and OFF to ON of the memory cell is performed by applying a pulse voltage to the word line and the bit line.

  In rewriting from OFF to ON, that is, the phase change from the crystalline state of the phase change material film 5 to the amorphous state, the voltage at which the phase change material film 5 is heated to the melting point Tm or higher is set to the word line (first metal wiring 2). This is performed by applying to the bit line (second metal wiring 7). At this time, by shortening the pulse width, the phase change material film 5 in the memory cell is rapidly cooled to be in an amorphous state.

On the other hand, when erasing from ON to OFF, that is, the phase change of the phase change material film 5 from the amorphous state to the crystalline state, the voltage is applied to the word line (first line) so that the phase change material becomes higher than the crystallization temperature Tc and lower than the melting point Tm. This is performed by applying to the metal wiring 2) and the bit line (second metal wiring 7). For example, when the phase change material film 5 is Ge ₂ Sb ₂ Te ₅ , the melting point Tm is about 600 ° C. (absolute temperature, about 870 ° C.), and the crystallization temperature Tc is about 160 ° C. (absolute temperature, about 430 ° C.). ). That is, since the melting point Tm is about twice as large as the absolute temperature compared to the crystallization temperature Tc, a current generally required for melting the phase change material (hereinafter referred to as a rewrite current) Larger than the required current.

  In the phase change memory according to the present embodiment, voids 13 and 14 are provided in interlayer insulating films 9 and 10 between a plurality of parallel lower electrode films 4, and between a plurality of parallel upper electrode films 6. Voids 15 and 16 are provided in the interlayer insulating films 11 and 12. Therefore, the heat generated in the phase change material film 5 during crystallization or amorphization is caused between the adjacent lower electrode films 4 or adjacent upper electrode films 6 through the interlayer insulating films 9, 10, 11 and 12. The phase change material film 5 can be efficiently heated by suppressing the escape through the gap. Therefore, as compared with the case where there are no gaps 13, 14, 15 and 16 and the interlayer insulating film is filled between the lower electrode films 4 and between the upper electrode films 6, the desired temperature (melting point Tm or A crystallization temperature Tc) can be obtained. That is, in the nonvolatile memory device using the phase change memory in this embodiment, power consumption during rewriting and reading of stored information can be reduced.

  The space between the lower electrode films 4 is completely filled with the interlayer insulating films 9 and 10 so that the gaps 13 and 14 are not formed, but only in the interlayer insulating films 11 and 12 between the upper electrode films 6. Even in the case where the gaps 15 and 16 are provided, less power is consumed than when the gaps 13, 14, 15 and 16 are not formed as in the prior art shown in Patent Document 1 and Patent Document 2. Can rewrite and read stored information. This is because the gaps between the upper electrode films 6 are completely filled with the interlayer insulating films 11 and 12 so that the gaps 15 and 16 are not formed, but in the interlayer insulating films 9 and 10 between the lower electrode films 4. This is the same even when only the gaps 13 and 14 are provided, and there is an effect of reducing power consumption. However, since the phase change material film 5 can be heated more efficiently when all the gaps 13, 14, 15, and 16 are formed, all the gaps 13, 14, 15, and 16 are formed as shown in FIG. Preferably it is formed.

FIG. 6 is a graph showing an example of a result of heat conduction analysis performed for examining the effect of reducing the rewrite current in the gap in the phase change memory of the present invention. For comparison, an analysis when there is no void is also shown. FIG. 6 is an analysis example showing the applied current dependence of the temperature of Ge ₂ Sb ₂ Te ₅ (GST) constituting the phase change material film. The vertical axis of the graph represents the temperature of the phase change material film (GST), and the horizontal axis of the graph represents the magnitude of the current flowing through the phase change material film. Here, the members of the first metal wiring 2, the second metal wiring 7, the lower electrode film 4, and the upper electrode film 6 in FIG. The lower electrode film 4 and the upper electrode film 6 have a thickness of 0.005 μm and an area of 0.001 μm ² . Note that the phase change material used here is Ge ₂ Sb ₂ Te ₅ (GST), and the melting point of GST is 600 ° C.

  As shown in FIG. 6, when there are no gaps 13 to 16 in the interlayer insulating films 9 to 12, a current of 140 μA or more is required for the temperature of the phase change material film 5 to exceed the melting point of 600 ° C. On the other hand, in the phase change memory of the present invention, the temperature of the phase change material film 5 reaches the melting point of 600 ° C. at 110 μA. That is, in the phase change memory according to the present invention, by providing the gaps 13 to 16 in the interlayer insulating films 9 to 12 between the upper electrode films 6 and between the lower electrode films 4, the rewrite current is larger than when there is no gap. It can be seen that it is possible to lower the value.

  Here, the operation method of the memory matrix in this embodiment will be described with reference to FIG. FIG. 7 is an equivalent circuit diagram of the memory matrix of the present embodiment. The memory cells MCij (i = 1, 2, 3,..., M) (j = 1, 2, 3,..., N) have a plurality of word lines WLi (i = 1, 1) arranged in parallel. 2, 3,..., M) and a plurality of bit lines BLj (j = 1, 2, 3,..., N) arranged in parallel so as to intersect the word line WLi. Is done. Here, the selection element SE and the phase change resistance element VR are connected in series. In FIG. 7, the diode 3 shown in FIG. 2 corresponds to the selection element SE, and the phase change material film 5 shown in FIG. 2 corresponds to the phase change resistance element VR.

  Recording in the phase change memory is performed as follows. For example, when rewriting the memory cell MC11, the voltage Vh is applied to the first word line WL1, the voltage V1 is applied to the other word line WLi, the voltage V1 is applied to the first bit line BL1, and the voltage Vh is applied to the other bit line BLj. Information is stored by applying a current to the memory element of the memory cell MC11. Here, Vh> V1. At the time of rewriting, a selection element SE having a rectifying action is required in order to prevent erroneous writing from being performed on unselected memory cells. Of course, the voltage Vh must be equal to or lower than the breakdown voltage of the selection element SE. Reading of recorded information is performed as follows. For example, when reading information from the memory cell MC11, the voltage Vm is applied to the first word line WL1, the voltage V1 is applied to the other word line WLi, the voltage V1 is applied to the first bit line BL1, and the current flowing through BL1 is Read information from size.

  In this embodiment, the first metal wiring 2 is a word line and the second metal wiring 7 is a bit line. However, the first metal wiring 2 is a bit line and the second metal wiring 7 is a word line. Good.

  Next, a method for manufacturing the phase change memory according to the present embodiment will be described with reference to FIGS. 8 is a cross-sectional view at the same position as FIG. 2, which is a cross-sectional view taken along line AA shown in FIG. 1. 9 to 44, there are four cross-sectional views at the same positions as the cross-sectional views along the lines AA, BB, CC, and DD shown in FIG. Shown one by one. 8, 9, 13, 17, 21, 25, 29, 33, 37, and 41 are the same positions as FIG. 2, which is a cross-sectional view taken along line AA shown in FIG. 1. FIG. 10, 14, 18, 22, 26, 30, 34, 38, and 42 are cross-sectional views at the same position as FIG. 3, which is a cross-sectional view taken along line BB in FIG. 1. . 11, FIG. 15, FIG. 19, FIG. 23, FIG. 27, FIG. 31, FIG. 35, FIG. 39 and FIG. 43 are cross-sectional views at the same position as FIG. . 12, FIG. 16, FIG. 20, FIG. 24, FIG. 28, FIG. 32, FIG. 36, FIG. 40, and FIG. 44 are cross-sectional views at the same position as FIG. . 45, 46, 47, and 48 are cross-sectional views taken along lines AA, BB, line CC, and DD, respectively, in FIG.

  First, as shown in FIG. 8, a first metal film 2a, a p-type semiconductor film 3a, an n-type semiconductor film 3b, a second metal film 4a, and a phase change material film 5a are sequentially formed on a semiconductor substrate 1.

  The first metal film 2a is made of, for example, W (tungsten) and can be formed by a CVD method or the like. In the case where the p-type semiconductor film 3a is polycrystalline silicon containing B (boron) as an impurity, the p-type semiconductor film 3a and the first metal film 2a are directly bonded to each other, and therefore the material of the first metal film 2a is used. It is preferable to reduce the contact resistance between the p-type semiconductor film 3a and the first metal film 2a as W (tungsten). The film thickness of the first metal film 2a is preferably 10 nm or more and 100 nm or less, for example. If the thickness of the first metal film 2a is too thin, the wiring resistance becomes high, and if it is too thick, it becomes difficult to control the processing shape.

  The material of the p-type semiconductor film 3a is polycrystalline silicon containing B (boron), Ga (gallium) or In (indium) as an impurity, and the material of the n-type semiconductor film 3b is P (phosphorus) or As ( It is polycrystalline silicon containing arsenic) as an impurity. The p-type semiconductor film 3a and the n-type semiconductor film 3b can each be formed by, for example, a CVD method. The total film thickness of the p-type semiconductor film 3a and the n-type semiconductor film 3b is preferably, for example, 30 nm or more and 250 nm or less. In this embodiment, a PN type diode is used as the selection element, but a PIN diode may be used. When a PIN diode is used, an intrinsic polycrystalline layer is provided between the p-type semiconductor film 3a and the n-type semiconductor film 3b. By forming an I layer (intrinsic polycrystalline layer) in which no impurities are mixed between the PN layers, the internal resistance can be varied widely according to the forward current. In addition, a P + / N− / N + diode may be used, and in that case, performance equivalent to that of a PIN diode can be obtained.

  The p-type semiconductor film 3a and the n-type semiconductor film 3b can also be formed by crystallizing by laser annealing after forming as amorphous silicon instead of forming as polycrystalline silicon from the beginning. Thereby, the thermal load in the process can be reduced. Further, in order to reduce the contact resistance, tungsten silicide, titanium silicide, or the like may be formed between the p-type semiconductor film 3a and the first metal film 2a using a silicide technique. Similarly, tungsten silicide or the like may be formed between the n-type semiconductor film 3b and the second metal film 4a.

The phase change material film 5a is made of, for example, Ge ₂ Sb ₂ Te ₅ and can be formed by a sputtering method or the like. As the other phase change material film 5a, a material containing at least one element of chalcogen elements (S, Se, Te) can be used, and the same as Ge ₂ Sb ₂ Te ₅ can be selected by selecting the composition. A degree of performance can be obtained. The film thickness of the phase change material film 5a is preferably 5 nm or more and 300 nm or less, for example.

  Next, as shown in FIGS. 9 to 12, using the lithography technique and the dry etching technique, the phase change material film 5a, the second metal film 4a, the n-type semiconductor film 3b, and the p-type semiconductor along the first direction. The film 3a and the first metal film 2a are sequentially processed into a stripe shape to form a plurality of grooves 20 reaching the semiconductor substrate 1 from the upper surface of the phase change material film 5a. Thereby, the first metal wiring 2 made of the first metal film 2a is formed. Due to the groove 20, the stacked pattern of the phase change material film 5a, the second metal film 4a, the n-type semiconductor film 3b, the p-type semiconductor film 3a, and the first metal wiring 2 becomes a word line pattern and is parallel to the adjacent pattern. Thus, it is formed in a stripe shape along the first direction. The first metal wiring 2 is electrically connected to the semiconductor substrate 1 including a peripheral circuit (not shown) so that the phase change memory can be read and written.

  Next, as shown in FIGS. 13 to 16, an interlayer insulating film 10 is formed on the semiconductor substrate 1. The interlayer insulating film 10 is made of, for example, TEOS and can be formed by a CVD method or the like. At this time, the interlayer insulating film 10 is formed in a part between the p-type semiconductor film 3a, the n-type semiconductor film 3b, the second metal film 4a, and the phase change material film 5a formed in a stripe shape. By using the poor condition, the gap 14 is provided with the interlayer insulating film 10 interposed between the adjacent second metal films 4a. Next, the upper surface of the interlayer insulating film 10 is polished using a CMP (Chemical Mechanical Polishing) technique to expose the surface of the phase change material film 5a.

  Here, the condition with poor embeddability means that a condition in which the interlayer insulating film 10 is formed isotropically is formed when the interlayer insulating film 10 is formed by a CVD method or the like. By forming the interlayer insulating film 10 using a highly isotropic CVD method, the adjacent second metal films 4a can be connected to each other before the interlayer insulating film 10 is filled between the adjacent second metal films 4a. The space between the upper phase change material films 5 a is filled with the interlayer insulating film 10, and the gap 14 is confined in the interlayer insulating film 10. As a result, the interlayer insulating film 10 has a structure having the gap 14 inside the interlayer insulating film 10.

  In addition, when it is desired to increase the thickness of the interlayer insulating film 10 formed below the gap 14, the film is first deposited on the exposed semiconductor substrate 1 using a film-forming condition with good embedding (low isotropic). After the interlayer insulating film 10 is deposited to some extent, the inter-layer insulating film 10 is formed between the adjacent p-type semiconductor film 3a, n-type semiconductor film 3b, second metal film 4a, and phase change material film 5a using the poor embedding condition described above. An interlayer insulating film 10 may be formed in the part.

  Next, as shown in FIGS. 17 to 20, using the lithography technique and the dry etching technique, the interlayer insulating film 10, the phase change material film 5 a, the second metal film 4 a, and the n-type semiconductor film along the second direction. 3b and the p-type semiconductor film 3a are sequentially processed to form a plurality of grooves 21 exposing the upper surface of the first metal wiring 2. As a result, the laminated pattern of the phase change material film 5a, the second metal film 4a, the n-type semiconductor film 3b, and the p-type semiconductor film 3a has a columnar shape, and the phase change material film 5 made of the phase change material film 5a and the second metal film A lower electrode film 4 made of 4a is formed. In addition, a diode 3 having a stacked structure including the n-type semiconductor film 3b and the p-type semiconductor film 3a is formed.

  Next, as shown in FIGS. 21 to 24, an interlayer insulating film 9 is formed on the semiconductor substrate 1. The interlayer insulating film 9 is made of, for example, TEOS and can be formed by a CVD method or the like. At this time, a portion between the laminated patterns composed of the diode 3, the lower electrode film 4 and the phase change material film 5 formed in a stripe shape is filled with the interlayer insulating film 9, but the above-described condition of poor burying property is used. Thus, the gap 13 is provided between the adjacent lower electrode films 4 with the interlayer insulating film 9 interposed therebetween. Thereafter, the surface of the interlayer insulating film 9 is polished using a CMP technique to expose the upper surface of the phase change material film 5.

  Here, the side wall of the phase change material film 5 is covered with the interlayer insulating film 10 and the interlayer insulating film 9, is not exposed, and is not in contact with the gap 14 and the gap 13.

  Next, as shown in FIGS. 25 to 28, third metal film 6 a electrically connected to phase change material film 5 is formed on phase change material film 5 and interlayer insulating films 9 and 10. The third metal film 6a is made of, for example, W (tungsten) and can be formed by a CVD method or the like.

  Next, as shown in FIGS. 29 to 32, the third metal film 6 a is processed into a stripe shape along the first direction by using a lithography technique and a dry etching technique, and each of the interlayer insulating films 9, 10 is processed. A plurality of grooves 22 exposing the upper surface are formed.

  Next, as shown in FIGS. 33 to 36, an interlayer insulating film 11 is formed on the entire surface of the semiconductor substrate 1. The interlayer insulating film 11 is made of, for example, TEOS and can be formed by a CVD method or the like. At this time, the gap 16 is provided between the adjacent third metal films 6a by using the above-described conditions with poor embedding property. Next, the surface of the interlayer insulating film 11 is polished using a CMP technique to expose the upper surface of the third metal film 6a.

  Next, as shown in FIGS. 37 to 40, a fourth metal film 7 a electrically connected to the third metal film 6 a is formed on the third metal film 6 a and the interlayer insulating film 11. The fourth metal film 7a is made of, for example, W (tungsten) and can be formed by a CVD method or the like.

  Next, as shown in FIGS. 41 to 44, the fourth metal film 7a and the third metal film 6a are sequentially processed along the second direction by using a lithography technique and a dry etching technique. Thereby, the second metal wiring 7 made of the fourth metal film 7a is formed, and the columnar upper electrode film 6 made of the third metal film 6a is formed. The upper electrode film 6 is electrically connected to the semiconductor substrate 1 including a peripheral circuit (not shown) so that the phase change memory can be read and written. Through this process, a memory cell having the diode 3, the lower electrode film 4, the phase change material film 5, and the upper electrode film 6 formed in a columnar shape is formed, and a memory matrix in which the memory cells are arranged in a matrix is formed. The

  Next, as shown in FIGS. 45 to 48, after the interlayer insulating film 12 is formed on the entire surface of the semiconductor substrate 1, the upper surface of the interlayer insulating film 12 is polished by a CMP technique to flatten the surface. The interlayer insulating film 12 is made of, for example, TEOS and can be formed by a CVD method or the like. At this time, the gap 15 is provided between the adjacent upper electrode films 6 by using the above-described conditions with poor embedding property. Thereby, the nonvolatile memory device having the phase change memory in this embodiment is completed.

  As described above, in the present embodiment, in the cross-point type phase change memory, heat is generated between the adjacent upper electrode films 6 and between the adjacent lower electrode films 4 than between the interlayer insulating films 9 to 12. By forming the gaps 13 to 16 having low conductivity, heat dissipation generated in the memory cell is prevented, and the phase change material film 5 can be efficiently heated with a lower current than in the past. As a result, power consumption during writing / erasing of the phase change memory can be reduced.

(Embodiment 2)
Next, a nonvolatile memory device in the case where the electrode film 25 is provided on the phase change material film 5 will be described with reference to FIG. 49 is a main-portion cross-sectional view of the phase change memory according to the present embodiment, and shows a cross-sectional view at the same position as FIG.

  The major difference between the phase change memory of the present embodiment and the phase change memory shown in the first embodiment is that a thin electrode film 25 is provided between the phase change material film 5 and the upper electrode film 6. That is.

  The electrode film 25 is formed by forming a metal film on the phase change material film 5a after forming the phase change material film 5a in the step shown in FIG. 8 of the above embodiment. The electrode film 25 is made of, for example, W (tungsten) and can be formed by a CVD method or the like.

  In the manufacturing process according to the present embodiment, before each phase change material film 5a is processed into a stripe shape in each etching process described with reference to FIGS. 9 to 12 and FIGS. 17 to 20 in the first embodiment. Then, the W (tungsten) film on the phase change material film 5a is etched in a stripe shape extending in the same direction as the pattern formed by processing in each step, and the electrode film 25 is formed on the phase change material film 5. .

  Further, in each polishing process using the CMP technique described with reference to FIGS. 13 to 16 and FIGS. 21 to 24 in the first embodiment, the upper surface of the phase change material film 5a or the phase change material film 5 is not exposed. The polishing is stopped when the upper surface of the electrode film 25 is exposed to leave the electrode film 25 on the phase change material film 5.

  In the present embodiment, in addition to the same effects as those of the first embodiment, an electrode film 25 is formed between the upper electrode film 6 and the phase change material film 5, so that the phase change material film 5 a or Exposure of the surface of phase change material film 5 can prevent phase change material film 5a or phase change material film 5 from sublimating, and adhesion between upper electrode film 6 and phase change material film 5 can be prevented. It is possible to improve.

(Embodiment 3)
Next, in this embodiment, a nonvolatile memory device in the case where the width of the phase change material film 5 is narrowed will be described with reference to FIG. 50 is a main-portion cross-sectional view of the phase change memory according to the present embodiment, and shows a cross-sectional view at the same position as FIG. In addition, the width | variety of each site | part here is a direction in alignment with the main surface of the semiconductor substrate 1, Comprising: The width | variety in the 1st direction shown in FIG.

  A major difference between the phase change memory of the present embodiment and the phase change memory shown in the first embodiment is the width of the phase change material film 5. In the phase change memory shown in the first embodiment, the width of the phase change material film 5 is the same as the width of the lower electrode film 4 and the upper electrode film 6, but in the phase change memory of the present embodiment, The width of the change material film 5 is smaller than the widths of the lower electrode film 4 and the upper electrode film 6.

  In the present embodiment, by reducing the width of the phase change material film 5, the cross-sectional area of the cross section of the phase change material film 5 on the surface along the main surface of the semiconductor substrate 1 is the surface along the main surface of the semiconductor substrate 1. The phase change material can be made smaller than the cross-sectional area of any cross section of the diode 3, the lower electrode film 4, and the upper electrode film 6 and the current density of the phase change material film 5 at the time of rewriting can be increased. It is possible to increase the heat generation density in the film 5. Thereby, the phase change material film 5 is efficiently heated, and the cross-sectional area of the phase change material film 5 and the lower electrode film 4 or the upper electrode film 6 on the surface along the main surface of the semiconductor substrate 1 is the same as that of the case. Rewriting can be performed with a low current, and power consumption can be further reduced as compared with the nonvolatile memory device shown in Embodiment Mode 1.

  As a method of reducing the width of the phase change material film 5 in the second direction as compared with the widths of the lower electrode film 4 and the upper electrode film 6, for example, the steps of FIGS. 9 to 12 shown in the first embodiment are used. After the dry etching step in FIG. 13 and before the steps of FIGS. 13 to 16, the phase change material film 5a is processed by isotropic dry etching and side etching is performed on the side surface of the phase change material film 5a. is there.

  Further, as a method for reducing the width of the phase change material film 5 in the first direction as compared with the widths of the lower electrode film 4 and the upper electrode film 6, for example, FIGS. 17 to 20 shown in the first embodiment. After the dry etching step in the step, and before the steps of FIGS. 21 to 24, the phase change material film 5 is processed by an isotropic dry etching method and side etching is performed on the side surface of the phase change material film 5. There is a way.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, the present invention can also be applied to a nonvolatile memory device that uses a plurality of stacked memory matrices shown in the first to third embodiments.

  The method for manufacturing a nonvolatile memory device of the present invention is widely used for nonvolatile memories using phase change memories.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st metal wiring 2a 1st metal film 3 Diode 3a p-type semiconductor film 3b n-type semiconductor film 4 Lower electrode film 4a 2nd metal film 5 Phase change material film 5a Phase change material film 6 Upper electrode film 6a 1st 3 Metal film 7 Second metal wiring 7a Fourth metal film 9, 10, 11, 12 Interlayer insulating films 13, 14, 15, 16 Gaps 20, 21, 22 Groove 23 Intersection 25 Electrode films WL1, WL2, WLi, WLm Word Lines BL1, BL2, BLj, BLn Bit line SE Select element VR Phase change resistance element

Claims (10)

A plurality of first metal wires extending along a first direction of the main surface of the semiconductor substrate;
A plurality of second metal wirings extending along a second direction orthogonal to the first direction;
A non-volatile memory device having a memory cell including a phase change material film as a memory element driven by current and a diode as a selection element at each intersection of the plurality of first metal lines and the plurality of second metal lines. There,
Each memory cell has
The diode formed on the first metal wiring;
A first metal electrode formed on the diode;
The phase change material film formed on the first metal electrode;
A second metal electrode formed on the phase change material film and below the second metal wiring;
Have
A non-volatile memory device , wherein gaps are formed between the adjacent first metal electrodes and between the adjacent second metal electrodes.   The non-volatile memory device according to claim 1, wherein the gap is formed in an interlayer insulating film formed between adjacent memory cells.   The cross-sectional area of the phase change material film on the surface along the main surface of the semiconductor substrate is equal to the cross-sectional area of either the diode, the first metal electrode, or the second metal electrode on the surface along the main surface of the semiconductor substrate The non-volatile memory device according to claim 1, wherein the non-volatile memory device is smaller.   The nonvolatile memory device according to claim 1, wherein a side wall of the phase change material film is covered with an interlayer insulating film formed between the memory cells.   The nonvolatile memory device according to claim 1, wherein a metal film is formed between the phase change material film and the second metal electrode. A method for manufacturing a nonvolatile memory device including a phase change memory including a diode and a resistance element including a phase change material film on a main surface of a semiconductor substrate,
(A) A first metal film, a first polysilicon film containing a first conductivity type impurity, a second polysilicon film containing a second conductivity type impurity, a second metal film, and the phase change material on the semiconductor substrate. A step of sequentially forming a film;
(B) After the step (a), along the first direction of the main surface of the semiconductor substrate, the phase change material film, the second metal film, the second polysilicon film, the first polysilicon film, and Etching the first metal film in a stripe shape sequentially;
(C) after the step (b), forming a first interlayer insulating film between the adjacent phase change material films on the semiconductor substrate;
(D) After the step (c), along the second direction orthogonal to the first direction, the first interlayer insulating film, the phase change material film, the second metal film, the second polysilicon film, Etching the first polysilicon film and the first metal film in stripes;
(E) after the step (d), forming a second interlayer insulating film between the adjacent phase change material films on the semiconductor substrate;
(F) After the step (e), a third metal electrically connected to the phase change material film on the first interlayer insulating film, the second interlayer insulating film, and the phase change material film Forming a film;
(G) After the step (f), a step of etching the third metal film in a stripe shape along the first direction;
(H) After the step (g), a step of forming a third interlayer insulating film between the adjacent third metal films;
(I) after the step (h), forming a fourth metal film electrically connected to the third metal film on the third metal film and the third interlayer insulating film;
(J) After the step (i), the third interlayer insulating film, the fourth metal film, and the third metal film are etched along the second direction, so that the third interlayer insulating film, Etching the four metal films and the third metal film in stripes;
(K) after the step (j), forming a fourth interlayer insulating film between the adjacent fourth metal films;
Have
A method for manufacturing a nonvolatile memory device, wherein a gap is formed between at least one of the adjacent second metal films or between the adjacent third metal films.   7. The nonvolatile memory device according to claim 6, wherein the air gap is formed in the first interlayer insulating film, the second interlayer insulating film, the third interlayer insulating film, or the fourth interlayer insulating film. Manufacturing method. Side walls of the phase change material film at least one of after the step (b) and before the step (c) or after the step (d) and before the step (e) A step of etching a part of
7. The cross-sectional area of the phase change material film on a surface along the main surface of the semiconductor substrate is made smaller than the cross-sectional area of the first metal film on a surface along the main surface of the semiconductor substrate. The manufacturing method of the non-volatile memory device of description. In the step (a), the first metal film, the first polysilicon film, the second polysilicon film, the second metal film, the phase change material film, and the fifth metal film are sequentially formed on the semiconductor substrate. Forming,
In the step (b), the fifth metal film, the phase change material film, the second metal film, the second polysilicon film, and the first poly film along the first direction of the main surface of the semiconductor substrate. The silicon film and the first metal film are sequentially etched into a stripe shape,
In the step (d), the first interlayer insulating film, the fifth metal film, the phase change material film, the second metal film, the second polysilicon film, and the first poly film along the second direction. Etching the silicon film and the first metal film in stripes;
In the step (f), the third metal film electrically connected to the phase change material film is formed on the first interlayer insulating film, the second interlayer insulating film, and the fifth metal film. The method of manufacturing a nonvolatile memory device according to claim 6.   In the step (c), the step (e), the step (h) or the step (k), the first interlayer insulating film, the second interlayer insulating film, the third layer are formed by an isotropic CVD method. 7. The method of manufacturing a nonvolatile memory device according to claim 6, wherein the interlayer insulating film or the fourth interlayer insulating film is formed.

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