JP2009075942A - Dma controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DMA controller which releases a bus according to a bus bandwidth used for data transfer. <P>SOLUTION: A DMA controller 24 comprises a bandwidth setting register 38 which acquires the bus bandwidth used for data transfer by each module, a transferring counter 36 which acquires data transfer count of each module, and a priority register 40 which acquires the priority of each module. The DMA controller 24 determines the priority order of each module on the basis of the bus bandwidth, the data transfer count, and the priority and releases the bus to each module according to the priority order, so that a module with a bandwith set thereto performs data transfer with bandwidth guarantee. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data transfer control device, and more particularly to a DMA controller that performs data transfer via a DMA (Direct Memory Access) and a bus.

As a method of controlling bus access by multiple modules, there is a method of giving higher priority to modules with high urgency and modules that require a certain amount of bandwidth and lowering the priority of other modules. is there. However, in this method, the necessary bandwidth may not be secured unless the priority of each module is set appropriately, and it is not guaranteed whether the bandwidth can be secured simply by increasing the priority. In addition, the bus bandwidth may be occupied more than necessary, which may affect the operation of other modules. For example, in a bus access by DMA or the like, a module with a high priority keeps occupying the bus for a long time, and a module with a low priority is kept waiting. In order to avoid these problems, even if the bus use right is secured, the bus use right may be transferred for every predetermined number of transfers according to other requests, or the priority of bus use may be changed within a certain period. And do not occupy for a long time.
JP 2003-6139 A JP-A-2005-165508

  However, in either method, it is not possible to easily determine how long the bus will be released or to change the priority, so it takes trial and error to set the priority. Difficult to set up.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer control device and a transfer control method thereof capable of transferring data without failure even for real-time data transfer.

  In order to achieve such an object, the present invention divides the data to be transferred into certain short units and transfers them. More specifically, the DMA controller of the present invention regards data as a plurality of divided transactions, and performs scheduling according to the bus bandwidth required by the module that transfers the data, the transfer rate of the module, and the like.

  Further, according to the present invention, scheduling is performed according to a time-varying band. More specifically, the DMA controller of the present invention acquires the bandwidth and transfer rate of the module that made the request for each DMA transfer request.

  According to the present invention, since the transfer data is divided into the smallest units and scheduling is performed, it is possible to prevent one transfer having a high priority from occupying the bus for a long time. In addition, by guaranteeing the bandwidth, it is possible to provide a system that does not fail even for real-time transfer.

  In addition, according to the present invention, since the bandwidth can be set frequently in one request unit, flexible setting is possible, and even if the transfer is performed by the same module, the real-time property is provided corresponding to the bus bandwidth that changes with time. It can be secured.

  Furthermore, according to the present invention, the bus operating frequency can be set in real time according to the required bus bandwidth, and power saving can be realized while the bus speed is increased.

  Embodiments of a DMA controller according to the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a bus control mechanism using a DMA controller according to the present invention. The bus control mechanism 10 according to this embodiment includes a bus 12, CPUs 14 and 16, a first module 18, a second module 20 to an nth module 22 (n is a positive integer), and a DMA controller 24. It should be noted that elements not directly related to the understanding of the present invention are omitted to avoid redundant description.

  Such a DMA controller can be used for any device equipped with a bus. For example, a real-time distribution system for audio and video, a system that requires real-time image processing, a video phone, a mobile phone, a digital video camera, a digital It can be used for a still camera or the like.

  The bus 12 is an information transmission path shared by the CPUs 14 and 16, the modules 18, 20 and 22, and the DMA controller 24. The CPUs 14 and 16 control and control the entire bus control mechanism 10 via the bus 12. The first module 18 is an arbitrary functional unit. For example, when the bus control mechanism of this embodiment is mounted on a digital camera, the first module 18 is a signal processing unit, an image processing unit, a memory, a recording / reproducing unit, and the like. The same applies to the second module 20 to the nth module 22. These modules transmit and receive data via the bus 12. The DMA controller 24 controls data transfer of each module. For example, when the first module 18 performs data transfer, a request signal 26 requesting release of the bus is sent from the first module 18. On the other hand, the DMA controller 24 returns an acknowledge signal 32. If this signal permits the first module 18 to use the bus 12, the first module can transfer data. In the bus control mechanism 10 in this embodiment, there are two CPUs and one DMA controller. However, the present invention is not limited to this, and an arbitrary number of CPUs and DMA controllers can be used. Is possible.

  The DMA controller 24 of this embodiment regards DMA transfer data as a plurality of transactions divided into basic time units, and schedules transfer of individual transactions. As shown in FIG. Each function unit includes a transfer counter 36, a band setting register 38, a priority register 40, and a bus arbiter 42.

  The period setting register 34 holds a value of a certain period and passes the certain period information 44 to the transfer counter. The fixed period can be set to an arbitrary value by an arbitrary method.

  The transfer counter 36 measures the number of transactions transferred from the first module 18, the second module 20 to the n-th module 22 over a certain period of time, and these values are respectively measured as the first module counter 46 and the second module counter 48. Or it is held in the nth module counter 50. The past transfer count information 52 is passed to the bus arbiter as necessary. The transfer counter is reset at regular intervals based on the information 44 received from the period setting register and newly measures the number of transfers.

  The band setting register 38 stores the bus band values required by the first module 18, the second module 20 through the nth module 22, and the first module band storage section 54, the second module band storage section 56 through the nth module, respectively. It is held in the band storage unit 58. In this embodiment, the bandwidth is expressed as a bus time occupation rate. The bandwidth may not be set for all modules, but the total value obtained by converting all bandwidth values into the time occupancy rate of the bus should not be greater than 1. The setting or changing of the bandwidth can be performed at an arbitrary time by an arbitrary method, and is performed by the CPU 14 in this embodiment. However, this setting or change is reflected in the control by the DMA controller at regular intervals. The bandwidth information 60 is transferred to the bus arbiter 42 as necessary, and scheduling is performed with the highest priority so that transfer within a predetermined time is surely performed for the module for which the bandwidth is set.

  The priority register 40 stores the priorities of the first module 18, the second module 20 through the nth module 22, respectively, and stores the first module priority storage unit 62, the second module priority storage unit 64 through the nth module priority, respectively. The unit 66 is held, and priority information 68 is passed to the bus arbiter as necessary. The priority can be set or changed by an arbitrary method at an arbitrary time, and is performed by the CPU 14 in this embodiment. This setting or change is reflected in the control by the DMA controller at regular intervals.

  The bus arbiter 42 performs transfer priority calculation of each transaction based on priority determination information including the bandwidth, past transfer count, and priority of each module, and outputs an acknowledge signal 32 to each module based on the result. It is. When there are multiple requests for the modules whose bandwidths are set at the same time and the total bus occupancy of these modules exceeds 1, an error signal 70 is output to the CPU to generate an interrupt.

  With reference to FIG. 2, the scheduling method by the DMA controller of the present invention will be described in more detail. In the example shown in FIG. 2, the data 74 from the first module, the data 76 and 78 from the second module, the data 80, 82 and 84 from the third module in the fixed period 72 set by the period setting register 34. Request to forward is accepted. First, requests for transferring data 74 and 80 are received from the first module and the third module, respectively, and these data are regarded as a plurality of transactions divided in basic time units. The basic time unit can be arbitrarily set. For example, when the basic time unit is set to 16 bytes, data having a data amount of 1 KB is regarded as 64 transactions. The amount of data required at this time can be obtained by an arbitrary method.For example, the method obtained from the DMA controller together with the DMA transfer request from each module, the method obtained from the CPU, or the transfer data transfer source and data size. There is a method of obtaining from a stored register or the like. In the example shown in FIG. 2, data 74 is considered as transactions 86, 88, etc., and data 80 is considered as transactions 90 and 92. Which transaction is transferred is determined by calculation for each basic time unit. For example, if the basic time unit is 16 bytes and the bus width is 4 bytes, the transferred transaction is determined every 4 bus cycles. As a result, in the example shown in FIG. 2, the third module is first permitted to use the bus and transfers the transaction 90, and then the first module is permitted to use the bus and transfers the transaction 86.

  In the example shown in FIG. 2, before the transfer of data 74 is completed, a request for transferring data 82 from the third module and subsequently data 76 from the second module is accepted. In this case, the DMA controller 24 does not wait until the transfer of the data 74 is completed, and based on the bandwidth, the number of past transfers, the priority, etc., the module from which module including the new request should be preferentially executed. Judgment is made and the use of the bus is permitted to the module having the highest priority. When the fixed period 72 elapses, the transfer counter 36 is reset once and counts again for a fixed period.

  The priority determination method will be described in more detail with reference to FIG. FIG. 3 shows the priority, bandwidth, and past transfer count of each module, and is used for priority determination. In the example shown in FIG. 3, the priority is higher as the numerical value is higher, with 5 being the highest and 1 being the lowest. In the example shown in FIG. 3, the first module and the fifth module are set, but the other modules are not set. The past transfer count is the number of transactions transferred from each module from the start of the most recent fixed period 72 to the present. In the example shown in FIG. 3, the past transfer count is a value when 10 basic hours have elapsed since the start of this fixed period.

  The priority determination is performed preferentially from the band-set module, and the band and the past transfer rate are first compared. In the present embodiment, the past transfer rate is represented by (the number of past transfers) / (basic time elapsed from the start of the latest fixed period to the present). That is, in the example shown in FIG. 3, the transfer rate of the first module is 0.2, and the priority rate of the fifth module is 0.3.

  The bandwidth is compared with the past transfer rate, and if the bandwidth <the past transfer rate, the urgency is low, and if the bandwidth> the past transfer rate, the urgency is determined to be high. That is, in the example shown in FIG. 3, the first module determines that the urgency level is low because the bandwidth value is 0.1 and the past transfer rate is 0.2. In the fifth module, the urgency is determined to be high because the bandwidth is 0.5 and the past transfer rate is 0.3. Data transfer from a module determined to have a high degree of urgency is executed with the highest priority. In the example of FIG. 3, data transfer from the fifth module is executed. When there are a plurality of modules having a bandwidth> past transfer rate, data transfer is performed from a module with a high priority or a module with a low transfer rate. In this case, which module is prioritized can be arbitrarily set. Therefore, when the priority is the same, priority is given to transfer from a module with a low transfer rate, and when the transfer rate is the same, priority is given to data transfer from a module with a low priority. In the case of exactly the same conditions, priority determination is performed using a round robin method or a fixed priority set separately from the priority for each module.

  The priority determination when there is no module with a bandwidth> past transfer rate may be performed in the same manner as the determination method when there are a plurality of modules with a bandwidth> past transfer rate, including modules for which no bandwidth is set. The same applies when there is no module for which the bandwidth is set.

  FIG. 4 is a flowchart showing an example of a priority determination processing procedure in the DMA controller 24 shown in FIG. With reference to FIG. 4, the processing procedure of the DMA controller 24 used in the present invention will be specifically described. First, when a request is received by the DMA controller (S10), data transferred by this request is regarded as a plurality of transactions divided into basic time units (S12).

  The past transfer count information 52 of the module that made this request is sent from the transfer counter 36 to the bus arbiter 42 (S14). Further, the band information 60 of this module is sent from the band setting register to the bus arbiter, and it is determined whether or not the band is set (S16).

  When the bandwidth is set (YES), the bandwidth value of this module is compared with the past transfer rate (S18). If the bandwidth value is larger than the transfer rate (NO), the request from this module is regarded as a highly urgent request (S20). Here, it is determined whether or not there is a request from another module (S22). If there is no request from another module (NO), this request is executed (S24). If YES, the request with the highest priority is selected based on the priority determination information (S26) and executed (S28).

  If no bandwidth is set for the module that made the request, a determination is made in step S22, and the same processing is performed thereafter.

  FIG. 5 conceptually shows another example of the bus control mechanism using the DMA controller according to the present invention. In the bus control mechanism 100 according to the present embodiment, data from each module is transferred corresponding to a band that changes with time. 5, the same reference numerals as those in FIG. 1 denote the same components.

  In the example shown in FIG. 5, the priority order of bus use is assigned according to the band designated for each transfer data. More specifically, the DMA controller 100 includes a data information acquisition unit 102, a band setting data scheduling unit 104, a non-band setting data scheduling unit 106, and an overall schedule management unit 108, and according to the band value specified for each data Scheduling. In the embodiment shown in FIG. 5, the bandwidth is represented by the time occupancy rate of the bus.

  The data information acquisition unit 102 acquires information about transfer data sent to the DMA controller together with the request, and determines whether or not a band is set for the transfer data. The transfer data information includes priority, bandwidth, data amount, and the like. The data information 110 of the data for which the bandwidth is set is sent to the bandwidth setting data scheduling unit 104, and the data information 112 of the data for which the bandwidth is not set is It is passed to the non-bandwidth setting data scheduling unit 106.

  The configuration of the transfer data will be described in more detail with reference to FIG. In the example shown in FIG. 6, the transfer data is composed of a header packet 114 and a data packet 116, and the priority, bandwidth value and data amount of this data are stored in the header packet 114. At the time of a DMA transfer request, this header packet is sent to the data information acquisition unit 102 and analyzed. Of course, the data information may be acquired using other known means, and the data configuration is not limited to the packet configuration.

  Band setting data scheduling unit 104 regards the band set data as a plurality of transactions, and determines transfer schedule 118 for each transaction based on data information 110 so that transfer according to the band of the data is performed. It is. The schedule 118 is transferred to the overall schedule management unit 108.

  The non-bandwidth data scheduling unit 106 regards data for which no band is set as a plurality of transactions, and determines a transfer schedule 120 for each transaction based on the data information 112. Allocation of the transfer order of data for which no band is set is basically performed in the accepted order. However, when a packet with a higher priority comes later, the schedule of data with a lower priority may be canceled and rescheduling may be performed. Of course, you may determine using the fixed priority provided separately from the round robin system and the priority. The schedule 120 is passed to the overall schedule management unit 108.

  The overall schedule management unit 108 receives the schedules 118 and 120 and adjusts both schedules. If the transfer cannot be performed according to the schedule 118, the overall schedule management unit 108 issues a rescheduling request 122 to the scheduling unit 104, and performs scheduling in consideration of transfer of all data including non-bandwidth setting data. Make it. If the transfer cannot be performed according to the schedule 120, the rescheduling request 124 is issued to the scheduling unit 106 to perform the scheduling so that the data is transferred in the idle time of the bandwidth setting data schedule. Once the schedules 118 and 120 have been adjusted to determine the overall data schedule 126, the overall schedule 126 is passed to the bus arbiter 42. If scheduling that can secure the bandwidth is not performed because the sum of the bandwidth values of all the modules that have made the requests exceeds 1, the overall schedule management unit 108 issues an error interrupt to the CPU.

  The state of data division and scheduling will be described in detail with reference to FIG. In the example shown in FIG. 7, a request for requesting transfer of first data 128, then second data 130, and finally third data 132 is accepted. The data amount of the first data 128 is 10, and the bandwidth value is set to 0.5. The data amount of the second data 130 is 6, the priority is 2, and no band is set. The data amount of the third data 132 is 2, the priority is 3, and no band is set. The first data is regarded as three transactions 134, 136, and 138. Since the bandwidth of the first data is 0.5, the data amount of each transaction is 4, 4, 2, and the transfer interval of each transaction is 4 data cycles. Scheduled. This scheduling is determined before the data 128 is transferred, and is not changed during the transfer. The number of transactions, the data amount of each transaction, and the transfer interval can be obtained using any method. For example, a value corresponding to the bandwidth or the transfer amount is stored in a register or data information, and is extracted as necessary And so on.

  The second data for which no bandwidth has been set is transferred as transactions 140 and 142, and the third data is transferred as a transaction 144 in the idle time of the data 128 transfer schedule. As a method for determining the number of transactions and the data amount of each transaction, a method similar to the method used for the band-set data may be used. In the example shown in FIG. 3, the transfer request for data 132 is accepted after the transfer request for data 130, but since data 132 has a higher priority, data 132 is scheduled to be transferred first. .

  FIG. 8 is a flowchart showing an example of a processing procedure in the DMA controller 24 shown in FIG. With reference to FIG. 8, the data transfer processing procedure of the present invention will be described in detail. In FIG. 8, the same reference numerals as those in FIG. 4 indicate similar processes. First, a DMA transfer request from a certain module and data information of data transferred by this request are received by the DMA controller 24 (S30). The data information is sent to the data information acquisition unit 102, and it is determined whether a band is set for this data (S32).

  The band-set data is scheduled according to the band by the band setting data scheduling unit 104 (S34). The scheduled data is judged by the overall schedule management unit 108 as to whether or not the scheduling can be performed as requested by the bandwidth setting data scheduling unit 104 (S36). If scheduled as requested (YES), it is transferred according to the schedule (S38). ), If it cannot be scheduled as requested (NO), it is rescheduled including other data (S40). At this time, if scheduling that satisfies the bandwidth cannot be performed according to the transfer schedule of other data that has already been determined, all the schedules of data for which bandwidth is not set are canceled and rescheduling is performed. After that, it is determined whether or not scheduling can be performed as requested by the scheduling unit 104 (S42). If scheduling can be performed as requested (YES), data transfer is performed according to this schedule (S38). NO) reports an error to the CPU 16 from the overall scheduling unit 108 (S44).

  On the other hand, the data for which the band is not set is scheduled to be transferred by the scheduling unit 106 during the idle time of the transfer schedule of other data (S46).

  FIG. 9 conceptually shows another example of the bus control mechanism using the DMA controller according to the present invention. In the bus control mechanism 200 shown in FIG. 9, the operating speed of the bus 12 is changed according to the required bus bandwidth. 9, the same reference numerals as those in FIG. 1 denote the same components.

  In the example shown in FIG. 9, bands are set for all modules, and the operating speed of the bus 12 is changed according to the sum of the band values of all modules. More specifically, the bus control mechanism 200 includes a bus clock control unit 202 and a clock controller 204, and the bus clock control unit 202 and the clock controller 204 actively control the bus clock. In the embodiment shown in FIG. 9, the bandwidth is represented by the transfer amount per unit time.

  The bus clock control unit 202 calculates the bus frequency based on the total data transfer amount of each module. The calculated frequency value 206 is output to the clock controller 204.

  The clock controller 204 performs clock control of the entire circuit including bus clock control by setting values from the bus control unit. The clock controller 204 passes a clock corresponding to the frequency value 206 to each module or CPU.

  The frequency calculation method will be described in more detail with reference to FIG. The past transfer count of the priority determination information shown in FIG. 10 is the transfer count of each module in the past 10 basic times. The total bandwidth value of all modules is 80MB / sec. The occupancy ratio of the bus requested by each module is expressed by (band value of each module) / (sum of the band values of all modules). For example, the bus occupancy ratio of the fifth module is 0.5. The bus frequency is represented by (total of band values of all modules) / (bus width). In the example shown in FIG. 9, if the bus width is 4 bytes, the bus frequency is calculated to be 20 MHz. Further, since the bus occupancy rate of the fifth module is 0.5 and the past transfer rate is 0.3, transfer is performed with the highest priority.

It is a functional block diagram which shows the structure of the Example of the bus control mechanism using the DMA controller by this invention. It is a figure which shows an example of the scheduling by the DMA controller shown in FIG. It is a figure which shows an example of the priority determination information in the Example. It is a flowchart which shows operation | movement of the DMA controller in the Example. It is a functional block diagram which shows the structure of the other Example of the bus control mechanism using the DMA controller by this invention. It is a figure which shows an example of a structure of the data transferred from the module shown in FIG. It is a figure which shows an example of the scheduling by the DMA controller in the Example. It is a flowchart which shows operation | movement of the DMA controller in the Example. It is a functional block diagram which shows the structure of the other Example of the bus control mechanism using the DMA controller by this invention. It is a figure which shows an example of the priority determination information in the Example shown in FIG.

Explanation of symbols

10 Bus control mechanism
36 Transfer counter
38 Band setting register
42 Bus Arbiter
102 Data information acquisition unit

Claims (11)

In a DMA controller that receives a transfer request from a module connected to the system bus and controls DMA transfer between the modules, the DMA controller
Band acquisition means for acquiring a bus band used for transferring data transferred by the request;
Measuring means for measuring the number of times of data transfer of the module;
A transfer control means for obtaining a bus time occupation rate from the bus band, obtaining a transfer rate from the number of transfers, comparing the occupation rate with the transfer rate, and releasing the system bus to the module according to a comparison result; DMA controller characterized by including.   2. The DMA controller according to claim 1, wherein the transfer control means releases the system bus to a module having the occupation rate higher than the transfer rate.   2. The DMA controller according to claim 1, wherein the transfer control unit performs transfer most when there are a plurality of modules having the higher occupation ratio than the transfer ratio, or when there is no module having the higher occupation ratio than the transfer ratio. A DMA controller that releases the system bus to a low-rate module. The DMA controller according to claim 1,
The DMA controller further includes second storage means for storing the priority of the module;
The transfer control means, when there are a plurality of modules having the higher occupation rate than the transfer rate, or when there is no module having the higher occupation rate than the transfer rate and there are a plurality of modules having the lowest transfer rate. A DMA controller, characterized by releasing the system bus to the highest priority module. The DMA controller according to claim 1,
The DMA controller further includes second storage means for storing the priority of the module;
The transfer control unit releases the system bus to the module having the highest priority when there are a plurality of modules having the occupation ratio higher than the transfer ratio or when there is no module having the occupation ratio higher than the transfer ratio. A DMA controller characterized by   2. The DMA controller according to claim 1, wherein the transfer control unit has the highest priority when there are a plurality of modules having the higher occupation ratio than the transfer ratio or when there is no module having the higher occupation ratio than the transfer ratio. A DMA controller, wherein when there are a plurality of modules having a high degree, the system bus is released to a module having the lowest transfer rate. In a DMA controller that receives a transfer request from a module connected to the system bus and controls DMA transfer between the modules, the DMA controller
Data information acquisition means for acquiring a bus bandwidth used for transferring data transferred by the request and a data amount of the data;
A DMA controller, comprising: transfer control means for releasing the system bus to a module that transmits the transfer data according to the bus bandwidth and the data amount.   8. The DMA controller according to claim 7, wherein the transfer control means releases the system bus to a module that transmits data for which bandwidth is not set during a free time of a data transfer schedule for which bandwidth is set. DMA controller.   8. The DMA controller according to claim 1, wherein the band is set for each module.   8. The DMA controller according to claim 1, wherein the band is set for each piece of data.   8. The DMA controller according to claim 1, further comprising bus clock control means for setting a frequency of the system bus in accordance with the bus band.

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