JP2009071598A - Image processing unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing unit efficiently making encoding without degrading image quality. <P>SOLUTION: A liquid display device is equipped with an RGB data transmitting circuit 1, an LCD(Liquid Crystal Display) source driver 2, and an LCD panel 3. The LCD source driver 2 has an RGB data receiving circuit 4, an ABD-BTC encoding circuit 5, a memory 6, an ABD-BTC decoding circuit 7, and an LCD driving circuit 8. A pixel block is made in a small size of 2×2 pixels. Thus, a simple circuit calculate an average value in the pixel block. Especially, a divider tending to have a large hardware scale can be comprised of only a 1/3 multiplier. The 1/3 multiplier can reduce the hardware scale by performing approximate calculation. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing apparatus that encodes or decodes RGB data.

  Image compression technology (hereinafter referred to as BTC technology) by block truncation coding (BTC) has been widely studied. BTC technology has been conventionally used in FAX machines and copiers, but in recent years, examples of use in display devices have increased. In the display device, it is necessary to reduce the frame memory used for the overdrive technology of the liquid crystal TV as much as possible, and the BTC technology is used to reduce the frame memory. There are two reasons why BTC technology is used in display devices. One reason is that TV images are processed by 420 decimation, MPEG compression, and the like, and originally the distortion of the moving image itself is large and the image degradation is large. Because it is not done. The other reason is that the frame memory required for overdrive is only the reference data necessary for processing.In fact, the correction amount is determined by directly using the data, so even if the stored image deteriorates. This is because since the data can be directly used, the deterioration as the overdrive correction amount is not so great.

  On the other hand, the embedded RAM mounted on the mobile phone also stores image data as a frame memory. This is directly used as a still image. Can be found. This is a big problem for BTC use, and BTC use cannot be assumed in the past.

  On the other hand, the present inventor proposed for the first time that BTC can be used as a compression technique for portable RAM by reducing the block error by extending BTC. According to the proposal by the present inventor, the VGA size memory can be reduced to a quarter QVGA memory size by 4 × 4 pixel block processing. The encoding hardware at this time is a comparatively large size of about 25 KG, and the increase in hardware of the encoder and decoder can be absorbed by greatly reducing the memory.

  On the other hand, in terms of the rate of commercial spread, QVGA is still the main display device for mobile phones. Therefore, I would like to consider applying BTC technology to QVGA. However, there are the following problems at this time. In QVGA, since the initial memory size is small, the increase in the hardware size of the encoder and decoder becomes larger than the reduction in the memory size, and the reduction effect cannot be obtained.

  Non-Patent Document 1 discloses a technique for adaptively controlling BTC. Two-dimensional quantization (also called joint coding coding) is based on the fact that high accuracy is not required in the high change region, but high accuracy is required in the low change region. In the two-dimensional quantization, the compression ratio is further increased by combining the average value X and the variance σ into one code. However, when two-dimensional quantization is performed, there is a problem that the hardware size increases.

Japanese Patent Application Laid-Open No. H10-228561 discloses a technique that uses the BTC technique for compressing an overdrive memory of a liquid crystal TV. Patent Document 2 is intended for large-sized liquid crystal TVs such as TVs, and requires strict image evaluation standards. For this reason, a complicated BTC algorithm is required. A small display device such as a cellular phone has a limited display size and resolution, and does not require a complicated BTC algorithm as in Patent Document 1.
JP 2006-208770 A OR Mitchell, EJ Delp, “Multilevel Graphics Representation Using Block Truncation Coding,” Proceedings of the IEEE, VOL. 68, NO.7, JULY 1980, pp.868-873.

  The present invention provides an image processing apparatus capable of efficiently encoding without degrading image quality.

According to one aspect of the present invention, an average value calculating means for calculating an average value of pixel values in the pixel block for each of adjacent 2 × 2 pixel block,
Representative value calculating means for calculating an upper representative value larger than the average value calculated by the average value calculating means and a lower representative value smaller than the average value for each of the pixel blocks;
Image change determination means for determining whether a difference between the upper representative value and the lower representative value is greater than a predetermined threshold for each pixel block;
If it is determined by the image change determination means that it is larger than the threshold value, it is determined that the image is rough and first encoded data is generated, and if the image change determination means determines that the threshold value is equal to or less than the threshold value, Encoding processing means for determining that the image is flat and generating second encoded data;
Storage means for storing the first encoded data and the second encoded data,
The average value calculating means includes
First and second adders for calculating in parallel the sum of pixel values of every two pixels in the pixel block;
A third adder that calculates the sum of the addition result of the first adder and the addition result of the second adder;
A quarter divider that shifts the bit string representing the addition result of the third adder by 2 bits and calculates the average value;
The representative value calculating means includes:
A comparison is made between the average value and each pixel value in the pixel block, and a first cumulative addition value obtained by cumulatively adding pixel values larger than the average value, and a pixel value less than the average value are cumulatively added. A cumulative adder that calculates a cumulative added value of 2;
Upper and lower calculating the upper representative value based on the first cumulative added value and the cumulative number of times and calculating the lower representative value based on the second cumulative added value and the cumulative number of times And a representative value calculating means.

  According to the present invention, encoding can be performed efficiently without degrading image quality.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device including an image processing device according to an embodiment of the present invention. The liquid crystal display device of FIG. 1 includes an RGB data transmission circuit 1, an LCD (Liquid Crystal Display) source driver 2, and an LCD panel 3. The LCD source driver 2 includes an RGB data receiving circuit 4, an ABD-BTC encoding circuit 5, a memory 6, an ABD-BTC decoding circuit 7, and an LCD driving circuit 8. An image processing apparatus according to an embodiment of the present invention includes at least an ABD-BTC encoding circuit 5 and a memory 6.

  The RGB data transmission circuit 1 is incorporated in a host computer (not shown), for example, and transmits RGB data. The RGB data is received by the RGB data receiving circuit 4. As will be described later, the ABD-BTC encoding circuit 5 encodes RGB data in units of pixel blocks each including 2 × 2 pixels. The encoded data that has been encoded is stored in the memory 6. The ABD-BTC decoding circuit 7 decodes the encoded data stored in the memory 6 into the original RGB data. The LCD drive circuit 8 converts the RGB data decoded by the ABD-BTC decoding circuit 7 into a gradation voltage and supplies it to each signal line of the LCD panel 3.

  FIG. 2 is a flowchart showing an outline of the processing procedure of the ABD-BTC encoding circuit 5. First, RGB data is input (step S1) and divided into 2 × 2 pixel blocks (step S2). Next, RGB data is encoded for each pixel block (step S3). Next, the encoded data obtained by encoding is stored in the memory 6 in units of pixel blocks (step S4).

  FIG. 3 is a flowchart showing an example of detailed processing in step S3 of FIG. First, an average value of pixel blocks is calculated (step S11). Here, an average value of RGB data of 2 × 2 = 4 pixels is calculated for each pixel block. An average value is calculated for each color of RGB data.

  Next, for each pixel block, the upper representative value larger than the average value and the lower representative value below the average value are calculated, and each of the four pixels constituting the pixel block is replaced with the upper representative value or the lower representative value. Data is generated (step S12).

  Next, the bit accuracy of the upper representative value and the lower representative value is determined based on the result of detecting the activity amount of the pixel block (step S13).

  FIG. 4 is a flowchart showing an example of detailed processing in step S11 of FIG. First, a variable SUM for calculating a cumulative pixel value is initialized to 0 (step S21). Next, it is determined whether or not the pixel values of all the pixels in the pixel block are cumulatively added for each color (step S22). If step S22 is NO, the pixel value that has not been cumulatively added is cumulatively added to the value of the variable SUM (step S23), and the process returns to step S22. If step S22 is YES, it is determined that all the pixel values in the pixel block are cumulatively added, and the variable SUM is divided by 4 to calculate an average value (step S24). In FIG. 4, the average value SUM is calculated for each color of RGB.

  FIG. 5 is a flowchart showing an example of detailed processing in step S12 of FIG. First, a variable SUMU that calculates a cumulative addition value of pixel values that are greater than the average value, a variable SUML that calculates a cumulative addition value of pixel values that are less than or equal to the average value, and a variable CNTU that calculates the number of pixel values that are greater than the average value The variable CNTL for calculating the number of pixel values below the average value is initialized to 0 (step S31).

  Next, it is determined whether or not the cumulative addition value has been calculated for all the pixels in the pixel block (step S32). If step S32 is NO, a pixel value (RGB data) in the pixel block that has not been cumulatively added is acquired, and it is determined whether this pixel value is equal to or less than the average value (step S33). When step S33 is YES, the acquired pixel value is cumulatively added to the variable SUML, and 1 is added to the variable CNTL. For this pixel, the bitmap data is set to 0 (step S34).

  When step S33 is NO, the acquired pixel value is cumulatively added to the variable SUMU, and 1 is added to the variable CNTU. For this pixel, the bitmap data is set to 1 (step S35).

On the other hand, when step S32 is YES, the upper representative value and the lower representative value are calculated by the following equations (1) and (2) (step S36).
Upper representative value = variable SUMU / CNTU (1)
Lower representative value = variable SUML / CNTL (2)

  In FIG. 5, the upper representative value and the lower representative value are calculated for each color of RGB to generate bitmap data.

  FIG. 6 is a flowchart showing an example of detailed processing in step S13 of FIG. First, the difference MAXDIF between the upper representative value and the lower representative value is calculated for each color of RGB (step S41). Next, it is determined whether or not the difference MAXDIF is equal to or less than a threshold value T (step S42). If YES in step S42, the pixel block is determined to be a flat image, and the average value of the upper representative value and the lower representative value is calculated, and the difference between the upper representative value and the lower representative value is calculated. Then, the determination flag bit is set to 0 (step S43). When step S42 is NO, it is determined that the pixel block is a rough image, and processing for rounding the upper representative value and the lower representative value is performed, and the determination flag bit is set to 1.

  As described above, in FIG. 6, the images in the pixel block are classified into two types. By limiting to two types, the hardware size can be reduced. Increasing the number of classifications can suppress image quality deterioration due to encoding, but intentionally limits the number of classifications to two. The reason is that this embodiment is designed to drive a small LCD panel 3 such as a mobile phone, and the pixel block size is as small as 2 × 2 pixels, so that rounding errors due to BTC encoding are small. It is. By making the pixel block 2 × 2 pixels, the average value, the upper representative value, and the lower representative value of the pixel block can be easily calculated.

  When calculating the average value or the representative value, the calculation of dividing by 2 or 4 is only required to shift the bit string by 1 bit or 2 bits, and can be performed without performing actual division processing. Also, the process of dividing by 3 can be obtained by relatively simple calculation as will be described later.

  FIG. 7A is a diagram showing an example of binarization by changing the threshold value of the image in three ways, and the image in the left column in FIG. 7A is the data after binarization, FIG. The images in the right-hand column indicate the original images. Although human vision can identify high gradations of 8 bits or more, it cannot distinguish differences with 8-bit accuracy for each pixel. Is obtained. The smaller the collection of pixels, the less bit accuracy is required. BTC uses this visual characteristic.

  Considering such human visual characteristics, 8-bit precision is required only for a flat region in which extremely close values such as a blue sky are gathered in a wide range, and rough changes such as the ground are severe. It can be seen that 8-bit precision is not necessary in such a region.

  In the left column image of FIG. 7A, the threshold value is compared in units of 2 × 2 pixels, and 2 × 2 pixels determined to be flat are expressed in white, and 2 × 2 pixels determined as rough are expressed in black. ing. The magnitude of the activity is defined as the difference between the maximum value and the minimum value in 4 pixels out of 2 × 2 pixels. This difference exists for each color of RGB.

  Here, when all the RGB colors are flat, it is defined as flat. If even one color of RGB is not flat, it is defined as rough. Such a definition may be changed as appropriate.

  As can be seen from FIG. 7A, the blue sky can be covered even with the threshold T = 6. Therefore, it is possible to specify an area where 8-bit accuracy should be secured with the threshold T = 6. With reference to this value, the threshold value in FIG. 7A is empirically determined.

  Strictly speaking, the threshold value in FIG. 7A is not the maximum and minimum width but the difference between the upper representative value and the lower representative value. However, since it behaves in the same way empirically, the threshold value of the difference between the representative values is set as the threshold value T in the calculation.

  FIG. 7B is a diagram illustrating an example of a pixel value of a rough image, and FIG. 7C is a diagram illustrating an example of a pixel value of a flat image. In the case of a rough image, it can be expressed by two pixel values having a large difference as shown in FIG. In the case of a flat image, each 2 × 2 pixel can be expressed by four pixel values having small differences as shown in FIG.

  FIG. 8 is a diagram for explaining rough image coding. The encoded data in this case includes an upper representative value and a lower representative value and a bitmap representing a pixel block for each color of RGB. A description will be given by taking an R pixel as an example. The lower representative value of 5 bits 01010 is obtained by omitting the lower 3 bits, and the actual data is 01010000 (binary). Numerically, it represents 64 + 16 = 80.

  As will be described later, when decoding encoded data, an offset is added to further adjust rounding by encoding. As an offset, for example, 4 is added and converted to 84 if the pixel value is 80, and to 172 if the pixel value is 168.

  In the example of FIG. 8, the bitmap of a pixel block of 2 × 2 pixels is 1010 for each color of RGB, 1 in the bitmap corresponds to the pixel value 172, and 0 corresponds to the pixel value 168.

  Before encoding, each RGB color is 8 bits, so 2 × 2 pixels require 4 × 8 × 3 = 96 bits. On the other hand, when encoding as shown in FIG. 8 is performed, 5 bits are required for each of the upper representative value and the lower representative value, and 4 bits are required for the bitmap. Therefore, for all the RGB colors, (10 + 4) × 3 = 42 bits can be compressed. Eventually, the number of bits can be compressed to 42/96 = about 44%.

  FIG. 9 is a diagram showing a bit string of encoded data obtained by the encoding described in FIG. A determination flag bit 1 meaning a rough image is added to the first bit of the encoded data. Following the determination flag bit, 10 × 3 bits representing a representative value and 4 × 3 bits representing a bitmap are arranged. The encoded data in FIG. 9 is stored in the memory 6 in FIG.

  FIG. 10 is a diagram for explaining encoding of a flat image. The encoded data in this case includes a median value and a difference value from the median value for each color of RGB. The median value is 8 bits to increase bit accuracy, and the difference value is 2 bits. In the example of FIG. 10, the median is 01010101 (binary) = 85, and the difference value is 10 (binary) = 3. Therefore, the upper representative value = 85 + 3 = 88 and the lower representative value = 85−3 = 82. The bitmap is the same as in FIG.

  For each RGB color, the median value is 8 bits, the difference value is 2 bits, and the bitmap is 4 bits, for a total of (8 + 2 + 4) × 3 = 42 bits.

  FIG. 11 is a diagram showing a bit string of encoded data obtained by the encoding described in FIG. A determination flag bit 0 indicating a flat image is added to the first bit of the encoded data. Following the determination flag bit, the median value and difference value of the R pixel, the median value and difference value of the G pixel, the median value and difference value of the B pixel, and the bitmap are sequentially arranged.

  As can be seen from FIGS. 8 and 10, the total number of bits is the same 42 + 1 = 43 bits for both rough and flat images.

  FIG. 12 is a diagram for explaining offset adjustment of a rough image composed of pixel values 0 and 255. FIG. In a rough image, the upper representative value and the lower representative value are both expressed by 5 bits, and therefore the maximum value in the 2 × 2 pixel block is 11111 and the minimum value is 00000. Actually, since the lower 3 bits 000 are added, the maximum value is 248 and the minimum value is 0. The offset 4 is added to both the maximum value and the minimum value, so that the upper representative value = 248 + 4 = 252 and the lower representative value = 0 + 4 = 4.

  13 and 14 are diagrams for explaining offset adjustment of a flat image composed of pixel values 127, 129, 125, and 131. FIG. The average value of these four pixel values is 128, and the average value of pixel values larger than the average value is 130, which is the upper representative value. Further, the average value of pixel values equal to or less than the average value is 126, which is the lower representative value.

  Thus, both the upper representative value and the lower representative value are deviated by 2 from the overall average value. Considering the rounding calculation, the difference between the upper representative value and the average value does not necessarily match the difference between the lower representative value and the average value, but even if an error occurs, it is a difference of only 1 at most. This error is allowed. Therefore, in practice, the difference is calculated using pixel values above or below the average value.

  In the case of the pixel block of FIG. 13, the median is 10000000 (binary) = 128 and the difference is 10 (binary) = 2, as shown in FIG. The bitmap is 0101. Upper representative value = 128 + 2 = 130, lower representative value = 128−2 = 126.

  Next, a processing procedure for performing the encoding according to the above processing procedure and decoding the encoded data stored in the memory 6 will be described.

  FIG. 15 is a flowchart showing an outline of the processing procedure of the ABD-BTC decoding circuit 7 of FIG. First, encoded data is read from the memory 6 (step S51). Next, the encoded data in the pixel block is decoded for each pixel block (step S52). Next, the pixel value with the pixel block as a unit is converted into the pixel value of the entire image (step S53). Next, the converted pixel value is stored (step S54).

  FIG. 16 is a flowchart showing an example of detailed processing in step S52 of FIG. First, the determination flag bit that is the first bit of the encoded data is extracted (step S61). Based on the value of the determination flag bit, it is possible to determine whether the image is flat or rough.

  Next, a bit string (representative value, difference, bitmap, etc.) arranged after the determination flag is acquired (step S62). More specifically, when the determination flag bit is 1, the upper representative value, the lower representative value, and the bitmap are acquired. When the determination flag bit is 0, a median value, a difference value, and a bitmap are acquired.

  Next, the pixel value before encoding is restored based on the bit string acquired in step S62 (step S63).

  FIG. 17 is a flowchart showing an example of detailed processing in step S53 of FIG. First, based on the determination flag bit, the upper representative value and the lower representative value are calculated, and in the case of a rough image, a process of extending to 8 bits is performed (step S71). At this time, offset addition processing is also performed.

  Next, it is determined whether or not the processing in step S71 has been performed for all the pixels in the pixel block (step S72). If there is a pixel that has not yet been processed, the corresponding bit in the bitmap is 0. Is determined (step S73). If the determination is YES, the lower representative value is selected as the pixel value (step S74), and if the determination is NO, the upper representative value is selected as the pixel value (step S75).

  When the process of step S74 or S75 ends, the process returns to step S72, and when the determination of step S72 is YES, the process ends.

  FIG. 18 is a diagram showing the relationship between the compression ratio and PSNR (Peak Signal Noise Ratio). PSNR shows the statistical result of 100 images. No. 1 shows 2 × 2 pixel encoding using conventional BTC. 2 shows 2 × 2 pixel encoding according to the present embodiment. 3 shows encoding of 4 × 4 pixels using conventional BTC. 4 shows 4 × 4 pixel encoding using MoMA-BTC. Reference numeral 5 denotes encoding by DCM4 (simple decimation).

  No. 1 is not desirable because the compression ratio does not exceed 2 and the compression efficiency is poor. No. 3 and 4 are not desirable because the PSNR value is low and the image quality is poor.

  On the other hand, no. The present embodiment shown in FIG. 2 is desirable because images are classified into rough or flat in advance so that an 8-bit accuracy can be obtained substantially, the PSNR value is maintained high, and the hardware scale can be reduced.

  In the present embodiment, the display control of the QVGA type LCD panel 3 used for a mobile phone or the like is performed in mind, and it is necessary to reduce the capacity of the memory 6 as much as possible and suppress deterioration in image quality as much as possible. Therefore, the above No. 2 is most desirable.

  FIG. 19 is a block diagram showing a modification of the liquid crystal display device. In FIG. 19, the same components as those in FIG. 1 are denoted by the same reference numerals, and different points will be mainly described below. The liquid crystal display device of FIG. 19 includes a controller (application processor) 11 in addition to the LCD source driver 2 a. The controller 11 includes an ABD-BTC encoding circuit 5 and a compressed data transmission circuit 12. The LCD source driver 2 a includes a compressed data receiving circuit 13, a memory 6, an ABD-BTC decoding circuit 7, and an LCD driving circuit 8.

  The compressed data transmission circuit 12 transmits the encoded data encoded by the ABD-BTC encoding circuit 5 to the LCD source driver 2a. The compressed data receiving circuit 13 receives the encoded data and stores it in the memory 6.

  19 does not have the ABD-BTC encoding circuit 5 in the LCD source driver 2a, the internal configuration of the LCD source driver 2a can be simplified, and the LCD source driver 2a can be reduced in size and reduced in power consumption. Can be planned. Further, since the controller 11 and the LCD source driver 2a send and receive the compressed encoded data, the amount of transfer data can be suppressed, and there is no possibility that the number of wires and EMI noise will increase.

  FIG. 20 is a block diagram showing an example of the internal configuration of the ABD-BTC encoding circuit 5 of FIG. 1 or FIG. The ABD-BTC encoding circuit 5 in FIG. 20 includes a 2H line memory 21, a 4-pixel storage register 22, an encoder 23, and a compressed data storage register 24.

  In the present embodiment, since the encoding process is performed in units of 2 × 2 pixel blocks, a 2H line memory 21 that stores pixel data for two lines is required. The 4-pixel storage register 22 extracts pixel data of 2 × 2 pixels constituting the pixel block from the pixel data for two lines stored in the 2H line memory 21.

  As will be described later, the encoder 23 performs encoding processing in units of pixel blocks, and generates determination flag bits, representative values (upper representative value, lower representative value, difference value, and the like), and a bitmap. The compressed data storage register 24 temporarily stores encoded data generated by combining the data generated by the encoder 23. The encoded data stored in the compressed data storage register 24 is stored in the memory 6.

  Instead of providing the 2H line memory 21, it is also possible to use a 1H line memory. When the 1H line memory is provided, the first 1H line is stored in the memory 6, and the encoding process is performed when the pixel value for the next 1H line is acquired and stored. Since it is sufficient to perform encoding processing for one pixel block in two clocks, it is sufficient if the memory capacity is sufficient to store only 1H line + 2 pixels.

  However, when the 1H line memory is provided, it is necessary to shift the data in the memory 6 every time, and EMI noise and power consumption increase somewhat. When it is necessary to reduce EMI and power consumption, it is desirable to provide the 2H line memory 21.

  FIG. 21 is a block diagram showing an example of the internal configuration of the encoder 23 of FIG. The encoder 23 in FIG. 21 includes a first hierarchical calculator (average value calculating means) 31 and a second hierarchical calculator 32. The first hierarchy calculator 31 calculates an average value of all the pixel values in the pixel block. The second hierarchy calculator 32 calculates representative values and bitmaps, and determines the activity of the image in the pixel block.

  The first hierarchy calculator 31 includes a first cumulative adder 33, a second cumulative adder 34, and an average value calculator (¼ divider) 35. The first cumulative adder 33 and the second cumulative adder 34 cumulatively add pixel values of 2 × 2 pixels hierarchically. More specifically, the first cumulative adder 33 has two adders (first and second adders) 36, and each adder 36 adds pixel values for two pixels. The second cumulative adder 34 has an adder (third adder) 37 that adds the outputs of the two adders 36 in the first cumulative adder 33.

  The average value calculation unit 35 calculates a value (average value) obtained by dividing the cumulative addition value of the pixel values for four pixels by 4 by shifting the output bit string of the second cumulative addition unit 34 by 2 bits.

  The second hierarchy calculator 32 includes a first comparison / addition unit 41, a second comparison / addition unit 42, a representative value calculation unit 43, and a bit width setting unit 44. The first comparison / addition unit 41 includes two comparison adders 45. Each comparison adder 45 compares the pixel values of two pixels with the average value, and the cumulative addition value of the pixel values larger than the average value. And the number thereof, the cumulative addition value of the pixel values below the average value, and the number thereof are calculated. The second comparison / addition unit 42 has one comparison / adder 46, and this comparison / adder 46 has a pixel value larger than the average value among the four pixels based on the output of the first comparison / addition unit 41. The cumulative addition value and its number, and the cumulative addition value and the number of pixel values below the average value are calculated.

  The representative value calculation unit 43 calculates the upper representative value based on the cumulative addition value and the number of pixel values larger than the average value, and the lower representative value based on the cumulative addition value and the number of pixel values less than the average value. Calculate

  The first comparison / addition unit 41 and the second comparison / addition unit 42 correspond to cumulative adders, and the representative value calculation unit 43 corresponds to upper and lower representative value calculation means. The first comparison / addition unit 41, the second comparison / addition unit 42, and the representative value calculation unit 43 correspond to the representative value calculation means.

  The bit width setting unit 44 determines the amount of activity of the pixel block based on the difference between the upper representative value and the lower representative value, and determines whether the image is a rough image or a flat image. Based on the determination result, the bit width of the representative value is determined.

  FIG. 22 is a block diagram showing an example of the internal configuration of the first cumulative adder 33 and the second cumulative adder 34 of FIG. Both the first cumulative adder 33 and the second cumulative adder 34 have a two-input arithmetic circuit 47. The first cumulative addition unit 33 directly inputs the pixel value of 2 × 2 pixels in the pixel block, and the second cumulative addition unit 34 adds the pixel values of two pixels out of 2 × 2 pixels. Is input and the sum of the pixel values for four pixels is output.

  The first cumulative adder 33 and the second cumulative adder 34 perform the processing operation shown in the flowchart shown in FIG.

  The bit width in the average value calculation unit 35 of FIG. 21 is increased by 2 bits from the calculation of the first cumulative addition unit 33 and the second cumulative addition unit 34 to 10 bits. When 8 bits are used as the average value, it is necessary to perform rounding. Alternatively, there is an option to perform the following calculation with a 10-bit width or a 9-bit width.

  FIG. 23 is a block diagram showing an example of the internal configuration of each comparison adder 45 in the first comparison adder 41 of FIG. As shown in FIG. 23, each comparison adder 45 has a comparison circuit 48 and an arithmetic circuit 49, and processes two pixels at a time. The comparison circuit 48 compares the pixel value A with the average value MID of the pixel block for each of the two corresponding pixels. Based on the comparison result of the comparison circuit 48, the arithmetic circuit 49 calculates the sum SU1 (or SU2) of pixel values and the number of pixels CU1 (or CU2) in a group (upper group) of pixels having pixel values larger than the average value. Then, the sum SL1 (or SL2) of pixel values and the number of pixels CL1 (or CL2) in a group of pixels having a pixel value equal to or less than the average value (lower group) are calculated. The arithmetic circuit 49 generates a pixel block bitmap BM with the upper group of pixels set to 1 and the lower group of pixels set to 0.

  FIG. 24 is a diagram showing the operation of the first comparison and addition unit 41 shown in FIG. As shown in FIG. 24, when the pixel value A is equal to or less than the average value MID, the pixel value A is cumulatively added to the variable SL1 and 1 is added to the variable CL1, and the corresponding pixel value in the bitmap BM is 0. become. When the pixel value A is larger than the average value MID, the pixel value A is cumulatively added to the variable SU1, and the variable CU1 is incremented by 1, so that the corresponding pixel value in the bitmap BM becomes 1.

  FIG. 25 is a block diagram showing an example of the internal configuration of the second comparison / addition unit 42 of FIG. As shown in FIG. 25, the second comparison / addition unit 42 receives the outputs SL1, CL1, SL2, and CL2 of the first comparison / addition unit 41 and calculates the total sum SUML and the number of pixels CNTL of the lower group. 50 and an arithmetic circuit 51 that receives the outputs SU1, CU1, SU2, and CU2 of the first comparison / addition unit 41 and calculates the sum SUMU of the upper group and the number of pixels CNTU.

  FIG. 26 is a block diagram showing an example of the internal configuration of the representative value calculation unit 43 in FIG. As shown in FIG. 26, the representative value calculation unit 43 includes a shift circuit 52 and an arithmetic circuit 53 for calculating the lower representative value, and a shift circuit 54 and an arithmetic circuit 55 for calculating the upper representative value. The shift circuits 52 and 54 extend the sum of pixel values SUML (or SUMU) by 2 bits to a 10-bit width. The arithmetic circuits 53 and 55 perform division processing according to the value of the number of pixels CNTL (or CNTU).

  FIG. 27 is a diagram for explaining the operation of the arithmetic circuits 53 and 55 of FIG. Hereinafter, the sum SUML (or SUMU) is generically called SUM, and the number of pixels CNTL (or CNTU) is generically called CNT.

  When the number of pixels CNT is 0 or 1, the bit-extended sum SUM is output as it is. The reason why the sum SUM is output as it is when the number of pixels CNT is 0 is that it cannot be divided by 0, but an indefinite value is not desirable in terms of hardware configuration.

  When the number of pixels CNT is 2, the division process of 2 is performed by shifting the sum SUM by 1 bit.

  When the number of pixels CNT is 3, it indicates that the sum SUM is divided by 3, which cannot be performed by a simple shift operation. Therefore, the division process of 3 is performed by a method described later.

  When the number of pixels CNT is 4, the division process of 4 is performed by shifting the sum SUM by 2 bits.

  FIG. 28 is a block diagram showing an example of a specific configuration of the shift circuit 52 or 54 and the arithmetic circuit 53 or 55 shown in FIG. As shown, the shift circuit 52 or 54 and the arithmetic circuit 53 or 55 include a 1-bit shift circuit 61, a 1/3 multiplication circuit 62, a 2-bit shift circuit 63, a switch circuit 64, and a switch control circuit 65. Have

  The sum SUM is input to the 1-bit shift circuit 61, the 1/3 multiplication circuit 62, and the 2-bit shift circuit 63. The switch circuit 64 selects one of the sum SUM, the output of the 1-bit shift circuit 61, the output of the 1/3 multiplier circuit 62, and the output of the 2-bit shift circuit 63 under the control of the switch control circuit 65. .

  FIG. 29 is a block diagram showing an example of the internal configuration of the 1/3 multiplication circuit 62. As shown in FIG. As illustrated, the 1/3 multiplication circuit 62 includes a 6-bit shift circuit 71, a 4-bit shift circuit 72, a 2-bit shift circuit 73, a 0-bit shift circuit 74, and adders 75 to 77.

  When 256 is divided by 3, the result is about 85.3. Therefore, when the division result is regarded as 85 and expressed in binary, it becomes 01010101. Therefore, in FIG. 29, a process of multiplying the sum SUM by 01010101 is performed, and as a result, a division of about 1/3 is performed.

  In 01010101, the first bit, the third bit, the fifth bit, and the seventh bit are each 1, and the original sum SUM is shifted by 0 bits, shifted by 2 bits, and shifted by 4 bits. And the value shifted by 6 bits are added to obtain the multiplication result of 01010101 and the sum SUM. These shift processing and addition processing are performed in FIG. As a result, the adder 77 in the final stage of FIG. 29 obtains a value obtained by dividing the sum SUM by approximately 3.

  The block configuration in FIG. 29 can be simplified. FIG. 30 is a simplified block diagram of FIG. 30 includes a 2-bit shift circuit 73, a 0-bit shift circuit 74, an adder, a 4-bit shift circuit 72, and an adder. In FIG. 30, the same result as in FIG. 29 is obtained.

  In order to further improve the accuracy of the 1/3 division result, a value obtained by dividing 256 by 3 may be taken into consideration. When considering up to two digits after the decimal point, 256/3 = about 85.25. When 85.25 is expressed in binary, it becomes 0101010101. By multiplying the total sum SUM by this 0101010101, a value approximate to a value obtained by dividing the total sum SUM by 3 is obtained.

  FIG. 31 is a block diagram of a 1/3 multiplication circuit 62b that performs a process of multiplying the sum SUM by 85.25. 31 includes an 8-bit shift circuit 70, a 6-bit shift circuit 71, a 4-bit shift circuit 72, a 2-bit shift circuit 73, a 0-bit shift circuit 74, and adders 75 to 78. FIG. 32 is a block diagram in which the circuit of FIG. 31 is optimized. 32 includes a 4-bit shift circuit 72, a 2-bit shift circuit 73, a 0-bit shift circuit 74, an adder, a 4-bit shift circuit 72, and an adder. The 1/3 multiplication circuit 62 in FIG. 32 omits the 8-bit shift circuit 70 and the 6-bit shift circuit 71 in FIG. 31 to reduce the number of adders.

  Thus, by dividing the value obtained by dividing 256 by 3 with higher accuracy, it is possible to perform the division by 1/3 more accurately. When the value obtained by dividing 256 by 3 is taken into consideration up to 4 digits after the decimal point, 1/3 division can be performed with higher accuracy than in the case of taking into consideration 2 digits after the decimal point. 256/3 = about 85.3125.

  FIG. 33 is a block diagram of the 1/3 multiplication circuit 62 when the value obtained by dividing 256 by 3 is 85.3125. 33 includes a 10-bit shift circuit 74, an 8-bit shift circuit 70, a 6-bit shift circuit 71, a 4-bit shift circuit 72, a 2-bit shift circuit 73, and a 0-bit shift circuit. 74 and an adder. FIG. 34 is a block diagram of a 1/3 multiplication circuit 62e optimized from FIG. 34 includes a 2-bit shift circuit 73, a 0-bit shift circuit 74, an adder 75, an 8-bit shift circuit 70, a 4-bit shift circuit 72, and adders 76 and 77. Have

  FIG. 35 is a block diagram showing an example of the internal configuration of the bit width setting unit 44 of FIG. The bit width setting unit 44 in FIG. 35 compares the difference between the upper representative value and the lower representative value with respect to the threshold value T, and the image in the pixel block based on the comparison result of the comparison circuit 81. And an arithmetic circuit 82 for determining whether or not is rough or flat.

  FIG. 36 shows the operation of the arithmetic circuit 47 of FIG. As shown in FIG. 36, if the difference between the upper representative value REPU and the lower representative value REPL is equal to or smaller than the threshold value T, it is determined that the image is flat, and the median value and the difference value from the median value are represented by REP1, REP2. And the determination flag bit is set to 0. If the difference between the upper representative value REPU and the lower representative value REPL is less than the threshold value, it is determined as a rough image, and a new upper representative value REP1 obtained by rounding the upper representative value REPU and a new one obtained by rounding the lower representative value REPL. The lower representative value REP2 is output and the determination flag bit is set to 1.

  FIG. 37 is a diagram in which the hardware size of each circuit in the encoder 23 of FIG. 21 is estimated. More specifically, the number of adders included in each circuit in the encoder 23 is shown.

  The first hierarchical calculator 31 has a first cumulative adder 33 and a second cumulative adder 34, and has a total of three adders. The second hierarchical calculator 32 includes a first comparison / addition unit 41 and a second comparison / addition unit 42, and these units have a total of four adders. The representative value calculation unit 43 has 4 to 6 adders, and the bit width setting unit 44 has 3 adders. After all, the encoder 23 as a whole has 14 to 16 adders.

  The 8 × 8 multiplier is composed of eight 8-bit string adders. As can be seen from FIG. 37, when the multiplier is estimated in units, the encoder 23 as a whole has the same hardware size as that of two multipliers. This is a sufficiently small hardware size.

  FIG. 38 is a block diagram showing a simplified example of the encoder 23 of FIG. In FIG. 38, since the configurations of the first hierarchical calculator 31 and the second hierarchical calculator 32 in FIG. 21 are similar, the hardware is shared. That is, the same processing as that of the first hierarchical calculator 31 and the second hierarchical calculator 32 is performed by one circuit by performing calculation while shifting the time using common hardware.

  The encoder 23a of FIG. 38 includes a first addition unit 83, a second addition unit 84, a representative value calculation unit 43, and a bit width setting unit 44. The first adder 83 has two adders 85, and the second adder 84 has one adder 86.

  The first adder 83 performs the same calculation as the first cumulative adder 33 in FIG. 21 at the first time, and performs the same calculation as the first comparison adder 41 in FIG. 21 at the second time. Do. The second adder 84 performs the same calculation as the second cumulative adder 34 in FIG. 21 at the first time, and performs the same calculation as the second comparison adder 42 in FIG. 21 at the second time. Do.

  The representative value calculator 43 in FIG. 38 performs the same calculation as the average value calculator 35 in FIG. 21 at the first time, and performs the same calculation as the representative value calculator 43 in FIG. 21 at the second time.

  As shown in FIG. 38, the hardware scale can be reduced by sharing some circuits and switching the calculation contents according to time. More specifically, the number of adders can be reduced.

  The hardware may be optimized by a method other than that shown in FIG. The average value calculator 35 in FIG. 21 calculates the average value by shifting by 2 bits. This means that the connection destination of the wiring is changed by shifting, and does not include hardware for the shift processing. For this reason, the processing time of the average value calculation unit 35 can be ignored from the viewpoint of controlling the whole at two times in consideration of the delay. Therefore, the processing from the first cumulative addition unit 33 to the first comparison addition unit 41 in FIG. 21 is performed at the first time, and the second comparison addition unit 42 in FIG. It is also conceivable to perform processing up to the width setting unit 44. Alternatively, the processing cycles may be switched in the middle of the processing of the first comparison / addition unit 41 and the second comparison / addition unit 42 in order to equalize the processing time.

  Thus, it is desirable to adjust where the processing cycle interval is set in consideration of the processing delay time of each circuit.

  FIG. 39 is a block diagram showing an example of the internal configuration of the ABD-BTC decoding circuit 7 of FIG. The decoding circuit 7 of FIG. 39 includes a compressed data storage register 91, a flag extraction unit 92, a representative value extraction unit 93, a bitmap extraction unit 94, a 2 × 2 pixel restoration calculation unit 95, and 2 × 2 pixels. A storage register 96 and a line memory 97 are provided.

  The compressed data storage register 91 temporarily stores the encoded data stored in the memory 6. The flag extraction unit 92 extracts a determination flag bit that is the first bit of the encoded data. A 1 indicates a rough image, and a 0 indicates a flat image.

  The representative value extraction unit 93 extracts the median value and the difference value or extracts the upper representative value and the lower representative value according to the value of the determination flag bit. The bitmap extraction unit 94 extracts a bitmap according to the value of the determination flag bit.

  The 2 × 2 pixel restoration calculation unit 95 restores the pixel value based on the outputs of the flag extraction unit 92, the representative value extraction unit 93, and the bitmap extraction unit 94. The restored pixel value is temporarily stored in the 2 × 2 pixel storage register 96 and then stored in the line memory 97.

  The line memory 97 has a memory capacity for 2H lines. The reason why such a memory capacity is required is that the decoding process is performed in units of 2 × 2 pixel blocks. However, since the 1H line memory 8 already exists, it is sufficient to provide the 1H memory as the line memory 97 even if the 2H memory is not provided.

  The flag extraction unit 92, the representative value extraction unit 93, and the bitmap extraction unit 94 correspond to an encoded data extraction unit.

  The decoding circuit 7 in FIG. 39 performs processing according to the flowchart in FIG. 15 described above. Step S51 of FIG. 15 is processing of the compressed data storage register 91, step S52 is processing of the flag extraction unit 92, representative value extraction unit 93, bitmap extraction unit 94, and 2 × 2 pixel restoration calculation unit 95, and step S53 is 2 ×. The process of the two-pixel storage register 96, step S54, corresponds to the process of the line memory 97.

  FIG. 40 is a diagram for explaining the processing contents of the 2 × 2 pixel restoration calculation unit 95 in FIG. 39. FIG. 40A is a block diagram illustrating an example of the internal configuration of the 2 × 2 pixel restoration calculation unit 95. The 2 × 2 pixel restoration calculation unit 95 illustrated in FIG. 40A includes four selection circuits 98. Representative values REP1 and REP2, determination flag bit FLAG, and values BM11, BM12, BM21, and BM22 constituting a bitmap are input to the four selection circuits 98. For example, if FLAG = 0, it is determined as a flat image, and each value of the input bitmap is converted using the representative values REP1, REP2, and C11, C12, C21, C22 are output. The 2 × 2 pixel restoration calculation unit 95 performs processing according to the flowchart of FIG.

  When performing image restoration, it is also possible to provide a function for rotating or inverting an image. In this case, it is possible to replace the restored pixel values C11, C12, C21, and C22 of the four pixels constituting the pixel block. However, since each pixel value is, for example, 8 bits wide, the replacement becomes large.

  Therefore, the positions of the values BM11, BM12, BM21, and BM22 constituting the bitmap may be exchanged. As a result, the hardware scale can be reduced because only 1 bit is replaced instead of 8 bits. The hardware (rotation / inversion circuit 99) for performing the replacement process is as shown in FIG.

  In FIG. 40B, input data B11, B12, B21, and B22 are bitmaps before rotation and inversion, and output data BM11, BM12, BM21, and BM22 are bitmaps after rotation and inversion.

  Instead of performing rotation / inversion at the decoding stage, rotation / inversion processing may be performed at the encoding stage. In this case, the encoded data after rotation / inversion is stored in the memory 6.

  In actual image processing, it is desirable to perform rotation / inversion processing during encoding. The reason is that the hardware of the decoder can be further reduced, and from the viewpoint of the utilization efficiency of the memory 6, when the image is stored with the vertical and horizontal directions reversed, the vertical and horizontal directions of the image and the vertical and horizontal directions of the memory 6 are matched. It is because it can do.

  If the vertical and horizontal directions of the image and the vertical and horizontal directions of the memory 6 do not coincide with each other, there is a possibility that an empty area that is not effectively used increases in the memory 6 while either the vertical or horizontal memory capacity is insufficient.

  FIG. 41 is a diagram for explaining image restoration of a rough image. The representative values in this case are an upper representative value and a lower representative value having a precision of 5 bits. When the bitmap is 0, the lower representative value is selected, and when the bitmap is 1, the upper representative value is selected. At the time of image restoration, the representative value is expanded from 5 bits to 8 bits. Then, each bit of the bitmap is replaced with a representative value (upper representative value or lower representative value) consisting of 8 bits to obtain C11, C12, C21, and C22.

  FIG. 42 is a diagram for explaining image restoration of a flat image. The representative value in this case is a median value of accuracy of 8 bits and a difference value of 2 bits. Lower representative value = median value−difference value, upper representative value = median value + difference value. Each bit of the bitmap is replaced with the upper representative value and the lower representative value to obtain C11, C12, C21, and C22.

  FIG. 43 is a block diagram showing an example of the internal configuration of the selection circuit 98 of FIG. The selection circuit 98 in FIG. 43 includes a difference restoration circuit 101, a bit expansion circuit 102, a first switch circuit 103, and a second switch circuit 104.

  The value of the data storage register 91 is input to the difference restoration circuit 101 and the bit extension circuit 102. The first bit of the data storage register 91 represents a determination flag bit, where 1 indicates a rough image and 0 indicates a flat image. For both a rough image and a flat image, 10 bits from the second bit to the eleventh bit of the data storage register are used to extract the representative value.

  In the case of a rough image, the difference restoration circuit 101 extracts the upper representative value and the lower representative value by the 10 bits. In the case of a rough image, the bit extension circuit 102 performs bit extension from 5 bit precision to 8 bit precision. The bit extension circuit 102 adds an offset for rounding adjustment.

  The first switch circuit 103 selects two representative values restored or expanded based on the determination flag bit. The second switch circuit 104 selects the upper representative value or the lower representative value based on each bit of the bitmap.

  An overflow / underflow processing circuit by addition / subtraction may be added to the difference restoration circuit 101. For example, as described above, an approximation error may occur in a 1/3 multiplier that obtains a representative value. Such accumulation of errors may require the overflow and underflow processing circuits described above. On the other hand, a method can be considered in which the bit width of the calculation is sufficiently increased to make it difficult for errors to occur. As described above, it is desirable to add the processing circuit as necessary depending on the actual circuit to be realized and the degree of deterioration of the image quality.

  Although the difference restoration circuit 101 and the bit extension circuit 102 each include an adder, it is conceivable to reduce the number of adders. The rounding adjustment performed by the bit extension circuit 102 is an operation for minimizing an error generated by numerical processing such as rounding off or truncation generated by rounding processing in the ABD-BTC encoding circuit 5. Such processing for minimizing errors can also be performed by the ABD-BTC encoding circuit 5. That is, the rounding process is executed after the offset adjustment is performed in consideration of an error caused by the rounding process by the encoding circuit 5 in advance.

  As a result, the adder in the bit extension circuit 102 can be omitted, and only the function of filling the LSB with 0 remains. Note that this is a case of a rough image related to rounding. In the case of a flat image, a representative value of 8-bit accuracy restored by the difference restoration circuit 101 is used. The 8-bit representative value passes through the bit extension circuit 102 regardless of rounding. Further, if the image quality is slightly deteriorated, there may be a method of deleting the rounding offset adjustment in the encoding circuit 5.

  As an alternative to reduce the above-described adder, it is conceivable to share the adder in the difference restoration circuit 101 and the adder in the bit extension circuit 102. In this case, even when the median-difference subtraction process is performed in the difference restoration circuit 101, since it can be performed by an adder using a complement, one adder is required for each of the two representative values, and bit extension is performed. It matches the two adders in.

  As a further alternative, the rounding adjustment offset is fixed at a specific value (eg, +4, +3, 0, etc.). This only needs to be added to binary 10, 011,000 on the lower side of the bit string, and can be realized without increasing the hardware scale. Although it is a very simple configuration, fine adjustment is not possible.

  As described above, in this embodiment, whether a rough image or a flat image is determined in units of a pixel block composed of 2 × 2 pixels, and if it is a rough image, encoded data with 5-bit accuracy is generated. If the image is flat, encoded data with 8-bit accuracy is generated. In both the case of a rough image and the case of a flat image, encoded data having the same bit width is generated. Therefore, the bit width of the encoded data does not vary depending on the type of image. Since the images are classified into only two types, rough and flat, the number of image divisions can be minimized, and the hardware scale can be reduced.

  In this embodiment, since the pixel block has a small size of 2 × 2 pixels, the average value in the pixel block can be calculated with a simple circuit. That is, a divider that tends to increase in hardware scale can be configured with only a 1/3 multiplier. This 1/3 multiplier can also reduce the hardware scale by performing approximate calculation.

  Furthermore, when calculating the average value of pixel blocks, it is possible to share hardware by performing hierarchical calculation. Also, image rotation and inversion processing can be performed without providing dedicated hardware.

  Further, since the pixel block is expressed by two representative values at the time of encoding, the number of representative values can be reduced and the bit width of the encoded data can be suppressed. In addition, since the bit accuracy of the encoded data is switched between a rough image and a flat image, the human eye does not feel deterioration in image quality.

  Thus, since the encoded data obtained by the encoding process of this embodiment has a small bit width, the memory capacity of the memory 6 for storing the encoded data can be reduced, and the hardware scale of the image processing apparatus can be reduced. Cost reduction can be achieved.

  As described above, according to the present embodiment, the compression effect of the BTC algorithm can be utilized when performing display control of the LCD panel 3 of a small size (for example, QVGA) used for a mobile phone or the like. In other words, the BTC algorithm that is effective with the conventional VGA memory 6 size is relatively large compared to the memory 6 reduction at the time of QVGA because its encoder and decoder are relatively large. Although the technology could not be used, the BTC technology can also be applied to the display control of the QVGA size in this embodiment.

1 is a block diagram showing a schematic configuration of a liquid crystal display device including an image processing device according to an embodiment of the present invention. 5 is a flowchart showing an outline of a processing procedure of an ABD-BTC encoding circuit 5; The flowchart which shows an example of the detailed process of step S3 of FIG. The flowchart which shows an example of the detailed process of FIG.3 S11. The flowchart which shows an example of the detailed process of FIG.3 S12. The flowchart which shows an example of the detailed process of FIG.3 S13. (A) is a diagram showing an example of binarization by changing the threshold value of an image in three ways, (b) is a diagram showing an example of a pixel value of a rough image, and (c) is a pixel value of a flat image. The figure which shows an example. The figure explaining encoding of a rough image. FIG. 9 is a diagram showing a bit string of encoded data obtained by the encoding described in FIG. 8. The figure explaining encoding of a flat image. FIG. 11 is a diagram showing a bit string of encoded data obtained by the encoding described in FIG. 10. The figure explaining the offset adjustment of the rough image comprised by pixel value 0 and 255. FIG. The figure explaining the offset adjustment of a flat image. The figure explaining the offset adjustment of a flat image. The flowchart which shows the outline of the process sequence of the ABD-BTC decoding circuit 7 of FIG. The flowchart which shows an example of the detailed process of FIG.15 S52. The flowchart which shows an example of the detailed process of step S53 of FIG. The figure which shows the relationship between a compression rate and PSNR (Peak Signal Noise Ratio). The block diagram which shows the modification of a liquid crystal display device. FIG. 20 is a block diagram showing an example of an internal configuration of the ABD-BTC encoding circuit 5 of FIG. 1 or FIG. FIG. 21 is a block diagram illustrating an example of an internal configuration of an encoder 23 in FIG. 20. FIG. 22 is a block diagram showing an example of the internal configuration of a first cumulative adder 33 and a second cumulative adder 34 in FIG. 21. FIG. 22 is a block diagram showing an example of the internal configuration of each comparison adder 45 in the first comparison adder 41 of FIG. 21. The figure which represented the operation | movement of the 1st comparison addition part 41 shown in FIG. 23 with a truth value. FIG. 22 is a block diagram illustrating an example of an internal configuration of a second comparison / addition unit in FIG. 21. FIG. 22 is a block diagram showing an example of an internal configuration of a representative value calculation unit 43 in FIG. 21. FIG. 27 is a diagram for explaining the operation of arithmetic circuits 53 and 55 in FIG. 26. FIG. 27 is a block diagram illustrating an example of a specific configuration of a shift circuit and an arithmetic circuit illustrated in FIG. 26. FIG. 3 is a block diagram showing an example of an internal configuration of a 1/3 multiplication circuit 62. The block diagram which simplified FIG. The block diagram of the 1/3 multiplication circuit 62b which performs the process which multiplies 85.25 to total SUM. The block diagram which optimized the circuit of FIG. The block diagram of the 1/3 multiplication circuit 62 when the value which divided 256 by 3 is set to 85.3125. The block diagram of the 1/3 multiplication circuit 62e which optimized FIG. FIG. 22 is a block diagram showing an example of an internal configuration of a bit width setting unit 44 in FIG. 21. FIG. 36 is a diagram showing an operation of the arithmetic circuit 47 in FIG. 35. The figure which estimated the hardware size of each circuit in the encoder 23 of FIG. The block diagram which shows the example which simplified the encoder 23 of FIG. The block diagram which shows an example of the internal structure of the ABD-BTC decoding circuit 7 of FIG. The figure explaining the processing content of the 2 * 2 pixel restoration calculation part 95 of FIG. The figure explaining the image restoration of a rough image. The figure explaining the image restoration of a flat image. FIG. 41 is a block diagram showing an example of the internal configuration of the selection circuit 98 in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 RGB data transmission circuit 2 LCD source driver 3 LCD panel 4 RGB data reception circuit 5 ABD-BTC encoding circuit 6 Memory 7 ABD-BTC decoding circuit 8 LCD drive circuit 11 Controller 12 Compressed data transmission circuit 13 Compressed data reception circuit 21 2H line memory 22 4 pixel storage register 23 encoder 24 compressed data storage register 31 first hierarchical calculator 32 second hierarchical calculator 33 first cumulative adder 34 second cumulative adder 35 average value calculator 41 first 1 comparison addition unit 42 second comparison addition unit 43 representative value calculation unit 44 bit width setting unit

Claims (5)

An average value calculating means for calculating an average value of pixel values in the pixel block for each of adjacent pixel blocks composed of 2 × 2 pixels;
Representative value calculating means for calculating an upper representative value larger than the average value calculated by the average value calculating means and a lower representative value smaller than the average value for each of the pixel blocks;
Image change determination means for determining whether a difference between the upper representative value and the lower representative value is greater than a predetermined threshold for each pixel block;
If it is determined by the image change determination means that it is larger than the threshold value, it is determined that the image is rough and first encoded data is generated, and if the image change determination means determines that the threshold value is equal to or less than the threshold value, Encoding processing means for determining that the image is flat and generating second encoded data;
Storage means for storing the first encoded data and the second encoded data,
The average value calculating means includes
First and second adders for calculating in parallel the sum of pixel values of every two pixels in the pixel block;
A third adder that calculates the sum of the addition result of the first adder and the addition result of the second adder;
A quarter divider that shifts the bit string representing the addition result of the third adder by 2 bits and calculates the average value;
The representative value calculating means includes:
A comparison is made between the average value and each pixel value in the pixel block, and a first cumulative addition value obtained by cumulatively adding pixel values larger than the average value, and a pixel value less than the average value are cumulatively added. A cumulative adder that calculates a cumulative added value of 2;
Upper and lower calculating the upper representative value based on the first cumulative added value and the cumulative number of times and calculating the lower representative value based on the second cumulative added value and the cumulative number of times An image processing apparatus comprising: representative value calculation means; The average value calculating means calculates an average value for each of RGB data for four pixels in the pixel block,
The representative value calculation means calculates the upper representative value and the lower representative value for each of RGB data for four pixels in the pixel block,
The image change determination means determines whether or not a difference between the upper representative value and the lower representative value is greater than a predetermined threshold for each of RGB data for four pixels in the pixel block,
The image processing apparatus according to claim 1, wherein the encoding processing unit generates the first and second encoded data for each of RGB data for four pixels in the pixel block. The first encoded data includes a bit indicating a determination result of the image change determination unit, a bit string indicating a center value in the pixel block, a bit string indicating a difference from the center value, and a bit string in the pixel block. Bitmap data,
The second encoded data includes a bit indicating a determination result of the image change determination unit, a bit string indicating the upper representative value, a bit string indicating the lower representative value, and bitmap data in the pixel block. The image processing apparatus according to claim 1, further comprising:   When the number of cumulative additions is 2 or 4, the upper and lower representative value calculating means shifts the bit string representing the first cumulative addition value or the second cumulative addition value to shift the upper representative value or the When the lower representative value is calculated and the cumulative number of additions is 3, the upper representative value or the approximate value is approximately calculated by multiplying the first cumulative addition value or the second cumulative addition value by a predetermined bit string. The image processing apparatus according to claim 1, wherein a lower representative value is calculated. Decoding means for decoding the first encoded data and the second encoded data stored in the storage device;
The decryption processing means includes:
A bit indicating a determination result of the image change determination means, a bit string corresponding to a representative value of the pixel block, and a bit in the pixel block, which are included in the first encoded data and the second encoded data An encoded data extraction unit for extracting map data;
5. A pixel restoration calculation unit that restores a pixel value before encoding for each of the pixel blocks based on data extracted by the encoded data extraction unit. An image processing apparatus according to 1.