KR101028161B1 - Data compression-decompression apparatus and method for flat display panel memory and apparatus of histogram data precessing, lut data compression and frame rate enhancement using the same - Google Patents

Abstract

PURPOSE: A data compressing-restoring method is provided to increase compression rate by adaptively selecting one among various algorithm according to image data. CONSTITUTION: A data compressing-restoring method is comprised as follows: a step of determining whether upper bits is same or not by comparing upper bit of n number and n+1 number pixel data with upper bits of previous pixel data which is before n number pixel data, a step of PPC, TPPC&PFC encoding which outputs pixel data, a step of RLE encoding which outputs compressed pixel data by removing the pixel data which is continued by run length encoding(RLE), a step of storing one between the PPC,TPPC&PFC encoding output and the RLE encoding output according to selected compressed algorithm based on a slop between compression rate and the pixel data, a step of restoring the compressed data by selecting restoring algorithm according to a slope between the compression rate and the pixel data.

Description

Data Compression-Decompression Apparatus and Method for Flat Display Panel Memory and Apparatus of Histogram data precessing, LUT data compression and Frame rate enhancement using the same}

The present invention relates to a data compression-restore method for a flat panel display memory, a histogram data processing, a LUT data compression method, and a frame rate improving method using the same.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting diode device (OLED). ). Liquid crystal display devices can meet the trend of light and short and short of electronic products and mass production is improving, and are rapidly replacing cathode ray tubes in many applications. In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

In recent years, SOP (System on Panel) which integrates a part or all of the circuits required for driving in the display panel of a flat panel display device is progressing. Samsung and Japanese LCD makers such as CG Silicon, NEC and Sharp are concentrating on SOP development. This SOP can be applied to any equipment that uses a display device, so it is useful in an application field and also has a signal delay due to reduced power consumption and on-chip (or in-chip) interconnection. Although it has the advantage of reducing, yet has a disadvantage of low yield (Yield), it is difficult to implement a large number of memories required for recent image quality improvement.

Recently, it has been applied to the operation of the frame rate control to improve the general image quality, the LCD overdrive to improve the response characteristics of the liquid crystal in the LCD, and the motion blur phenomenon. It requires a lot of memory. In addition, more memory is required to improve the resolution and color depth required. This increase in memory leads to an increase in cost, which requires image memory data compression techniques and an algorithm suitable for SOP characteristics.

Conventional memory data compression techniques can be roughly divided into lossy compression algorithm and lossless compression algorithm. Lossy compression algorithms include a compression scheme using block truncation coding (BTC) and a discrete cosine transform (DCT), and a truncation scheme and a YcbCr422 scheme for discarding and storing a part of pixel data. The lossy compression algorithm can obtain a higher compression rate than other algorithms, but the data loss ratio is also significant, which is not suitable for the emotional quality of display devices, which has recently increased in importance due to the loss of image quality. Compression algorithm using DCT has relatively low quality deterioration but high hardware complexity and slow processing speed. Lossless algorithms have very low compression rates or very high complexity. Typical lossless compression algorithms, such as FAX and RLE (Run Length Encoding), have very low compression rates for general images except for special cases, and algorithms such as JPEG-LS Lossless can achieve high compression ratios, but the complexity of the compression algorithms is very high. It is not suitable as a compression algorithm of image memory.

Accordingly, an object of the present invention is to devise a data compression-restore method which is devised to solve the problems of the prior art, which has no image quality damage due to compression, or is incomprehensible to humans, increases the compression ratio and minimizes the complexity of hardware. To provide.

Another object of the present invention is to provide a histogram data processing method which enables efficient image processing operation by reducing the height section of the histogram for each grayscale section based on the compressed image data.

Another object of the present invention is to divide the pixel data into upper and lower bit groups when storing a look-up table (LUT) based on the compressed image data, and to correct it by using a scale factor and an error look-up table. It is to provide a LUT data compression method that can reduce the number of lookup tables required.

It is still another object of the present invention to provide a frame rate improving method capable of reducing the amount of computation during a frame rate enhancement operation that can remove motion blur and the like based on compressed image data.

In order to achieve the above object, the data compression-restore method for the flat panel display memory of the present invention generates a flag indicating the identity of the upper bits in the pixel data except for the same upper bits and outputs instead of the upper bits. A compression algorithm, a TPPC compression algorithm that further removes some of the remaining lower bits except for the same upper bits from the pixel data, and generates the flag, and partially shares a compression scheme with the PPC and the TPPC compression algorithms; A PPC that selectively removes them or compresses the same pixel data within a continuous constant pixel data length by selecting one of the PFC compression algorithms according to the compression rate of the previous frame and the average value, and outputs the compressed pixel data; TPPC & PFC encoding step; An RLE encoding step of outputting compressed pixel data by removing the pixel data consecutive in run length encoding (RLE); Selecting one of the PPC, TPPC & PFC encoding output and the RLE encoding output according to a compression algorithm selected based on the compression rate and the average value and storing the selected one in a memory; And reconstructing the compressed data by selecting a reconstruction algorithm according to a slope between the compression ratio and the pixel data.

The PFC algorithm is a partial type that removes the upper bits and generates the flag based on the identity of the upper bits, when the contiguous pixel data is the same as the full bit of any one of the pixel data. The pixel data are compressed using a full bit type for generating a code indicating a number of times and an uncompressed type for bypassing each of the pixel data to full bit when the consecutive pixel data are different.

The compressed data stored in the memory includes a lower bit group in which lower bits of pixel data having the same upper bits are collected.

The histogram data processing method of the present invention, in addition to the data compression-restore method for the flat panel display memory, includes a histogram based on gradation intervals consisting of a plurality of gradation values using the code, the flag, and the higher bits. Generating and storing in the second memory; And limiting the maximum frequency of the histogram read out from the second memory to a predetermined clipping level lower than the maximum image resolution, and reducing the frequency level by adjusting the step size of the histogram.

The LUT data compression method of the present invention divides the upper bits X _upper and the lower bits X _lower of the pixel data X stored in the memory in addition to the data compression-restore method for the flat panel display memory. The upper bits X _upper and the lower bits X _lower are respectively partitioned by a lookup table characteristic function f _pbl (X _partitioned ) using a lookup table, and the result of the operations of the upper bits f _pbl (X _upper ) and Outputting an operation result f _pbl (X _lower ) of the lower bits; The gray scale interval is determined according to the upper bits X _upper using a scale factor lookup table, and the following step_size (f _pbl (X _upper )) is referred to as the step size of f _pbl (X _upper ) and DR (g (x) ) Selects a scale factor k that satisfies the following local scale factor SF _local when defining a) as the dynamic range of the function g (x); The operation result to the operation result of the scale factor k, and the lower bits by using a shifter _pbl f (X _lower) to a variable processing the _{f pbl (X lower) / 2} k; Receiving the pixel data X using an error lookup table and outputting an operation result f _{error_reduced} (X) for compensating for the error; And summing the f _pbl (X _lower ) / 2 ^k , the f _pbl (X _upper ) and the f _{error_reduced} (X).

step_size (f _pbl (X _upper )) = | f _pbl (x _upper )-f _pbl (x _upper +1) |

k = ^┌ log ₂ (SF _local ) ^┐

In addition to the data compression-restore method for the flat panel display memory, the frame rate improving method of the present invention receives continuous frame compressed block data composed of compressed data stored in the memory and receives upper bits X _upper . Calculating a motion vector by performing a motion estimation operation; Grouping the plurality of compressed pixel blocks into a macroblock of larger size and calculating a grouped motion motion vector of the compressed blocks; And correcting the motion vector through auxiliary motion estimation using the motion vectors of the grouped macroblocks.

The present invention compresses data by selectively removing a part of the data based on the identity of neighboring pixel data, or maximizes the compression ratio by cutting off the lower bit part of the pixel data, sharing a comparator, an encoder, and the like, in an RLE operation. Not only can the position value shifter be applied to reduce the complexity of the hardware, but also the prediction method based on the adaptive compression mode prediction unit based on the compression rate of the previous frame. By applying Prediction Scheme, any one of various compression algorithms can be appropriately selected according to the image data to further increase the compression ratio.

The present invention is capable of restoring data compressed with the compression algorithms PPC, PFC and RLE without loss, and the compression algorithm TPPC capable of further improving the compression rate is capable of restoring the loss to a degree that humans cannot feel.

According to the present invention, the memory update can be optimized by comparing the compressed pixel data between the frames after the frames based on the similarity between successive frames. The storage time and the fetch time of the entire image can be optimized. Fetch Time can be reduced.

The present invention can efficiently process histogram-related operations widely used in image quality processing by simplifying the gradation section and the height section of the histogram based on the compressed image data. In addition, the present invention provides a partitioned lookup table (Partitioned bit LUT) of the lookup table by dividing it into upper and lower partial bits of the pixel data compression type so that calculation is possible by using a scale factor and an error lookup table. The number of can be reduced. The split bit lookup table may be applied to a frame insertion lookup table (Frame insertion LUT) or to reduce the complexity of an LCD overdrive circuit, for example, to improve response characteristics in a liquid crystal display. It can also be applied to correct the gamma curve by checking only the change of the reference bit.

The present invention enables efficient frame rate improvement by reducing the amount of computation of motion estimation based on pixel data compressed according to the compression algorithms.

The present invention can be applied to an RLE encoder of a data compression apparatus, and can implement a position value shifter that can be designed with low hardware complexity while simultaneously checking a segment boundary that continuously represents the boundary of the same pixel data.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 37.

The data compression apparatus and method of the present invention perform compression based on similarity between neighboring pixel data. In general images, spatial redundancy is not significant between neighboring pixel data, and thus, most significant bits of data previously stored in the memory are the same. Thus, by removing the upper bits identical to the upper bits stored in the memory in the compression process, a high compression ratio compression effect can be obtained.

The data compression apparatus and method of the present invention compresses data using a partial pixel compression (hereinafter, referred to as "PPC") algorithm as shown in FIG. The PPC algorithm removes the same upper bits in the pixel data to compress the data and generate a flag indicating the identity of the removed upper bits.

Referring to FIG. 1, it is assumed that the PPC algorithm includes upper partial pixel data “b” and lower partial pixel data “2” including lower bits in the n-th pixel data of an original image. The upper partial pixel data "b" includes upper bits of the n-th pixel data, and the lower partial pixel data "2" includes lower bits of the n-th pixel data.

The PPC algorithm inserts the mth compressed data including uncompressed upper bits “b” and lower bits “2” into the memory when the upper bits of the nth pixel data are different from the upper bits of the n−1 pixel data. A flag bit "0" is added to the m th compressed data indicating that the data is not actually compressed.

Each of the n + 1 th pixel data and the n + 2 th pixel data is the same as the upper bits "b" of the previous n th pixel data with the upper bits "b". In this case, the PPC algorithm stores the lower bits "3" and the lower bits "4" of the n + 1st pixel data in memory as m + 1st compressed data, and the data compressed to the m + 1st compressed data. Add a flag "1" indicating that.

The process of restoring the data compressed by the PPC algorithm is as follows. The decompression algorithm of the PPC first checks a flag, which is the least significant bit, to determine whether to compress each of the compressed data. The PPC decompression algorithm determines the remaining bits except the flag as uncompressed full bit data when the flag is "0" like the mth compressed data, and selects the remaining bits "b" except the flag as upper bits. To restore the n-th pixel data using "2" as the lower bits. When the flag is "1" like the m + 1st compressed data, the PPC decompression algorithm determines the remaining bits except the flag as the compressed data from which the upper bits have been removed, and thus the upper bits of the m + 1st compressed data "3." Adds the upper bits of the previous pixel data, i.e., the upper bits "b" of the m th compressed data, before "" to restore n + 1 th pixel data, and the lower bits of the m + 1st compressed data "4" The upper bits " b " of the previous pixel data are added before to restore the n + second pixel data.

The present invention shares a compression algorithm that removes the same pixel data continuously, such as a Trunked Partial Pixel Compression (TPPC) algorithm, a Run Loss Encoding (RLE) algorithm, which is a conventional lossless compression algorithm, and some compression schemes with the PPC. Data is compressed by selectively applying a Partial and Fixed Run Length Compression (hereinafter referred to as "PFC") algorithm.

In the PPC algorithm, the compressed pixel data is 1 bit larger than the pixel data before compression due to flag overhead. Therefore, when there are many pixel data that are not compressed due to different upper bits among adjacent pixel data in the image, the total capacity increases after compression, and thus it is not possible to guarantee a reduction in memory through compression.

Since the amount of memory in the system design is determined by the lowest compression rate, it is necessary to have a sufficient compression rate even in the image of the worst case, which will be referred to as a compression rate guard. Therefore, in order to maintain such a compression rate guard, and to reduce the complexity of the operation, a compression algorithm having the same operation method as PPC and showing high image quality is proposed. In order to maintain the minimum compression rate, the compressed pixel data must be smaller than the size of the original pixel data. Therefore, some lower bits of the stored pixel data are truncated to minimize the deterioration of image quality and to increase the compression rate.

When 2 bits are cut off as shown in (c) of FIG. 2, image quality degradation such as pseudo edges can be confirmed in a portion such as a sky having similar values between neighboring pixel data. However, it is difficult to feel a deterioration in the case of the ground, which is largely different from neighboring pixel data. When 1 bit is cut off as shown in (b) of FIG. 2, it is difficult to feel a deterioration in image quality in the sky as well as the ground. If this feature is applied to PPC, if the difference between neighboring pixel data such as the ground is large, 2 bits are truncated and stored in memory as uncompressed type, and the difference between neighboring pixel data such as the sky is small. 1 bit is cut from two pixel data and stored in memory as a partial type. In the case of cutting 1 bit or 2 bit through the proposed method as shown in FIG. 2 (d), there is no deterioration in image quality in terms of emotional image through an eye test. In addition, PSNR has a very high picture quality of 45.2dB. The proposed compression scheme will be referred to as truncated partial pixel compression (TPPC).

The TPPC algorithm differs only by truncating the lower bits, but basically has the same compression-restore process as the PPC algorithm. If the upper bit group is different from the previous pixel data as in the n th original pixel data of FIG. If the upper bit is the same as the previous pixel data such as n + 1, n + 2nd pixel data, the LSB of the lower bit group c and d are truncated, and the flag is set to 1 as in the PPC algorithm. partial type). The restoration process is similar to the PPC algorithm, except that the padding is taken from the MSB by the number of bits truncated as shown in FIG. 3.

When the compression rate of the PPC algorithm is low, TPPC is applied. Since the overall quality and trade-off of the compression rate occur depending on the application level, the criteria to be applied can be determined according to the requirements of the application or the system. It can also be applied in units of frames or blocks. In implementing this approach, we can consider two methods of algorithm selection based on image characteristics and algorithm selection after compression.

By applying the TPPC algorithm on a limited compression image, the compression rate can be maintained above a certain level. In selecting a suitable algorithm for an image, it is possible to determine the characteristics of the target image and then select a compression algorithm to obtain the highest compression rate, but a large buffer memory is required, so that the complexity of the hardware and the image are high. There is a problem that a delay occurs due to the characterization of the. However, the scene change of the displayed image is a very short moment in the entire displayed image, and the characteristics of the image tend to exhibit the same or similar characteristics as the previous frame while one scene is maintained. Therefore, the present invention proposes a method of applying the algorithm showing the highest compression rate in the previous frame as the compression algorithm of the current frame. Specifically, a method of adaptively selecting a compression algorithm through prediction based on frame property history is used. In addition to a method of adaptively selecting a compression algorithm through the prediction, a method of selecting whether to perform the TPPC compression algorithm through the image slope is proposed. The algorithm selected through this method will be referred to as a compression mode.

6 shows a format of compressed data according to each compression mode.

Compression mode is divided into PPC algorithm, TPPC algorithm, PFC algorithm, and RLE algorithm. First, PPC algorithm can be divided into partial type and uncompressed type. Are distinguished.

Referring to FIG. 6, in the PFC algorithm, the flag is used to distinguish whether or not the flag is compressed into a partial pixel type, similar to the PPC algorithm. When three consecutive pixel data are the same, the fixed run length type compression is performed. When performing, the flag is always '0' and distinguishes whether it is compressed to a fixed run length type or uncompressed type data that stores pixel data without compression through the code of FIG. 4. In the fixed run length-type compression algorithm, since the three pixels from the nth to n + 2th of the original pixel data are the same as “A”, the mth compressed data is the pixel data “A” and code = 1 Save flag = 0. The PFC algorithm uses code and flags to indicate that the n + 3rd original pixel data "B" and the n + 4th pixel data "C" are different and therefore not actually compressed when storing the m + 1st compressed data. 0 ”indicates that it is stored in memory as uncompressed type. The PFC algorithm restores the m th compressed pixel data “A” compressed with the fixed run length type to the n th to n + second pixel data, and the m + 1 th compressed pixel data “B” which is the uncompressed type data n + 3. Restore to the first pixel data.

The RLE algorithm stores a run length which is the number of repetitions of the pixel data when the same pixel data is continuously present from any pixel. Since the RLE algorithm is the same from the n th pixel data to the n + k th pixel data as shown in FIG. 5, the pixel “B” and its repetition frequency “k” are stored as run lengths. Since the RLE algorithm differs from n + k + 1st pixel data "C" and the next pixel data "D", it stores "C" and the repetition number "0" as m + 1st compressed pixel data. The RLE algorithm restores the compressed pixel data by outputting the stored pixel data by the run-length number of times.

The TPPC algorithm is substantially the same as the PPC algorithm except for the difference in the process of cutting off the lower bits in the data format as shown in FIG. 3.

In the PFC algorithm, data storage is divided into a partial type, a fixed run length type, and an uncompressed type. These storage types can be distinguished by flags and codes. The partial type saves and compresses only the remaining lower partial bits in the memory except for the same upper bits as in the example of FIG. 1. The fixed run length type stores in the memory a code having a code value of "1" and a flag having a flag value of "0" in memory together with a full bit of pixel data when three consecutive pixel data are the same. do. The uncompressed type stores only one pixel data when not compressed to a partial type or fixed run length, and stores a code and a flag set to "0" in memory, respectively.

The flag distinguishes whether the compressed data is a partial type or not, and the code is compressed with a fixed run length type when it is not a partial type, or not compressed in any way, so that the original data is bypassed as it is and not compressed. Indicates whether it is stored as a type.

If the flag is "1", it is stored as a partial type. The partial type compares the upper 4 bits between the n-th pixel data, which is the previous pixel data, and the n-th pixel data adjacent to each other, as shown in FIG. 1, and the distance between the n−1th pixel data and the n + 1th pixel data is farther away. Considering this, the upper three bits are compared to store partial pixel data in a memory. If the flag is "0", it is a case of being stored in the fixed run length type or the uncompressed type. This fixed run length type or uncompressed type stores a run length including one pixel data, a code and a flag in full bit form, and stores the data in a memory similar to an RLE. The fixed run length type stores the data in the memory when the n th pixel data and the n + k th pixel data, that is, the k consecutive pixel data are the same in the continuous data. If two consecutive pixel data are identical, they are stored in memory as a partial type.

The fixed run length type represents a case where two pixel data are contiguous from any pixel data, and the uncompressed type represents a case where there is no continuous pixel data from any pixel. In this case, the code and the flag are (10) in the fixed run length type and (00) in the uncompressed type, and when viewed in binary, it can be seen as the run length of the RLE to indicate the number of repetitions of pixel data. Therefore, such compressed data may be recovered through the recovery device (or RLE decoder) of the RLE in the form of run length of the RLE. That is, since the code and the flag can be used as the run length of the RLE, it can be shared with the RLE decoder of the restoration device.

The partial type of the PFC algorithm and the partial type of the PPC and TPPC algorithms basically compress pixel data using the same compression principle. In PFC, in combination with the partial type and the fixed run length type, the compression ratio can be improved in more various cases. The fixed run length type may indicate three repetitions of pixel data using a code and a flag.

According to the present invention, the fixed run length type and the uncompressed type are distinguished by code when the flag is zero. For example, the case where the code is 1 may indicate a fixed run length type, and when the code is 0, the data is stored in an uncompressed type. Accordingly, the present invention can store the case where the full pixels are continuously the same in the fixed run length type by controlling the code = 1 and the flag = 0. Since the present invention shows the highest compression ratio when storing the case where three pixel data are consecutively the same, the case where the three pixel data are consecutively the same is stored. The previous embodiment has been described on the assumption that k = 2.

PPC compares and stores each 4 bits of pixels in a pixel comparison range (hereinafter, referred to as "PCR") as shown in FIG. 1. PCR is defined as the number of consecutive pixels to be compared in any successive pixels. The compression principle of the partial type of the PFC and the partial type of the PPC is substantially the same. As described above, the TPPC algorithm differs in that the lower bits are truncated in the data format, except that the TPPC algorithm is substantially the same as the PPC algorithm.

The PFC algorithm, the PPC algorithm, the TPPC algorithm and the RLE algorithm are selected by an adaptive compression mode prediction unit described later. The adaptive compression mode prediction apparatus determines a compression algorithm having the highest compression rate in a previous frame among PPC, PFC, and RLE compression algorithms, and generates a signal for selecting a compression algorithm calculated at the highest compression rate in the current frame. The image slope calculator generates a signal for selecting a TPPC compression algorithm when the compression algorithm selected by the adaptive compression mode prediction unit does not comply with the compression rate guard based on the average value of the difference between the pixel data.

When the pixel data can be compressed in the fixed run length type in the PFC, the present invention stores the fixed run length type even though the partial data can be compressed in the partial type. This is because the compression ratio test resulted in a higher compression ratio and also simply stored as a fixed run length type to reduce the complexity of the selection process of the partial type and the fixed run length type.

In the PFC partial type compression algorithm, the number of bits is different between the lower 4 bits of the first pixel data and the lower 5 bits of the second pixel data. This means that the PFC partial type compression algorithm has the same compression scheme as the PPC partial type, but in the case of PFC, there is an additional space for storing the code that distinguishes the fixed run length type from the uncompressed type. This is because it is not used when storing compressed data. Like the PPC, the previous pixel data and the first pixel data store 4 bits different from each other by comparing 4 bits, and only the upper 3 bits can be compared in consideration of the fact that the pixel distance is far from the second pixel data.

The flag indicates whether high order bits of pixel data stored as compressed data are removed. In addition, as described above, the flag indicates whether or not the upper bit is removed, and can also distinguish whether the flag is a partial type or a fixed run length type or an uncompressed type. Compressed storage of the partial type means that the upper bits have been removed, and that the upper bits have not been removed in the case of the fixed run length type or the uncompressed type.

7 shows a hardware configuration of the data compression and decompression apparatus of the present invention.

Referring to FIG. 7, the data compression and decompression device of the present invention is connected to an input / output end of the memory 4, and shares a part of hardware for each algorithm, thereby having a low complexity hardware configuration. This configuration makes it possible to program the same hardware to process the compression and decompression algorithms respectively.

The compression algorithm of the data compression device 100 and the decompression algorithm of the data decompression device 200 are selected by the adaptive compression mode prediction device 5.

The data compression device 100 includes a first circular buffer 1, a comparator 2, an encoder 3, and a TPPC converter 8. The first circular buffer 1 temporarily stores the original data and supplies the original data to the comparator 2. The comparator 2 compares the upper bits of consecutive pixel data input from the first circular buffer 1 and determines the identity of the pixel data. The comparator 2 supplies the pixel data to the encoder 3 together with the identity determination information indicating the identity according to the comparison determination result of the continuous pixel data. The encoder 3 includes a PFC encoder and an RLE encoder. The PFC encoder and the RLE encoder share a comparator 2. The encoder 3 compresses the pixel data from the first circular buffer 1 into three compression algorithms of the RLE algorithm, the PFC algorithm, and the PPC algorithm, and then the compression algorithm input from the adaptive compression mode prediction device 5. As a result, among the data compressed by the three compression algorithms, the data compressed by the compression algorithm showing the best compression ratio in the previous frame is stored in the memory 4. The compression algorithm with the best performance on the previous frame is likely to perform well on the next frame. Thus, the encoder 3 compresses the pixel data of the next frame with the compression algorithm selected by the adaptive compression mode prediction device 5.

The PFC encoder compresses data for both the PFC algorithm, the PPC algorithm, and the TPPC algorithm. By adjusting the size (or bit length) of the partial pixel data, the PFC encoder converts the data from the PFC algorithm to the PPC / TPPC algorithm and vice versa. Can be easily switched. Thus, the encoder 3 can share hardware that handles the compression operation of the PFC algorithm and the PPC algorithm.

The TPPC converter 8 cuts out the lower 1 bit or 2 bits from the pixel data from the encoder 3 and stores the pixel data including the remaining bits in the memory 4.

The data recovery apparatus 200 includes a decoder 6 and a second circular buffer 7. The decoder 6 decompresses the compressed data from the memory 4 into decompression algorithms such as the RLE algorithm, the PFC algorithm, and the PPC / TPPC algorithm, and then decompresses corresponding to the compression algorithm selected by the adaptive compression mode prediction device 5. The restored data restored by the algorithm is selected and supplied to the second circular buffer 7. In addition, the decoder 6 may restore the compressed data from the memory 4 to the second circular buffer 7 by using a decompression algorithm corresponding to the compression algorithm selected by the adaptive compression mode prediction apparatus 5. . In the decoder 6, the partial pixel decoder restores data with a PFC algorithm, a PPC algorithm, a TPPC algorithm, and the like, by adjusting the size of the partial pixel data, for example, the size of the partial type and the fixed run length type. The restoration method can be switched to the TPPC algorithm or vice versa. Therefore, the decoder 6 can share hardware for processing the reconstruction operation of the PFC algorithm and the PPC algorithm.

The adaptive compression mode prediction apparatus 5 compares the compression ratio of each compression algorithm of the previous frame image and applies the algorithm having the highest compression rate in the previous frame to the compression of the current frame image. In detail, the adaptive compression mode prediction apparatus 5 obtains the compression ratios of the PPC algorithm, the TPPC algorithm, the PFC algorithm, and the RLE algorithm through the codes, flags, and run lengths, which are intermediate encoded data generated during the compression process. At the end of the compression of the frame to be compressed, the compression algorithm calculated at the highest compression rate is selected as the next compression algorithm. As a result, the adaptive compression mode prediction device 5 selects the compression algorithm having the highest compression ratio and indicates the selected algorithm as a result of compressing the data of the previous frame with the PFC algorithm, the RLE algorithm, the PPC algorithm, and the TPPC algorithm. The selection signal is supplied to the encoder 3 and the decoder 6 to select a compression and decompression algorithm of the encoder 3 and the decoder 6.

The adaptive compression mode prediction apparatus 5 receives the compressed pixel data from the encoder 3 of the compression apparatus 100 and grasps an algorithm indicating a high compression ratio in the current frame, and adaptively compresses the algorithm according to image characteristics. Can be selected. In this case, the TPPC converter 8 can be used to keep the compression rate guard. In the case of the TPPC converter 8, when the compression rate of the compressed pixel data is low, the TPPC algorithm converts and stores the compressed data to maintain the compression rate. This is performed by the TPPC algorithm in the same process as the PPC algorithm. Likewise, only the LSB of the lower bit group is truncated.

The image slope calculator 9 performs a compression algorithm selection through prediction, and calculates an image slope of pixel data input to the compression device 100. When the image slope is larger than a predetermined image slope corner, a signal for selecting the TPPC algorithm may be transmitted to the adaptive compression mode prediction apparatus 5 to maintain the compression rate.

Referring to the operation of the data compression and decompression apparatus shown in FIG. 7 in detail, the comparator 2 compares the upper bits of the consecutive pixel data input from the first circular buffer 1 to determine the identity of the pixel data. The pixel data is supplied to the encoder 3 together with the identity determination information indicating the identity according to the determination result. The encoder 3 compresses the pixel data with the algorithm selected by the adaptive compression mode prediction device 5 and stores it in the memory 4. The decoder 6 decompresses the compressed data from the memory 4 with the decompression algorithm selected according to the compression algorithm input from the adaptive compression mode prediction device 5 and supplies it to the second circular buffer 7.

FIG. 8 shows the data compression apparatus 100 shown in FIG. 7 in detail. In Fig. 8, "Pixel 1", "Pixel 2", "Pixel 3" and "Pixel 4" are first to fourth pixel data to be compressed, and "Previous Pixel" is original data of previous pixel data which has already been compressed. to be. These pixel data are compression target pixel data input through the first circular buffer 1.

The data compression apparatus 100 compresses the currently input pixel data by the PFC partial type or the PPC compression algorithm when the upper bits between previously stored previous pixel data and the currently input pixel data are the same. The data compression apparatus 100 compares the currently input Pixel 1 to Pixel 3 and compresses the pixel data currently input by the fixed run length type and the uncompressed type of the PFC. In the case of compression using the RLE compression algorithm, the data compression device 100 compares and simultaneously compares Pixel 1 to the last pixel data to the extent that the I / O Line Width allows.

The comparator 2 has a plurality of comparators. The encoder 3 includes a PFC encoder and an RLE encoder. The PFC encoder includes a partial pixel encoder and a full pixel encoder. The RLE encoder includes a position value shifter and a subtractor for quickly calculating the boundary of the same pixel data, that is, the run length. The first comparator compares the previous pixel data with the first pixel data Pixel 1 and supplies a comparison result indicating whether the data is identical to the partial pixel encoder. The second comparator compares the first pixel data Pixel 1 and the second pixel data Pixel 2 and supplies a comparison result indicating whether the data is identical to the partial pixel encoder, the full pixel encoder, and the position value shifter. do. The third comparator compares the second pixel data Pixel 2 and the third pixel data Pixel 3 and supplies a comparison result indicating whether the data is identical to the full pixel encoder and the position value shifter.

The partial pixel encoder generates a flag based on the comparison result from Previous Pixel to Pixel 2. The full pixel encoder generates code based on the comparison result from Pixel 1 to Pixel 3. The RLE encoder can calculate run lengths quickly and efficiently through position value shifters and subtractors. The generated code, flag, and runlength are combined with pixel data through a pass transistor according to a compression algorithm selected by the adaptive compression mode prediction device 5 to compressed data having a data format as shown in FIG. Is compressed.

The partial pixel encoder selects one of the partial type of the PFC algorithm and the partial type of the PPC / TPPC algorithm according to the algorithm selected by the adaptive compression mode prediction apparatus 5. In addition, the partial pixel encoder receives the comparison result of the first and second comparators, and if the upper bits of the previous pixel data and the second pixel data Pixel2 are the same, the partial pixel encoder of the PFC algorithm selected by the adaptive compression mode prediction apparatus 5 is equal. The upper bits of the pixel data are removed by compression to the partial type or the partial type of the PPC / TPPC algorithm, and the flag bits are generated as "1" to store the flag bits in the memory 4 together with the compressed data.

Since the fixed runlength type and the uncompressed type of the PFC algorithm are not compressed, the full pixel encoder stores all bits of one pixel data in memory, so that the full pixel encoder has the first pixel data Pixel 1 to the third pixel data Pixel 3 Compare

9 is a diagram illustrating a compression pattern and a compression ratio according to a comparison range of a partial type compression method. The partial type compression algorithm of PFC and PPC reduces the number of duplicate high-order bits and stores only the low-order bits. If you compare only the currently input pixel data without comparing with previous pixel data like <Case A>, even if the upper bit is the same as the previous pixel data, it cannot be checked. Therefore, the lower bit must be stored after storing the upper bit. . Therefore, when comparing only the currently input pixel data without comparing with previous pixel data as shown in <Case A>, the same upper bit is repeatedly stored and thus shows a low compression rate. On the other hand, when comparing with previous pixel data such as <Case B>, it is not necessary to store the same high bit redundantly, which shows high compression ratio. In this case, the higher bit represents a larger difference in compression ratio when the same pixel data are continuously present. Therefore, the partial type compares the previous pixel data with the currently input pixel data and compresses them.

In the case of the partial type, since the currently input data is compressed based on previously stored pixel data, the previous pixel data is compared, but the fixed run length type and the RLE of the PFC do not need to compare the previous pixels together. RLE can cover a very wide range of comparisons, so that pixel data within consecutively identical ranges can all be seen as already compressed. Since the probability of the previous pixel data and the currently input compression target pixel data is the same, it is inefficient to compare with the previous pixel data. The fixed run length type of the PFC has a fixed range for comparison and storage, so the range showing the highest compression ratio should be compared. Since the probability of successive pixel data being the same becomes very low as the comparison range becomes larger, it may be possible to have a high compression rate only by comparing a small range. Therefore, the fixed run length type and the RLE of the PFC compares only the pixel data currently input because it is inefficient to lose the compression ratio while comparing with the previous pixel data.

FIG. 10 shows the data recovery apparatus 200 shown in FIG. 7 in detail.

Referring to FIG. 10, the data restoration apparatus 200 shares hardware for processing a restoration algorithm corresponding to each of the PFC algorithm, the RLE algorithm, the PPC algorithm, and the TPPC algorithm, thereby satisfying a low hardware complexity. The data recovery apparatus 200 restores data compressed to the full pixel type of the PFC algorithm through the RLE decoder and restores the data compressed to the partial pixel type of the PFC and PPC to the partial pixel decoder.

The data decompression device 200 largely includes a demultiplexer 63 and 64 for selecting the decoders 61 and 62 according to an algorithm, a decoder 61 and 62 for decompressing, and a latch having a size of 1 pixel having a previous pixel value. Consists of 65. The input compressed pixel data is first divided into a PFC / PPC algorithm and an RLE algorithm according to a compression mode in the first demultiplexer 63, and then again a partial type when the flag of the compressed pixel data is 1 in the second demultiplexer 64. Is 0, it is classified as being stored in the full type or the bypass type and sent to the corresponding decoder (61, 62). Since the TPPC algorithm is identical to the PPC algorithm, it is processed through the same path and process as the PPC algorithm. First, when looking at the full pixel / RLE decoder 61, since the pixel data is compressed by the run length in the case of the RLE, the counter 611 is used to repeatedly output and restore the pixel data by the run length. (decompression), the full type and bypass type of the PFC algorithm recovers in the same way as the RLE algorithm using the lower 2 bits of code and flags as run lengths. The partial pixel decoder 62 restores data compressed to a partial type. Since the compressed pixel data has only the lower bit of the pixel data, the partial pixels 1 and 2 are sequentially written to the lower bit position of the latch 65 having the upper bit data of the previous pixel to decompress. In the case of the TPPC algorithm, padding of the truncated LSB is required. In general, unlike the method of filling '0', the MSB 2 bits transmitted from the latch 65 are filled with the truncated LSB to generate pixel data. Done.

The first demultiplexer 63 supplies the compressed data from the memory 4 to the full pixel / RLE decoder 61 or the partial pixel decoder 62 according to the compression algorithm from the adaptive compression mode prediction device 5. The first demultiplexer 63 supplies compressed data from the memory 4 with the flag bit to the partial pixel decoder 62 if the compression algorithm from the adaptive compression mode prediction device 5 is a PFC algorithm or a PPC / TPPC algorithm. On the other hand, if the compression algorithm selected by the adaptive compression mode prediction device 5 is an RLE algorithm, the compressed data from the memory 4 is supplied to the full pixel / RLE decoder 61.

The second demultiplexer 64 supplies the data from the first demultiplexer 63 to the partial pixel decoder 62 or the full pixel / RLE decoder 61 according to the flag bits. The multiplexer 621 of the partial pixel decoder 62 recovers compressed data of pixel portions of unequal portions of consecutive pixels in the partial type of the PFC and PPC / TPPC algorithms. Data compressed with the fixed run length type of the PFC is recovered by the full pixel RLE decoder 61. The latch 65 stores old pixel data that has already been restored.

An apparatus and method for compressing and decompressing data can obtain a high compression ratio on average by programmably selecting a high compression ratio among the PFC algorithm, the PPC / TPPC algorithm, and the RLE algorithm according to the characteristics of the image.

The adaptive compression mode prediction apparatus 5 determines a compression algorithm indicating the highest compression rate in the current frame and applies it to the compression algorithm of the next frame. To this end, the adaptive compression mode prediction apparatus 5 includes a first counter 51 for counting flags from the data compression apparatus 100 and counting flags and codes from the data compression apparatus 100 as shown in FIG. A second counter 52 and a third counter 53 for counting run lengths from the data compression device 100 are provided. In addition, the adaptive compression mode prediction apparatus 5 includes a compression ratio determination unit 54 that determines, as a compression / reconstruction algorithm of the current frame, the algorithm having the highest compression ratio in the previous frame according to the count result of the flag, code, and run length. do. The adaptive compression mode prediction apparatus 5 counts each flag, code, and run length generated during the compression process to determine the number of data to be stored for each algorithm. After the compression of one frame is completed, the compression algorithm stored the least number of times is designated as the compression algorithm of the next frame.

The adaptive compression mode prediction apparatus 5 grasps the algorithm showing the highest compression rate in the current frame, selects it as the compression algorithm of the next frame, and applies the TPPC algorithm according to the image slope calculation result. Based on flags, codes, and run lengths generated during the compression process, counters 51 to 53 are counted for each algorithm to count the number of data to be stored. After the compression of one frame is finished, the compression rate determination unit 54 selects the stored algorithm the smallest number of times. When the compression rate does not reach the compression rate guard because the image slope calculated by the image slope calculation unit 9 exceeds a preset image slope corner, the adaptive compression mode prediction apparatus 5 selects the TPPC through the TPPC selection signal. If it is not exceeded, the selected algorithm is selected based on the history and stored in the current mode to designate the compression mode of the next frame. previous mode) to generate a compression mode signal when restoring a frame stored in a memory in the future.

When changing the compression rate according to an image sequence, when pixel data is compressed, the pixel data is compressed by combining pixel data through flags, codes, and run lengths, which are intermediate information. Know how many times you need to compress a frame. By multiplying the number of storage times and the size of one compressed pixel data, the image capacity after compression of the entire frame can be determined by each compression algorithm.The algorithm with the smallest image capacity after compression is selected as the algorithm that shows the highest compression ratio, and the next frame is compressed. Used as an algorithm. According to the compression algorithm according to the same video as in FIG. The change in the compression ratio is calculated as shown in FIG. 13. 12 and 13, it is shown that the method of selecting an adaptive compression algorithm through history-based prediction that applies a compression algorithm having a high compression rate in the previous frame to the compression of the current frame is useful. You can improve the compression rate of the entire image.

The algorithm is selected based on the prediction, and the compression algorithm is selected by identifying the characteristics of the image data before compression. Since the compression rate of the PPC algorithm varies according to the identity with neighboring pixel data, an index of an image slope indicating this is proposed and used as a criterion for applying the TPPC algorithm. When the number of pixels in the image is n and the value of the x th pixel data is P _x , the image slope is expressed by Equation 1 below.

As shown in Equation 1, the image slope represents an average value of the difference between neighboring pixel data. The larger the image slope has a larger value, the lower the probability that the neighboring pixel data and the upper bit group are the same and thus the compression ratio is low. Therefore, the image slope and the compression ratio have a high correlation and can be used as an application index of the TPPC algorithm.

In FIG. 14, the compression ratios of the PPC algorithm and the TPPC algorithm for 152 selected images of various features were obtained according to Equation 2 to be described below, and aligned according to the image slope. Both the PPC algorithm and the TPPC algorithm tend to decrease the compression rate as the image slope increases. The PPC algorithm has a compression ratio of 41.7% to -9.1% and an average of 23.4%, and the TPPC algorithm has a compression ratio of 54.7% to 15.2% and an average of 40.4%. In terms of image quality, the TPPC algorithm maintains a very high image quality of 44.4 dB at an PSNR of 42.3 dB and an average of 46.0 dB, and the actual emotional loss (Loss) that is visually felt as shown in FIG.

As shown in Fig. 14, the image slope has a high correlation with the compression ratio and selects an algorithm accordingly. The image slope, which is the basis of the compression algorithm selection, will be referred to as an image slope corner. If the value of the image slope is smaller than the image slope corner, the PPC algorithm is applied. 14 shows a case where the PPC algorithm and the TPPC algorithm are selectively applied by setting the image slope corner to 9, and when the image slope is 9 or less, the PPC algorithm is applied and the lossless (lossless) compression is applied. PSNR shows a high image quality of about 45dB and shows that a high compression ratio can be obtained.

15 is a result of obtaining the compression ratio (Equation 2) according to each algorithm of the experimental image.

Referring to FIG. 15, among the lossless compression algorithms, the compression rate of the PPC algorithm is high, and when compressed using the RLE algorithm, the compression rate is low or the capacity is increased. However, the compression rate is very high when there are many consecutive identical pixel data such as "coin" and "word" images. In addition, the PFC algorithm shows the intermediate characteristics of the PPC algorithm and the RLE algorithm. In general, the compression ratio of the TPPC algorithm is high, but in the general case, the PPC algorithm is applied and limited for the compression rate guard according to the image slope corner. In other words, the present invention obtains a high compression ratio by using a PPC algorithm and a PFC algorithm in a general image, and programmatically using an algorithm, such as an RLE algorithm, in an image in which many identical pixel data appear continuously such as a GUI or a text screen. Can be.

Even in the same image, the compression rate is changed as shown in FIG. 16 according to image processing. In case of damage or scaling due to JPEG, the compression rate increases because the probability of the partial pixel data being the same as that of neighboring pixel data increases. In case of damage caused by JPEG, the PPC algorithm increased by 0.4%, the TPPC algorithm by 0.4%, the PFC algorithm by 1.6%, and the RLE algorithm by 2.1% and 3.3%, respectively, depending on the run length. Increases of 6.3%, 5.0%, 8.5%, 6.3% and 8.9%. That is, a compression algorithm that is more suitable for a mobile display device that uses a lot of lossy compressed image and displays a scaled image due to the fixed resolution characteristic of the LCD.

FIG. 17 shows the results of comparing the compression ratios of the PPC algorithm, the TPPC algorithm, the PFC algorithm and the existing lossless compression algorithms LZW and JPEG-LS Lossless with respect to the experimental images "lena", "peppers" and "baboon". Comparing the average compression ratio of the three images by each algorithm, the PPC algorithm is 14.0%, the TPPC algorithm is 33.1%, the PFC algorithm is 11.6%, the LZW algorithm is 12.0%, and the JPEG-LS lossless algorithm is 38.5%. JPEG-LS lossless compression rate is higher than other algorithms, but the hardware complexity is relatively high, about 37 times higher, which requires large hardware, slow operation speed as mentioned above, and is not applicable to SOP, which is a future implementation method. However, the PPC algorithm and the PFC algorithm, including the TPPC algorithm, can exhibit similar or higher compression rates with only 2% of the hardware of LZW. In the case of TPPC, unlike other proposed algorithms, PPC and PFC, the image quality is deteriorated, but the compression ratio is similar to that of the JPEG-LS lossless algorithm with very low hardware complexity.

The average compression ratio of the PFC algorithm and PPC algorithm is about 22%, and the TPPC algorithm has a high compression ratio of more than 39%. The average operation time is about 45ns as shown in FIG. 18, which is very short compared to 260ns, which is a write cycle time of the SOP memory. The time required for one-time compression and storage increases to 305ns, but the computation time required for _compression is called t _compression , the write cycle time is t _write , the original image size is size _original , and the compressed image capacity is size _compressed . According to Equations 3 and 4, the total time for compressing and storing the entire image is 12% shorter than storing the uncompressed image rather than storing the uncompressed image.

As described above, the present invention eliminates redundant upper bits of adjacent pixel data to reduce the image frame buffer. Through this calculation method, PSNR can achieve high image quality of 46dB or more, and it is possible to program the existing RLE algorithm by applying the algorithm adaptively based on the characteristics of each frame, and hardware with very low hardware complexity. Can be designed. According to the present invention, a compression ratio of at least 12.5% or more can be obtained, and the hardware amount is 2% or less in comparison with LZW, which shows a similar compression ratio, and the calculation scheme is very simple and suitable for the internal memory. The simulation results of the designed circuit also show that the compression time is very short compared to the write cycle time of the memory, which greatly reduces the time required to compress and store the entire image.

Priority encoders used to detect segment boundaries that continuously indicate boundaries between the same pixel data have high hardware complexity and require a fast clock cycle. Priority encoders have a slow processing speed as well as hardware overhead when sequentially determining input pixel data using a counter. In order to solve the disadvantage of the priority encoder, the present invention uses the position value shifter 321 used for the run length calculation.

19 shows the position value shifter in detail. The position value shifter 321 is applied to the RLE encoder of the data compression device 100, and can be designed with a low hardware complexity while quickly checking a segment boundary indicating a boundary of the same pixel data. The position value shifters 321 are connected to each other in series, and receive run information of pixel data through a comparator, and transmit run lengths of the same pixel data group boundary to a subtractor shown in FIG. 20. It is responsible for calculating. Position value is a value corresponding to a pixel data position to represent the same pixel data group boundary based on the first input pixel data in the input pixel data, and a token is a position of the pixel data group boundary. The position value shifter operates according to a clock so that the value value is sequentially passed to a predetermined position.

The position value shifter 321 includes a first buffer 3211, a pass transistor 3212, a master-slave latch 3214, a second buffer 3215, and an exclusive OR gate (XOR) 3213.

When the token is delivered according to the comparison result of the comparator, the first buffer 3211 selects to pass the right position value to the left or the current position value to the left. Master-slave latches 3212 allow tokens and position values to be delivered on a clock. The second buffer 3215 serves to pass the token to the right according to the comparison result of the comparator.

The i-th binary value of the position value shifter is input to the source terminal of the pass transistor 3212. The drain terminal of the pass transistor 3212 is connected to a position value path, and the gate terminal of the pass transistor 3212 is connected to an output terminal of the XOR 3213. The input terminal of the XOR 3213 is connected to the output terminal of the comparator and the master latch output terminal of the master-slave latch 3214. With this configuration, when the token is input and the comparison result of the comparator becomes zero, the position value connected to the source terminal of the pass transistor 3212 can be transmitted to the position value pass.

The comparator outputs "1" when the compared pixel data are the same, and in response to the output of the comparator, the pass transistor 3212 is turned off and the first buffer 3211 is enabled to receive the position value received from the right side. Pass to the left. The second buffer 3215 is also enabled to pass tokens to the right without passing through the master-slave latch 3214 according to the clock. When the comparator outputs "0", the first buffer 3211 is disabled and the pass transistor array 3212 is enabled so that the current position value i is passed to the left through the position value pass, and the master Master-slave latch 3214 is enabled to allow one clock cycle to pass the token to the right position value shifter. In this way, the position value is sequentially transmitted by one clock difference, and the run length can be calculated through the difference between the position values transmitted to the subtractor.

For example, the operation of the RLE based on the actual logic value will be described with reference to FIG. 20. The comparator outputs 1 if the pixel data values are the same and 0 if it is different, which is input to the position value shifter 321. When the first position value shifter receives 1 from the comparator, the token is transmitted to the right position value shifter through the second buffer 3215 regardless of the clock. In addition, since the values inputted to the XOR gate 3213 from the comparator and the master-slave latch are all 1, the fast transistor connected with the position value is disabled so that the value is not connected to the position value pass and the first buffer 3211 is enabled. The position value transmitted from the right side is transmitted to the left side. When the third position value shifter receives 0 from the comparator, the second buffer 3215 is disabled and the token is transmitted to the right position value shifter according to the clock. In addition, since the values inputted from the comparator and the master-slave latch 3214 to the XOR gate 3213 are different from each other, the first buffer 3211 is disabled to transmit the position value received from the right side, and the fast transistor is enabled. The position value is then linked to the position value pass and sent to the left. As such, if the pixel data values are the same, the token is passed to the right by the second buffer 3215 regardless of the clock, and the pixel data values are synchronized to the clock by the master-slave latches in the other position value shifters, and the compared pixels The pixel data compared to the position value of the position value shifter whose data is different is passed by the first buffer of the same position value shifter and transmitted to the latch. In this way, the position values corresponding to the segment boundaries are transmitted one by one according to the clock, and the position values are transmitted to the latch master and the latch slave, and the run length of the RLE is calculated and outputted every clock through the subtractor. The value shown in the comparator output is input to each position value shifter, and the position values 000010, 110000, and 110001 are stored sequentially in the latch master and latch slave according to the clock, and these position values are run through the subtractor. 000010, 101110, 000001 are sequentially outputted.

21 shows a PFC encoder in detail. PFC encoders correspond to data compressors and are used to compute PFC, PPC and TPPC compression algorithms. The PFC encoder can be implemented with only a few gates because there is already an XOR that compares the pixel data by using the comparators used for runlength encoding. That is, XOR comparing current pixel data with next pixel data already exists, so it is implemented with four XOR gates, eight NOR gates, three NAND gates, and one inverter to compare the previous 4 bits of the current pixel data with the previous pixel data. It is possible.

Hereinafter, embodiments of a histogram data control method and apparatus interoperating with the aforementioned data compression algorithm will be described.

The method and apparatus for controlling data compression-linked histogram data according to the present invention obtain a histogram having a "reduced number of gray scale intervals" displayed only through a higher bit group of pixel data according to the characteristics of the above-described compression algorithm, and calculate the histogram of each gray scale interval. Reduce the presentation level to simplify histogram data. The method and apparatus for data compression interworking histogram data control of the present invention can obtain an optimal histogram that is interoperable with the above-described compression algorithm, and can be operated with low hardware complexity. The data traffic and the amount of calculation can be reduced during the image calculation through.

In the conventional histogram, in the case of 8-bit color depth, the frequency of occurrence in the image is detected for each of 256 gray levels from 0 to 255, respectively, and stored as the histogram representation level. In the image information, all pixel data may be concentrated in one gradation section, and thus, in the worst case, a storage space for counting the resolution of an image for each gradation section is required. Therefore, a histogram of an image with mxn resolution at C color depth requires 2 ^C x log ₂ (mxn) bits of memory. Reducing the amount of data in the histogram can reduce the traffic during the movement of the histogram data, simplify the histogram, and reduce the amount of computation to find the necessary information in the histogram. This will be described in detail later in image quality evaluation and data amount comparison (FIG. 23).

Histogram data control method and apparatus for data compression have two steps to simplify histogram, which includes setting a gradation section composed of several successive gradation values and simplifying the expression level of the sum of the frequencies of the corresponding gradation sections. Here, 'frequency' is defined as the number of pixel counts corresponding to each gray level in an image.

The gray scale section setting is simplified by adding up gray scale values having the same high order bits as shown in FIG. The width of the upper bit for grading the gradation interval may be the same as the upper bit group in the above-described partial type compression algorithm of the PPC and PFC and thus may be linked with the aforementioned compression algorithm.

^┏ F (X) ^┐ of ^{'┏ ┐'} is the gray level region as compared to the required mathematical operators, and the general histogram _{^{2 C * ┏ log 2 (mxn}} ) storage space ^┐ bit word for lifting (Ceiling) i (i is a natural number) pieces may reduce the i * ^┏ log ₂ (mxn) effects of storage space required by the amount of memory for obtaining a histogram reduced to i / 2 of the ^{C ┐} bits. The second step is a process of reducing the frequency level of the histogram by limiting the frequency representation step of the histogram obtained in the first step to several steps as shown in FIG. 22 (b). In this process, in determining the histogram frequency level, the amount of memory required to obtain the histogram may be further reduced by clipping the frequency limit of each gray section so as not to be counted above a predetermined value. Memory for computing a histogram for each gray level interval when the clipped to limit the maximum value of the frequency in the count limit (count_limit) is i * ^┏ log ₂ (count_limit) requires a bit ^┐. When the histogram frequency level is limited to j (j is a natural number), the final simplified histogram data size requires i * ^┏ log ₂ (j) ^┐ bits, which has a much smaller amount of data than an ^unsimplified histogram. .

Referring to FIG. 22, the gray level section of 256 steps is simplified to 16 levels, and the frequency level of the histogram is simplified to 5 levels. The method and apparatus for controlling data compression-linked histogram data of the present invention can be applied to a color depth different from the example of FIG. 22, and the simplification of the gradation interval and the histogram frequency level is not limited to 16 and 5 steps, but also to other steps. It is possible. As shown in the horizontal axis of FIG. 22 (a), the gradation interval is simplified from the existing 256 steps to the 16 steps. The yellow semi-transparent graph represents a 256 gray scale section in general, and the red column-shaped graph is a histogram in which the gray scale section is simplified to 16 stages in the present invention. The next step is to simplify the histogram frequency level as shown in Figure 22 (b). In the case of the histogram for each gradation section, each gradation section has a frequency ranging from 0 to resolution, and the complexity of the histogram can be reduced by reducing the frequency level to a few limited steps. In FIG. 22 (b), the pink column is a simplified histogram as shown in FIG. 21 (a). In FIG. 22 (b), the black solid line finally shows the simplified histogram by reducing the frequency level of the histogram. FIG. 22 (b) shows the maximum pixel count of the histogram to 20000 and the level in 5000 count units. Example of dividing by levels.

The method and apparatus for controlling data compression-linked histogram data according to the present invention can increase the resolution and color depth of an image and increase the reduction level of the amount of histogram data as the simplified level is increased, but in this case, the histogram The accuracy of may be lowered. In order to identify an appropriate histogram simplification level, the inventors measured the degradation of accuracy in image processing according to the histogram simplification level through simulation. The simulation was performed using Matlab, and histograms with different simplification levels were applied to eight different images having a 24-bit color depth by applying a clipping level, a number of gradation intervals, and a histogram frequency. Histogram equalization of the images was performed through the simplified histogram, and the degradation of the accuracy of image processing was measured. Histogram equalization applies the most common method of applying the cumulative distribution of histograms to a lookup table (LUT). The degradation of the image quality was compared with the distortion ratio, which is an indicator close to the human visual system (HSV). Comparison was made with the Normalized Size representing the ratio.

The histogram of the present invention is simplified by reducing the gradation interval and the histogram frequency level. When the gradation interval is i and the histogram frequency level is j, the histogram has the size of i * ^┏ log ₂ (j) ^┐ bits. As such, reducing the gradation interval rather than reducing the histogram frequency level can significantly reduce the amount of histogram, which was confirmed in the simulation result shown in FIG. 23 (b). As can be seen from the simulation result of FIG. 23 (a), it can be seen that the image quality deterioration due to the decrease in the histogram frequency level is relatively large and decreases linearly, but the image quality deterioration due to the decrease in the gradation intervals. We can see that it happens very rapidly. However, when the gradation section is 16 or more, the image quality decrease is very small, and when the gradation section decreases, the image quality is greatly reduced. Since the image quality deterioration is not substantially high even at a very high histogram simplification level, it is desirable to determine the histogram simplification level according to the importance of the histogram data size in an application field.

FIG. 24 is a diagram illustrating a histogram generation method in which a gradation interval is reduced by using compressed pixel data in the data compression-linked histogram data control method and apparatus of the present invention.

Referring to FIG. 24, when H (Y) is defined as the frequency of the reduced grayscale section Y, and h (y) is defined as the frequency of the histogram grayscale y between the grayscale interval Y and Y + 1, H (Y) is this value. The sum of them. For example, assuming that 'C' is the color depth of an image, and the gradation interval is reduced to i, the relationship between the frequency H (Y) for each gradation section of the histogram for each gradation interval and the frequency for each gradation h (y) for the gradation of the histogram is It may be expressed as Equation 5 below.

The mathematical expression is shown in Equation 5, and a method of obtaining a histogram for each gray level using compressed pixel data is shown in FIG. In FIG. 25, compressed pixel data represents an example of pixel data compressed with the aforementioned partial pixel type of PPC, TPPC, and PFC and fixed run length of PFC. The data format includes a flag and a code like m-1st data.In case of m-th pixel data with a flag of 0 and a code of 1, three pixel data with high bit A and low bit a are compressed. Therefore, the pixel count of H (A) corresponding to A, the upper bit group of the histogram memory, is increased by three. m + 1th pixel data is H and B pixel count corresponding to B, which is the upper bit group, because one pixel data with B and lower bit is compressed. Increment by 1 m + 2nd pixel data is partial type compressed data whose flag is '1', and since m + 1st pixel data and lower bits of two pixel data having the same upper bit group are stored, the pixel count of H (B) is counted. Increase by 2. As described above, the histogram generation method having the reduced gray scale interval can be linked with the compression memory 4, and the flag and the code are generated during the compression process of the compression device 100, so that the compression is not necessary without a separate memory access. The intermediate result of the process can generate a histogram with a simplified gradation interval.

The histogram generation method can reduce the access rate of the histogram arithmetic memory by the compression rate + α, thereby reducing the power consumption required for memory access. This allows the number of pixel data having the same upper bit group to be consecutively counted at one time through the compression process, and increases the access rate at the time of generating the histogram at a time. In addition, when compressed pixel data is continuously stored as a partial type, an access rate as much as α can be reduced. More detailed description of the α indicates that when the pixel count of the compressed pixel data is obtained, the upper bits of the previous pixel data are the same. Therefore, since the histogram memory does not need to be read again, the cumulative operation is performed on the pixel count operation value of the previous pixel, and data is written only at the end, thereby reducing the access rate of the histogram memory. In the case where the histogram data with the reduced gradation interval generated through this process is to be read from the histogram arithmetic memory, there is no decrease in the access rate. The amount of data for transmitting histogram information with the device used can be reduced.

In FIG. 24, compressed pixel data has been described as an example to describe interlocking with a compression algorithm. However, the data compression interlocking histogram data control apparatus of the present invention interoperates with the data compression apparatus 100 to store intermediate encoding data. It uses the histogram to compute memory so you don't access it separately.

Compressed data format is the same as m-1, and in case of m-th flag with 0 and code 1, the upper bit group of histogram memory The pixel count of H (A) corresponding to A is increased by three. In m + 1, since the flag and the code are all 0, one pixel having one upper bit B and one lower bit b is compressed, so that the pixel count of H (B) corresponding to the upper bit group B is increased by one. m + 2th is a partial type when the flag is 1, and since the lower bit of two pixels having the same m + 1th and upper bit group are stored, the pixel count of H (B) is increased by 2. The operation of the histogram with reduced gray scale can be linked with the compressed image memory, and the flags and codes are generated during the compression process in the compression device, so the gray scale interval can be simplified through intermediate results of the compression device without the need for separate memory access. You can create a histogram.

25 is a block diagram showing an apparatus for controlling data compression interlocking histogram data according to the present invention.

Referring to FIG. 25, the memory 4 is accessed by the histogram representation level reduction apparatus 7 and the first memory region 41 which is accessed by the histogram calculation apparatus 8 for each gradation interval, and by the data compression and decompression apparatus. A second memory area 42.

The data compression device 100 compresses pixel data and stores the pixel data in the second memory area 42 of the memory 4. The data reconstruction device 200 reads the compressed pixel data from the second memory area 42 of the memory 4 and reconstructs the pixel data according to the compression algorithm selected by the adaptive compression mode prediction device 5.

The data compression device 100 supplies encoding data including a code and a flag generated in the compression process to the histogram computing device 8 for each gray level section as pixel information having the same high order bit. The histogram operation apparatus 8 for each gray level section receives information of pixel data having the same higher bit in succession through the upper bits of the code, the flag, and the pixel data to be compressed, which are encoded data generated during the compression process. Create a star histogram. The histogram calculation apparatus 8 for each gray level section can determine the corresponding gray level through the upper bits of the pixel data to be compressed, and use it as an address to access the first memory area 41 and increase the frequency through the code and the flag. While generating a histogram for each gradation section in which the gradation section is simplified, the histogram is stored in the first memory 41. The histogram for each gradation section stored in the first memory 41 is finally converted into a simplified histogram by the histogram expression level reduction device 7 and then transferred to an image processing unit for use in various image processing. The histogram representation level reduction device 7 generates a simplified histogram through the case comparison of the histogram for each gradation section stored in the first memory 41. The histogram's frequency can have a frequency from zero to the maximum image resolution, and has a power level as high as the resolution. The histogram representation level reduction apparatus 7 limits the maximum frequency of the histogram to a predetermined clipping level lower than the maximum image resolution, and reduces the frequency level of the histogram by reducing the frequency from 0 to the maximum frequency in a predetermined step. Since the simplification of the histogram frequency level is calculated based on the histogram obtained through the histogram calculating device 8 for each gradation section, the memory capacity of the first memory area 41 cannot be reduced, but the amount of data transmitted to the image processing device is greatly increased. Can be reduced.

Fig. 26 is a block diagram showing in detail the histogram computing device 8 for each gray scale section. Referring to FIG. 26, pixel data of a pixel 1 position among pixel data compressed by the data compression apparatus 100 is pixel data necessarily stored in full bit. Therefore, the histogram operation apparatus 8 for each gray scale interval analyzes an upper bit group from the pixel data of Pixel 1 to grasp the gray scale interval of the compressed pixel data, and accesses the first memory 41 using this as a memory address. In FIG. 26, a part represented by the multiplexer in the first memory 41 represents a decoder that performs data input / output of the histogram.

The histogram computing device 8 for each gray level section includes first and second multiplexers 81 and 82, an adder 83, and the like. The first multiplexer 81 selects any one of the frequency of the corresponding gradation section of the histogram input from the memory 41 according to the flag from the data compression apparatus 100 and the result of the previous frequency operation input from the adder 83. It selects and inputs into the adder 83. If the flag is 1, since the currently compressed pixel data is compressed in the partial types of PPC, TPPC, and PFC, the gradation section including the same high bit as the previous pixel data is the same, and the next pixel data is read again from the memory 41. Reuse previous calculation results without the need. The second multiplexer 82 selects an increase value for increasing the frequency of the corresponding gray level input through the first multiplexer 81 according to a flag and a code input from the data input device 100. In this case, the code and the flag are used as the selection signal of the second multiplexer 82, and the second multiplexer 82 selects one of three values of 1, 2, and 3 according to the selection signal as shown in Table 1 below. The adder 83 receives the frequency and the increase value of the corresponding gradation intervals input from the first and second multiplexers 81 and 82, and adds the sum values and stores the sum values in the memory 41.

flag code number One X 2 0
One 3 0 One

As described above, when the pixel data is compressed and stored in the partial type, the histogram calculation apparatus 8 includes the same upper bits as the previous pixel data, and thus determines that the current pixel data is the same as the grayscale interval. It is possible to reduce the number of memory accesses by recursive operation results without having to read pixel data from one memory 41. The histogram computing device 8 for each gray scale section increases the frequency of the gray scale section through a flag and a code generated during the compression process. This process is performed through the multiplexers 81 and 82 and the adder 83.

In the data compression interlocking histogram data control apparatus of the present invention, as shown in FIGS. 25 and 26, a code and a flag generated in the compression process are used to generate the number of iterations of a series of pixel data having the same gray scale interval using the linkage with the data compression apparatus 100. The number of one to three pixel counts can be processed by one memory access and operation, which greatly reduces the number of memory accesses. The conventional histogram calculating apparatus has a high hardware complexity by processing the counter in parallel with the counter for each gray scale section, whereas the histogram computing device 8 for each gray scale section of the present invention is characterized by the characteristics of image data sequentially input as memory data. Accordingly, the adder 83 may be shared to sequentially process histogram operations, thereby reducing hardware complexity.

In the case of the lookup table for pixel data operation processing in conjunction with the data compression scheme, the amount of hardware can be reduced by dividing the upper bit group and the lower bit group and performing the operation using the same lookup table as in the aforementioned compression algorithm.

The data compression interlocked lookup table minimizes the error lookup table to compensate for the error to minimize the amount of errors that can occur when the function of the lookup table is non-linear, thereby minimizing errors while reducing hardware complexity. We propose a lookup table design method.

FIG. 27 is a diagram illustrating a partitioned bit LUT ROM 9 interoperable with the memory 42.

Referring to FIG. 27, the lookup table ROM count (LUT ROM Count, LUTC), that is, the lookup table size is changed exponentially according to the input bit width as shown in Equation 6, thereby reducing the complexity of the lookup table. In order to reduce the bit width of the input data, it is effective. In order to reduce the bit width of the input data of the lookup table, a method of partitioning the pixel data and sharing the lookup table is required. The lookup table that performs the operation on the divided pixel data by reducing the input bit width will be defined as a partitioned bit LUT.

LUTC = 2 ^{input bit width} × output bit width

The aforementioned compression algorithms compress pixel data by dividing the pixel data into upper bit groups and lower bit groups. Therefore, the pixel data stored in the memory 42 is composed of a combination of an upper bit group and a lower bit group. Since the partition bit lookup table ROM 9 uses pixel data divided into an upper bit group and a lower bit group as an input, a partitioning level of the input pixel data is used to store the compressed pixel data stored in the memory 42 described above. When designing in consideration of division, it can be linked. Through this interworking, the lookup table operation can be performed without any reconstruction process, thereby reducing the data rate between modules and reducing the number of operations of the redundant upper bit group, thereby reducing the overall operation amount. 21 is a diagram illustrating an interworking scheme through pixel division between the memory 42 and the divided bit lookup table. As shown in FIG. 21, data transmission between the two modules 9 and 42 is performed through compressed pixel data including divided pixel data. Thus, the above-described compression algorithm and the image processing lookup table through the divided bit lookup table may be linked to each other.

The split bit lookup table ROM 9 receives pixel data from the memory 42 into an upper bit group X _upper and a lower bit group X _lower from the memory 42 to perform an operation. When the pixel data having the m bit color depth is divided in the nth bit, the divided pixel data is expressed by Equation 7.

X _upper = X [m-1: n]

X _lower = X [n-1: 0]

X = X _upper × 2 ⁿ + X _lower

The relationship between the pixel data X and the divided pixel data input to the split bit lookup table ROM 9 is expressed by Equation 7, and the function f (X) of the original partitioned lookup table (Original LUT) is linear. In this case, Equation 8 below is established.

f (X) = f (X _upper × 2 ⁿ + X _lower ) = f (X _upper × 2 ⁿ ) + f (X _lower ) (4)

The partitioned bit lookup table takes a partitioned bit as an input and therefore has a function different from that of the full bit lookup table before being partitioned. If the X _upper and X _lower inputs all use the same lookup table and are computed to use a smaller lookup table, and the X _upper and X _lower inputs are collectively referred to as X _partitioned , then the split bit lookup table function is called f _pbl (X _partitioned ), the more f _fbl (X _partitioned ) is similar to the function f (X) of the full-bit lookup table, the fewer errors, and f (X _upper × Since 2 ⁿ ) is similar to f (X) with the upper bits as input, rather than f (X _lower ), it is used as a function of f _pbl (X _partitioned ) with split bits as input. If f (X) is linear, f _pbl (X _partitioned ) is also linear, and satisfies Equations 9 and 10 as follows.

f _pbl (X _partitioned ) = f (X _partitioned × 2 ⁿ )

f (X _lower ) = f _pbl (X _lower ) / 2 ⁿ

 Therefore, when Equations 9 and 10 are substituted into Equation 8, it can be seen that a linear function as shown in Equation 11 can be operated without error even with a split bit lookup table. The size of the lookup table ROM 9 can be reduced.

f (X) = f _pbl (X _upper ) + f _pbl (X _lower ) / 2 ⁿ (7)

In addition to the linear functions described above, an error may occur when a non-linear function is operated as described above. The error generated in this way can be compensated with a separate error lookup table to be operated without errors in the final result, and this operation process can be defined as in Equation 12 below. The size of the error lookup table is determined according to the range of errors that occur and is defined as in Equation 13.

f (X) = f _pbl (X _upper ) + f _pbl (X _lower ) / 2 ⁿ + f _error (X)

LUTC _error = 2 ^{color depth} × ^┌ log ₂ (Error Range) ^┐

The size of the error lookup table can vary more precisely depending on the error range, depending on the number of quantization steps representing the error range if the step size is constant, and the operation error through the split bit lookup table should be reduced to reduce the overall lookup table size. Can be reduced in size. This will be described with reference to FIG. 28.

The operation result f _pbl (X _lower ) of the _lower bit group is summed with the operation result of the upper bit group. In this case, the number of dividing the lower bit group is defined as a scale factor. In the case of linear functions, if the 1/2 ⁿ scale factor is applied as in Equation 7, the operation can be performed without error, but in the case of nonlinear functions, the same scale factor as the linear function is applied. An error occurs and the error must be compensated in the same manner as in Equation 8.

As shown in FIG. 28 (a), in the case of the linear function, the step size of the _upper bit group operation result f _pbl (X _upper ) is the same in the entire gray scale interval, and the operation result of the lower bit group applying the same scale factor f _pbl (X _lower ) / ³ is equal to the dynamic range of ³ . It can be seen that the function of f _pbl (X _lower ) / 2 ³ increases linearly and can be combined with f _pbl (X _upper ) to perform the same operation as the function of the full bit lookup table. As described above, a scale factor that is equally applied to all sections is defined as a global scale factor.

In the case of the nonlinear function as shown in FIG. 28 (b), the step size of f _pbl (X _upper ) may be different for each section. When combined with f _pbl (X _lower ) / 2 ³ as a result of calculation of the lower bit group to which the global scale factor is applied, such as a linear function, it may show a big difference from the characteristic curve of the full bit lookup table. This difference should be compensated for using the error lookup table.

As shown in FIG. 28 (c), when the scale factor is differently applied to each gray scale interval so that the step size of f _pbl (X _upper ) and the dynamic range of _lower f _pbl (X _lower ) / 2 ^k are similar, The difference from the characteristic curve of the bit lookup table becomes small. As described above, a scale factor that is applied differently for each gradation interval is defined as a local scale factor. The local scale factor is determined by the upper bit group operation result of the interval, the step size of f _pbl (X _upper ) and the dynamic range of the _lower bit group operation result f _pbl (X _lower ). Is equal to the dynamic range of the split bit lookup table, and the step size of the result of the upper bit group operation of the interval becomes | f _pbl (X _upper +1)-f _pbl (X _upper ) |, so that DR (g (x) ) Is the dynamic range of the function g (x), the local scale factor (SF _local ) can be expressed as shown in Equation 14.

SF _local = | f _pbl (X _upper +1)-f _pbl (X _upper ) | / DR (f _pbl (X _partitioned ))

In this case, a different scale factor for dividing f _pbl (X _lower ) according to the step size of f _pbl (X _upper ) for each section having the same upper bit group value becomes a previously defined local scale factor. As described above, it can be confirmed from FIG. 28C that the calculation result of the divided bit lookup table to which the local scale factor is applied is very small from the curve of the original lookup table.

The local scale factor adjusts the step size of the interval divided by X _upper equally and the dynamic range of f _pbl (X _lower ). Therefore, it can be obtained through the step size of the interval and the dynamic range of the function f _pbl (X _partitioned ) of the _partitioned bit lookup table. When step_size (f _pbl (X _upper )) is a step size of f _pbl (X _upper ), it is arranged as in Equation (15). In addition, when DR (g (x)) is defined as the dynamic range of the function g (x), the optimal local scale factor is expressed by Equation 16 below.

step_size (f _pbl (X _upper )) = | f _pbl (X _upper )-f _pbl (X _{upper + 1} ) |

This local scale factor is changed to 2 ^k for integer k for efficiency in hardware implementation. In this case, the reduction rate of the error range is reduced by 10%, but the amount of scale factor lookup table that stores the scale factor can be greatly reduced, and the operation can be efficiently performed through the shifter. This is bigger.

By making a local scale factor of 2 ^k and storing only k values in the form of a lookup table, scaling can be performed to suit the rate of change of the interval using a shifter. Equations 17 and 18 are equations for calculating a scale factor k and a ROM count of a lookup table for storing the scale factor.

k = ^┌ log ₂ (SF _local ) ^┐

LUTC _{scale factor} = 2 ^{upper bit width} × ^┌ log ₂ (color depth) ^┐

As shown in FIG. 28, the characteristic curve of the operation result of the split bit lookup table obtained by scaling the operation result of the lower bit group by applying a local scale factor and adding the operation result of the upper bit group is shown in FIG. 28. It is very similar to the characteristic curve, which minimizes the error.

Error range LUTCerror Global Scale Factor Figure 28 (b) -30 to 48 1792 Local Scale Factor Figure 28 (c) -9 to 24 1536

Table 2 shows the error occurrence range of the lookup table according to the application method of the two scale factors and the minimum error lookup table count to compensate for the error. When the local scale factor is applied, the error range is reduced to 1/2 or less, and the number of error lookup tables (LUT error) is also reduced by 14% compared with the global scale factor.

According to the present invention, the size of the lookup table ROM 9 is reduced by dividing the input pixel data into upper bit groups and lower bit groups, and sharing the same divided bit lookup table. In addition, the present invention minimizes an error that may occur during nonlinear function calculation by applying a local scale factor, and thus may be operated in the same manner without error as a calculation result of a full bit lookup table through error compensation using a small amount of error lookup table. Do.

Equation 19 is a summary by applying the above to Equation 12, and the operation process is shown in FIG.

f (X) = f _pbl (X _upper ) + f _pbl (X _lower ) / 2 ^k + f _{error_reduced} (X)

Referring to FIG. 29, the divided pixel data is divided into X _upper and X _lower and calculated through the divided bit lookup table 9, respectively. At this time, the function of the split bit lookup table 9 is equal to f _pbl (X _partitioned ). The result of the calculation of X _lower is to apply the local scale factor, which is the same as the operation of the second term in Equation 15. To this end, k, which determines a scale factor suitable for a corresponding interval through the scale factor lookup table 10, is input to the shifter 11 to scale by 1/2 ^k to f _pbl (X _lower ), which is a result of the lower bit group operation. Shift by k bits. k is a value previously calculated by the method described above with reference to FIG. 28 and stored in the scale factor lookup table 10. The scale factor lookup table 10 outputs the k value of the interval using the gray scale section as an address through X _upper . The shifter 11 uses the scale factor k input from the scale factor lookup table 10 and f _pbl (X _lower ) input from the split bit lookup table 9 to calculate the result f _pbl (X _lower ) / 2 ^k. Occurs. The error lookup table 12 receives pixel data X including X _upper and X _lower and outputs a function f _{error_reduced} (X) for compensating for an error. The lookup table arithmetic result adder 13 is the result of the operation of the scaled lower bit group f _pbl (X _lower ) / 2 ^k , the upper bit group operation result f _pbl (X _upper ), and the function f of the error lookup table 12. By adding _{error_reduced} (X) to generate the same operation result as f (X) of the existing full bit lookup table, the overall lookup table ROM count can be reduced.

The above-described compression algorithm of pixel data is a partial pixel type compression that divides pixel data into upper bit groups and lower bit groups to perform compression, and includes two divided pixel data and flags. The present invention can determine the combination of the two divided pixel data through the flag, and can control the operation of the divided bit lookup table ROM 9.

30 is a block diagram schematically illustrating a split bit lookup table apparatus according to another embodiment of the present invention.

A detailed structure will be described based on the PPC in the compression algorithm of the present invention which performs compression by partitioning pixel data into upper bit groups and lower bit groups. The compressed data format of FIG. 30 is composed of two divided pixel data and flags, and the divided bit lookup table apparatus of FIG. 30 includes a partitioned bit aligner 15 and a latch 14 in addition to the circuit configuration of FIG. 29. And the like.

The compressed pixel data includes pixel data in which the upper bit group and the lower bit group are combined by the aforementioned compression algorithms, and pixel data in which the lower bit group and the lower bit group of the next pixel data are combined. In order to distinguish the types of the pixel data, a flag is used for the least significant 1 bit of the compressed pixel data.

The split bit alignment unit 15 detects the flag '0' of the m-th compressed data of FIG. 30 and determines the compressed data as uncompressed type as compressed data in which the upper bit group and the lower bit group are combined, and thus the full bit pixel data. The error lookup table 12 is supplied in a format. The division bit alignment unit 15 divides the upper bit group and the lower bit group of the m-th compressed data and sequentially supplies them to the division bit lookup table 9. In addition, the division bit alignment unit 15 determines that the compressed data having the flag '1' is compressed data such that the lower bit group and the lower bit group are combined, such as the m + 1st compressed data, and thus the upper bit of the m th compressed data previously stored. The group and the lower bit group of the m + 1 th compressed data are combined and supplied to the error lookup table 12 as a full bit pixel data type.

The partition bit lookup table 9 sequentially calculates partition pixel data input from the partition bit alignment unit 15. The partition bit lookup table 9 calculates an upper bit group, stores the result in the latch 14, and then calculates a lower bit group. Store the calculation results so that they can be summed. Since the operations of the error lookup table 12, the scale factor lookup table 10, the shifter 11, and the lookup table calculation result adder 13 are substantially the same as those of the above-described embodiment of FIG. 28, a detailed description thereof is omitted. do.

Accordingly, the divided bit lookup table may be calculated on the compressed pixel data of the divided bit alignment unit 15 and the latch 14 without a separate pixel data decompression process. The memory 42 and the partition bit lookup table 9 are interlocked through the division method of pixel data by the compression algorithm described above. Therefore, determining the pixel division level suitable for this linkage is important for the efficiency of linkage. The size of the split bit lookup table is smaller as the input bit width is smaller. In the case of dividing the pixel data into several divided pixel data, the smaller the partition, the smaller the size of the divided bit lookup table. However, the error increases rapidly, resulting in an increase in the overall lookup table, and the operation is complicated. Splitting into groups is effective.

The error that occurs in the split bit lookup table operation increases as the size of the upper bit group decreases. FIG. 31A illustrates a case in which a lookup table that calculates a Sine, Cosine, X1 / 2, X2, Gaussian, and Exponential function is applied to an error compensation scheme using a split bit lookup table 9 and an error lookup table 12. This graph shows the average of the lookup table size according to the partitioning level. FIG. 31B is a graph showing an expected compression ratio of an image according to the same division level. The size of the split bit lookup table 9 is represented by Equation 6, the size of the error lookup table 12 is represented by Equation 13, and the size of the scale factor lookup table 10 is equal to Equation 18.

As can be seen in FIG. 31 (a), applying the global scale factor does not significantly reduce the error range as shown in FIG. 28, and thus there is no significant difference in the amount of the entire lookup table compared to the operation calculated only by the result of the upper bit group. In the case of applying the scale factor, it can be seen that the overall lookup table amount can be greatly reduced due to the reduction of the error range. It was confirmed that the lookup table ROM count (LUTC) is the lowest when the division level of the upper bit group is 4 bits, that is, when the pixel data is divided into 1/2. As shown in (b) of FIG. 31, when the partition level of the upper bit group is 4 bits, the compression rate of the compressed data stored in the memory 4 is also the highest, so that the split bit lookup table 9 and the memory 4 both have pixel data 1/1. Dividing by 2 yields the highest memory capacity savings. In addition, when the pixel data is divided into 1/2, the size of the upper bit group is the same as the size of the lower bit group, so that an additional operation such as extending the bit width separately during the lookup table and compression is unnecessary.

The above-described data compression and decompression device and the partitioned bit lookup table device and method can be linked based on common pixel data partitioning, and the partitioned bit lookup table device and method are in the form of compressed pixel data without passing through the decompression device 200. Operation is possible. Through this interlocking structure, the lookup table operation through compressed pixel data can be reduced, and the data access rate between modules can be reduced, and the amount of calculation through the lookup table is reduced by eliminating redundant upper bit group operations, thereby reducing the overall power consumption. Can be reduced.

32 illustrates a split bit lookup table apparatus according to another embodiment of the present invention.

Referring to FIG. 32, the split bit lookup table apparatus includes a split bit sorter 15, an error lookup table 12, a split bit lookup table 9, a lookup table operation result adder 13, and the like.

The divided bit aligner 15 receives the compressed pixel data from the memory 42 to generate the full pixel data and the divided pixel data, and supplies them to the error lookup table 12 and the divided bit lookup table 9, respectively. In detail, the division bit alignment unit 15 determines the compressed storage form of the pixel data through the flag of the pixel data input from the memory 42. If the flag is 0, partial pixel 1 of the pixel data is the upper bit group and partial pixel 2 is the lower bit group. On the other hand, if the flag is 1, partial pixel 1 and partial pixel 2 are both lower bit groups. The division bit alignment unit 15 stores the upper bit group in the latch 151 when the flag is zero. When the pixel data without the upper bit group is input, that is, when the pixel data having the flag 1 is input, the division bit alignment unit 15 stores the upper bit group stored in the latch 12 through the multiplexer 152. The input lower bit group is combined into full pixel data and supplied to the error lookup table 12. The multiplexer 152 sequentially outputs partitioned pixels 1 and 2 when pixel data having a flag of 1 is input.

The split bit lookup table 9 receives the divided pixel data and calculates the split bit lookup table by using a preset bit lookup table function, and the error lookup table 12 receives the full pixel data and calculates a preset error correction function. The lookup table operation result adder 13 adds the operation results of the split bit lookup table 9 and the error lookup table 12 to generate a final result.

The lookup table calculation result adder 13 adds the calculation results of the error lookup table 12 and the split bit lookup table 9 to generate a final result. The lookup table operation result adder 13 includes a multiplexer 132, a shifter 133, a latch 134, first and second adders 135 and 136, and the like. The multiplexer 132 switches the transmission paths of the upper bit group and the lower bit group calculated in the split bit lookup table 9 in response to the flag of the pixel data. When the operation result of the upper bit group is input from the split bit lookup table 9, the multiplexer 132 supplies the operation result of the upper bit group to the latch 134. On the other hand, when the operation result of the lower bit group is input from the split bit lookup table 9, the multiplexer 132 shifts the operation result of the lower bit group so that the scale factor is applied to the operation result of the lower bit group. 133). The first adder 135 sums the operation result of the lower bit group to which the scale factor is applied and the operation result of the upper bit group input from the latch 134. The shifter 133 shifts the scale factor prestored in the scale factor lookup table 131 using the upper bit group of the full pixel data to the right by the scale factor for each input to the right. Apply the scale factor to the group's result. The operation result of the generated upper bit group, the operation result of the lower bit group to which the scale factor is applied, and the operation result of the error lookup table are added by the second adder 136 to the final lookup table operation result.

The LCD generates a motion blur due to the hold type driving characteristic. Motion blur is the leading cause of image degradation when displaying video on the LCD. As a method for improving the motion blur problem, a frame rate enhancement method using motion estimation and motion compensation (ME / MC) is effective. The frame rate enhancement method increases the frame rate by generating a compensated interpolated image frame by estimating motion between before and after frames and inserting the interpolated image frame between before and after frames. Pel-recursive and Block Matching Algorithm (BMA) are known as the existing moving methods. However, due to the huge amount of computation and high data access rate, power consumption is large and inefficient.

Another embodiment of the present invention can effectively remove motion blur by reducing hardware complexity and cost by reducing the amount of computation required for motion prediction in conjunction with the aforementioned data compression method. Hereinafter, a method of performing motion prediction in conjunction with a data compression method will be defined as a compressed BMA motion estimation method.

The CBMA motion estimation method maximizes the efficiency of computation required for motion prediction (ME) by linking existing computation cost reduction schemes and memory compression. The CBMA motion estimation method compares blocks based on reduced pixel precision based on the upper reference bits of the compressed block as shown in FIG. 33. In the CBMA motion estimation method, a motion vector operation is performed by compressing and restoring pixel data in a pixel data block unit. When a size of a compressed block is determined as m × m, a subpixel of m pixel unit is determined through a sub-sample of m pixel distance. Calculate the motion vector. The effect of the CBMA motion estimation method is that the operation cost can be effectively extended to PSNR similar to the existing FBMA due to the drastically reducing the computational cost, and the memory access rate and hardware complexity are reduced.

In the CBMA motion estimation method, an operation cost saving effect through memory compression can be seen in FIG. 33. When the original pixel width is 8 bits, the reduced pixel width in the present invention is 4 bits or less as a result of memory compression using PPC or TPPC. Accordingly, the present invention can reduce the computational cost through memory data compression, reduce the overall memory access rate, and reduce the computational cost and complexity in the hardware with the reduced comparison pixel bits.

In the CBMA motion estimation method, subsampling is performed as shown in FIG. In the subsampling, the amount of calculation is reduced in proportion to the square of the sampling distance of the macro block (MB) size, and the PSNR decrease is less than the operation cost reduction when the sampling distance is 2 pixels. There is almost no change in PSNR reduction according to the size of the macro block (MB).

In the CBMA motion estimation method, as shown in FIG. 36, a compressed macro block (m × m, m is a positive integer of 2 or more, m = 2 in the case of FIG. Xn and n are positive integers larger than m, grouping at n = 16 in the case of FIG. 36, so that the accuracy of the motion vector can be improved. This method solves the noise problem due to the small macro block size, thereby increasing the accuracy of the motion vector (MV) and reducing the computational cost compared to the small macro block size.

In order to perform an auxiliary motion estimation operation for improving the accuracy of the motion vector of the CBMA motion estimation method, after calculating the motion vector of the m × m macroblock MB as shown in FIG. 37, the auxiliary motion vector ( Auxilliary MV) is calculated. The auxiliary motion vector is used for the improvement of the motion vector (MV) based on the surrounding motion vector at the time of the estimated estimation operation. When the motion vector is improved, it can be used for determining whether to expand the frame rate and for solving an overlapped region in an empty region in the before and after frames. The auxiliary motion compensation of the CBMA motion estimation method can improve the low reliability of motion compensation by coping with the empty pixel data region generated by interpolation through BMA, and calculate operation cost considering the temporal dependency of motion vector. Can reduce the cost.

 FIG. 37 illustrates a method of calculating a motion vector in conjunction with the aforementioned data compression method based on the contents described with reference to FIGS. 33 to 36. The input frame data is compressed by the memory data compression apparatus and stored in the compressed frame memory, and simultaneously input to the CBMA motion estimation apparatus as current frame data. The previous frame data of the compressed form previously stored in the compressed frame memory is also input to the CBMA motion estimation apparatus to calculate a motion vector through the aforementioned subsampling and pixel precision reduction. Then, the macroblock grouping described in FIG. 35 is performed through this motion vector to calculate a highly accurate motion vector, and the auxiliary motion operation described in FIG. 36 further improves the accuracy of the motion vector to finally generate the motion vector. do.

The data compression and decompression apparatus and method of the present invention can be applied to data compression and decompression of not only LCD but also other flat panel display devices such as FED, PDP and OLED.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a diagram schematically illustrating a compression and decompression principle of a PPC algorithm according to an embodiment of the present invention.

2 is a lower bit truncated image, (a) an original image (b) is a lower 1 bit trimmed image, (c) a lower 2 bit truncated image, and (d) is a 1 or 2 bit truncated image.

3 is a diagram schematically illustrating the compression and decompression principle of the TPPC algorithm according to an embodiment of the present invention.

4 is a diagram schematically illustrating a compression and decompression principle of a fixed run length type in a PFC algorithm according to an embodiment of the present invention.

5 is a diagram schematically illustrating a compression and decompression principle using run length encoding according to an embodiment of the present invention.

6 is a diagram illustrating a data storage format in each of PPC, TPPC, PFC, and RLE according to an embodiment of the present invention.

7 is a block diagram illustrating a data compression and decompression device of a flat panel display device according to an exemplary embodiment of the present invention.

8 is a block diagram showing in detail the data compression apparatus shown in FIG.

9 is a view for explaining the change in the compression pattern and compression ratio according to the comparison range in the partial type compression method.

FIG. 10 is a block diagram illustrating in detail the apparatus for restoring data shown in FIG. 7.

FIG. 11 is a detailed block diagram illustrating an adaptive compression mode prediction apparatus illustrated in FIG. 7.

12 is a diagram illustrating an example of a video image sequence.

FIG. 13 is a graph showing a compression ratio in each of the compression algorithms when data is compressed by each of the compression algorithms of the present invention in the moving image as shown in FIG. 12.

14 is a diagram illustrating a correlation between an image slope and a compression ratio.

15 is a diagram illustrating a result of obtaining a compression ratio according to each algorithm of an experimental image.

16 is a diagram illustrating a compression ratio according to an image state.

17 is a diagram illustrating a result of comparing the compression ratios of the PPC algorithm, the TPPC algorithm, the PFC algorithm, and the existing lossless compression algorithm with respect to the experimental images.

18 is a diagram illustrating experimental results in which the computation speeds of the PPC algorithm, the TPPC algorithm, the PFC algorithm, and the RLE algorithm are compared.

19 is a circuit diagram showing in detail the position value shifter shown in FIG.

FIG. 20 is a diagram illustrating an example of implementing the RLE encoder illustrated in FIG. 8 through the position value shifter illustrated in FIG. 19.

21 is a circuit diagram illustrating a PFC encoder in detail.

22 is a graph illustrating a histogram simplification principle of a method and apparatus for controlling data compression interlocking histogram data according to an embodiment of the present invention.

FIG. 23 is a graph illustrating image quality evaluation and data amount comparison showing a histogram simplification effect in a method and apparatus for controlling data compression-linked histogram data according to an embodiment of the present invention.

FIG. 24 is a diagram illustrating a histogram calculation scheme in which a gradation interval is reduced by using compressed pixel data in a data compression interlocked histogram data control method and apparatus according to an exemplary embodiment of the present invention.

25 is a block diagram illustrating an apparatus for controlling data compression interlocking histogram data according to an embodiment of the present invention.

FIG. 26 is a block diagram illustrating in detail a histogram calculating apparatus for each gray level shown in FIG. 25.

FIG. 27 is a diagram illustrating a split bit lookup table that can be linked with a memory.

28 is a diagram illustrating a scale factor application according to an error change.

29 is a block diagram illustrating a split bit lookup table apparatus according to an embodiment of the present invention.

30 is a block diagram schematically illustrating a split bit lookup table apparatus according to another embodiment of the present invention.

FIG. 31 is a diagram of an experimental result for verifying the effect of the split bit lookup table apparatus of FIG. 30.

32 is a block diagram illustrating a split bit lookup table apparatus according to another embodiment of the present invention.

33 to 37 are diagrams for describing a data compression coordinated motion estimation algorithm.

Description of the Related Art

1, 7: Buffer 2: Comparator

3: encoder 4: memory

5: adaptive compression mode prediction device 6: decoder

421: Partial Pixel Encoder 422: Full Pixel Encoder

423: position value shifter 424: subtractor

43: Pass Transistor Array

Claims (18)

comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; A PPC compression algorithm that generates a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and outputs the flag instead of the upper bits, and some of the remaining lower bits except for the same upper bits in the pixel data PFC to remove the higher bits and to selectively remove the higher bits or to compress the same pixel data within a continuous constant pixel data length by further removing a and partially sharing the compression scheme with the TPPC compression algorithm, the PPC, and the TPPC compression algorithm that generate the flag. PPC, TPPC & PFC encoding step of selecting any one of the compression algorithm according to the compression ratio of each compression algorithm of the previous frame and the average value of the slope difference between the pixel data to output the compressed pixel data; An RLE encoding step of outputting compressed pixel data by removing the pixel data consecutive in run length encoding (RLE); Selecting one of the PPC, TPPC & PFC encoding output and the RLE encoding output according to a compression algorithm selected based on the compression ratio and the slope between the pixel data and storing in the memory; And Reconstructing the compressed data by selecting a reconstruction algorithm according to a slope between the compression rate and the pixel data, The PFC algorithm is a partial type that removes the upper bits and generates the flag based on the identity of the upper bits, when the contiguous pixel data is the same as the full bit of any one of the pixel data. Compressing the pixel data by using a full bit type for generating a code indicating a number of times, an uncompressed type for bypassing each of the pixel data to full bit when the consecutive pixel data are different, The compressed data stored in the memory includes a lower bit group in which lower bits of pixel data having the same upper bits are collected. The method of claim 1, The PPC encoding step, If the upper bits of the n th and n + 1 th pixel data are the same as the upper bits of the previous pixel data, the lower bits of the n th pixel data and the lower bits of the n + 1 th pixel data indicate the identity of the upper bits. Storing the flag of the first logical value as the least significant bit in the memory as compressed data; And If the upper bits of the previous pixel data and the upper bits of the n-th pixel data are different, the flag of the second logical value indicating that the upper bits are different together with all the lower lower bits of the n-th pixel data is changed to the least significant bit. And storing the data in the memory as compressed data. The method of claim 2, The PFC encoding step, If the upper bits of the n-th and n + 1th pixel data are the same as the upper bits of the previous pixel data, the lower bits of the n-th pixel data and the lower bits of the n + 1-th pixel data of the upper bits Storing in the memory as the compressed data with the flag of a first logical value indicating identity; Assigning a flag to the second logical value indicating that the upper bits are different if the upper bits of the previous pixel data and the upper bits of the n-th pixel data are different; And if the flag has a second logic value and the lower whole bits of the n th pixel data, the n + 1 pixel data, and the n + 2 th pixel data are the same, the upper lower whole bits of the n th pixel data and the storing a code of a first logic value indicating that n + 1 pixel data and the n + 2th pixel data are the same as the compressed data in the memory with the flag of the second logic value; And If the flag has a second logical value and the upper lower whole bits of the n th pixel data, the n + 1 th pixel data and the n + 2 th pixel data are different, the upper lower whole bits of the n th pixel data; Storing said code of a second logic value indicating that said n + 1st pixel data and said n + 2nd pixel data are different as said compressed data in said memory with said flag of a second logic value; And a data compression-restore method for the flat panel display memory. The method of claim 3, wherein The TPPC encoding step, The lower bits of the nth pixel data and the lower 1 bit of the n + 1th pixel data if the upper bits of the nth and n + 1th pixel data are the same as the upper bits of the previous pixel data. Selectively removing a and storing the compressed data in the memory together with a flag of the first logical value indicating the identity of the upper bits; And A flag of the second logical value indicating that the upper bits are different together with the nth pixel data from which the lower bit is selectively removed when the upper bits of the previous pixel data and the upper bits of the nth pixel data are different And storing the compressed data in the memory with the least significant bit as the least significant bit. The method according to any one of claims 2 to 4, Restoring the compressed data, And restoring original pixel data by applying all of the compression methods inversely to the data compression-restore method for the flat panel display memory. The method of claim 1, The RLE encoding step, Connecting a plurality of position value shifters with a plurality of comparators to generate position values indicating a position of the pixel data for detecting a boundary between identical pixel data in the consecutively inputted pixel data; ; Generating a token for generating the position values through the position value shifter at one clock and transferring the token to the position value shifter located at a boundary between the same pixel data; Sequentially transferring the boundary position values between the same pixel data to the latch master and the latch slave every clock through the position value shifter; And Calculating a difference between the position values through a latch-master, a latch-slave, and a subtractor connected to the plurality of position value shifters to generate a run length. Way. Determining whether the upper bits are the same by comparing the upper bits of the n (n is a positive integer) th and n + 1st pixel data X with the upper bits of previous pixel data preceding the n th pixel data using a comparator And a PPC compression algorithm for generating a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and outputting the flag instead of the upper bits, and the remaining lower bits except for the same upper bits in the pixel data. Partially share a compression scheme with the TPPC compression algorithm, the PPC, and the TPPC compression algorithm to further remove some of the flag and generate the flag, selectively removing the upper bits or compressing the same pixel data within a continuous constant pixel data length. One of the previous frames in the PFC compression algorithm A PPC, TPPC & PFC encoder that selects and outputs the compressed pixel data according to a compression ratio for each compression algorithm and an average value of a slope difference between the pixel data; An RLE encoder for removing the pixel data consecutive in run length encoding (RLE) to output compressed pixel data; A memory for selectively storing any one of an output of the PPC, TPPC & PFC encoder and an output of the RLE encoder according to a compression algorithm selected based on the compression ratio and the slope between the pixel data; And And a decoder configured to reconstruct the compressed data by selecting a reconstruction algorithm according to the slope between the compression rate and the pixel data. The PFC algorithm is a partial type that removes the upper bits and generates the flag based on the identity of the upper bits, when the contiguous pixel data is the same as the full bit of any one of the pixel data. Compressing the pixel data using a full bit type for generating a code indicating a number of times, an uncompressed type for bypassing each of the pixel data to full bit when the consecutive pixel data are different, And the compressed data stored in the memory comprises a lower bit group in which lower bits of pixel data having the same upper bits are collected. The method of claim 7, wherein The RLE encoder, Connecting a plurality of position value shifters with a plurality of comparators to generate position values indicating a position of the pixel data for detecting a boundary between identical pixel data in the continuously input pixel data, Generate a token for generating the position values through the position value shifter in one clock and transfer the token to the position value shifter located at the boundary between the same pixel data every clock; The position value shifter sequentially transfers the boundary position values between the same pixel data to the latch master and the latch slave every clock. And a run length by calculating a difference between the position values through a latch-master, a latch-slave, and a subtractor connected to the plurality of position value shifters. The method of claim 8, The position value shifter, If the token is passed, the comparison value of the comparator has a first logical value, and the position value on the right is passed to the left, and if the comparison result of the comparator has a second logic value, the position value shifter selects to pass the position value of its own to the left. A first buffer; A second buffer which passes the token to the right regardless of a clock when the comparison result of the comparator has a first logic value; A master-slave latch that generates a signal for passing the position value shifter's position value according to a clock when the token is transferred; And An XOR gate connected between the output of the comparator and the master-slave latch 3214 that selects to output the position value shifter's own position value when a token is passed and the result of the comparator has a second logical value. 3213) When the result of the XOR gate has a first logic value, the first buffer is controlled through a pass transistor controlled by an output terminal of the XOR gate that outputs the position value of the position value shifter, and the position value value is converted into a position value path. And a data compression-restore device. comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; An encoding step of outputting pixel data compressed by using a PPC compression algorithm that generates a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and outputs the flag instead of the upper bits; Storing pixel data extruded by the PPC compression algorithm in a memory; And Restoring original pixel data by applying the PPC compression algorithm inversely to the data compression-restore method for the flat panel display memory. 11. The method of claim 10, The encoding step, If the upper bits of the n th and n + 1 th pixel data are the same as the upper bits of the previous pixel data, the lower bits of the n th pixel data and the lower bits of the n + 1 th pixel data indicate the identity of the upper bits. Storing the flag of the first logical value as the least significant bit in the memory as compressed data; And If the upper bits of the previous pixel data and the upper bits of the n-th pixel data are different, the flag of the second logical value indicating that the upper bits are different together with all the lower lower bits of the n-th pixel data is changed to the least significant bit. And storing the data in the memory as compressed data. comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; Generate a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and output the flag instead of the upper bits, and further remove some of the remaining lower bits except for the same upper bits in the pixel data. An encoding step of outputting compressed pixel data using a TPPC compression algorithm; Storing pixel data extruded by the TPPC compression algorithm in a memory; And Restoring original pixel data by applying the TPPC compression algorithm inversely to the data compression-restore method for the flat panel display memory. 13. The method of claim 12, The encoding step, The lower bits of the nth pixel data and the lower one bit of the n + 1th pixel data if the upper bits of the nth and n + 1th pixel data are the same as the upper bits of the previous pixel data. Selectively removing an anomaly and storing it in the memory as the compressed data with a flag of the first logical value indicating the identity of the upper bits; And A flag of the second logical value indicating that the upper bits are different together with the nth pixel data from which the lower bit is selectively removed when the upper bits of the previous pixel data and the upper bits of the nth pixel data are different And storing the compressed data in the memory with the least significant bit as the least significant bit. comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; Generate a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and output the flag instead of the upper bits, and further remove some of the remaining lower bits except for the same upper bits in the pixel data. Encoding the pixel data compressed using a PFC compression algorithm that selectively removes the upper bits or compresses the same pixel data within a continuous constant pixel data length; Storing pixel data extruded by the PFC compression algorithm in a memory; And Restoring original pixel data by applying the PFC compression algorithm inversely to the data compression-restore method for the flat panel display memory. The method of claim 14, The encoding step, If the upper bits of the n-th and n + 1th pixel data are the same as the upper bits of the previous pixel data, the lower bits of the n-th pixel data and the lower bits of the n + 1-th pixel data of the upper bits Storing in the memory as the compressed data with the flag of a first logical value indicating identity; Assigning a flag to the second logical value indicating that the upper bits are different if the upper bits of the previous pixel data and the upper bits of the n-th pixel data are different; And if the flag has a second logic value and the lower whole bits of the n th pixel data, the n + 1 pixel data, and the n + 2 th pixel data are the same, the upper lower whole bits of the n th pixel data and the storing a code of a first logic value indicating that n + 1 pixel data and the n + 2th pixel data are the same as the compressed data in the memory with the flag of the second logic value; And If the flag has a second logic value and the upper lower whole bits of the n th pixel data, the n + 1 th pixel data and the n + 2 th pixel data are different, the upper lower whole bits of the n th pixel data and the storing said code of a second logic value indicating that n + 1 pixel data and said n + 2th pixel data are different as said compressed data in said memory with said flag of a second logic value; A data compression-restore method for a flat panel display memory, characterized in that. comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; A PPC compression algorithm that generates a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and outputs the flag instead of the upper bits, and some of the remaining lower bits except for the same upper bits in the pixel data PFC to remove the higher bits and to selectively remove the higher bits or to compress the same pixel data within a continuous constant pixel data length by further removing the? A PPC, TPPC & PFC encoding step of selecting any one of compression algorithms according to a compression rate of a previous frame and an average value of gradient differences between the pixel data and outputting the compressed pixel data; An RLE encoding step of outputting compressed pixel data by removing the pixel data consecutive in run length encoding (RLE); Selecting one of an output of the PPC, TPPC & PFC encoder and an output of the RLE encoder according to a compression algorithm selected based on the compression ratio and the slope between the pixel data and storing in the memory; Restoring the compressed data by selecting a decompression algorithm according to a slope between the compression ratio and the pixel data; Generating a gradation section including a plurality of gradation values through higher bits of the pixel data by the compression algorithms to generate a histogram based on the number of gradation intervals less than the gradation values; And Limiting the maximum frequency of the histogram to a predetermined clipping level lower than the maximum image resolution, and adjusting the step size representing the pixel data of the frequency to simplify to have a frequency representation level less than the number of pixel data; The PFC algorithm is a partial type that removes the upper bits and generates the flag based on the identity of the upper bits, when the contiguous pixel data is the same as the full bit of any one of the pixel data. Compressing the pixel data by using a full bit type for generating a code indicating a number of times, an uncompressed type for bypassing each of the pixel data to full bit when the consecutive pixel data are different, The compressed data stored in the memory includes a lower bit group in which lower bits of pixel data having the same upper bits are collected. comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; A PPC compression algorithm that generates a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and outputs the flag instead of the upper bits, and some of the remaining lower bits except for the same upper bits in the pixel data PFC to remove the higher bits and to selectively remove the higher bits or to compress the same pixel data within a continuous constant pixel data length by further removing the? A PPC, TPPC & PFC encoding step of selecting any one of compression algorithms according to a compression rate of a previous frame and an average value of gradient differences between the pixel data and outputting the compressed pixel data; An RLE encoding step of outputting compressed pixel data by removing the pixel data consecutive in run length encoding (RLE); Selecting one of an output of the PPC, TPPC & PFC encoder and an output of the RLE encoder according to a compression algorithm selected based on the compression ratio and the slope between the pixel data and storing in the memory; Restoring the compressed data by selecting a decompression algorithm according to a slope between the compression ratio and the pixel data; Receiving compressed data stored in a memory and dividing the pixel data X into upper bits X _upper and lower bits X _lower of the pixel data X; Setting a characteristic function f _pbl (X _partitioned ) of the divided bit lookup table of which the ROM size is reduced by inputting the upper bits X _upper and the lower bits X _lower which are divided bits; Compute the _upper bits X _upper and the lower bits X _lower by using the split bit lookup table, respectively, so that the operation result of the upper bits f _pbl (X _upper ) and the operation result of the lower bits f _pbl (X _lower Outputting; The gray scale interval is determined according to the upper bits X _upper using a scale factor lookup table, and the following step_size (f _pbl (X _upper )) is referred to as the step size of f _pbl (X _upper ) DR (g (x)) Selecting the preset scale factor k that satisfies the local scale factor SF _local when defining x as the dynamic range of function g (x); step_size (f _pbl (X _upper )) = | f _pbl (x _upper )-f _pbl (x _upper +1) | k = ^┌ log ₂ (SF _local ) ^┐ Using a shifter processes the computation result _{f pbl (X lower) / 2} k for an operation result f _pbl (X _lower) of the scale factor k, and the low-order bit to the variable error is caused in the divided bit look-up table calculation process Reducing the size of the; Receiving the pixel data X using the error lookup table and outputting a characteristic function f _{error_reduced} (X) of a preset error lookup table to compensate for an error during an operation; And _Summing f _fbl (X _lower ) / 2 ^k , f _fbl (X _upper ), and f _{error_reduced} (X) to calculate f (X) below, f (X) = f _pbl (X _upper ) + f _pbl (X _lower ) / 2 ^k + f _{error_reduced} (X) The PFC algorithm is a partial type that removes the upper bits and generates the flag based on the identity of the upper bits, when the contiguous pixel data is the same as the full bit of any one of the pixel data. Compressing the pixel data by using a full bit type for generating a code indicating a number of times, an uncompressed type for bypassing each of the pixel data to full bit when the consecutive pixel data are different, And the compressed data stored in the memory includes a lower bit group in which lower bits of pixel data having the same upper bits are collected. comparing upper bits of n (n is a positive integer) and n + 1st pixel data X with upper bits of previous pixel data preceding the nth pixel data to determine whether the upper bits are identical; A PPC compression algorithm that generates a flag indicating the identity of the upper bits except for the same upper bits in the pixel data and outputs the flag instead of the upper bits, and some of the remaining lower bits except for the same upper bits in the pixel data PFC to remove the higher bits and to selectively remove the higher bits or to compress the same pixel data within a continuous constant pixel data length by further removing a and partially sharing the compression scheme with the TPPC compression algorithm, the PPC, and the TPPC compression algorithm that generate the flag. PPC, TPPC & PFC encoding step of selecting any one of the compression algorithm according to the compression ratio of each compression algorithm of the previous frame and the average value of the slope difference between the pixel data to output the compressed pixel data; An RLE encoding step of outputting compressed pixel data by removing the pixel data consecutive in run length encoding (RLE); Selecting one of the PPC, TPPC & PFC encoding output and the RLE encoding output according to a compression algorithm selected based on the compression ratio and the slope between the pixel data and storing in the memory; Restoring the compressed data by selecting a decompression algorithm according to a slope between the compression ratio and the pixel data; And Calculating a motion vector by performing a motion estimation operation using upper bits of a compression block of consecutive frame data composed of the compressed data compressed by the compression algorithms; Grouping the plurality of compressed blocks into macro blocks of larger size and calculating a grouped motion vector of the grouped macro blocks of the compressed blocks; And Correcting the motion vector through auxiliary motion estimation through the motion vectors of an auxiliary macro block comprising a plurality of the grouped macro blocks, The PFC algorithm is a partial type that removes the upper bits and generates the flag based on the identity of the upper bits, when the contiguous pixel data is the same as the full bit of any one of the pixel data. Compressing the pixel data by using a full bit type for generating a code indicating a number of times, an uncompressed type for bypassing each of the pixel data to full bit when the consecutive pixel data are different, The compressed data stored in the memory includes a lower bit group in which lower bits of pixel data having the same upper bits are collected.

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