JP2009071473A - Data-processing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data-processing circuit simplifying a circuit configuration. <P>SOLUTION: In the data-processing circuit, raw image data of horizontal 3840 pixels × vertical 2160 pixels periodically outputted from a CMOS-type imaging apparatus is divided into four blocks of partial image data by a distributor 44. The divided four blocks of partial image data are preprocessed in parallel by preprocessing blocks PB1-PB4. The raw image data of horizontal 1280 pixels × vertical 960 pixels periodically outputted from a CCD-type imaging device are serially preprocessed by a preprocessing block PB5. The number of pixels of the raw image data outputted from the CCD-type imaging device is a fourth or less of the number of pixels of the raw image data outputted from the CMOS type imaging apparatus. A numerical value "4" is equivalent to the number of parallel preprocessings to the raw image data outputted from the CCD-type imaging apparatus. As a result, a common clock frequency can be applied to preprocessing for the CCD-type imaging apparatus and that for the CMOS-type imaging apparatus. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing circuit that performs predetermined data processing on image data output from an imaging apparatus.

An example of this type of device is disclosed in Patent Document 1. According to this background art, when a 400,000-pixel solid-state imaging device is mounted, video processing is executed according to a clock having a frequency of 14.3 MHz or 28.6 MHz (= 14.3 MHz × 2). On the other hand, when a 500,000-pixel solid-state imaging device is mounted, video processing is executed according to a clock having a frequency of 18 MHz or 36 MHz (= 18 MHz × 2). Thereby, cross-color interference can be sufficiently reduced.
JP-A-9-284660 [H04N 5/335, 5/208, 5/21]

  However, in the background art, it is necessary to prepare a different clock frequency for each image sensor, so that the circuit configuration may be complicated.

  Therefore, a main object of the present invention is to provide a data processing circuit capable of simplifying the circuit configuration.

  A data processing circuit according to the present invention (IC1: a reference symbol corresponding to the embodiment; the same applies hereinafter) has N pixels corresponding to a first number and outputs first image data periodically output from the first imaging device to N Dividing means (44) for dividing the image into partial image data of blocks (N: an integer of 2 or more), and first processing means for executing the first processing in parallel on the N block partial image data divided by the dividing means (FB1 to FB4) and a second process in series with respect to the second image data having pixels corresponding to the second number which is 1 / N of the first number and periodically output from the second imaging device Second processing means (FB5) to be executed automatically.

  The dividing unit divides the first image data having pixels corresponding to the first number and periodically output from the first imaging device into N block partial image data. The first processing means executes the first processing in parallel on the N block partial image data divided by the dividing means. The second processing means serially performs the second processing on the second image data that has pixels corresponding to the second number that is 1 / N of the first number and is periodically output from the second imaging device. To run.

  As described above, the first image data has pixels corresponding to the first number, and the second image data has pixels corresponding to the second number. Furthermore, the second number is 1 / N of the first number. The first image data is divided into N block partial image data and subjected to the first processing in parallel, and the second image data is subjected to the second processing in series. As a result, a clock having a common frequency can be applied to the first processing for the first imaging device and the second processing for the second imaging device, and the circuit configuration can be simplified.

  In a preferred aspect, the image processing apparatus further includes writing means (20a, 20b) for writing the first image data processed by the first processing means and the second image data processed by the second processing means to the memory (22a, 22b).

  In another preferred aspect, the first imaging device outputs the first image data in the first cycle, the second imaging device outputs the second image data in the second cycle, and the first processing means is synchronized with the first frequency. The second processing means executes the second processing in synchronization with the second frequency, and the ratio of the first frequency to the second frequency is 1 / N of the first number and the first period. This is equivalent to the ratio between the numerical value obtained by multiplying by 2 and the numerical value obtained by multiplying the second number by the second period.

  In another preferable aspect, the cycle in which the first imaging device outputs the first image data is shorter than the cycle in which the second imaging device outputs the second image data.

  In still another preferred aspect, third processing means (BB1) for executing a third process on each of the first image data processed by the first processing means and the second image data processed by the second processing means. Is further provided.

  In another preferred aspect, the allocation means (72) for allocating an extraction area covering the pixels corresponding to the second number on the imaging surface of the first imaging device, and allocation among the first image data processed by the first processing means The image processing apparatus further includes extraction means (20a) for extracting a part of the image data belonging to the extraction area assigned by the means for the third processing.

  More preferably, it further includes moving means (S5) for moving the extraction area in a direction that cancels the movement of the imaging surface in the direction orthogonal to the optical axis.

  According to this invention, the first image data has pixels corresponding to the first number, and the second image data has pixels corresponding to the second number. Furthermore, the second number is 1 / N of the first number. The first image data is divided into N block partial image data and subjected to the first processing in parallel, and the second image data is subjected to the second processing in series. As a result, a clock having a common frequency can be applied to the first processing for the first imaging device and the second processing for the second imaging device, and the circuit configuration can be simplified.

  The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

  Referring to FIG. 1, the video camera 10 of this embodiment includes an optical lens 12. The optical image of the object scene is irradiated on the imaging surface of the imaging device 14 through the optical lens 12. A plurality of pixels are two-dimensionally arranged on the imaging surface, and charges corresponding to the amount of light are generated at each pixel. The imaging surface is covered with a primary color Bayer array color filter (not shown), and the charge generated in each pixel has color information of R (Red), G (Green), or B (Blue).

  When the power is turned on, the CPU 38 gives a corresponding command to the preprocessing circuit 18, the postprocessing circuit 24 and the video display circuit 26 constituting the imaging device 14 and the data processing circuit IC1 in order to execute through image processing. . In response to a timing signal (including a vertical synchronization signal Vsync and a clock signal) output from an SG (Signal Generator) 16, the imaging device 14 exposes the imaging surface and charges generated on the imaging surface by the exposure. Read in raster scan mode. From the imaging device 14, raw image data based on the charge generated on the imaging surface is periodically output.

  As the imaging device 14, either a CMOS type imaging device or a CCD type imaging device is employed. The CMOS imaging device has an imaging surface shown in FIG. 2A, while the CCD imaging device has an imaging surface shown in FIG.

  The imaging surface illustrated in FIG. 2A has horizontal 3840 pixels × vertical 2160 pixels. Of these, the horizontal center of 3325 pixels × vertical 1870 pixels (resolution: about 6 million pixels) corresponds to the effective image area, and the remaining area around the optical black area. In addition, the imaging surface illustrated in FIG. 2B has horizontal 1280 pixels × vertical 960 pixels. Of these, the horizontal center of 1024 pixels × vertical 768 pixels (resolution: XGA) corresponds to the effective image area, and the remaining area around the periphery corresponds to the optical black area.

  When a CMOS imaging device is employed as the imaging device 14, the vertical synchronization signal Vsync is output every 1/60 seconds, and as a result, the raw image data of horizontal 3840 pixels × vertical 2160 pixels including an optical black component is 60 fps. Is output from the imaging device 14 at a frame rate of. On the other hand, when a CCD type image pickup device is employed as the image pickup device 14, the vertical synchronization signal Vsync is output every 1/30 seconds. As a result, the raw image data of horizontal 1280 pixels × vertical 960 pixels including an optical black component is obtained. Is output from the imaging device 14 at a frame rate of 30 fps.

  The preprocessing circuit 18 performs processing such as digital clamping, pixel defect correction, gain control, and Knee processing on the raw image data output from the imaging device 14, and the processed raw image data is processed as shown in FIG. The data is output to the data bus A as shown in (B). When the CMOS type imaging device is adopted, raw image data of horizontal 3840 pixels × vertical 2160 pixels including an optical black component is output from the preprocessing circuit 18 to the data bus A in the manner shown in FIG. . When the CCD type imaging device is employed, the raw image data of horizontal 1280 pixels × vertical 960 pixels including the optical black component is output from the preprocessing circuit 18 as shown in FIG. The raw image data output to the data bus A is given to the memory control circuit 20a constituting the memory device MD1, and written to the SDRAM 22a by the memory control circuit 20a.

  An extraction area is allocated to the imaging surface in the manner shown in FIG. 2 (A) or 2 (B). The size of the extraction area allocated to the imaging surface of the CMOS imaging device is equivalent to horizontal 1920 pixels × vertical 1080 pixels (resolution: about 2 million pixels), and the size of the extraction area allocated to the imaging surface of the CCD imaging device. Corresponds to horizontal 640 pixels × vertical 480 pixels (resolution: VGA). The post-processing circuit 24 defines such an extraction area with respect to the memory control circuit 20a, and requests reading of a part of raw image data belonging to the extraction area. The memory control circuit 20a reads the raw image data belonging to the defined extraction area from the SDRAM 22a every time the vertical synchronization signal Vsync is generated.

  The raw image data extracted from the extraction area in this manner is input to the post-processing circuit 24 via the data bus A and subjected to processing such as color separation, white balance adjustment, and YUV conversion. As a result, when the CMOS type imaging device is adopted, YUV image data of horizontal 1920 pixels × vertical 1080 pixels is output from the post-processing circuit 24 in the manner shown in FIG. When the CCD type imaging device is employed, YUV image data of horizontal 640 pixels × vertical 480 pixels is output from the post-processing circuit 24 as shown in FIG. 4B.

  The YUV image data output from the post-processing circuit 24 is given to the memory control circuit 20b constituting the memory device MD2 via the data bus B, and is written into the SDRAM 22b by the memory control circuit 20b.

  The video display circuit 26 reads the YUV image data stored in the SDRAM 22b through the memory control circuit 20b every time the vertical synchronization signal Vsync is generated. The read YUV image data is input to the video display circuit 26 via the data bus B. The video display circuit 26 drives the LCD monitor 30 based on the input YUV image data, whereby a real-time moving image representing a scene, that is, a through image is displayed on the monitor screen.

  The post-processing circuit 24 also detects minute movements of the imaging surface in the direction orthogonal to the optical axis based on the YUV image data generated by YUV conversion as camera shake, and a motion vector indicating the detected camera shake is a vertical synchronization signal. Every time Vsync is generated, it is given to the CPU 38. The CPU 38 moves the extraction area shown in FIG. 2A or 2B in the direction in which the motion vector is canceled. The extraction area defined by the post-processing circuit 24 for the memory control circuit 20a is an extracted area after movement, and some raw image data read by the memory control circuit 20a is also image data belonging to the extracted area after movement. . As a result, a through image in which camera shake is suppressed is output from the LCD monitor 30.

  When a moving image recording start operation is performed by the key input device 42 during the through image processing, the CPU 38 gives a processing command to the H264 encoder 32 and the I / F 34. Similarly to the post-processing circuit 24, the H264 encoder 32 defines the extraction area shown in FIG. 2A or FIG. 2B for the memory control circuit 20b, and stores some YUV image data belonging to the extraction area. Request reading. The memory control circuit 20b reads YUV image data belonging to the defined extraction area from the SDRAM 22b every time the vertical synchronization signal Vsync is generated.

  The read YUV image data is input to the H264 encoder 32 via the data bus B and subjected to compression processing according to the H264 format. The H264-compressed image data, that is, H264 data is given to the memory control circuit 20b via the data bus B, and is written into the SDRAM 22b by the memory control circuit 20b.

  The I / F circuit 34 reads a plurality of frames of H264 data stored in the SDRAM 22b through the memory control circuit 20b, inputs the read H264 data from the data bus B, and records the input H264 data in a file format. Recorded on the medium 36. A plurality of frames of H264 data generated in response to the moving image recording start operation are accumulated in the same moving image file in the recording medium 36. When the moving image recording end operation is performed on the key input device 40, the moving image recording task is stopped. When the moving image recording task is stopped, the above-described operations by the H264 encoder 32 and the I / F circuit 34 are also stopped, thereby completing the moving image file.

  The CPU 38 writes character codes corresponding to the various operations described above into the SDRAM 20a (or 20b) through the memory control circuit 20a (or 20b). The character display circuit 28 reads out the character code stored in the SDRAM 22a (or 22b) through the memory control circuit 20a (or 20b), inputs the read character code from the data bus A (or B), and is inputted. The LCD monitor 30 is driven based on the character code. As a result, the character that guides the various operations described above is displayed on the monitor screen in the OSD manner.

  The preprocessing circuit 18 is configured as shown in FIG. When the COMS type imaging device is employed as the imaging device 14, the raw image data output from the imaging device 14 is given to the distributor 44. The distributor 44 divides the given raw image data into four in the horizontal direction, and inputs the divided four blocks of raw image data to the preprocessing blocks FB1 to FB4, respectively.

  The raw image data given to the preprocessing block FB1 is composed of 4 × Nth (N: 0, 1, 2, 3,...) Horizontal pixels, and the raw image data given to the preprocessing block FB2 is 4 × N + 1th. Of horizontal pixels. The raw image data given to the preprocessing block FB3 is composed of 4 × N + 2 th horizontal pixels, and the raw image data given to the preprocessing block FB4 is composed of 4 × N + 3 th horizontal pixels.

  The preprocessing block FB1 includes a digital clamp circuit 46a, a pixel defect correction circuit 48a, a gain control circuit 50a, and a knee processing circuit 52a. The preprocessing block FB2 includes a digital clamp circuit 46b, a pixel defect correction circuit 48b, a gain control circuit 50b, and A knee processing circuit 52b is used. The preprocessing block FB3 includes a digital clamp circuit 46c, a pixel defect correction circuit 48c, a gain control circuit 50c, and a knee processing circuit 52c. The preprocessing block FB4 includes a digital clamp circuit 46d, a pixel defect correction circuit 48d, and a gain control circuit. 50d and a Knee processing circuit 52d.

  Accordingly, all of the raw image data of each block is subjected to a series of processes of digital clamping, pixel defect correction, gain control, and Knee processing in common and in parallel. The raw image data output in parallel from the preprocessing blocks FB1 to FB4 is then written in the SRAM 66.

  When a CCD type imaging device is employed as the imaging device 14, the raw image data output from the imaging device 14 is given to the preprocessing block FB5. The preprocessing block FB5 includes a digital clamp circuit 54, a pixel defect correction circuit 56, a smear correction circuit 58, a gain control circuit 60, and a knee processing circuit 62. The raw image data includes digital clamp, pixel defect correction, smear correction, A series of processing of gain control and Knee processing is performed in series. The raw image data output in series from the preprocessing block FB5 is then written into the SRAM 66.

  The controller 64 issues a write request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 66 reaches a threshold value, and generates a predetermined amount of raw image data when an approval signal is returned from the issue destination. Read from SRAM 66. The selector 68 has two output terminals respectively connected to the data buses A and B, and outputs the read raw image data from one of the two output terminals.

  The controller 64 refers to the register R1 to specify the issue destination of the write request, and the selector 68 refers to the register R1 to specify the output destination of the raw image data. Identification information for identifying the memory device MD1 is registered in the register R1. Therefore, the write request is issued toward the memory control circuit 20a constituting the memory device MD1, and the raw image data read from the SRAM 66 is output toward the data bus A connected to the memory device MD1.

  Each pixel forming the raw image data is expressed by 12 bits regardless of whether a CMOS image pickup device or a CCD image pickup device is used. When the CMOS type imaging device is employed, the raw image data of each pixel output in parallel from each of the preprocessing blocks MD1 to MD4 is written into the SRAM 66 by 12 bits in a time division manner, and corresponds to four horizontal pixels. 48 bits are read from the SRAM 66. When the CCD type imaging device is employed, the raw image data is written to the SRAM 66 by 12 bits (= 1 pixel) and read from the SRAM 66 by 12 bits (= 1 pixel).

  Since each of the data buses A and B has a bus width of 64 bits and 64 bits> 48 bits> 12 bits, the data transfer process does not fail. Each of the SDRAMs 22a and 22b is a DDR type SDRAM having a × 32 bit configuration, and the transferred raw image data is stored in 32 bits in each storage element.

  The post-processing circuit 24 is configured as shown in FIG. The controller 72 issues a read request to the memory control circuit 20a or 20b every time the amount of data stored in the SRAM 74 falls below a threshold value, and executes data writing to the SRAM 74 when an approval signal is returned from the issue destination. To do. The raw image data to be written to the SRAM 74 is a predetermined amount of data output from the read request issuing destination, and is transferred to the data bus A or B. The selector 70 has two input terminals respectively connected to the data buses A and B, and has one output terminal connected to the SRAM 74. The raw image data transferred through the data bus A or B is given to the SRAM 74 through such a selector 70.

  The controller 72 refers to the register R2 to identify the issue destination of the read request, and the selector 70 refers to the register R2 to identify the input source of the raw image data. Identification information indicating the memory device MD1 is registered in the register R2. Accordingly, the read request is issued to the memory control circuit 20a constituting the memory device MD1, and the raw image data is input to the selector 70 via the data bus A connected to the memory control circuit MD1.

  The color separation circuit 76 constituting the post-processing block BB1 performs color separation processing on the raw image data stored in the SRAM 74. As a result, RGB image data in which each pixel has all the R, G, and B color information is generated. The white balance adjustment circuit 78 adjusts the white balance of the RGB image data output from the color separation circuit 76, and the YUV conversion circuit 80 converts the RGB image data output from the white balance adjustment circuit 78 into YUV image data. The converted YUV image data is written into the SRAM 86.

  Similar to the controller 64 shown in FIG. 5, the controller 84 issues a write request to the memory control circuit 20a or 20b each time the amount of data stored in the SRAM 86 reaches a threshold value, and an approval signal is returned from the issue destination. Sometimes a predetermined amount of YUV image data is read from the SRAM 86. The selector 88 has two output terminals connected to the data buses A and B, respectively, and outputs YUV image data read from the SRAM 86 from one of the two output terminals.

  The controller 84 refers to the register R3 to specify the issue destination of the write request, and the selector 88 refers to the register R3 to specify the output destination of the YUV image data. Identification information indicating the memory device MD2 is registered in the register R3. Therefore, the write request is issued toward the memory control circuit 20b constituting the memory device MD2, and the raw image data read from the SRAM 54 is output toward the data bus B connected to the memory device MD2.

  The motion detection circuit 82 refers to the two frames of YUV image data continuously output from the YUV conversion circuit 80 and detects minute movements of the imaging surface in the direction orthogonal to the optical axis as camera shake. Such a detection process is executed every time the vertical synchronization signal Vsync is generated. The motion detection circuit 82 further creates a motion vector indicating the detected camera shake, and outputs the created motion vector to the CPU 38.

  Among the clock signals output from SG16, the clock signal applied to preprocessing blocks FB1 to FB5 shown in FIG. 5 and postprocessing block BB1 shown in FIG. 6 has a frequency of 125 MHz. The preprocessing blocks FB1 to FB5 and the postprocessing block BB1 execute the above-described processing in synchronization with the clock frequency of 125 MHz. Here, the numerical value “125 MHz” is derived from the reason described below.

  The raw image data output from the CMOS type imaging device has a number of pixels of horizontal 3840 pixels × vertical 2160 pixels and a frame rate of 60 fps. In order to perform preprocessing in series on such raw image data, a clock frequency of about 500 MHz (= 3840 × 2160 × 60) is required if one clock is assigned to one pixel. However, according to this embodiment, the raw image data output from the CMOS imaging device is divided into four blocks and preprocessed in parallel. For this reason, the clock frequency required for the preprocessing of the raw image data output from the CMOS type imaging device can be suppressed to 125 MHz (= 500 MHz / 4).

  On the other hand, the raw image data output from the CCD type imaging device has a number of pixels of horizontal 1280 pixels × vertical 960 pixels and a frame rate of 30 fps. The clock frequency required for serial preprocessing for such raw image data is approximately 37 MHz (= 1280 × 960 × 30). Therefore, the raw image data output from the CCD type imaging device can be sufficiently processed with the 125 MHz clock described above.

  Further, the YUV image data generated in the post-processing block BB1 when the CMOS type imaging device is employed has a horizontal 1920 pixel × vertical 1080 pixel number and a frame rate of 60 fps. That is, the number of pixels of the image data noted by the post-processing block BB1 is ¼ of the number of pixels of the image data noted by the pre-processing blocks FB1 to FB4 (the frame rate is common). Further, the post-processing block BB1 performs post-processing in series. Therefore, the clock frequency necessary for the processing of the post-processing block BB1 is 125 MHz. Note that a clock frequency exceeding 125 MHz may be prepared in order to provide a margin for processing.

  The YUV image data generated in the post-processing block BB1 when the CCD type imaging device is employed has a number of pixels of horizontal 640 pixels × vertical 480 pixels and a frame rate of 30 fps. A clock frequency of 125 MHz is sufficient for such post-processing of YUV image data.

  The CPU 38 executes a plurality of tasks including the camera shake correction task shown in FIG. 7 in parallel. Note that control programs corresponding to these tasks are stored in the flash memory 42.

  First, in step S1, it is determined whether or not the vertical synchronization signal Vsync has been generated. If YES is determined here, a motion vector is fetched from the post-processing circuit 24 in a step S3. In step S5, the extraction area is moved in a direction in which the captured motion vector is canceled. When the process of step S5 is completed, the process returns to step S1.

  As can be seen from the above description, the CMOS imaging device outputs raw image data of horizontal 3840 pixels × vertical 2160 pixels. The output raw image data is written into the SDRAM 22a through preprocessing by the preprocessing circuit 18. The memory control circuit 20a extracts raw image data of horizontal 1920 pixels × vertical 1080 pixels belonging to the extraction area from the raw image data stored in the SDRAM 22a. The post-processing circuit 24 executes post-processing synchronized with the clock frequency of 125 MHz on the raw image data extracted by the memory control circuit 20a.

  Here, the numerical value of 125 MHz is (horizontal 1920 pixels × vertical 1080 pixels) with a clock frequency (= 500 MHz) necessary for serially preprocessing raw image data of horizontal 3840 pixels × vertical 2160 pixels as a reference frequency. ) / (Horizontal 3840 pixels × vertical 2160 pixels) multiplied by the reference frequency.

  That is, the post-processing clock frequency of 125 MHz is determined based on the difference between the number of pixels of the image data to be preprocessed and the number of pixels of the image data to be postprocessed. As a result, the post-processing frequency can be set to an appropriate value, and thus the circuit scale can be optimized.

  Further, the preprocessing circuit 18 divides the raw image data output from the imaging device 14 into partial image data of N blocks (N: “4” as an integer equal to or larger than 2), and the divided N block partial images Perform preprocessing on data in parallel. On the other hand, the post-processing circuit 24 executes post-processing on the raw image data given from the memory control circuit 20a in series.

  By executing the preprocessing in parallel, the clock frequency required for the preprocessing is 1 / N of the reference frequency (= 500 MHz). Since N = 4, the clock frequency for preprocessing is specifically 125 MHz. As a result, the preprocessing frequency can be kept low, and a frequency common to the preprocessing circuit 18 and the postprocessing circuit 24 can be used.

  Further, the number of pixels that the preprocessing circuit 18 focuses on (= horizontal 3840 pixels × vertical 2160 pixels), the number of pixels that the postprocessing circuit 24 focuses on (= horizontal 1920 pixels × vertical 1080 pixels), and the number of preprocessing blocks (= 4) The relationship of “(horizontal 1920 pixels × vertical 1080 pixels) / (horizontal 3840 pixels × vertical 2160 pixels) = number of preprocessing blocks” is established. By determining the number of preprocessing blocks so that this relationship holds, the number of preprocessing blocks, that is, the number of parallel preprocessing is optimized, and the performance of image data processing is improved.

  Further, when looking at the preprocessing circuit 18 from another aspect, the raw image data of horizontal 3840 pixels × vertical 2160 pixels periodically output from the CMOS type imaging device is divided into partial image data of 4 blocks by the distributor 44. The The divided partial image data of the four blocks are preprocessed in parallel by the preprocessing blocks FB1 to FB4. On the other hand, the raw image data of horizontal 1280 pixels × vertical 960 pixels periodically output from the CCD type imaging device is preprocessed in series by the preprocessing block FB5.

  Here, the number of pixels of the raw image data output from the CCD type image pickup device is ¼ or less of the number of pixels of the raw image data output from the CMOS type image pickup device. The numerical value “4” corresponds to the number of parallel preprocessing for the raw image data output from the CCD imaging device. As a result, a common clock frequency (= 125 MHz) can be applied to the preprocessing for the CCD imaging device and the preprocessing for the CMOS type imaging device, and the circuit configuration can be simplified.

  Note that since the frame rate is different between the CCD type imaging device and the CMOS type imaging device, the number of pixels output from the CCD type imaging device per unit time when the time axis is taken into consideration is the CMOS type imaging device. 1/8 of the number of pixels output per unit time.

  In this embodiment, as shown in FIG. 5, the CMOS imaging device is fixedly assigned to the preprocessing blocks FB1 to FB4, and the CCD imaging device is fixedly assigned to the preprocessing block FB5. However, since the CMOS image pickup device and the CCD image pickup device are alternatively employed, the preprocessing block FB4 may be shared by the CMOS image pickup device and the CCD image pickup device. In this case, the preprocessing circuit 18 is preferably configured as shown in FIG.

  According to FIG. 8, the preprocessing circuit FB5 is omitted, a selector 90 is added in front of the preprocessing block FB4, and a selector 92 is added between the smear correction circuit 58 and the gain control circuit 50d. The selector 90 alternatively inputs the image data of the fourth block output from the distributor 44 and the raw image data output from the CCD type imaging device to the preprocessing block FB4. The selector 92 alternatively inputs the output of the pixel defect correction circuit 48d and the output of the smear correction circuit 58 to the gain control circuit 50d. The selection mode of the selectors 90 and 92 is changed depending on which of the CMOS imaging device and the CCD imaging device is adopted as the imaging device 14.

  In this embodiment, the raw image data is divided into four blocks in order to preprocess the raw image data output from the CMOS type imaging device, but the number of blocks to be divided is "4". It is not limited.

  Furthermore, in this embodiment, an imaging device having the number of pixels shown in FIG. 2A is assumed as a CMOS type imaging device, but the number of pixels shown in FIG. 2A is the clock frequency (125 MHz or 500 MHz) described above. ) And the number of parallel preprocessing (= 4), and it goes without saying that a CMOS type imaging device having a number of pixels smaller than this may be adopted. Similarly, the CCD imaging device has the number of pixels shown in FIG. 2B, and the frame rate of the raw image data output from the CCD imaging device is 30 fps, but the clock frequency of the preprocessing block FB5 is Since it is 125 MHz, the number of pixels and the frame rate of the CCD type imaging device can be increased to horizontal 1920 pixels × vertical 1080 pixels and 60 fps, respectively.

In other words, if the number of pixels and the frame rate of the CCD type imaging device are set as in this embodiment, the frequency of the preprocessing block FB5 can be suppressed to a value lower than 125 MHz (about 37 MHz described above). In other words, the optimum clock frequency of the preprocessing block FB5 can be calculated according to Equation 1, and the preprocessing block FB5 may be driven by the clock signal having the clock frequency thus calculated.
[Equation 1]

Fccd = (PXccd × FPSccd) / (PXcmos / N × FPCSmos) × Fcmos
Fccd: clock frequency of preprocessing block FB5: clock frequency of preprocessing blocks FB1 to FB4 PXccd: number of pixels of CCD type imaging device FPSccd: frame rate of CCD type imaging device PXcmos: number of pixels of CMOS type imaging device FPScmos: CMOS Type imaging device frame rate

  In this embodiment, the CMOS image pickup device and the CCD image pickup device are alternatively adopted. However, if the preprocessing circuit 18 shown in FIG. 5 is used, both the CMOS image pickup device and the CCD image pickup device are used. You may make it comprise the video camera provided with. In this case, it is necessary to output 60-bit data from the SRAM 66 shown in FIG. 5. However, since the data buses A and B have a 64-bit bus width and 64 bits> 60 bits, the processing fails. There is nothing.

  In this embodiment, one pixel is expressed by 12 bits, but one pixel may be expressed by 14 bits. In this case, the bus width of the data buses A and B can be increased as appropriate.

It is a block diagram which shows the structure of one Example of this invention. (A) is an illustration figure which shows an example of the imaging surface of a CMOS type imaging device, (B) is an illustration figure which shows an example of the imaging surface of a CCD type imaging device. (A) is a timing chart showing an example of the output operation of the preprocessing circuit when the CMOS type imaging device is employed, and (B) is an output operation of the preprocessing circuit when the CCD type imaging device is employed. It is a timing diagram which shows an example. (A) is a timing chart showing an example of the output operation of the post-processing circuit when the CMOS type image pickup device is adopted, and (B) is an output operation of the post-processing circuit when the CCD type image pickup device is adopted. It is a timing diagram which shows an example. It is a block diagram which shows an example of a structure of a pre-processing circuit. It is a block diagram which shows an example of a structure of a post-processing circuit. It is a flowchart which shows a part of operation | movement of CPU. It is a block diagram which shows an example of a structure of the pre-processing circuit applied to another Example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Video camera 14 ... Imaging device 18 ... Pre-processing circuit MD1, MD2 ... Memory device 24 ... Post-processing circuit 26 ... Video display circuit 32 ... H264 encoder 38 ... CPU

Claims (8)

A dividing unit that divides first image data having pixels corresponding to the first number and periodically output from the first imaging device into partial image data of N blocks;
First processing means for executing a first process in parallel on partial image data of N blocks (N: an integer equal to or greater than 2) divided by the dividing means; and a first processing means that is 1 / N of the first number A data processing circuit comprising second processing means for performing second processing in series on second image data that has two pixels and is periodically output from the second imaging device.   The data processing circuit according to claim 1, further comprising a writing unit that writes the first image data processed by the first processing unit and the second image data processed by the second processing unit into a memory. The first imaging device outputs the first image data in a first period;
The second imaging device outputs the second image data in a second period;
The first processing means executes the first processing in synchronization with a first frequency;
The second processing means executes the second processing in synchronization with a second frequency;
The ratio between the first frequency and the second frequency is a numerical value obtained by multiplying 1 / N of the first number by the first period and a numerical value obtained by multiplying the second number by the second period. The data processing circuit according to claim 1, which corresponds to a ratio of   4. The data processing circuit according to claim 1, wherein a period in which the first imaging device outputs the first image data is shorter than a period in which the second imaging device outputs the second image data.   The third processing means for executing a third process on each of the first image data processed by the first processing means and the second image data processed by the second processing means. 5. The data processing circuit according to any one of 4. Allocating means for allocating an extraction area covering pixels corresponding to the second number on the imaging surface of the first imaging device, and allocating by the allocating means among the first image data processed by the first processing means. 6. The data processing circuit according to claim 1, further comprising extraction means for extracting a part of image data belonging to the extraction area for the third processing.   The data processing circuit according to claim 6, further comprising moving means for moving the extraction area in a direction that cancels out the movement of the imaging surface in a direction orthogonal to the optical axis.   A video camera comprising the data processing circuit according to claim 1.

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