JP2009071319A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the nitrogen concentration of nitrogen contained in a gate insulating film without unnecessarily increasing the concentration of nitrogen near the interface between a substrate and the gate insulating film. <P>SOLUTION: A gate insulating film of a field-effect transistor includes a first region close to a semiconductor substrate, and a second region which is more close to a gate electrode than the first region, wherein the first region has a peak nitrogen concentration which is different from that of the second region. The first region has a peak nitrogen concentration of 2.5 atomic% to 10 atomic%, and the second region has higher peak nitrogen concentration than that of the first region. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device in which a gate insulating film of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed of a silicon oxynitride film.

  In order to realize the low voltage operation of the MISFET (field effect transistor), it is necessary to make the gate oxide film thinner in proportion to the miniaturization of the MISFET. However, when the thickness of the gate oxide film is reduced, the direct tunnel current flowing through the film increases, and a gate leakage current that cannot be ignored from the viewpoint of reducing power consumption is generated.

As a countermeasure, the physical film thickness of the gate insulating film is obtained by using a high dielectric film such as a titanium oxide (TiO ₂ ) or tantalum oxide (Ta ₂ O ₅ ) film having a relative dielectric constant larger than that of silicon oxide. Attempts have been made to increase. However, the gate insulating film composed of this type of high dielectric film has many problems in interface control and so on, and is currently considered difficult to apply to mass production devices.

  A silicon oxynitride film formed by nitriding a part of a silicon oxide film has a higher dielectric constant than silicon oxide. Therefore, it has the effect of reducing the leakage current by increasing the physical thickness of the gate insulating film. I can expect. In addition, the gate insulating film formed of the silicon oxynitride film suppresses so-called boron leakage, in which impurities (boron) in the p-type gate electrode penetrates into the channel region of the substrate by heat treatment during the process, and the hot carrier resistance of the MISFET. It has been reported that it is effective for improving the electron mobility of the n-channel type MISFET.

  As a technique for nitriding a gate insulating film made of silicon oxide, a method in which a silicon oxide film is formed on the surface of a silicon substrate and then the substrate is heat-treated in a high-temperature atmosphere of about 1000 ° C. containing NO (nitrogen monoxide) gas ( Oxynitriding treatment is known.

  Japanese Patent Laid-Open No. 2001-332724 (Patent Document 1) discloses a p-type MIS device in which an n-type gate electrode is used for an n-channel MISFET and a p-type gate electrode is used for a p-channel MISFET. A technique for forming a gate insulating film made of silicon oxynitride having nitrogen concentration peaks at two points in the interface with the silicon substrate and in the film for the purpose of preventing penetration of boron in the gate electrode and improving hot carrier resistance. Disclosure.

  In order to form the silicon oxynitride film as described above, first, a silicon substrate is wet-oxidized to form a silicon oxide film having a thickness of about 7 nm on the surface, and then the substrate is formed in an atmosphere containing NO gas. After heat treatment, nitrogen is segregated at the interface between the silicon oxide film and the substrate, and then the substrate is dry oxidized. When this dry oxidation is performed, the interface between the silicon oxide film and the substrate is oxidized, and a silicon oxide film having a thickness of about 1 nm to 2 nm is also formed in the lower layer of the region where nitrogen is segregated. After that, when the substrate is heat-treated again in an atmosphere containing NO gas, nitrogen is segregated also at the interface between the silicon oxide film and the substrate formed in the lower layer of the nitrogen segregated region. A gate insulating film made of silicon oxynitride having nitrogen concentration peaks at two locations is obtained.

  Japanese Unexamined Patent Publication No. 2000-357688 (Patent Document 2) discloses a technique for forming a gate insulating film made of silicon oxynitride having a nitrogen concentration distribution having two peaks in the thickness direction by a method different from the above publication. Yes.

In this publication, a silicon substrate is first heated in an oxygen atmosphere to form a silicon oxide film having a film thickness of about 5 nm on its surface, and then heated in a NO gas atmosphere to thereby form nitrogen near the interface with the substrate. A silicon oxynitride film having a concentration peak and a film thickness of about 5.5 nm is formed. Next, the surface of the silicon oxynitride film is etched with a hydrofluoric acid aqueous solution to remove the surface layer portion, thereby obtaining a silicon oxynitride film having a thickness of about 1 nm containing nitrogen at a high concentration over the entire thickness direction. . Thereafter, by performing a second heat treatment in an NO gas or N ₂ O gas atmosphere, a new thermal oxide film is grown and formed on the substrate side, and nitrogen is introduced into the thermal oxide film. A silicon oxynitride film having a concentration distribution with two peaks in the thickness direction is obtained.
JP 2001-332724 A JP 2000-357688 A

  In the case where the gate insulating film of the MISFET is composed of the above-described silicon oxynitride film, if the gate insulating film becomes thinner as the MISFET is miniaturized, in order to reduce the gate leakage current, It is required to increase the dielectric constant by increasing the nitrogen concentration.

However, a silicon oxynitride film formed by a conventional oxynitriding process in which nitrogen is introduced into a silicon oxide film by heating the substrate in an NO gas or N ₂ O gas atmosphere is nitrogen in the vicinity of the interface between the film and the substrate. Even if the concentration can be increased, the surface side of the film is not nitrided, so it is difficult to increase the dielectric constant by increasing the nitrogen concentration of the entire film.

  Further, if the vicinity of the interface between the gate insulating film and the substrate is excessively nitrided, the interface states and traps in the film increase, causing a problem that the carrier mobility of the MISFET is lowered.

  FIG. 30 is a graph showing the relationship between the nitrogen concentration at the interface between the gate insulating film and the substrate and the carrier mobility of the MISFET. As shown in the graph, in the case of an n-channel MISFET using electrons as carriers, introduction of several atomic% of nitrogen at the interface improves carrier mobility compared to the case of not introducing nitrogen, but the nitrogen concentration is further increased. If so, the effect is gradually reduced. On the other hand, in the case of a p-channel MISFET using holes as carriers, the carrier mobility decreases almost in proportion to the nitrogen concentration at the interface, and when the nitrogen concentration exceeds 10 atomic%, the carrier mobility decreases by about 20%. As a result, the drain current (Ids) is reduced by about 10%, and circuit design becomes practically difficult.

  Thus, the method of introducing nitrogen into the silicon oxide film by oxynitriding has a limit in the amount of nitrogen introduced.

  In addition, as in the prior art described above, the technique for forming a silicon oxynitride film having a nitrogen concentration distribution having two peaks in the thickness direction performs high-temperature oxynitriding multiple times. As the film thickness increases, it is difficult to form a thin gate insulating film of 5 nm or less.

  An object of the present invention is to provide a technique capable of forming a silicon oxynitride film having a high nitrogen concentration in a semiconductor integrated circuit device in which a gate insulating film of a MISFET is composed of a silicon oxynitride film.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor integrated circuit device in which a gate insulating film of a MISFET is composed of a silicon oxynitride film.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor integrated circuit device according to one aspect of the present invention is a gate insulating film formed on a semiconductor substrate and made of a silicon oxide film into which nitrogen is introduced, and a gate electrode formed on the gate insulating film A semiconductor integrated circuit device having a field effect transistor comprising:
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The nitrogen concentration peak in the second region is higher than the nitrogen concentration peak in the first region.
(2) A semiconductor integrated circuit device according to another invention of the present application includes a gate insulating film formed on a semiconductor substrate and made of a silicon oxide film into which nitrogen is introduced, and a gate formed on the gate insulating film A semiconductor integrated circuit device having a field effect transistor including an electrode,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The peak of nitrogen concentration in the second region is higher than the peak of nitrogen concentration in the first region,
The gate insulating film has a thickness of 5 nm or less.
(3) A semiconductor integrated circuit device according to another invention of the present application includes a gate insulating film formed on a semiconductor substrate and made of a silicon oxide film into which nitrogen is introduced, and a gate formed on the gate insulating film A semiconductor integrated circuit device having a field effect transistor including an electrode,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The peak of nitrogen concentration in the second region is higher than the peak of nitrogen concentration in the first region,
The gate insulating film has a thickness of 5 nm or less,
The field effect transistor is a field effect transistor for selecting a DRAM memory cell.
(4) A semiconductor integrated circuit device according to another invention of the present application includes a gate insulating film formed on a semiconductor substrate and made of a silicon oxide film into which nitrogen is introduced, and a gate formed on the gate insulating film A semiconductor integrated circuit device having a field effect transistor comprising a part of a DRAM memory cell,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The peak of nitrogen concentration in the second region is higher than the peak of nitrogen concentration in the first region,
The gate insulating film has a thickness of 5 nm or less,
The gate electrode constitutes a word line of the memory cell and includes a polycrystalline silicon film, a refractory metal nitride film, and a refractory metal film,
One of a source region or a drain region of the field effect transistor is electrically connected to a bit line of the memory cell,
The other of the source region and the drain region of the field effect transistor is electrically connected to the capacitor element of the memory cell.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A high nitrogen concentration gate insulating film can be formed without increasing the nitrogen concentration in the vicinity of the interface between the substrate and the gate insulating film more than necessary.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. Also, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
A manufacturing method of the CMOS-LSI of this embodiment will be described in the order of steps with reference to FIGS.

  First, as shown in FIG. 1, an element isolation trench 2 is formed on the main surface of a semiconductor substrate (hereinafter referred to as substrate) 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm. In order to form the element isolation trench 2, first, the substrate 1 is thermally oxidized to form a silicon oxide film 30 having a thickness of about 10 nm on the surface thereof, and then a film thickness of 100 nm deposited on the silicon oxide film 30 by the CVD method. After patterning the silicon nitride film 31 to the extent, the substrate 1 is etched using the silicon nitride film 31 as a mask.

  Next, as shown in FIG. 2, a silicon oxide film 3 having a thickness of about 500 nm is deposited on the substrate 1 by a CVD method, and then the silicon oxide film 3 outside the element isolation trench 2 is formed by a chemical mechanical polishing method. After the removal, the silicon nitride film 31 on the substrate 1 is removed by wet etching using hot phosphoric acid. Thereafter, the silicon oxide film 3 inside the element isolation trench 2 is densified by heat-treating the substrate 1.

  Next, as shown in FIG. 3, the p-type well 4 is formed on a part of the main surface of the substrate 1, and the n-type well 5 is formed on the other part. In order to form the p-type well 4 and the n-type well 5, boron is ion-implanted into a part of the substrate 1, phosphorus is ion-implanted into the other part, and then the substrate 1 is heat-treated so that these impurities (boron And phosphorus) are diffused into the substrate 1.

  Next, after removing the silicon oxide film 30 on the surface of the substrate 1 by wet etching using hydrofluoric acid, the substrate 1 is wet-oxidized as shown in FIG. 4 to thereby form the p-type well 4 and the n-type well 5. A silicon oxide film 6a having a film thickness of 5 nm or less (3.0 nm in this embodiment) is formed on each surface. The silicon oxide film 6a may be formed by an oxidation method other than the wet oxidation method described above, for example, a dry oxidation method or a method of exposing the substrate 1 to an atmosphere containing active oxygen.

Next, the substrate 1 is heat-treated in an atmosphere of 900 ° C. to 1100 ° C. containing about 5% NO (nitrogen monoxide) gas. When this heat treatment is performed, nitrogen is introduced into the silicon oxide film 6a formed on the surface of the substrate 1, and the silicon oxide film 6a becomes the silicon oxynitride film 6b (FIG. 5). Note that the silicon oxynitride film 6b may be formed by heat-treating the substrate 1 in an atmosphere containing N ₂ O (nitrous oxide) gas instead of NO gas.

  FIG. 6 is a graph showing a nitrogen concentration profile in the silicon oxynitride film 6b formed by the heat treatment (oxynitriding treatment), and the horizontal axis shows the depth (nm) from the surface of the substrate 1. .

  As shown in the graph, the nitrogen concentration in the silicon oxynitride film 6b is the highest near the interface (depth 3.4 nm) between the silicon oxynitride film 6b and the substrate 1. This is because the reactivity of NO to silicon (Si) is low, so that NO introduced into the silicon oxide film 6a diffuses almost without reacting with silicon near the surface of the film and segregates at the interface with the substrate 1. It shows that

  When performing the above heat treatment (oxynitriding treatment), the heat treatment conditions are set so that the nitrogen concentration in the vicinity of the interface between the silicon oxynitride film 6b and the substrate 1 is in the range of 1 atomic% to 10 atomic%. When the nitrogen concentration in the vicinity of the interface exceeds 10 atomic%, the carrier mobility (Mobility) of the p-channel MISFET is reduced by about 20%, thereby reducing the drain current (Ids) by about 10%. It becomes practically difficult. On the other hand, when the nitrogen concentration in the vicinity of the interface is less than 1 atomic%, the effect of the oxynitriding treatment cannot be obtained.

  Next, nitrogen is further introduced into the silicon oxynitride film 6b by exposing the substrate 1 to a nitrogen plasma atmosphere. This nitrogen plasma treatment is performed, for example, using a known plasma processing apparatus that introduces a high frequency into a processing chamber in which a magnetic field coil is installed around and generates plasma by the interaction between an electric field and a magnetic field. Alternatively, a remote plasma processing apparatus that introduces plasma generated in a plasma generation chamber provided separately from the processing chamber into the processing chamber may be used.

  When the substrate 1 is accommodated in the processing chamber of the plasma processing apparatus and then nitrogen gas is introduced into the processing chamber, nitrogen radicals activated by the plasma are introduced into the silicon oxynitride film 6b and react with the silicon in the film. Then, the gate insulating film 6 made of silicon oxynitride having a higher nitrogen concentration than the silicon oxynitride film 6b is formed (FIG. 7).

  FIG. 8 is a graph showing a nitrogen concentration profile in the gate insulating film 6 made of silicon oxynitride formed by the above-described oxynitridation treatment and plasma treatment, and the horizontal axis represents the depth (nm) from the surface of the substrate 1. ).

  As shown in the graph, the nitrogen concentration in the gate insulating film 6 has a first peak concentration near the interface between the substrate 1 and the gate insulating film 6 and a second peak concentration near the surface of the gate insulating film 6. have. Nitrogen existing in the vicinity of the interface between the substrate 1 and the gate insulating film 6 is mainly nitrogen introduced by the oxynitriding process, and nitrogen existing in the vicinity of the surface of the gate insulating film 6 is mainly introduced by nitrogen plasma processing. Nitrogen. That is, active nitrogen introduced by the nitrogen plasma treatment has a higher reactivity with silicon than nitrogen introduced by the oxynitriding treatment, and most of them react with silicon near the surface of the silicon oxynitride film 6b. . On the other hand, as described above, since nitrogen introduced by the oxynitriding process has low reactivity, most of the nitrogen diffuses in the film and segregates at the interface with the substrate 1.

  Further, the higher the nitrogen concentration in the vicinity of the surface of the gate insulating film 6, the higher the leakage current reducing effect. Therefore, the nitrogen concentration in this region is the upper limit of the nitrogen concentration near the interface between the substrate 1 and the gate insulating film 6 ( Higher than 10 atomic%).

  The nitrogen plasma treatment is performed at a low temperature of 600 ° C. or lower in order to prevent nitrogen introduced into the film from diffusing up to the interface with the substrate 1. When the temperature of the substrate 1 is high, nitrogen may diffuse to the interface with the substrate 1 and exceed the above-described upper limit (10 atomic%) of the nitrogen concentration. On the other hand, even when the nitrogen plasma treatment is performed at room temperature, the temperature of the substrate 1 rises to about 200 ° C. by exposure to the plasma, so that it is heated to 200 ° C. or more from the viewpoint of ensuring process controllability. Is desirable.

  Note that the order of the oxynitriding treatment and the nitrogen plasma treatment may be opposite to the above-described order. That is, after performing nitrogen plasma treatment, oxynitridation treatment may be performed. However, since the oxynitriding process involves a heat treatment at a high temperature (900 ° C. to 1100 ° C.), if the oxynitriding process is performed after the nitrogen plasma process, the nitrogen in the vicinity of the surface of the gate insulating film 6 introduced by the nitrogen plasma process is used. Diffuses in the vicinity of the interface with the substrate 1 during the oxynitriding process, and there is a possibility that the nitrogen concentration in this region will be higher than necessary. Therefore, it is necessary to set the processing conditions in consideration of this point.

  Next, as shown in FIG. 9, a gate electrode conductive film 7 a is deposited on the gate insulating film 6. The gate electrode conductive film 7a is, for example, a laminated film (polycide film) of an n-type polycrystalline silicon film and a W (tungsten) silicide film deposited by the CVD method, or an n-type polycrystalline silicon film deposited by the CVD method and a sputtering method. A laminated film (polymetal film) of a tungsten nitride (WN) film and a W film deposited by the method is used.

  Next, as shown in FIG. 10, the gate electrode conductive film 7a is patterned by dry etching using the photoresist film 32 as a mask, so that the gate oxide film 6 on each of the p-type well 4 and the n-type well 5 is formed. Then, the gate electrode 7 is formed.

Next, after removing the photoresist film 32 on the gate electrode 7 by ashing (ashing) or the like, phosphorus or arsenic is ion-implanted into the p-type well 4 as shown in FIG. An n ⁻ type semiconductor region 8 is formed, and boron is ion-implanted into the n type well 5 to form a low impurity concentration p ⁻ type semiconductor region 9.

Next, a silicon nitride film is deposited on the substrate 1 by the CVD method, and then the silicon nitride film is anisotropically etched to form a sidewall spacer 10 on the side wall of the gate electrode 7, and then p-type. High impurity concentration n ⁺ type semiconductor regions 11 (source and drain) are formed by implanting phosphorus or arsenic into the well 4, and high impurity concentration p ⁺ type by implanting boron into the n type well 5. A semiconductor region 12 (source, drain) is formed. The n-channel MISFET (Qn) and p-channel MISFET (Qp) are completed through the steps so far.

Next, as shown in FIG. 12, the silicon oxide film 16 is dry-etched using the photoresist film 33 as a mask, so that the upper part of the source / drain (n ⁺ type semiconductor region 11) of the n-channel type MISFET (Qn) is obtained. In addition, contact holes 17 are formed above the source and drain (p ⁺ -type semiconductor region 12) of the p-channel MISFET (Qp), respectively.

  Next, after removing the photoresist film 33 on the silicon oxide film 16 by an ashing (ashing) process or the like, a sputtering method or the like is formed on the silicon oxide film 16 including the inside of the contact hole 17 as shown in FIG. A wiring metal film 18a is deposited using The wiring metal film 18a is composed of an Al alloy film or a composite metal film in which a Ti film or a TiN film is laminated on the lower and upper layers of the Al alloy film.

  Next, as shown in FIG. 14, after a photoresist film 34 is formed on the wiring metal film 18a, the wiring metal film 18a is dry-etched using the photoresist film 32 as a mask, thereby forming a silicon oxide film. A first layer metal wiring 18 made of a wiring metal film 18 a is formed on the upper portion 16.

  Next, after removing the photoresist film 34 on the metal wiring 18 by an ashing process or the like, a silicon oxide film 19 is deposited on the metal wiring 18 by a CVD method as shown in FIG. After the silicon oxide film 19 on the upper part of 18 is dry-etched to form a through hole 20, and a metal film for wiring is deposited on the silicon oxide film 19 including the inside of the through hole 20 by using a sputtering method or the like. The second metal wiring 21 is formed on the silicon oxide film 19 by dry etching the wiring metal film.

  Hereinafter, although not shown in the drawings, by repeating the above-described wiring formation process, the interlayer insulating film and the wiring are alternately formed on the second-layer metal wiring 21, thereby making the CMOS-LSI of the present embodiment. Complete.

  As described above, in the present embodiment, the gate insulating film 6 made of silicon oxynitride is formed by using both the oxynitriding treatment and the nitrogen plasma processing, and therefore, in the vicinity of the interface between the substrate 1 and the gate insulating film 6. The nitrogen concentration in the film can be increased without increasing the nitrogen concentration more than necessary.

  As a result, the gate dielectric film 6 having a high dielectric constant can be formed without reducing the carrier mobility of the p-channel MISFET (Qp), so that the MISFET (n-channel MISFET (Qn) and p-channel MISFET) can be formed. (Qp)) leakage current can be reduced. Further, it is possible to improve the hot carrier resistance of the MISFET (n-channel type MISFET (Qn) and p-channel type MISFET (Qp)) and the electron mobility of the n-channel type MISFET.

  In addition, since the oxynitridation process requiring high-temperature heat treatment is performed only once, excessive growth of the gate insulating film 6 is suppressed, and a thin gate insulating film 6 having a thickness of 5 nm or less can be realized.

(Embodiment 2)
The semiconductor integrated circuit device of this embodiment is a DRAM-logic mixed LSI in which a DRAM (Dynamic Random Access Memory) and a logic circuit are formed on the same semiconductor substrate. Hereinafter, a method for manufacturing the embedded LSI will be described in the order of steps with reference to FIGS. Note that the left and center regions in each figure indicate a DRAM memory cell formation region (hereinafter referred to as a DRAM formation region), and the right region indicates a logic circuit formation region.

  First, as shown in FIG. 16, the element isolation trench 2, the p-type well 4 and the n-type well 5 are formed on the main surface of the substrate 1 by the same method as in the first embodiment, and then the p-type well 4 is formed. After the silicon oxide film 6a is formed on the surface of each of the n-type well 5 and nitrogen is introduced into the silicon oxide film 6a by using the above-described oxynitridation treatment and nitrogen plasma treatment together, the p-type well 4 and A gate insulating film 6 made of silicon oxynitride and having a thickness of 1.5 nm is formed on each surface of the n-type well 5. The nitrogen concentration in the gate insulating film 6 has a first peak concentration in the vicinity of the interface with the substrate 1 as in the gate insulating film 6 in the first embodiment, and the first peak concentration in the vicinity of the surface of the film. Has a second peak concentration of a high concentration (10 atomic% or more).

  Next, as shown in FIG. 17, an n-type polycrystalline silicon film 13 n is formed on the gate insulating film 6 of the p-type well 4, and a p-type polycrystalline silicon film 13 p is formed on the gate insulating film 6 of the n-type well 5. Form. In order to form the n-type polycrystalline silicon film 13n and the p-type polycrystalline silicon film 13p, first, an amorphous silicon film is deposited on the gate insulating film 6 by the CVD method, and then the p-type using the photoresist film as a mask. After phosphorus is ion-implanted into the amorphous silicon film above the well 4 and boron is ion-implanted into the amorphous silicon film above the n-type well 5, the substrate 1 is heat-treated. These ion implantations are performed in order to make each of the n-channel MISFET constituting the DRAM memory cell, the n-channel MISFET and the p-channel MISFET constituting the logic circuit a surface channel type.

Next, as shown in FIG. 18, a polycrystalline silicon film (13p, 13n) after depositing a WN _X film 14 and W film 15 and the silicon nitride film 22 on top of, as shown in FIG. 19, a photoresist silicon nitride film 22 and the film 35 as a mask, W film 15, WN _X film 14 and the polycrystalline silicon film (13p, 13n) by sequentially dry-etched, the gate electrode 23a on the gate insulating film 6 in the DRAM formation region (Word line WL) is formed, and gate electrodes 23b and 23c are formed on the gate insulating film 6 in the logic circuit formation region.

Next, after removing the photoresist film 35, as shown in FIG. 20, phosphorus or arsenic is ion-implanted into the p-type well 4 to form a low impurity concentration n ⁻ -type semiconductor region 24, thereby forming an n-type well. 5 is formed to form a p ⁻ type semiconductor region 25 having a low impurity concentration.

Next, after a silicon nitride film 26 is deposited on the substrate 1 and the silicon nitride film 26 in the logic circuit formation region is anisotropically etched, side wall spacers 26s are formed on the side walls of the gate electrodes 23b and 23c. Then, phosphorus or arsenic is ion-implanted into the p-type well 4 in the logic circuit formation region to form a high impurity concentration n ⁺ -type semiconductor region 27 (source, drain), and boron is ion-implanted into the n-type well 5. As a result, a p ⁺ type semiconductor region 28 (source and drain) having a high impurity concentration is formed. The n-channel type MISFET (Qn) and p-channel type MISFET (Qp) of the logic circuit are completed through the steps up to here.

Next, as shown in FIG. 21, after depositing a silicon oxide film 40 on the gate electrodes 23a, 23b, and 23c, contact holes 41 and 42 are formed on the n ⁻ type semiconductor region 24 in the DRAM formation region. Subsequently, a plug 43 made of n-type polycrystalline silicon is formed inside the contact holes 41 and 42. Thereafter, the substrate 1 is heat-treated, and n-type impurities (phosphorus) in the polycrystalline silicon film constituting the plug 43 are diffused into the n ⁻ -type semiconductor region 24, thereby forming a low-resistance source and drain. Through the steps so far, the memory cell selection MISFET (Qt) is formed in the DRAM formation region.

Next, as shown in FIG. 22, after depositing a silicon oxide film 44 on top of the silicon oxide film 40, the silicon oxide films 44 and 40 in the logic circuit formation region are dry-etched to form an n-channel MISFET (Qn ), Contact holes 45 are formed above the source and drain (n ⁺ type semiconductor region 27), and contact holes 46 are formed above the source and drain of the p channel MISFET (Qp) (p ⁺ type semiconductor region 28). To do. Further, a through hole 47 is formed above the contact hole 41 by etching the silicon oxide film 44 in the DRAM formation region.

  Next, after the plugs 48 are formed inside the contact holes 45 and 46 and the through holes 47, the bit lines BL are formed on the silicon oxide film 44 in the DRAM formation region, and the silicon oxide film 44 in the logic circuit formation region is formed. Wirings 50 to 53 are formed in the upper part. The plug 48 is composed of, for example, a laminated film of a TiN film and a W film, and the bit line BL and the wirings 50 to 53 are composed of a W film.

The bit line BL is electrically connected to one of the source and drain (24) of the memory cell selection MISFET (Qt) through the through hole 47 and the contact hole 41. Further, the wirings 50 and 51 are electrically connected to the source and drain (n ⁺ type semiconductor region 27) of the n-channel type MISFET (Qn) through the contact holes 45 and 45, and the wirings 52 and 53 are connected to the contact hole 46, 46 is electrically connected to the source and drain (p ⁺ -type semiconductor region 28) of the p-channel type MISFET (Qp).

  Next, as shown in FIG. 23, a silicon oxide film 54 is deposited on the bit lines BL and the wirings 50 to 53, and then the silicon oxide films 54 and 44 on the contact holes 41 are etched to form through holes 55. Then, a plug 56 made of an n-type polycrystalline silicon film is formed inside the through hole 55. Next, after depositing a silicon nitride film 57 and a silicon oxide film 58 on the silicon oxide film 54, the silicon oxide film 58 and the silicon nitride film 57 above the through hole 55 are etched to form a groove 59.

Next, as shown in FIG. 24, a lower electrode 60 made of a polycrystalline silicon film is formed on the inner wall of the groove 59. In order to form the lower electrode 60, first, after depositing an n-type amorphous silicon film inside the trench 60 and on the silicon oxide film 58, an unnecessary amorphous silicon film on the silicon oxide film 58 is removed. Next, monosilane (SiH ₄ ) is supplied to the surface of the amorphous silicon film in a reduced-pressure atmosphere, and then the substrate 1 is heat-treated to polycrystallize the amorphous silicon film and grow silicon grains on the surface. As a result, the lower electrode 60 made of a polycrystalline silicon film having a roughened surface is obtained.

Next, as shown in FIG. 25, a capacitive insulating film 61 made of a Ta ₂ O ₅ (tantalum oxide) film is formed on the lower electrode 60 formed inside the trench 59. The Ta ₂ O ₅ film is deposited by the CVD method, and then the substrate 1 is heat-treated at 700 ° C. to 750 ° C. in order to modify the film.

As described above, the gate electrode 23c of the p-channel type MISFET (Qp) constituting a part of the logic circuit includes the p-type polycrystalline silicon film (13p) doped with boron, but the p-channel type MISFET. Since the (Qp) gate insulating film 6 is composed of a silicon oxynitride film having a high nitrogen concentration, a p-type polycrystalline silicon film (13p) can be obtained even if heat treatment for modifying the Ta ₂ O ₅ film is performed. Since boron therein can be prevented from passing through the gate insulating film 6 and diffusing into the substrate 1 (n-type well 5), fluctuations in the threshold voltage of the p-channel MISFET (Qp) can be suppressed.

  Next, as shown in FIG. 26, an upper electrode 62 made of, for example, TiN is formed on the capacitor insulating film 61 to thereby form an information storage capacitor element C made up of the lower electrode 60, the capacitor insulating film 61 and the upper electrode 62. Form. Through the steps up to here, a DRAM memory cell comprising the memory cell selection MISFET (Qt) and the information storage capacitor C connected in series is completed.

The capacitive insulating film 61 of the information storage capacitive element C may be a perovskite type, such as PZT, PLT, PLZT, PbTiO ₃ , SrTiO ₃ , BaTiO ₃ , BST, SBT, or Ta ₂ O ₅ in addition to a Ta ₂ O ₅ film. You may comprise with the high dielectric material film or ferroelectric film which has a compound perovskite type crystal structure. Further, the lower electrode 60 may be made of a platinum group metal film such as Ru or Pt in addition to the polycrystalline silicon film. When the capacitive insulating film 61 is composed of the high dielectric film or the ferroelectric film, and when the lower electrode 60 is composed of the platinum group metal film, the heat treatment for modifying the film after film formation is performed. However, since the gate insulating film 6 of the p-channel type MISFET (Qp) is made of a silicon oxynitride film having a high nitrogen concentration, the p-type polycrystalline silicon film (13p) can be obtained even if these heat treatments are performed. Since boron therein can be prevented from passing through the gate insulating film 6 and diffusing into the substrate 1 (n-type well 5), fluctuations in the threshold voltage of the p-channel MISFET (Qp) can be suppressed.

  Although not shown, after that, an Al wiring of about two layers is formed on the information storage capacitor C with an interlayer insulating film made of a silicon oxide film interposed therebetween, and a silicon nitride film and a silicon oxide are further formed on the Al wiring. By forming a passivation film composed of a laminated film with the film, the DRAM-logic mixed LSI of this embodiment is completed.

  According to the present embodiment, since the gate insulating film 6 made of silicon oxynitride is formed by using both the oxynitriding treatment and the nitrogen plasma processing, the nitrogen concentration in the vicinity of the interface between the substrate 1 and the gate insulating film 6 is formed. The nitrogen concentration in the film can be increased without increasing the value more than necessary.

  As a result, the gate dielectric film 6 having a high dielectric constant can be formed without reducing the carrier mobility of the p-channel MISFET (Qp), so that the leakage current of the MISFET can be reduced. Further, the hot carrier resistance of the MISFET and the electron mobility of the n-channel MISFET can be improved. Furthermore, fluctuations in the threshold voltage of the p-channel MISFET (Qp) due to boron leakage can be suppressed.

  In addition, since the oxynitridation process requiring high-temperature heat treatment is performed only once, excessive growth of the gate insulating film 6 is suppressed, and a thin gate insulating film 6 having a thickness of 5 nm or less can be realized.

(Embodiment 3)
A method for forming a gate insulating film according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 27, the element isolation trench 2, the p-type well 4 and the n-type well 5 are formed on the main surface of the substrate 1 by the same method as in the first embodiment, and then the substrate 1 is wetted. By oxidation, a silicon oxide film 6a having a thickness of about 1 nm to 1.5 nm is formed on the surface of each of the p-type well 4 and the n-type well 5.

  Next, as shown in FIG. 28, the substrate 1 is heat-treated in an atmosphere of 900 ° C. to 1100 ° C. containing about 5% NO gas. When this heat treatment is performed, nitrogen is introduced into the silicon oxide film 6a formed on the surface of the substrate 1, and the silicon oxynitride film 6b in which nitrogen is segregated in the vicinity of the interface with the substrate 1 as in the first embodiment. Is formed. When performing the above heat treatment (oxynitriding), the nitrogen concentration in the vicinity of the interface between the silicon oxynitride film 6b and the substrate 1 is in the range of 1 atomic% to 10 atomic%, as in the first embodiment. Set heat treatment conditions.

  Next, as shown in FIG. 29, a silicon oxynitride film 6b and a silicon nitride film 6c are deposited on the silicon oxynitride film 6b by depositing a silicon nitride film 6c having a thickness of about 1 nm to 1.5 nm by a CVD method. Thus, a gate insulating film 70 composed of the laminated film is obtained.

  The gate insulating film 70 composed of the laminated film of the silicon oxynitride film 6b and the silicon nitride film 6c is composed of the silicon nitride film 6c on the surface side, so that the nitrogen segregates near the interface with the substrate 1. The dielectric constant is higher than that of the gate insulating film composed only of the silicon nitride film 6b.

  Thus, by forming the gate insulating film 70 with the laminated film of the silicon oxynitride film 6b and the silicon nitride film 6c, a high dielectric constant can be obtained without unnecessarily increasing the nitrogen concentration in the vicinity of the interface with the substrate 1. The gate insulating film 70 can be realized.

  Thus, the leakage current of the MISFET can be reduced without reducing the carrier mobility of the p-channel type MISFET (Qp). Further, the hot carrier resistance of the MISFET and the electron mobility of the n-channel MISFET can be improved. Furthermore, fluctuations in the threshold voltage of the p-channel MISFET (Qp) due to boron leakage can be suppressed.

  In addition, since the oxynitridation process requiring high-temperature heat treatment is performed only once, excessive growth of the gate insulating film 70 is suppressed, and a thin gate insulating film 70 having a thickness of 5 nm or less can be realized.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a semiconductor integrated circuit device having a MISFET (field effect transistor).

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a graph which shows the nitrogen concentration profile in the silicon oxynitride film | membrane formed by the oxynitriding process. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is a graph which shows the nitrogen concentration profile in the gate insulating film which consists of a silicon oxynitride formed by the oxynitridation process and the plasma process. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor integrated circuit device which is other embodiment of this invention. It is a graph which shows the relationship between the nitrogen concentration in the interface of a gate insulating film and a board | substrate, and the carrier mobility of MISFET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 Silicon oxide film 4 P type well 5 N type well 6a Silicon oxide film 6b Silicon oxynitride film 6c Silicon nitride film 6 Gate insulating film 7a Conductive film for gate electrode 7 Gate electrode 8 n ^- type semiconductor Region 9 p ⁻ type semiconductor region 10 Side wall spacer 11 n ⁺ type semiconductor region (source, drain)
12 p ⁺ type semiconductor region (source, drain)
13n n-type polycrystalline silicon film 13p p-type polycrystalline silicon film 14 WN _X film 15 W film 16 silicon oxide film 17 contact hole 18a wiring metal film 18 metal wiring 19 silicon oxide film 20 through hole 21 metal wiring 22 silicon nitride film 23a, 23b, 23c Gate electrode 24 n ⁻ type semiconductor region 25 p ⁻ type semiconductor region 26 Silicon nitride film 26s Side wall spacer 27 n ⁺ type semiconductor region (source, drain)
28 p ⁺ type semiconductor region (source, drain)
30 Silicon oxide film 31 Silicon nitride film 32-35 Photoresist film 40 Silicon oxide film 41, 42 Contact hole 43 Plug 44 Silicon oxide film 45, 46 Contact hole 47 Through hole 48 Plug 50-53 Wiring 54 Silicon oxide film 55 Through hole 56 plug 57 silicon nitride film 58 silicon oxide film 59 groove 60 lower electrode 61 capacitive insulating film 62 upper electrode 70 gate insulating film BL bit line C information storage capacitive element Qn n-channel MISFET
Qp p-channel MISFET
Qt MISFET for memory cell selection
WL Word line

Claims (8)

A semiconductor integrated circuit device having a field effect transistor formed on a semiconductor substrate and including a gate insulating film made of a silicon oxide film into which nitrogen is introduced, and a gate electrode formed on the gate insulating film. ,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
2. The semiconductor integrated circuit device according to claim 1, wherein a peak of nitrogen concentration in the second region is higher than a peak of nitrogen concentration in the first region. A semiconductor integrated circuit device having a field effect transistor formed on a semiconductor substrate and including a gate insulating film made of a silicon oxide film into which nitrogen is introduced, and a gate electrode formed on the gate insulating film. ,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The peak of nitrogen concentration in the second region is higher than the peak of nitrogen concentration in the first region,
A semiconductor integrated circuit device, wherein the gate insulating film has a thickness of 5 nm or less. A semiconductor integrated circuit device having a field effect transistor formed on a semiconductor substrate and including a gate insulating film made of a silicon oxide film into which nitrogen is introduced, and a gate electrode formed on the gate insulating film. ,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The peak of nitrogen concentration in the second region is higher than the peak of nitrogen concentration in the first region,
The gate insulating film has a thickness of 5 nm or less,
2. The semiconductor integrated circuit device according to claim 1, wherein the field effect transistor is a field effect transistor for selecting a DRAM memory cell. An electric field comprising a gate insulating film formed on a semiconductor substrate and made of a silicon oxide film into which nitrogen is introduced, and a gate electrode formed on the gate insulating film, and constituting a part of a DRAM memory cell A semiconductor integrated circuit device having an effect transistor,
The gate insulating film has different nitrogen concentration peaks in a first region closer to the semiconductor substrate and a second region closer to the gate electrode than the first region,
The peak of the nitrogen concentration in the first region is 2.5 atomic% to 10 atomic%,
The peak of nitrogen concentration in the second region is higher than the peak of nitrogen concentration in the first region,
The gate insulating film has a thickness of 5 nm or less,
The gate electrode constitutes a word line of the memory cell and includes a polycrystalline silicon film, a refractory metal nitride film, and a refractory metal film,
One of a source region or a drain region of the field effect transistor is electrically connected to a bit line of the memory cell,
2. The semiconductor integrated circuit device according to claim 1, wherein the other of the source region and the drain region of the field effect transistor is electrically connected to the capacitor element of the memory cell. The semiconductor integrated circuit device according to claim 4.
The semiconductor integrated circuit device, wherein the refractory metal film is tungsten. The semiconductor integrated circuit device according to claim 4 or 5,
The semiconductor integrated circuit device, wherein the refractory metal nitride film is tungsten nitride. The semiconductor integrated circuit device according to any one of claims 1 to 6,
The semiconductor integrated circuit device, wherein the field effect transistor is an n-channel field effect transistor. The semiconductor integrated circuit device according to claim 7,
The semiconductor integrated circuit device, wherein the gate electrode includes a polycrystalline silicon film into which an n-type impurity is introduced.

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