JP2009071155A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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JP2009071155A
JP2009071155A JP2007239555A JP2007239555A JP2009071155A JP 2009071155 A JP2009071155 A JP 2009071155A JP 2007239555 A JP2007239555 A JP 2007239555A JP 2007239555 A JP2007239555 A JP 2007239555A JP 2009071155 A JP2009071155 A JP 2009071155A
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adhesive layer
semiconductor element
circuit board
semi
semiconductor device
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JP5104149B2 (en
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Taiji Sakai
泰治 酒井
Seiki Sakuyama
誠樹 作山
Daisuke Mizutani
大輔 水谷
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Fujitsu Ltd
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Fujitsu Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To form an adhesive layer between a semiconductor element and a circuit board into a shape whose bottom is spread enough toward the circuit board, when the semiconductor element is mounted on the circuit board. <P>SOLUTION: In a method for manufacturing a semiconductor device, a first adhesive layer 12 is beforehand formed at the periphery of a mounting position of the semiconductor element 13 on the circuit board 11 on which the semiconductor element is mounted. Further a second adhesive layer 15 is beforehand formed on the mounting surface of the semiconductor element. The semiconductor element is arranged on the circuit board, and the first adhesive layer and the second adhesive layer are melted and integrated to form a fillet 16. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、広くは半導体の技術分野に関し、特に、半導体素子(チップ)と回路基板との間の接合性を向上するための技術に関する。   The present invention relates generally to the technical field of semiconductors, and more particularly to a technique for improving the bonding between a semiconductor element (chip) and a circuit board.

近年、携帯機器、特に携帯電話やノート型パソコン等の小型化、薄型化、高性能化に伴って、搭載される半導体装置にも、さらなる小型化、薄型化が要求されている。このような小型化、薄型化への要請に応じて、回路基板と、これにフリップチップ接合される半導体素子(チップ)との間のギャップも小さくなり、接合後に封止趣旨を後入れ方式で注入するのが困難になってきている。   In recent years, along with downsizing, thinning, and high performance of mobile devices, particularly mobile phones and laptop computers, there is a demand for further downsizing and thinning of mounted semiconductor devices. In response to such demands for miniaturization and thinning, the gap between the circuit board and the semiconductor element (chip) that is flip-chip bonded to the circuit board is also reduced. It has become difficult to inject.

この問題に対処するため、あらかじめ半導体チップ側、又は回路基板側に半硬化の封止樹脂層を形成しておき、電極と封止樹脂を一括してフリップチップ接合する方式(「先アンダーフィル方式」と称する)が多用されてきている。   In order to cope with this problem, a semi-cured sealing resin layer is formed on the semiconductor chip side or circuit board side in advance, and the electrode and the sealing resin are collectively flip-chip bonded (the “first underfill method” ")" Has been widely used.

図1(a)は、一般的な先アンダーフィル方式のチップ接合を説明するための概略図である。この例では、接合に先立って、突起電極104が形成された半導体チップ103側に、半硬化状態の封止樹脂層105が形成されている。回路基板101上へ実装する際には、半導体チップ103を逆さにして、突起電極104が回路基板101上のパッド電極108上に位置するように、フリップチップ接合する。   FIG. 1A is a schematic diagram for explaining general tip-underfill type chip bonding. In this example, a semi-cured sealing resin layer 105 is formed on the semiconductor chip 103 side where the protruding electrodes 104 are formed prior to bonding. When mounting on the circuit board 101, the semiconductor chip 103 is turned upside down and flip-chip bonded so that the protruding electrode 104 is positioned on the pad electrode 108 on the circuit board 101.

しかし、この方法では以下の問題がある。すなわち、あらかじめ半導体チップ103側に半硬化封止樹脂層105を設けておくと、ウェーハの輸送やダイシングプロセスなどを経るため、半硬化封止樹脂層105の硬化が進行し、フリップチップ接合時に流動性が低下する。この結果、図1(A)で破線のサークルCで示すように、樹脂層105が横方向に膨らんではみ出してしまい、フィレットと呼ばれる樹脂だまりの形成が、十分になされない。   However, this method has the following problems. That is, if the semi-cured encapsulating resin layer 105 is provided in advance on the semiconductor chip 103 side, the semi-cured encapsulating resin layer 105 is cured due to a wafer transport, a dicing process, and the like, and flows at the time of flip chip bonding. Sex is reduced. As a result, as indicated by a broken-line circle C in FIG. 1A, the resin layer 105 swells and protrudes in the lateral direction, and a resin pool called a fillet is not sufficiently formed.

フィレットは、半導体素子103と回路基板101との密着性を確保し、接続信頼性を向上させるために有効な構造である。図1(B)に理想的なフィレット106の形状を示す。理想的なフィレット106は、サークルAで示すように、半導体チップ103の端面を確実に覆い、滑らかに裾を引くように回路基板101側に拡がる形状を有する。このような形状だと、熱膨張係数の相違等に起因して半導体チップ103や回路基板101に反りが生じる場合でも、両者の接合を安定して保持することができるからである。   The fillet is an effective structure for ensuring the adhesion between the semiconductor element 103 and the circuit board 101 and improving the connection reliability. FIG. 1B shows an ideal fillet 106 shape. The ideal fillet 106 has a shape that reliably covers the end face of the semiconductor chip 103 and expands toward the circuit board 101 so as to draw a skirt smoothly, as indicated by a circle A. This is because, with such a shape, even when the semiconductor chip 103 or the circuit board 101 is warped due to a difference in thermal expansion coefficient or the like, the bonding between the two can be stably held.

半導体チップの外周端面にも濡れ拡がる良好なフィレットを形成するために、あらかじめ回路基板側の半導体搭載位置の内部領域に半硬化樹脂を形成しておくと同時に、半導体チップの端面にも樹脂を形成しておき、フリップチップ接合時に、チップ端面の樹脂と、回路基板上の半硬化樹脂とを融合させてフィレットを形成する方法が提案されている(たとえば、特許文献1参照)。   In order to form a good fillet that also spreads on the outer peripheral end face of the semiconductor chip, a semi-cured resin is formed in advance on the internal area of the semiconductor mounting position on the circuit board side, and at the same time, a resin is also formed on the end face of the semiconductor chip. In addition, a method has been proposed in which a fillet is formed by fusing a resin on a chip end surface and a semi-cured resin on a circuit board at the time of flip chip bonding (see, for example, Patent Document 1).

しかし、この方法では、半導体チップの端面をカバーすることはできるが、回路基板上での末広がりの裾の部分の形成については考慮されていない。言い換えると、半導体チップの端面部分に関しては、あらかじめ樹脂を配置しておくことで、制御されたフィレットが形成されるが、裾部分のフィレット、すなわち、回路基板近傍のフィレットの形状を制御することは難しい。   However, this method can cover the end face of the semiconductor chip, but does not take into account the formation of the flared hem portion on the circuit board. In other words, with respect to the end face portion of the semiconductor chip, a controlled fillet is formed by arranging the resin in advance, but it is possible to control the shape of the fillet in the bottom portion, that is, the fillet near the circuit board. difficult.

また、一般に、フリップチップ接合時のツールとステージの傾きなどにより、フィレットが均一に形成されないことが多く、裾部分でのフィレットの形状を制御するのは、いっそう困難である。フィレットの裾が十分に形成されない場合は、半導体チップと回路基板の接合が不十分になり、接合信頼性を満足することができない。
特開2006−32625号公報
In general, the fillet is often not uniformly formed due to the tilt of the tool and stage during flip chip bonding, and it is even more difficult to control the shape of the fillet at the skirt. When the fillet skirt is not sufficiently formed, the bonding between the semiconductor chip and the circuit board becomes insufficient, and the bonding reliability cannot be satisfied.
JP 2006-32625 A

そこで、本発明は上記の問題点に鑑みて、必要な範囲に必要な量のフィレットを良好な形状で形成する方法を提供することを課題とする。   Therefore, in view of the above-described problems, an object of the present invention is to provide a method for forming a necessary amount of fillets within a necessary range in a good shape.

上記課題を解決するために、第1の側面では、半導体装置の製造方法を提供する。この方法は、
(a)半導体素子を実装する回路基板の、前記半導体素子の実装位置の外周にあらかじめ第1の接着層を形成し、
(b)前記半導体素子の実装面に、あらかじめ第2の接着層を形成し、
(c)前記半導体素子を前記回路基板上に配置し、前記第1の接着層と前記第2の接着層とを溶融・一体化してフィレットを形成する、
工程を含む。
In order to solve the above problems, according to a first aspect, a method for manufacturing a semiconductor device is provided. This method
(A) forming a first adhesive layer in advance on the outer periphery of the mounting position of the semiconductor element of the circuit board on which the semiconductor element is mounted;
(B) forming a second adhesive layer in advance on the mounting surface of the semiconductor element;
(C) disposing the semiconductor element on the circuit board and fusing and integrating the first adhesive layer and the second adhesive layer to form a fillet;
Process.

好ましい実施例では、前記第1接着層は、前記半導体素子の実装位置から所定の間隔、たとえば、10〜20μmの間隔をあけて形成される。   In a preferred embodiment, the first adhesive layer is formed at a predetermined interval from the mounting position of the semiconductor element, for example, 10 to 20 μm.

また別の良好な実施例では、前記第1の接着層は、前記半導体素子の実装位置のコーナー近傍での樹脂量が、その他の部分よりも多くなるように形成される。   In another preferred embodiment, the first adhesive layer is formed so that the amount of resin in the vicinity of the corner of the mounting position of the semiconductor element is larger than that of other portions.

いずれの場合も、前記第1の接着層と前記第2の接着層は、互いに相溶性があることが望ましい。   In any case, it is desirable that the first adhesive layer and the second adhesive layer are compatible with each other.

第2の側面では、半導体素子を回路基板上に実装した半導体装置を提供する。この半導体装置において、前記半導体素子と前記回路基板の間に位置する接着層を有し、前記接着層は、前記半導体素子の外周端面を覆い、かつ前記回路基板に向かって裾が拡がる形状を有し、前記接着層に含まれる充填剤の濃度分布が、前記裾拡がりの部分の端部に向かうほど低くなっていることを特徴とする。   In a second aspect, a semiconductor device having a semiconductor element mounted on a circuit board is provided. The semiconductor device includes an adhesive layer positioned between the semiconductor element and the circuit board, and the adhesive layer has a shape that covers an outer peripheral end surface of the semiconductor element and has a hem that extends toward the circuit board. And the density | concentration distribution of the filler contained in the said contact bonding layer becomes low, so that it goes to the edge part of the said skirt expansion part.

一実施例では、前記半導体素子は、前記回路基板にフリップチップ接合されている。   In one embodiment, the semiconductor element is flip-chip bonded to the circuit board.

半導体素子(チップ)と回路基板の間の接合信頼性を確保することができる。   Bonding reliability between the semiconductor element (chip) and the circuit board can be ensured.

以下、添付図面を参照して、本発明の良好な実施形態を説明する。図2は、本発明の一実施形態にかかる半導体装置の製造工程図であり、図3は、半導体チップ実装前と実装後の平面図である。まず、図2(A)に示すように、回路基板としてのビルトアップ基板11のフィレットが形成されるべき箇所に、基板側接着層としての半硬化封止樹脂層12を形成する。ここでは、エポキシ樹脂を主成分とする半硬化樹脂を用いた。その他の樹脂材料として、シアネートエステル樹脂、フェノキシ樹脂、ウレタン系樹脂、あるいはこれらを主成分とする樹脂を用いることができる。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings. FIG. 2 is a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a plan view before and after mounting a semiconductor chip. First, as shown in FIG. 2A, a semi-cured sealing resin layer 12 as a substrate-side adhesive layer is formed at a place where a fillet of a built-up substrate 11 as a circuit board is to be formed. Here, a semi-cured resin mainly composed of an epoxy resin was used. As other resin materials, a cyanate ester resin, a phenoxy resin, a urethane resin, or a resin containing these as a main component can be used.

ビルトアップ基板11上に形成される半硬化封止樹脂層12の粘度は、接合時に100〜500Pa・sとなって、半導体チップ側の接合面に形成される樹脂層15(図2(B)参照)と融合しやすくなるように調整される。一般に樹脂の粘度は、温度によって大きく変化するので、接合温度を制御することで半硬化封止樹脂層12の粘度を調整することができる。その他の粘度調整方法として、ビルトアップ基板11側に形成する半硬化封止樹脂層12のシリカ含有量を低く、たとえば0〜40wt%に設定しておくことで流動性を確保することもできる。   The viscosity of the semi-cured sealing resin layer 12 formed on the built-up substrate 11 is 100 to 500 Pa · s at the time of bonding, and the resin layer 15 formed on the bonding surface on the semiconductor chip side (FIG. 2B) Adjustment) so that it can be easily integrated. In general, the viscosity of the resin greatly varies depending on the temperature. Therefore, the viscosity of the semi-cured sealing resin layer 12 can be adjusted by controlling the bonding temperature. As another viscosity adjusting method, the fluidity can be ensured by setting the silica content of the semi-cured sealing resin layer 12 formed on the built-up substrate 11 side to be low, for example, 0 to 40 wt%.

ビルトアップ基板11上への封止樹脂層12の形成には、武蔵エンジニアリング製のディスペンサー装置(FAD320s)を用いた。ディスペンサー装置では、塗布圧、塗布速度、塗布時間を調整することで、樹脂量を精度よく制御することができる。   For the formation of the sealing resin layer 12 on the built-up substrate 11, a dispenser device (FAD320s) manufactured by Musashi Engineering was used. In the dispenser device, the amount of resin can be accurately controlled by adjusting the coating pressure, coating speed, and coating time.

図3(A)は、ビルトアップ基板11上への半硬化封止樹脂12の塗布例1を示す図である。この例では、点線で示す半導体チップ実装位置の外側に均一な幅で半硬化封止樹脂層12を形成する。このとき、フリップチップ接合時にビルトアップ基板11側の半硬化封止樹脂12と、半導体チップ13との干渉を避けるため、チップ実装位置と半硬化封止樹脂層12との間に、ギャップ(間隙)Gを設定しておく。フリップチップボンダの搭載精度を考慮すると、10〜20μmのギャップGを設けておくのが望ましい。   FIG. 3A is a diagram illustrating an application example 1 of the semi-cured sealing resin 12 on the built-up substrate 11. In this example, the semi-cured sealing resin layer 12 is formed with a uniform width outside the semiconductor chip mounting position indicated by the dotted line. At this time, in order to avoid interference between the semi-cured sealing resin 12 on the built-up substrate 11 side and the semiconductor chip 13 at the time of flip chip bonding, a gap (gap) is formed between the chip mounting position and the semi-cured sealing resin layer 12. ) Set G. Considering the mounting accuracy of the flip chip bonder, it is desirable to provide a gap G of 10 to 20 μm.

図2(B)に戻って、あらかじめ半硬化封止樹脂層12が形成された基板11上に、同じくあらかじめ半硬化封止樹脂層15が形成された半導体チップ13を、フリップチップ接合する。チップ13側の半硬化封止樹脂層15は、エポキシ樹脂、フェノキシ樹脂、ウレタン系樹脂、あるいはこれらを主成分とする樹脂を用いることができるが、ビルトアップ基板11側の半硬化封止樹脂12と互いに相溶性のある材料を選択する。接合に先立って、半導体チップ13の突起電極14が、ビルトアップ基板11上に形成されたパッド電極18上に位置するように半導体チップ13を位置決めする。   Referring back to FIG. 2B, the semiconductor chip 13 on which the semi-cured sealing resin layer 15 has been formed in advance is flip-chip bonded onto the substrate 11 on which the semi-cured sealing resin layer 12 has been formed in advance. For the semi-cured sealing resin layer 15 on the chip 13 side, an epoxy resin, a phenoxy resin, a urethane resin, or a resin containing these as a main component can be used, but the semi-cured sealing resin 12 on the built-up substrate 11 side. Select materials that are compatible with each other. Prior to bonding, the semiconductor chip 13 is positioned so that the protruding electrode 14 of the semiconductor chip 13 is positioned on the pad electrode 18 formed on the built-up substrate 11.

接合条件は、用いる電極材料の組み合わせや超音波の印加の有無などによって任意に設定することができる。たとえば、基板11側のパッド電極18にNi/Au電極、半導体チップ13側の突起電極14に、台座径30μmのAuスタッドバンプ又はワイヤバンプを用い、熱圧着によって接合させる場合、220℃、20sec、バンプ当たりの圧力が15gfの条件で、上段の半導体チップ13がビルトアップ基板11に接合される。熱圧着以外にも、溶融接続、超音波接続などの接合方法を用いてもよい。   The bonding conditions can be arbitrarily set depending on the combination of electrode materials to be used and the presence / absence of application of ultrasonic waves. For example, when a Ni / Au electrode is used for the pad electrode 18 on the substrate 11 side and an Au stud bump or wire bump with a pedestal diameter of 30 μm is used for the protruding electrode 14 on the semiconductor chip 13 side and bonded by thermocompression bonding, 220 ° C., 20 sec, bump The upper semiconductor chip 13 is bonded to the built-up substrate 11 under the condition that the hit pressure is 15 gf. In addition to thermocompression bonding, a joining method such as fusion connection or ultrasonic connection may be used.

このとき、接合時の圧力によって、半導体チップ13側の半硬化封止樹脂層15が矢印で示すように外側に向かって押し出され、同時に、接合温度によって、半導体チップ13側の封止樹脂層15と基板11側の封止樹脂層12が溶融し、一体化する。その結果、図2(C)に示すように、半導体チップ13の端部をカバーし、かつサークルBで示すように、十分な裾を持ったフィレット16が形成される。すなわち、図3(B)の平面図で示すように、半導体チップ13のエッジから外側に向けて、隙間なく均一に拡がるフィレット16が形成される。これにより、接合の信頼性が確保される。   At this time, the semi-cured sealing resin layer 15 on the semiconductor chip 13 side is pushed outward as indicated by an arrow by the pressure during bonding, and at the same time, the sealing resin layer 15 on the semiconductor chip 13 side is pressed by the bonding temperature. And the sealing resin layer 12 on the substrate 11 side are melted and integrated. As a result, as shown in FIG. 2C, a fillet 16 that covers the end of the semiconductor chip 13 and has a sufficient hem as shown by the circle B is formed. That is, as shown in the plan view of FIG. 3B, a fillet 16 is formed that extends uniformly from the edge of the semiconductor chip 13 toward the outside without a gap. Thereby, the reliability of joining is ensured.

図2および図3の例では、半導体チップ13はフリップチップ接合されるので、電極間の接続と同時に、半導体チップ13をビルトアップ基板11に接着するフィレット16を形成することができる。   2 and 3, since the semiconductor chip 13 is flip-chip bonded, the fillet 16 for bonding the semiconductor chip 13 to the built-up substrate 11 can be formed simultaneously with the connection between the electrodes.

なお、半導体チップ13側の半硬化封止樹脂層15と、ビルトアップ基板11側の半硬化封止樹脂層12のいずれか一方または双方がシリカフィラーを含有する場合は、これらの樹脂層の溶融・一体化の結果、シリカフィラーの含有量が、フィレット16の端に向かうほど少なくなるグラデーション構造となる。これはシリカフィラーよりも、それ以外の樹脂成分の流動性の方が高いので、フィレット16の裾の端部に向かうほど、シリカフィラーの含有量が少なくなるからである。   In addition, when one or both of the semi-cured encapsulating resin layer 15 on the semiconductor chip 13 side and the semi-cured encapsulating resin layer 12 on the built-up substrate 11 side contain a silica filler, these resin layers are melted. As a result of integration, a gradation structure in which the content of the silica filler decreases toward the end of the fillet 16 is obtained. This is because the fluidity of the other resin components is higher than that of the silica filler, so that the content of the silica filler decreases toward the end of the bottom of the fillet 16.

最後に、接合された半導体チップ13とビルトアップ基板11をオーブンでベークして(たとえば170℃、1.5時間の条件で)、封止樹脂(フィレット)が硬化され、半導体装置10が完成する。   Finally, the bonded semiconductor chip 13 and built-up substrate 11 are baked in an oven (for example, at 170 ° C. for 1.5 hours), the sealing resin (fillet) is cured, and the semiconductor device 10 is completed. .

図4(A)および図4(B)は、ビルトアップ基板11上への半硬化封止樹脂層22の塗布例2を示す図である。図4の例では、破線で示すチップ実装位置のコーナー間の中央部分に対応する領域で、半硬化封止樹脂層22の幅が狭く、コーナー付近で幅が広くなるように、半硬化封止樹脂層22が形成されている。この場合も、半硬化封止樹脂層22と半導体チップ実装位置との間に、ギャップGを設定しておく。   4 (A) and 4 (B) are diagrams showing an application example 2 of the semi-cured sealing resin layer 22 on the built-up substrate 11. In the example of FIG. 4, the semi-cured sealing is performed so that the width of the semi-cured encapsulating resin layer 22 is narrow and wide near the corner in the region corresponding to the central portion between the corners of the chip mounting position indicated by the broken line. A resin layer 22 is formed. Also in this case, a gap G is set between the semi-cured sealing resin layer 22 and the semiconductor chip mounting position.

図4(A)の半硬化封止樹脂層22の塗布形状は、半硬化封止樹脂層22の塗布圧を30〜100kPaの範囲で一定にし、かつ、各コーナー部で保持する時間を0.5s〜1.0sec程度設けることによって、実現することができる。また、フリップチップ接合時の半硬化封止樹脂層22と半導体チップ13との干渉を防止するためのギャップGは、フリップチップボンダの搭載精度を考慮して、10〜20μmとする。この場合のギャップGは、半硬化封止樹脂層22の中央のくびれ部分が、半導体チップ実装位置から10〜20μm離れるように設定される。   The application shape of the semi-cured encapsulating resin layer 22 in FIG. 4 (A) is such that the application pressure of the semi-cured encapsulating resin layer 22 is constant in the range of 30 to 100 kPa, and the time for holding at each corner is 0.00. It can be realized by providing about 5 s to 1.0 sec. Further, the gap G for preventing the interference between the semi-cured sealing resin layer 22 and the semiconductor chip 13 at the time of flip chip bonding is set to 10 to 20 μm in consideration of the mounting accuracy of the flip chip bonder. In this case, the gap G is set such that the constricted portion at the center of the semi-cured sealing resin layer 22 is 10 to 20 μm away from the semiconductor chip mounting position.

半硬化封止樹脂層22をこのような形状とするのは、半導体チップ13を接合する際の圧力の印加によって、半導体チップ13のコーナー部分よりも、各エッジの中央部分からの封止樹脂の流出量が多くなる場合が多いからである。   The semi-cured sealing resin layer 22 has such a shape because the sealing resin from the central portion of each edge rather than the corner portion of the semiconductor chip 13 is applied by applying pressure when the semiconductor chip 13 is bonded. This is because the amount of outflow often increases.

半硬化封止樹脂22の平面塗布形状は、図4(A)の例に限定されず、樹脂量がコーナー部分で多くなるのであれば、任意の塗布形状を選択できる。たとえば、半硬化封止樹脂層22の内側(チップ13に対向する側)では、中央部がくびれるように湾曲し、一方、半硬化封止樹脂層22の外側(基板11の端部に対向する側)では、直線状に延びるように形成してもよい。   The planar application shape of the semi-cured sealing resin 22 is not limited to the example in FIG. 4A, and any application shape can be selected as long as the amount of resin increases at the corner portion. For example, on the inner side of the semi-cured sealing resin layer 22 (side facing the chip 13), the central portion is curved so as to be constricted, while on the other hand, the outer side of the semi-cured sealing resin layer 22 (opposite the end of the substrate 11). (Side), it may be formed to extend linearly.

半硬化封止樹脂層22の材料としては、上述したように、エポキシ樹脂、シアネートエステル樹脂、フェノキシ樹脂、ウレタン系樹脂、あるいはこれらを主成分とする樹脂である。また、シリカ含有量は、チップ接合時の流動性を確保するために、0〜40wt%としておく。   As described above, the material of the semi-cured sealing resin layer 22 is an epoxy resin, a cyanate ester resin, a phenoxy resin, a urethane resin, or a resin containing these as a main component. Further, the silica content is set to 0 to 40 wt% in order to ensure fluidity at the time of chip bonding.

このような半硬化封止樹脂層22を有するビルトアップ基板11に半導体チップ13を接合する場合は、図2(B)で説明したのと同様に、熱圧着、溶融、超音波接合などの方法を採用することができる。基板11側の半硬化封止樹脂層22が、半導体チップ13のコーナー近傍で厚くなるように形成されているので、半導体チップ13の各エッジの中央部分からの封止樹脂の流出が多い場合でも、半導体チップ13側の封止樹脂層15と基板11側の封止樹脂層22とが溶融、一体化する際に、フィレット16の形成がより均一になる。その結果、図2(C)に示すように、半導体チップ13の端部を確実にカバーし、かつ裾が滑らかに拡がったフィレット16の断面形状が得られるとともに、図4(B)に示すように、半導体チップ13のエッジから外側に向けて均一に隙間なく拡がる平面形状となる。   When the semiconductor chip 13 is bonded to the built-up substrate 11 having such a semi-cured sealing resin layer 22, methods such as thermocompression bonding, melting, and ultrasonic bonding are the same as described with reference to FIG. Can be adopted. Since the semi-cured sealing resin layer 22 on the substrate 11 side is formed to be thick in the vicinity of the corner of the semiconductor chip 13, even when the sealing resin flows out from the central portion of each edge of the semiconductor chip 13. When the sealing resin layer 15 on the semiconductor chip 13 side and the sealing resin layer 22 on the substrate 11 side are melted and integrated, the formation of the fillet 16 becomes more uniform. As a result, as shown in FIG. 2C, a cross-sectional shape of the fillet 16 that reliably covers the end of the semiconductor chip 13 and has a hem that smoothly spreads is obtained, and as shown in FIG. 4B. Further, the semiconductor chip 13 has a planar shape that spreads uniformly from the edge toward the outside without a gap.

半導体チップ13側の半硬化封止樹脂層15と、ビルトアップ基板11側の半硬化封止樹脂層22のいずれか一方、又は双方にシリカフィラー等の充填材が含有されている場合は、図2(C)に示したように、充填剤の含有プロファイルは、フィレット22の裾部分の端部に向かうほど少なくなる。   When a filler such as silica filler is contained in one or both of the semi-cured sealing resin layer 15 on the semiconductor chip 13 side and the semi-cured sealing resin layer 22 on the built-up substrate 11 side, As shown in FIG. 2 (C), the content profile of the filler decreases toward the end of the bottom portion of the fillet 22.

最後に、接合された半導体チップ13とビルトアップ基板11を170℃で1.5時間ベークして、封止樹脂を硬化して半導体装置を完成する。   Finally, the bonded semiconductor chip 13 and built-up substrate 11 are baked at 170 ° C. for 1.5 hours, and the sealing resin is cured to complete the semiconductor device.

図5は、図2の方法で作製した半導体装置のフィレット16の形状を示す写真である。半導体チップ13の端部を覆い、基板表面に向かって裾が十分かつ均一に拡がるフィレット16が形成されている。   FIG. 5 is a photograph showing the shape of the fillet 16 of the semiconductor device manufactured by the method of FIG. A fillet 16 is formed which covers the end portion of the semiconductor chip 13 and has a skirt sufficiently and uniformly spreading toward the substrate surface.

上述した実施例の方法では、フィレット樹脂をビルトアップ基板11上の必要な箇所に必要なだけ供給するので、フィレット形成領域の基板上に凹凸がある場合でも、十分な裾をもったフィレット16を形成することができる。その結果、接合信頼性が向上する。また、通常の封止樹脂注入プロセスで樹脂の流れが悪い材質の基板に対しても、確実にフィレットを供給、形成することができる。さらに、接合時に溶融・一体化するため、樹脂の不連続性が生じない。すなわち、樹脂内の局所的な残留応力の発生を防止することもでき、接合信頼性をより確実にすることができる。   In the method of the embodiment described above, the fillet resin is supplied to the necessary portions on the built-up substrate 11 as much as necessary. Therefore, even when the substrate in the fillet forming region has irregularities, the fillet 16 having a sufficient skirt is formed. Can be formed. As a result, the bonding reliability is improved. Further, the fillet can be reliably supplied and formed even on a substrate made of a material having a poor resin flow in a normal sealing resin injection process. Furthermore, since it melts and integrates at the time of joining, there is no resin discontinuity. That is, it is possible to prevent the occurrence of local residual stress in the resin and to further ensure the bonding reliability.

なお、本発明の半導体装置およびその製造方法は、上述した実施例に限定されず、当業者にとって実施可能な種々の変形例を含む。たとえば、半導体チップ13に設けられる突起電極14は、AuスタッドバンプやAuワイヤバンプの代わりに、ハンダ、Auメッキバンプ、Cuメッキバンプ、ペースト状バンプ等を用いることができる。この場合も、熱圧着時の温度を、樹脂が自由流動できる温度、例えば200℃〜240℃の範囲で制御することによって、半導体チップ13側の半硬化封止樹脂層15と、ビルトアップ基板11側の半硬化封止樹脂層12(又は22)を溶融、一体化して、十分な裾を持ったフィレット16を形成することができる。   The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiments, but include various modifications that can be performed by those skilled in the art. For example, the protruding electrodes 14 provided on the semiconductor chip 13 can be solder, Au plated bumps, Cu plated bumps, paste bumps, or the like instead of Au stud bumps or Au wire bumps. Also in this case, the temperature at the time of thermocompression bonding is controlled within a range where the resin can flow freely, for example, in the range of 200 ° C. to 240 ° C., so that the semi-cured sealing resin layer 15 on the semiconductor chip 13 side and the built-up substrate 11 The side semi-cured sealing resin layer 12 (or 22) can be melted and integrated to form a fillet 16 having a sufficient hem.

また、上述した実施例の方法は、とくに半導体チップ13の回路形成面を下側(ビルトアップ基板11側)に向けてフリップチップ接合に好適であるが、これに限定されず、半導体チップ13とビルトアップ基板11との間の電気的な接続をワイヤボンディングで行う場合にも適用できる。その場合は、ビルトアップ基板11上のボンディングパッドは、あらかじめ半導体素子13をビルトアップ基板11に接着する接着層(フィレット)の末広がりの裾部分の外側に位置するように配置しておく。ワイヤボンディングの後にキャップ樹脂を形成する。この適用例でも、半導体チップ13とビルトアップ基板11間の良好なフィレットの形状により、接合の信頼性が維持される。   The method of the above-described embodiment is suitable for flip chip bonding particularly with the circuit formation surface of the semiconductor chip 13 facing downward (the built-up substrate 11 side), but is not limited to this. The present invention can also be applied to a case where electrical connection with the built-up substrate 11 is performed by wire bonding. In that case, the bonding pads on the built-up substrate 11 are arranged in advance so as to be located outside the bottom end of the adhesive layer (fillet) that adheres the semiconductor element 13 to the built-up substrate 11. Cap resin is formed after wire bonding. Even in this application example, the reliability of bonding is maintained by the good fillet shape between the semiconductor chip 13 and the built-up substrate 11.

また、ビルトアップ基板11の裏側にさらにハンダボール等の電極を形成して、さらに別の配線基板(マザーボード)等に搭載可能にしてもよい。   Further, an electrode such as a solder ball may be further formed on the back side of the built-up board 11 so that it can be mounted on another wiring board (motherboard) or the like.

従来の半導体チップの接合方法の問題点を示す概略図である。It is the schematic which shows the problem of the joining method of the conventional semiconductor chip. 本発明の実施形態における半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device in the embodiment of the present invention. 実施形態における半硬化封止樹脂の塗布例1を示す図である。It is a figure which shows the application example 1 of the semi-hardening sealing resin in embodiment. 実施形態における半硬化封止樹脂の塗布例2を示す図である。It is a figure which shows the application example 2 of the semi-hardening sealing resin in embodiment. 実施形態の方法で作製した半導体装置のフィレット形状を示す写真である。It is a photograph which shows the fillet shape of the semiconductor device produced by the method of the embodiment.

符号の説明Explanation of symbols

10 半導体装置
11 ビルトアップ基板(回路基板)
12、22 回路基板側接着層(第2の接着層;半硬化封止樹脂層)
13 半導体素子(半導体チップ)
14 突起電極
15 チップ側接着層(第1の接着層;半硬化封止樹脂層)
16、26 フィレット
18 基板側パッド電極
19 充填剤(シリカフィラー)
G ギャップ
10 Semiconductor device 11 Built-up board (circuit board)
12, 22 Circuit board side adhesive layer (second adhesive layer; semi-cured sealing resin layer)
13 Semiconductor element (semiconductor chip)
14 Protruding electrode 15 Chip side adhesive layer (first adhesive layer; semi-cured sealing resin layer)
16, 26 Fillet 18 Substrate side pad electrode 19 Filler (silica filler)
G gap

Claims (6)

半導体素子を実装する回路基板の、前記半導体素子の実装位置の外周にあらかじめ第1の接着層を形成し、
前記半導体素子の実装面に、あらかじめ第2の接着層を形成し、
前記半導体素子を前記回路基板上に配置し、前記第1の接着層と前記第2の接着層とを溶融・一体化してフィレットを形成する、
工程を含むことを特徴とする半導体装置の製造方法。
Forming a first adhesive layer in advance on the outer periphery of the mounting position of the semiconductor element of the circuit board on which the semiconductor element is mounted;
A second adhesive layer is formed in advance on the mounting surface of the semiconductor element,
The semiconductor element is disposed on the circuit board, and the first adhesive layer and the second adhesive layer are melted and integrated to form a fillet.
The manufacturing method of the semiconductor device characterized by including a process.
前記第1接着層は、前記半導体素子の実装位置から所定の間隔をあけて形成されることを特徴とする請求項1に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first adhesive layer is formed at a predetermined interval from a mounting position of the semiconductor element. 前記第1の接着層は、前記半導体素子の実装位置のコーナー近傍での樹脂量が、その他の部分よりも多くなるように形成されることを特徴とする請求項1又は2に記載の半導体装置の製造方法。   3. The semiconductor device according to claim 1, wherein the first adhesive layer is formed such that a resin amount in the vicinity of a corner of the mounting position of the semiconductor element is larger than that of other portions. Manufacturing method. 前記第1の接着層は、前記半導体素子の実装位置のコーナー近傍での幅よりも、コーナー間の中央部に対応する位置での幅が狭くなるように形成されることを特徴とする請求項1〜3のいずれかに記載の半導体装置の製造方法。   The first adhesive layer is formed so that a width at a position corresponding to a central portion between corners is narrower than a width near a corner at a mounting position of the semiconductor element. The manufacturing method of the semiconductor device in any one of 1-3. 半導体素子を回路基板上に実装した半導体装置において、
前記半導体素子と前記回路基板の間に位置する接着層を有し、
前記接着層は、前記半導体素子の外周端面を覆い、かつ前記回路基板に向かって裾が拡がる形状を有し、前記接着層に含まれる充填剤の濃度分布が、前記裾拡がりの部分の端部に向かうほど低くなっていることを特徴とする半導体装置。
In a semiconductor device in which a semiconductor element is mounted on a circuit board,
Having an adhesive layer located between the semiconductor element and the circuit board;
The adhesive layer covers the outer peripheral end surface of the semiconductor element and has a shape in which a skirt expands toward the circuit board, and a concentration distribution of the filler contained in the adhesive layer is an end portion of the skirt expanded portion. The semiconductor device is characterized by being lowered toward
前記半導体素子は、前記回路基板にフリップチップ接合されていることを特徴とする請求項5に記載の半導体装置。   The semiconductor device according to claim 5, wherein the semiconductor element is flip-chip bonded to the circuit board.
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Publication number Priority date Publication date Assignee Title
JP2011029516A (en) * 2009-07-28 2011-02-10 Shinko Electric Ind Co Ltd Method of manufacturing electronic component device, and tool

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004134821A (en) * 2004-02-06 2004-04-30 Toshiba Corp Semiconductor apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004134821A (en) * 2004-02-06 2004-04-30 Toshiba Corp Semiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011029516A (en) * 2009-07-28 2011-02-10 Shinko Electric Ind Co Ltd Method of manufacturing electronic component device, and tool

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