JP2009069187A - Display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus capable of suppressing transistor malfunctions, even when noise is generated in a power supply. <P>SOLUTION: The display apparatus includes a shift register circuit 41 including a plurality of transistors NT1, NT6 and NT7, whose sources are connected to a low voltage potential VL. In each of the plurality of transistors NT1, NT6 and NT7 whose sources are connected to the low voltage potential VL, two transistors are connected in series, and gate electrodes of two transistors are electrically connected together. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device including a shift register circuit.

  Conventionally, a display device including a shift register circuit is known (for example, see Patent Document 1). In Patent Document 1, a first circuit portion having an n-channel transistor connected to a start signal line and connected to a negative potential, and an n connected to the first circuit portion and connected to a negative potential. A display device including a shift register circuit including a second circuit portion having a channel transistor is disclosed. In this display device, a negative potential is used to turn off the n-channel transistor. Further, a display device including a shift register circuit using a p-channel transistor connected to a positive potential instead of an n-channel transistor connected to a negative potential is also disclosed.

JP 2005-17969 A

However, in the display device described in Patent Document 1, noise is generated in the negative potential and the positive potential due to the influence of various signals. Thereby, for example, when a noise of −ΔV is generated in the negative potential, the voltage V _gs between the gate and the source of the n-channel transistor increases by + ΔV, so that the n-channel transistor is not completely turned off. There is. Further, when + ΔV noise is generated in the positive potential, the voltage V _gs between the gate and the source of the p-channel transistor is lowered by −ΔV, so that the p-channel transistor is not completely turned off. As a result, there is a problem that the transistor malfunctions when noise occurs in the power supply (positive side potential or negative side potential).

  The present invention has been made to solve the above-described problems, and one object of the present invention is a display capable of suppressing malfunction of a transistor even when noise occurs in a power supply. Is to provide a device.

Means for Solving the Problems and Effects of the Invention

  A display device according to one aspect of the present invention includes a shift register circuit including a plurality of transistors each having one of a source / drain connected to a predetermined potential, and each of the plurality of transistors connected to the predetermined potential is 2 Two transistors are connected in series, and the gate electrodes of the two transistors are electrically connected to each other.

  In the display device according to this aspect, as described above, in the plurality of transistors connected to the predetermined potential, two transistors are connected in series, and the gate electrodes of the two transistors are electrically connected to each other. Thus, even when noise occurs in the power supply (positive potential or negative potential) and the potential difference between the source and drain of the transistor becomes large, the transistor is configured by one transistor. Since the resistance between the source and the drain of the transistor is larger than that in the case where the transistor is connected, the increase in current flowing between the source and the drain can be reduced. This point has been confirmed by an experiment by the inventor described later. This can prevent the transistor from being kept off. As a result, malfunction of the transistor can be suppressed.

  In the display device according to the above aspect, the shift register circuit includes a first circuit portion and a second circuit portion, and the plurality of transistors are provided in the first circuit portion provided in the first circuit portion and the second circuit portion. A gate connected to the first circuit portion, a second transistor connected between the first output signal line and a predetermined potential, a gate connected to the first circuit portion, and a second A third transistor connected between the output signal line and a predetermined potential may be included.

  In this case, preferably, the first transistor, the second transistor, and the third transistor are composed of transistors of the same conductivity type. With this configuration, unlike the case where the first transistor, the second transistor, and the third transistor are transistors of different conductivity types, the manufacturing process of the first transistor can be simplified.

  In the display device in which the first transistor, the second transistor, and the third transistor are configured by transistors of the same conductivity type, the display device preferably further includes a high voltage potential and a low voltage potential, The second transistor and the third transistor are n-channel transistors, and the predetermined potential connected to the first transistor, the second transistor, and the third transistor is a low voltage potential. With this configuration, a low voltage potential can be easily used as a potential for turning off the first transistor, the second transistor, and the third transistor.

In this case, it is preferable to further include a fourth transistor including an n-channel transistor connected between the high voltage potential and the first transistor, and the fourth transistor is configured by one transistor. With this configuration, the configuration of the transistor can be simplified, unlike the case where the fourth transistor is configured with two transistors. Note that when the fourth transistor formed of an n-channel transistor is connected to a high voltage potential, the voltage V _gs between the gate and the source is generated even when noise occurs in the high voltage potential. Therefore, the transistor does not malfunction due to the fluctuation of the above, so that it is not necessary to configure with two transistors.

  In the display device in which the first transistor, the second transistor, and the third transistor are configured by transistors of the same conductivity type, the display device preferably further includes a high voltage potential and a low voltage potential, The second transistor and the third transistor are p-channel transistors, and the predetermined potential connected to the first transistor, the second transistor, and the third transistor is a high voltage potential. With this configuration, a high voltage potential can be easily used as a potential for turning off the first transistor, the second transistor, and the third transistor.

In this case, it is preferable to further include a fourth transistor formed of a p-channel transistor connected between the low voltage potential and the first transistor, and the fourth transistor is configured by one transistor. With this configuration, the configuration of the transistor can be simplified, unlike the case where the fourth transistor is configured with two transistors. Note that when the fourth transistor formed of a p-channel transistor is connected to a low voltage potential, the voltage V _gs between the gate and the source even when noise occurs in the low voltage potential. Therefore, the transistor does not malfunction due to the fluctuation of the above, so that it is not necessary to configure with two transistors.

  The display device including the first transistor, the second transistor, and the third transistor preferably further includes a first capacitor connected to one of the source / drain of the first transistor. With this configuration, even when the on / off state of the first transistor changes, the electric potential accumulated before the on / off state changes can be held by the charge accumulated in the first capacitor.

  In the display device including the first transistor, the second transistor, and the third transistor, preferably, a second capacitor connected to one of the source / drain of each of the second transistor and the third transistor and the first output signal line. Is further provided. With this configuration, the potential of the first output signal line can be easily increased by the charge accumulated in the second capacitor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view of a display device according to a first embodiment of the present invention. First, the configuration of the display device according to the first embodiment will be described with reference to FIG.

  As shown in FIG. 1, the display device according to the first embodiment is provided on a glass substrate 1 corresponding to the intersection of gate lines (scanning lines) and data lines, and corresponding to the thin film transistors. A display unit 2 composed of the pixel electrodes, a precharge switch 3, a V driver 4, an H switch 5, and a driver IC 6 are formed. The precharge switch 3, the V driver 4, and the H switch 5 are connected to the display unit 2. The driver IC 6 is connected to the precharge switch 3, the V driver 4, and the H switch 5, and receives an external signal. The precharge switch 3, the V driver 4, and the H switch 5 are formed by a system-on-glass (SOG) technology that integrates circuit functions necessary for driving on the glass substrate 1 by a low-temperature polysilicon TFT process. Yes. As a result, the number of semiconductor components can be reduced, the assembly can be simplified, the external circuit board can be reduced, and the overall reduction in size, weight, and cost can be realized.

  FIG. 2 is a circuit diagram inside the V driver of the display device according to the first embodiment of the present invention. 3 and 4 are circuit diagrams of the shift register circuit of the display device according to the first embodiment of the present invention. Next, the configuration of the V driver 4 of the display device according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 2, the V driver 4 includes a shift register circuit unit 40, an output unit 50, and an input unit 60 inside the V driver 4. In FIG. 2, only four shift register circuits 41 to 44 are shown for simplification of the drawing, but in actuality, the number of shift register circuits corresponding to the number of pixels is provided.

  As shown in FIG. 3, the first-stage shift register circuit 41 includes a first circuit unit 41a and a second circuit unit 41b. The first circuit portion 41a includes n-channel transistors NT1 to NT3, a diode-connected n-channel transistor NT4, and a capacitor C1. The n-channel transistor NT1 is an example of the “first transistor” in the present invention. The capacitor C1 is an example of the “first capacitor” in the present invention. Hereinafter, the n-channel transistor is referred to as a transistor.

  In the first circuit section 41a, the source of the transistor NT1 is connected to the low voltage potential VL, and the drain is connected to the source of the transistor NT2. The gate of the transistor NT1 is connected to the clock signal line (CKV). Here, in the first embodiment, the transistor NT1 is configured such that two transistors are connected in series and the gate electrodes of the two transistors are electrically connected to each other. The drain of the transistor NT2 is connected to the node ND1, and the gate is connected to the input signal line IN. The input signal line IN is connected to the transistor NT65 shown in FIG. Here, in the first embodiment, one electrode of the capacitor C1 is connected to the low voltage potential VL and to the source of the transistor NT1. The other electrode of the capacitor C1 is connected to the node ND1.

  The source of the transistor NT3 is connected to the node ND1 through the transistor NT4, and the drain is connected to the clock signal line (CKV). The gate of the transistor NT3 is connected to the input signal line SR2. The input signal line SR2 is connected to the transistor NT62 shown in FIG.

  A high voltage potential VH is connected between the drain of the transistor NT2 and the source of NT4 via a transistor NT61 described later.

  Second circuit portion 41b includes n-channel transistors NT5 to NT8, diode-connected n-channel transistor NT9, and capacitors C2 and C3. The n-channel transistors NT6 and NT7 are examples of the “second transistor” and the “third transistor” in the present invention, respectively. The capacitor C2 is an example of the “second capacitor” in the present invention. Hereinafter, the n-channel transistor is referred to as a transistor.

  In the second circuit portion 41b, the source of the transistor NT5 is connected to the node ND3, and the drain is connected to the bootstrap signal line (VBP1). The gate of the transistor NT5 is connected to the node ND2. The source of the transistor NT6 is connected to the negative potential VL, and the drain is connected to the node ND3. The gate of the transistor NT6 is connected to the node ND1 of the first circuit portion 41a. The source of the transistor NT7 is connected to the low voltage potential VL, and the drain is connected to the node ND2. The gate of the transistor NT7 is connected to the node ND1 of the first circuit portion 41a. Here, in the first embodiment, in the transistors NT6 and NT7 whose sources are connected to the low voltage potential VL, the two transistors are connected in series, and the gate electrodes of the two transistors are electrically connected to each other. It is configured as follows.

  As described above, in the first embodiment, the transistors NT1 to NT9 provided in the first-stage shift register circuit 41 are all n-channel transistors (field effect transistors).

  In the first embodiment, one electrode of the capacitor C2 is connected to the drain of the transistor NT7 and the output signal line S Rout1, and the other electrode is connected to the drain of the transistor NT6. The output signal line S Rout1 is an example of the “first output signal line” in the present invention.

  The source of the transistor NT8 is connected to the node ND2 via the transistor NT9, and the drain is connected to the clock signal line (CKV). The gate of the transistor NT8 is connected to the input signal line IN of the first circuit portion 41a. A capacitor C3 is connected between the gate and source of the transistor NT8.

  Further, the output signal line (SR1) of the shift register circuit 41 is connected to the node ND3. The output signal line (SR1) is an example of the “second output signal line” in the present invention. Further, the output signal line (SR1) functions as an input signal line IN of the shift register circuit unit 42 located at the subsequent stage of the shift register circuit 41.

  The shift register circuit unit 42 includes a first circuit unit 42a and a second circuit unit 42b. The first circuit portion 42a includes n-channel transistors NT101 to NT103, a diode-connected n-channel transistor NT104, and a capacitor C11. The n-channel transistor NT101 is an example of the “first transistor” in the present invention. The capacitor C1 is an example of the “first capacitor” in the present invention.

  The connection of the first circuit portion 42a is similar to the connection of the first circuit portion 41a, but the clock signal line in which the gate of the transistor NT101 and the drain of the transistor NT103 are inverted signals of the clock signal line (CKV). The difference is that it is connected to (XCKV).

  Second circuit portion 42b includes n-channel transistors NT105 to NT108, a diode-connected n-channel transistor NT109, and capacitors C12 and C13. The n-channel transistors NT106 and NT107 are examples of the “second transistor” and the “third transistor” in the present invention, respectively. The capacitor C12 is an example of the “second capacitor” in the present invention.

  The connection of the second circuit portion 42b is similar to the connection of the second circuit portion 41b, but the drain of the transistor NT108 is connected to the clock signal line (XCKV) that is an inverted signal of the clock signal line (CKV). The difference is that the drain of the transistor NT105 is connected to the bootstrap signal line (VBP2) whose phase is shifted by half a cycle of CKV and XCKV from the bootstrap signal line (VBP1).

  As shown in FIG. 4, the shift register circuits 43 and 44 have the same configuration as the shift register circuits 41 and 42, respectively.

  As shown in FIG. 2, the output unit 50 includes four stages of output circuits 51 to 54. The output circuit 51 includes n-channel transistors NT51 to NT55 and a capacitor C51. The source of the transistor NT51 is connected to the low voltage potential VL, and the drain is connected to the source of the NT54. The gate of the transistor NT51 is connected to the capacitor C51. The source of the transistor NT52 is connected to the low voltage potential VL, and the drain is connected to the capacitor C51. The gate of the transistor NT52 is connected to the gate line 1. The source of the transistor NT53 is connected to the drain of the transistor NT52. The drain and gate of the transistor NT53 are diode-connected and also connected to an enable signal line (XVENB). The source of the transistor NT54 is connected to the drain of the transistor NT51, and the drain is connected to the source of the transistor 55. The gate of the transistor NT54 is connected to the output signal line S Rout1 (see FIG. 3) of the shift register circuit 41. The source of the transistor NT55 is connected to the drain of the transistor 54, and the drain is connected to the enable signal line (VENB). The gate of this transistor NT52 is connected to the output signal line of the preceding shift register circuit.

  The configurations of the output circuits 52 to 54 are the same as the configuration of the output circuit 51.

  As shown in FIG. 2, the input unit 60 that inputs to the shift register circuit 41 includes n-channel transistors NT61 to NT65. The source of the transistor NT61 is connected to the node ND1 of the shift register circuit 41, and the drain is connected to the high voltage potential VH. The gate of the transistor NT61 is connected to the start signal line (STV). The source of the transistor NT62 is connected to the gate of the transistor NT3 of the shift register circuit 41, and the drain is connected to the output signal line of the preceding shift register circuit. The gate of the transistor NT62 is connected to the scan direction switching signal line (XCSV). The source of the transistor NT63 is connected to the gate of the transistor NT3 of the shift register circuit 41, and the drain is connected to the output signal line SR1 of the shift register circuit 41. The gate of the transistor NT63 is connected to the scan direction switching signal line (CSV). The source of the transistor NT64 is connected to the transistor NT164 that controls the input of the rear shift register circuit, and the drain is connected to a transistor that controls the input of the front shift register circuit (not shown). The gate of the transistor NT64 is connected to the scan direction switching signal line (XCSV). The source of the transistor NT65 is connected to the transistor NT165 that controls the input of the rear-stage shift register circuit 42, and the drain is connected to a transistor that controls the input of the front-stage shift register circuit (not shown). The gate of this transistor NT65 is connected to a scan direction switching signal line (CSV).

  The configuration of the input unit 60 that controls the input of the shift register circuits 42 to 44 is the same as the configuration of the input unit 60 that controls the input of the shift register circuit 41.

  FIG. 5 is a waveform diagram for explaining the operation of the V driver according to the first embodiment of the present invention. Next, the operation of the V driver 4 according to the first embodiment of the present invention will be described with reference to FIGS.

  Here, a case where the scanning direction of the V driver 4 is the forward direction will be described. That is, a case where the potential of the scan direction switching signal line (CSV) is set to H level will be described. As a result, the transistors NT65, NT165, NT265, NT365, NT63, NT163, NT263, and NT363 to which the scan direction switching signal line (CSV) is connected to the gate are turned on. Further, the transistors NT64, NT164, NT264, NT364, NT62, NT162, NT262 and NT362 to which the scan direction switching signal line (XCSV) is connected to the gate are turned off.

  First, in the initial state, the potentials of the nodes ND1, ND11, ND21, and ND31 of the shift register circuits 41 to 44 are unstable potentials between H level and L level. In this state, the signal on the start signal line (STV) is input to the transistors NT61, NT161, NT261, and NT361 that function as reset transistors. Accordingly, transistors NT61, NT161, NT261, and NT361 are turned on, and an H level potential (VH) is supplied to nodes ND1, ND11, ND21, and ND31 via transistors NT61, NT161, NT261, and NT361. Accordingly, transistors NT6, NT106, NT206, and NT306 and NT7, NT107, NT207, and NT307 are turned on, so that the potentials of nodes ND7, ND17, ND27, and ND37 are at the L level.

  Next, at the time point a, an H level potential is supplied to the node ND4. Thereby, transistors NT2 and NT8 are turned on. At this time, since the potential of the clock signal line (CKV) is at the L level, the transistors NT1 and NT9 are in the off state. As a result, the node ND1 maintains the initial H level potential by the capacitor C1, and the nodes ND6 and ND7 maintain the initial L level potential.

  Next, when the potential of the clock signal line (CKV) is raised to the H level at the time point b, since the H level potential is input to the gates of the transistors NT1 and NT9, the transistors NT1 and NT9 are turned on. It becomes. As a result, the potential of the node ND1 becomes L level. As a result, transistors NT6 and NT7 are turned off. At the same time, an H level potential of the clock signal line (CKV) is supplied to the node ND7 through the transistor NT9. Further, when the transistor NT5 is turned on, the L level potential of the bootstrap signal line (VBP1) is supplied to the node ND6. At this time, the H-level potential of the node ND7 and the L-level potential of the node ND6 are supplied to both ends of the capacitor C2.

  Next, at time point c, the potential of the bootstrap signal line (VBP1) is raised to the H level. Thereby, transistor NT5 is turned on, and the potential of node ND6 rises to the H level. Accordingly, the capacitor C2 tries to hold the potential difference between both ends as VH−VL, so that the potential of the node ND7 connected to the capacitor C2 changes to VH + VH−VL (bootstrap effect). In this manner, the potential of the node ND7 connected to the gate of the transistor NT5 changes to a potential sufficiently higher than the H level potential (VH). Thereby, the transistor NT5 continues to be on.

  Thereafter, the node ND6 transfers a signal to the node ND14 which is the input portion of the subsequent shift register circuit 42 via the transistor NT164. In FIG. 5, this state is indicated by a broken line frame and an arrow. Unlike the shift register circuit 41 in the previous stage, the shift register circuit 42 in the subsequent stage is connected to the clock signal line (XCKV) and the bootstrap signal line (VBP2).

  Further, the rear-stage shift register circuit 42 operates in the same manner as the front-stage shift register circuit 41, and a signal is output from the node ND17. Further, an input signal of the shift register circuit 43 is output from the node ND16 and is input to the node ND5 of the shift register circuit 41 as a second signal to the shift register circuit 41. In FIG. 5, this state is indicated by a broken line frame and an arrow.

  When an H level potential is supplied as the second signal to the node ND5, the transistor NT3 is turned on. At this time, since the potential of the clock signal line (CKV) is at the L level, the transistor NT4 is in an off state.

  Next, when the potential of the bootstrap signal line (VBP1) falls to L level at the time point d, the potential of the node ND6 becomes L level via the transistor NT5. At this time, due to the capacitor C2, the potential of the node ND7 drops by the amount increased by the bootstrap effect.

  Next, when the potential of the clock signal line (CKV) is raised to the H level at the time point e, the transistor NT4 is turned on via the transistor NT3, and the potential of the node ND1 rises to the H level. Thereby, transistors NT6 and NT7 are turned on, so that the potential of node ND7 drops to the L level.

  Finally, the potential of the node ND5 falls to the L level, so that the transistors NT3 and NT4 are turned off. Further, the potential of the node ND1 is kept at the H level by the capacitor C1, so that the shift register circuit 41 returns to the initial state before the operation.

  By repeating these operations in the shift register circuits 41 to 44, the signal can be shifted in synchronization with the clock signal. As shown in FIG. 5, the odd-numbered shift register circuits 41 and 43 and the even-numbered shift register circuits 42 and 44 have the same configuration. Further, the difference between the odd-stage shift register circuits 41 and 43 and the even-number shift register circuits 42 and 44 is that the clock signal line (CKV) is changed to the clock signal line (XCKV), and the bootstrap signal line (VBP1). Is changed to the bootstrap signal line (VBP2).

  The node ND7 of the shift register circuit 41 is connected to the transistor NT155 and the transistor NT54 of the output unit 50. The output signal is gated by taking the logical sum of the enable signal line (VENB) and the node ND7. Output to line 1. Similarly, the shift register circuits 42 to 44 output signals to the gate lines 2 to 4.

  In the first embodiment, as described above, the transistors NT1, NT6, NT7, NT101, NT106, NT107, NT201, NT206, NT207, NT301, NT306, and NT307 connected to the low voltage potential VL are each two. Since the transistors are connected in series and the gate electrodes of the two transistors are electrically connected to each other, noise is generated in the low-voltage potential VL, and the potential difference between the source and drain of the transistor Since the resistance between the source and drain of the transistor is large compared to the case where the transistor is constituted by one transistor even when the transistor becomes large, the increase in current flowing between the source and drain is reduced. be able to. This can prevent the transistor from being kept off. As a result, malfunction of the transistor can be suppressed.

  In the first embodiment, as described above, the transistors NT1 (NT101, NT201, NT301), NT6 (NT106, NT206, NT306) and NT7 (NT107, NT207, NT307) are replaced with n-channel transistors of the same conductivity type. Unlike the case where the transistors NT1 (NT101, NT201, NT301), NT6 (NT106, NT206, NT306) and NT7 (NT107, NT207, NT307) are composed of transistors of different conductivity types, the transistor manufacturing process Can be simplified.

  In the first embodiment, as described above, a high voltage potential VH and a low voltage potential VL are provided, and transistors NT1 (NT101, NT201, NT301), NT6 (NT106, NT206, NT306) and NT7 ( The transistors NT1 (NT101, NT201, NT301), NT6 (NT106, NT206, NT306) and NT7 (NT107, NT207) can be easily obtained by setting the potential connected to the NT107, NT207, NT307) to the low potential VL. , NT307) can be a low voltage potential as a potential for turning off.

In the first embodiment, as described above, the transistor NT61 (NT161, NT261, NT361) connected between the high-voltage potential VH and the transistor NT1 (NT101, NT201, NT301) made of n-channel transistors. Unlike the case where the transistor NT61 (NT161, NT261, NT361) is composed of two transistors, the transistor NT61 (NT161, NT261, NT361) is composed of one transistor, thereby simplifying the transistor configuration. be able to. Note that when the transistor NT61 (NT161, NT261, NT361) formed of an n-channel transistor is connected to a high voltage potential, even if noise occurs in the high voltage potential, the transistor NT61 is not connected between the gate and the source. Since the transistor does not malfunction due to the fluctuation of the voltage V _gs of the transistor Vs, there is no need to form the transistor with two transistors.

  Further, in the first embodiment, as described above, the transistor NT1 (NT101, NT201, NT301) is provided by including the capacitor C1 (C11, C21, C31) connected to the source of the transistor NT1 (NT101, NT201, NT301). ), The potential before the on / off state is changed can be held by the charge accumulated in the capacitor C1 (C11, C21, C31).

  In the first embodiment, as described above, the sources of the NT6 (NT106, NT206, NT306) and the transistor NT7 (NT107, NT207, NT307) and the output signal lines S Rout1 (S Rout2, S Rout3, S Rout4) ), The potential of the output signal line S Rout1 (S Rout2, S Rout3, S Rout4) connected to the capacitor C2 can be raised by the capacitor C2 (bootstrap effect). .

(Experiment)
FIG. 6 is a diagram illustrating a relationship between a gate / source voltage V _gs and a drain / source current I _ds in a transistor having one gate (single gate). FIG. 7 is a diagram illustrating a relationship between a gate / source voltage V _gs and a drain / source current I _ds in a transistor having two gates (double gate) including two transistors. It is. With reference to FIGS. 6 and 7, in the case of changing the voltage V _ds between the drain / source, and the voltage V _gs between the gate / source, a change in the current I _ds flowing between the drain / source was measured The experiment will be described.

As shown in FIG. 6, if a single gate, a drain / about 0.1V voltage _{V ds} between source, about 5.1V, about 10.1V, about 15.1V, about 20.1V and about 25.1V For example, when the gate-source voltage V _gs is 0.5 V, the current I _ds flowing between the drain / source is about 1.1 × 10 ⁻⁹ to about 8.0 ×. It was confirmed that it changed to ^10-7 .

Further, as shown in FIG. 7, when the double gate, about 0.1V voltage _{V ds} between the drain / source, about 5.1V, about 10.1V, about 15.1V, about 20.1V and about 25 For example, when the voltage V _gs between the gate and the source is 0.5 V, the current I _ds flowing between the drain and the source is about 8.0 × 10 ⁻¹⁰ to about 6.0. It was confirmed that it changed to × 10 ⁻⁹ . As a result, even if the drain-source voltage _Vds changes, the double-gate transistor has a smaller change in the current _Ids flowing between the drain / source than the single-gate transistor. Was found to be less prone to malfunction than single-gate transistors.

(Second Embodiment)
8 and 9 are circuit diagrams of the shift register circuit of the display device according to the second embodiment of the present invention. Next, with reference to FIGS. 8 and 9, in the second embodiment, shift register circuits 45 to 48 using p-channel transistors will be described, unlike the first embodiment.

  The configuration of the shift register circuits 45 to 48 shown in FIGS. 8 and 9 is obtained by replacing the n channel transistors with p channel transistors in the shift register circuits 41 to 44 according to the first embodiment. In the configuration of the V driver 4 shown in FIG. 2, the n-channel transistor is replaced with a p-channel transistor. Here, in the second embodiment, the p-channel transistors PT1 (PT101, PT201, PT301), the p-channel transistors PT6 (PT106, PT206, PT306) and the p-channel transistors PT7 (PT107, PT207, PT307) have two transistors. The gate electrodes of the two transistors are connected in series and are electrically connected to each other, and are connected to a high voltage potential VH. In the second embodiment, the transistor PT61 (PT161, PT261, PT361) connected between the low voltage potential VL and the p-channel transistors PT1 (PT101, PT201, PT301) is provided. PT261 and PT361) are configured by one transistor.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  In the second embodiment, as described above, the transistors PT1 (PT101, PT201, PT301), the transistors PT6 (PT106, PT206, PT306), and the transistors PT7 (PT107, PT207, PT307), which are channel transistors, have high voltage potentials. By being connected to VH, a high voltage is easily set as a potential for turning off the transistor PT1 (PT101, PT201, PT301), the transistor PT6 (PT106, PT206, PT306) and the transistor PT7 (PT107, PT207, PT307). Potential VH can be used.

In the second embodiment, as described above, the transistor PT61 (PT161, PT261, PT361) connected between the low voltage potential VL and the PT1 (PT101, PT201, PT301) composed of p-channel transistors is provided. Unlike the case where the transistor PT61 (PT161, PT261, PT361) is composed of two transistors, the transistor PT61 (PT161, PT261, PT361) is composed of one transistor, thereby simplifying the transistor configuration. Can do. In the case where the transistor PT61 (PT161, PT261, PT361) formed of a p-channel transistor is connected to a low voltage potential, even when noise occurs in the low voltage potential, the transistor PT61 is not connected between the gate and the source. Since the transistor does not malfunction due to the fluctuation of the voltage V _gs of the transistor Vs, there is no need to form the transistor with two transistors.

  The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

(Third embodiment)
FIG. 10 is a circuit diagram of the shift register circuit of the display device according to the third embodiment of the present invention. Next, with reference to FIG. 10, in the second embodiment, unlike the first embodiment, shift register circuits 71 and 72 in which the first circuit portion 41a and the second circuit portion 42a are not provided will be described.

  As shown in FIG. 10, the shift register circuit 71 according to the third embodiment includes n-channel transistors NT501 to NT507 and a capacitor C501.

  One of the source / drain of the transistor NT501 is connected to the shift register circuit 72 in the subsequent stage, and the other of the source / drain is connected to the gate of the transistor NT501. Thereby, the transistor NT501 is diode-connected. One of the source / drain of the transistor NT502 is connected to the output signal line SR1, and the other of the source / drain is connected to the gate of the transistor NT502. Thereby, the transistor NT502 is diode-connected.

  One of the source / drain of the transistor NT503 is connected to the other of the source / drain of the transistors NT501 and NT502, and the other of the source / drain is connected to the clock signal line (CKV). The gate of the transistor NT503 is connected to one of the source / drain of the transistor NT504. A capacitor C501 is connected between one of the source / drain of the transistor NT503 and the gate. Note that the gate of the transistor NT503 and one electrode of the capacitor C501 are connected to the output signal line S Rout1. The gate of the transistor NT503 is connected to one of the source / drain of the transistor NT504, and the input signal line IN is connected to the other of the source / drain. A high voltage potential VH is connected to the gate of the transistor NT504.

  Here, in the third embodiment, the transistor NT505 is configured such that two transistors are connected in series and the gate electrodes of the two transistors are electrically connected to each other. The source of the transistor NT505 is connected to the low voltage potential VL, and the drain is connected to the shift register circuit 72 at the subsequent stage. The gate of this transistor NT505 is connected to the input signal line IN. In the third embodiment, the transistor NT506 is configured such that two transistors are connected in series and the gate electrodes of the two transistors are electrically connected to each other. The source of the transistor NT506 is connected to the low voltage potential VL, and the drain is connected to the input signal line IN. The gate of this transistor NT506 is connected to the signal line SR2.

  One of the source / drain of the transistor NT507 is connected to the RESET signal line, and the other of the source / drain is connected to the signal line SR2. The gate of this transistor NT507 is connected to the RESET signal line.

  Next, operations of the shift register circuits 71 and 72 according to the third embodiment of the present invention will be described with reference to FIG.

  First, since the high voltage potential VH is applied to the gate of the transistor NT504, the transistor NT504 is turned on, and the potential of the input signal line IN is output to the output signal line S Rout1 as it is. As a result, the potential of the output signal line S Rout1 becomes an H level potential.

  Next, the potential of the clock signal line (CKV) is raised to the H level. As a result, the transistor NT502 is turned on. Further, the potential of the output signal line S Rout1 is bootstrapped and raised to VH + α by the capacitor C501. At this time, since the potential of the gate of the transistor NT504 is VH, the transistor NT504 is turned off.

  Next, the potential of the node ND501 (the signal of the clock signal line (CKV)) is shifted to the subsequent shift register circuit 72 through the transistor NT501.

  Note that the transistor NT506 has a function of resetting the output signal line S Rout1 based on the output of the subsequent transistor NT602. The transistor NT505 has a function of setting the subsequent transistor NT606 to an off state.

  In the third embodiment, as described above, the transistors NT505, NT506, NT605, and NT606 connected to the low voltage potential VL are respectively connected in series, and the gate electrodes of the two transistors are connected to each other. By being configured to be electrically connected to each other, even when noise is generated in the low voltage potential VL and the potential difference between the source and drain of the transistor becomes large, the transistor is configured by one transistor. Since the resistance between the source and the drain of the transistor is larger than that in the case where the current is applied, an increase in current flowing between the source and the drain can be reduced. This can prevent the transistor from being kept off. As a result, malfunction of the transistor can be suppressed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first and third embodiments, all the n-channel transistors connected to the low voltage potential VL are connected in series with two transistors, and the gate electrodes of the two transistors are electrically connected to each other. Although the present invention is not limited to this, the present invention is not limited to this. Among the n-channel transistors connected to the low voltage potential VL, two transistors are connected in series, and the two transistors are connected in series. The gate electrodes may be configured to be electrically connected to each other.

  In the second embodiment, all of the p-channel transistors connected to the high voltage potential VH are configured such that two transistors are connected in series and the gate electrodes of the two transistors are electrically connected to each other. However, the present invention is not limited to this. Of the p-channel transistors connected to the high voltage potential VH, two transistors are connected in series, and the gate electrodes of the two transistors are connected to each other. You may comprise so that it may mutually be electrically connected.

1 is a plan view of a display device according to a first embodiment of the present invention. 3 is a circuit diagram inside a V driver of the display device according to the first embodiment of the present invention; FIG. 3 is a circuit diagram inside a V driver of the display device according to the first embodiment of the present invention; FIG. FIG. 3 is a circuit diagram of a shift register circuit of the display device according to the first embodiment of the present invention. It is a wave form diagram for demonstrating operation | movement of the V driver of 1st Embodiment of this invention. FIG. 6 is a diagram illustrating a relationship between a gate / source voltage V _gs and a drain / source current I _ds in a transistor having one gate (single gate). It is a figure showing the relationship between the voltage _Vgs between gate / sources, and the electric current _Ids which flows between drains / sources in a transistor with two gates (double gate) comprised by two transistors. FIG. 6 is a circuit diagram of a shift register circuit of a display device according to a second embodiment of the present invention. FIG. 6 is a circuit diagram of a shift register circuit of a display device according to a second embodiment of the present invention. It is a circuit diagram of the shift register circuit of the display apparatus by 3rd Embodiment of this invention.

Explanation of symbols

41, 42, 43, 44, 45, 46, 47, 48, 71, 72 Shift register circuit 41a, 42a, 43a, 44a, 45a, 46a, 47a, 48a First circuit part 41b, 42b, 43b, 44b, 45b 46b, 47b, 48b Second circuit part NT1, NT101, NT201, NT301, PT1, PT101, PT201, PT301 Transistor (first transistor)
NT6, NT106, NT206, NT306, PT6, PT106, PT206, PT306 Transistor (second transistor)
NT7, NT107, NT207, NT307, PT7, PT107, PT207, PT307 Transistor (third transistor)
NT61, NT161, NT261, NT361, PT61, PT161, PT261, PT361 Transistor (fourth transistor)
C1, C11, C21, C31 capacity (first capacity)
C2, C12, C22, C32 capacity (second capacity)

Claims (9)

A shift register circuit including a plurality of transistors connected to one of the source / drain at a predetermined potential;
Each of the plurality of transistors connected to the predetermined potential is configured such that two transistors are connected in series and the gate electrodes of the two transistors are electrically connected to each other. The shift register circuit includes a first circuit unit and a second circuit unit,
The plurality of transistors are provided in the first circuit portion and the second circuit portion, the gate is connected to the first circuit portion, the first output signal line and the predetermined transistor A second transistor connected to the potential; and a third transistor having a gate connected to the first circuit portion and connected between the second output signal line and the predetermined potential. The display device according to claim 1.   The display device according to claim 2, wherein the first transistor, the second transistor, and the third transistor are configured by transistors of the same conductivity type. It further comprises a high voltage potential and a low voltage potential,
The first transistor, the second transistor, and the third transistor are n-channel transistors,
The display device according to claim 3, wherein the predetermined potential connected to the first transistor, the second transistor, and the third transistor is the low-voltage potential. A fourth transistor comprising an n-channel transistor connected between the high-voltage potential and the first transistor;
The display device according to claim 4, wherein the fourth transistor includes one transistor. It further comprises a high voltage potential and a low voltage potential,
The first transistor, the second transistor, and the third transistor are p-channel transistors,
The display device according to claim 3, wherein the predetermined potential connected to the first transistor, the second transistor, and the third transistor is the high-voltage potential. A fourth transistor comprising a p-channel transistor connected between the low-voltage potential and the first transistor;
The display device according to claim 6, wherein the fourth transistor includes one transistor.   The display device according to claim 2, further comprising a first capacitor connected to one of a source / drain of the first transistor.   9. The display according to claim 2, further comprising a second capacitor connected to one of a source / drain of each of the second transistor and the third transistor and the first output signal line. apparatus.

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