JP2009064878A - Printed wiring board and, mounting wiring board, and current detector - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress by a simple constitution the malfunctions of a current detecting circuit which are caused by the parasitic capacities formed out of the electrostatic couplings interposed between a conductor having a potential and the wiring patterns of a mounting wiring board of the current detecting circuit. <P>SOLUTION: A current detector 10 has a conductor 2 wherein a detected current flows, a magnetic core 4 having an air gap provided in a portion of its ring-form magnetic circuit, a magnetic sensor 6 disposed in the air gap, and a mounting wiring board 100 disposed near the conductor 2. The mounting wiring board 100 has a plurality of input-signal-terminal portions for receiving a plurality of input signals, an operational processing element 30 for performing the operational processings with respect to the respective input signals, a plurality of wiring portions in each of which its one end is so connected with each input-signal-terminal portion as to be connected simultaneously with circuit elements, and its another end is connected with the operational processing element 30, and parasitic-capacity adjusting portions provided in one or more wiring portions and for making equal to each other the values of parasitic capacities formed by the electrostatic couplings interposed between the conductor 2 and the respective wiring portions. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a printed wiring board, a mounting wiring board, and a current detector, and more particularly, to a printed wiring board, a mounting wiring board, and a current detector including the mounting wiring board in which conductors having a potential are arranged close to each other.

  When the external conductor is disposed close to the measurement circuit, a stray capacitance is formed between the conductor and the measurement circuit, and the measurement circuit may malfunction. Therefore, in Patent Document 1, in the current detection device that detects the detection current by detecting the current flowing to the output side in response to the detection current flowing to the input side of the current transformer, the output of the current transformer is the current input type. When using the differential amplification means, it is possible to prevent the common-mode noise voltage from entering the secondary side of the current transformer via the stray capacitance between the input side of the current transformer and the ground. Therefore, it is disclosed that a variable resistor is connected and adjusted to remove a noise voltage.

  Patent Document 2 discloses a voltage measurement circuit that measures a voltage difference between a first voltage and a second voltage, and the first wiring to which the first voltage is supplied and the second voltage are supplied. The first wiring and the second wiring are configured so that the stray capacitance of the first wiring and the stray capacitance of the second wiring are substantially equal to each other. A device including a pair wiring and a differential amplifier that differentially amplifies a voltage input from a first wiring and a voltage input from a second wiring is disclosed. Here, it is disclosed that the noise voltage superimposed on both signal lines is differentially amplified and canceled by making the stray capacitances of the first signal line and the second signal line substantially equal.

Japanese Patent Laid-Open No. 10-274665 JP 2006-351064 A

  When the conductor having the potential and the mounting wiring board are arranged close to each other, the conductor and the wiring pattern of the mounting wiring board are electrostatically coupled, and the stray capacitance causes, for example, the operation of the amplifier circuit arranged on the mounting wiring board. May be affected. Here, Patent Document 1 describes that a variable resistor is connected and adjusted to remove a noise voltage, but it is inconvenient because a variable resistor needs to be attached.

  Further, as in Patent Document 2, even if the stray capacitance of the first wiring and the stray capacitance of the second wiring are substantially equal, noise superimposed on the parasitic capacitance between the external conductor having a potential and the wiring in the amplifier The voltage cannot be dealt with.

  An object of the present invention corresponds to a wiring board in which a signal input terminal portion and an arithmetic processing element are connected by a wiring portion via a calculation input terminal portion or a differential amplifier as disclosed in Patent Document 2, for example, with a simple configuration. For a wiring board having an arithmetic processing element and a circuit element, and the signal input terminal part and the arithmetic processing element are connected by a wiring part, a wiring pattern formed on the wiring board forms a parasitic capacitance with a nearby external conductor having a potential. Thus, it is to provide a printed wiring board, a mounting wiring board, and a current detector that suppress the influence on the circuit operation on the wiring board.

  A printed wiring board according to the present invention is a printed wiring board in which external conductors having a potential are arranged close to each other, and each has a plurality of input signal terminal portions for receiving a plurality of input signals, and one end of each input signal. At least one wiring unit, each of which is connected to the terminal unit, the other end of which is connected to the arithmetic processing element that performs arithmetic processing based on each input signal, the plurality of wiring input units via the plurality of arithmetic input terminal units, respectively And a parasitic capacitance adjusting unit that makes the value of each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit the same value.

  A mounting wiring board according to the present invention is a mounting wiring board in which external conductors having a potential are arranged close to each other, and a plurality of input signal terminal portions each receiving a plurality of input signals, and an operation based on each input signal An arithmetic processing element that performs processing, and one end connected to each input signal terminal unit, and the other end connected to the arithmetic processing element via a plurality of arithmetic input terminal units, respectively, and connected to one or more circuit elements A wiring unit, and a parasitic capacitance adjusting unit that is provided in at least one wiring unit and that has the same value as each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit. Features.

  A current detector according to the present invention is a conductor through which a current to be detected flows, an annular magnetic circuit through which a magnetic flux generated by the current flowing through the conductor passes, and a magnetic core having a gap in a part thereof, a magnetic core A magnetic sensor disposed in the magnetic gap of the body core, and a mounting wiring board disposed close to the conductor, the mounting wiring board including a plurality of input signal terminal portions each receiving a plurality of input signals, An arithmetic processing element that performs arithmetic processing based on an input signal, one end is connected to each input signal terminal unit, one or more circuit elements are connected, and the other end is connected to the arithmetic processing element and a plurality of arithmetic input terminal units. Parasitic capacitance adjustment that is provided in at least one wiring unit and each parasitic capacitance that is formed by electrostatic coupling between the external conductor and each wiring unit to have the same value. And having a part The features.

  In the printed wiring board according to the present invention, it is preferable that the parasitic capacitance adjusting unit changes the wiring width of the wiring unit so that the values of the parasitic capacitances are the same.

  In the printed wiring board according to the present invention, it is preferable that the parasitic capacitance adjusting unit is provided with a dummy pad for arranging dummy circuit elements having the same value of each parasitic capacitance in at least one wiring unit. .

  In the printed wiring board according to the present invention, the parasitic capacitance adjusting unit may be provided with a conductor piece pad for arranging conductor pieces having the same value of each parasitic capacitance in at least one wiring portion. preferable.

  In the mounting wiring board according to the present invention, it is preferable that the parasitic capacitance adjustment unit changes the wiring width of the wiring unit so that the values of the parasitic capacitances are the same.

  Further, in the mounting wiring board according to the present invention, the parasitic capacitance adjusting unit sets the value of each parasitic capacitance to the same value in at least one wiring unit when the number of circuit elements connected to each wiring unit is different from each other. It is preferable to connect such dummy circuit elements.

  Moreover, in the mounting wiring board according to the present invention, the parasitic capacitance adjusting unit connects the conductor pieces to at least one wiring unit and sets the size or height of the conductor pieces so that the values of the parasitic capacitances are the same. It is preferable to change.

  With at least one of the above-described configurations, the printed wiring board includes a parasitic capacitance adjusting unit that sets each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit to the same value. As the parasitic capacitance adjustment unit, it is preferable to change the wiring width of the wiring unit. Moreover, it is preferable to provide a dummy pad for arranging the dummy circuit element in the wiring part as the parasitic capacitance adjusting part. Moreover, it is preferable to provide the conductor piece pad for arrange | positioning a conductor piece in a wiring part as a parasitic capacitance adjustment part. Therefore, it is possible to suppress malfunction of the circuit due to parasitic capacitance formed by electrostatic coupling between the conductor having a potential and the wiring pattern of the printed wiring board.

  With at least one of the above-described configurations, the mounting wiring board includes a parasitic capacitance adjusting unit that makes each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit have the same value. As the parasitic capacitance adjusting unit, it is preferable to connect a dummy circuit element to the wiring unit. Moreover, it is preferable that the conductor piece is connected to the wiring part as the parasitic capacitance adjusting unit to change the size or height of the conductor piece. Therefore, it is possible to suppress malfunction of the circuit due to parasitic capacitance formed by electrostatic coupling between a conductor having a potential and the wiring pattern of the mounting wiring board.

  With at least one of the above-described configurations, the current detector includes a parasitic capacitance adjusting unit that sets each parasitic capacitance formed by electrostatic coupling between a conductor having a potential and each wiring unit to the same value. Therefore, it is possible to suppress malfunction of the circuit due to parasitic capacitance formed by electrostatic coupling between a conductor having a potential and the wiring pattern of the mounting wiring board.

  Embodiments according to the present invention will be described below in detail with reference to the drawings. In the following description, an amplifier circuit using an operational amplifier is described as an arithmetic processing element. For example, a wiring portion between the input signal terminal portion and the arithmetic processing element is a pair wiring, and no two elements are arranged in the wiring portion. Any circuit that performs an operation based on a plurality of inputs may be used, such as a comparator that compares input voltages and outputs a high level (for example, 5 V) and a low level (for example, 0 V). In the following description, the current detector is described as using a magnetic core and a Hall element. However, a current detector that detects current based on other principles, such as a current detector using a current transformer, may be used. Good. In the following description, the parasitic capacitance adjusting unit is described as being provided in one of the two wiring units connected to the arithmetic processing element, but may be provided in both.

  FIG. 1 is a diagram showing a current detector 10. The current detector 10 is a measuring device that detects a current flowing through the conductor 2. The current detector 10 includes a magnetic core 4, a magnetic sensor 6, and a mounting wiring board 100 disposed close to the conductor 2.

  The magnetic core 4 is a magnetic circuit that passes a magnetic flux generated by a current flowing through the conductor 2, and a magnetic sensor 6 is disposed in a gap portion provided in a part thereof. The magnetic core 4 is a member surrounding the conductor 2 in an annular shape, and is made of a magnetic material.

  The magnetic sensor 6 has a function of converting the magnetic flux generated by the current flowing through the conductor 2 and guided to the gap portion by the annular magnetic core 4 into an electric signal and outputting the electric signal. Be placed. As the magnetic sensor 6, for example, a Hall element can be used. The Hall element has four terminals including two input terminals and two output terminals.

  Of the four terminals of the Hall element that is the magnetic sensor 6, the two input terminals are connected to the input wirings 61 and 63, and the two output terminals are connected to the output wirings 65 and 67. Since the input wirings 61 and 63 cause a current to flow in the direction perpendicular to the magnetic flux of the magnetic circuit in the Hall element from the voltage source 8 via the power supply terminal 62 and the ground terminal 64 (see FIG. 3), a voltage is applied to the Hall element. It is wiring to give. The output wirings 65 and 67 are wirings for drawing out potentials at both ends of the Hall element that generate a potential difference due to magnetic flux.

  The mounting wiring board 100 includes a printed wiring board 99, a circuit element unit 20 and an arithmetic processing element unit 30 mounted thereon. The mounting wiring board 100 includes a circuit corresponding to a differential amplifier as disclosed in Patent Document 2, for example, with the circuit element unit 20 and the arithmetic processing element unit 30.

  FIG. 2 is a circuit diagram in which the magnetic sensor 6 is connected to the differential amplifier. Elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The differential amplifier formed by being mounted on the mounting wiring board 100 in FIG. 2 receives two output signals of the Hall element as the magnetic sensor 6 as input signals, and performs arithmetic processing based on the two input signals. It has a function. Specifically, a minute potential difference that is a difference between the two input signals is appropriately amplified and output. Note that when the noise voltages of ΔV1 and ΔV2 are applied to the two outputs V1 and V2 of the Hall element, respectively, an amplified noise voltage is output to the output of the differential amplifier as described later.

  The arithmetic processing element unit 30 is an operational amplifier that performs differential amplification together with the circuit element unit 20. An operational amplifier is an amplifying element that ideally has an infinite voltage gain and input resistance and zero output resistance. The operational amplifier includes two input terminals and one output terminal. In FIG. 2, the input wiring 83 connected to the inverting input terminal, the input wiring 81 connected to the non-inverting input terminal, and the output terminal are connected. Output wiring 85 to be connected is shown.

  The circuit element unit 20 includes an input resistance element 22, a ground resistance element 28, an input resistance element 24, a feedback resistance element 26, and a feedback capacitance element 29 arranged on the mounting wiring board 100. As will be described later, the resistance values (R1) of the input resistance element 22 and the input resistance element 24 are set equal (for example, 20 kΩ), and the resistance values (Rf) of the ground resistance element 28 and the feedback resistance element 26 are set equal (see FIG. For example, 470 kΩ).

  FIG. 3 is a diagram showing the printed wiring board 99. Elements similar to those in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted. The printed wiring board 99 has an input signal terminal unit 60, a calculation input terminal unit 80 connected to the input terminal of the arithmetic processing element unit 30, one end connected to the input signal terminal unit 60, and the other end calculated input terminal. A first wiring unit 40 and a second wiring unit 50, which are two wiring units connected to the unit 80, an output wiring unit 92 connected to the output terminal of the arithmetic processing element unit 30 and the arithmetic output terminal unit 86; A parasitic capacitance adjustment unit 70 is included. In the following, after describing each element of the input signal terminal unit 60 in detail, the calculation input terminal unit 80, the first wiring unit 40, the second wiring unit 50, the calculation output terminal unit 86, the output wiring unit 92, Each element will be described in detail in the order of the parasitic capacitance adjusting unit 70.

  The input signal terminal portion 60 is a terminal for connecting to the output wirings 65 and 67 of the Hall element that is the magnetic sensor 6, and is a terminal for inputting the output voltage of the Hall element to the mounting wiring board 100. The input signal terminal unit 60 includes a first input unit 66 and a second input unit 68.

  The first input unit 66 is a terminal connected to the output wiring 65 on one side of the Hall element. The first input unit 66 takes out the potential of the magnetic sensor 6 and inputs the potential to the arithmetic processing element unit 30 through the first wiring unit 40.

  The second input unit 68 is a terminal connected to the output wiring 67 on the other side of the Hall element. The second input unit 68 takes out the potential of the magnetic sensor 6 and inputs the potential to the arithmetic processing element unit 30 through the second wiring unit 50.

  The arithmetic input terminal unit 80 is a terminal connected to the input wirings 81 and 83 of the arithmetic processing element unit 30. The calculation input terminal unit 80 includes a first calculation terminal unit 82 and a second calculation terminal unit 84.

  The first calculation terminal unit 82 is a terminal connected to the input wiring 81 of the calculation processing element unit 30. The second arithmetic terminal unit 84 is a terminal connected to the input wiring 83 of the arithmetic processing element unit 30.

  The first wiring unit 40 includes a wiring pattern 42, an element arrangement land 44, a wiring pattern 46, and an element arrangement land 48. One end side of the first wiring unit 40 is connected to the first input unit 66, and the other end side is connected to the first calculation terminal unit 82.

  The wiring pattern 42 is a wiring that connects the first input unit 66 and the element placement land 44 and is previously placed on the printed wiring board 99, and has the same width as a wiring pattern 52 described later. As shown in FIG. 2, the parasitic capacitance 101 is generated by electrostatic coupling between the conductor 2 having a potential and the wiring pattern 42.

  The element arrangement land 44 is an area for attaching the input resistance element 22. The element placement land 44 is connected between the wiring pattern 42 and the wiring pattern 46.

  The wiring pattern 46 connects the element arrangement land 44, the element arrangement land 48, and the first calculation terminal portion 82, and is arranged in advance on the printed wiring board 99, and has the same width as the wiring pattern 56 described later. . As shown in FIG. 2, the parasitic capacitance 102 is generated by electrostatic coupling between the conductor 2 having a potential and the wiring pattern 46.

  The element arrangement land 48 is an area for attaching the ground resistance element 28. The element placement land 48 is connected between the wiring pattern 46 and a ground wiring 69 that is grounded via a ground terminal 64.

  The second wiring unit 50 includes a wiring pattern 52, an element arrangement land 54, a wiring pattern 56, an element arrangement land 58, and an element arrangement land 59.

  The wiring pattern 52 is a wiring that connects the second input unit 68 and the element placement land 54 and is previously placed on the printed wiring board 99, and has the same width as the wiring pattern 42. As shown in FIG. 2, the parasitic capacitance 103 is generated by electrostatic coupling between the conductor 2 having a potential and the wiring pattern 52.

  The element arrangement land 54 is an area for attaching the input resistance element 24. The element placement land 54 is connected between the wiring pattern 52 and the wiring pattern 56.

  The wiring pattern 56 is a wiring that connects the element placement land 54, the element placement land 58, the element placement land 59, and the second calculation terminal portion 84 and is previously placed on the printed wiring board 99, and is the same as the wiring pattern 46. Have a width. As shown in FIG. 2, the parasitic capacitance 104 is generated by electrostatic coupling between the conductor 2 having a potential and the wiring pattern 56.

  The element arrangement land 58 is an area for attaching the feedback resistance element 26. The element placement land 58 is connected between the wiring pattern 56 and the output wiring portion 92.

  The element arrangement land 59 is an area for attaching the feedback capacitive element 29. The element arrangement land 59 is arranged in parallel with the element arrangement land 58.

  The arithmetic output terminal unit 86 is a terminal connected to the output wiring 85 of the arithmetic processing element unit 30 and is also a terminal for connecting to the feedback resistance element 26 and the feedback capacitance element 29.

  The output wiring section 92 is a wiring that is connected to the calculation output terminal section 86 and is arranged in advance on the printed wiring board 99, and is used to draw out the voltage output by the arithmetic processing element section 30 to the outside of the mounting wiring board 100. Wiring.

  Here, returning to FIG. 2 again, the operation of the differential amplifier arranged on the mounting wiring board 100 will be described. In FIG. 2, the potential difference between the wiring pattern 52 and the ground wiring 69 is V1, and the potential difference between the wiring pattern 42 and the ground wiring 69 is V2. A potential difference between the output wiring portion 92 and the ground wiring 69 is set to Vo. When the resistance values (R1) of the input resistance element 22 and the input resistance element 24 are set equal and the resistance values (Rf) of the ground resistance element 28 and the feedback resistance element 26 are set equal, the output of the differential amplifier is Vo = (V2−V1). ) × Rf / R1.

  Further, since the mounting wiring board 100 is disposed in the vicinity of the conductor 2 having a potential, parasitic capacitance is generated by electrostatic coupling between the conductor 2 and the first wiring portion 40 and the second wiring portion 50. The noise voltage may be input to the differential amplifier through the parasitic capacitance.

  The factors that cause the input potential difference of the arithmetic processing element unit 30 to fluctuate due to each noise voltage are the parasitic capacitance 102 of the wiring pattern 46 and the parasitic capacitance 104 of the wiring pattern 56 of the first wiring unit 40 and the second wiring unit 50. This is due to the difference in capacitance value. This is because the impedance of the input resistance elements 22 and 24 (for example, 22 kΩ) is sufficiently larger than the impedance of the magnetic sensor 6, and therefore noise added via the parasitic capacitance 101 of the wiring pattern 42 and the parasitic capacitance 103 of the wiring pattern 52. This is because the voltage is sufficiently smaller than the noise voltage applied through the parasitic capacitance 102 included in the wiring pattern 46 and the parasitic capacitance 104 included in the wiring pattern 56. Therefore, if the noise voltage applied via the parasitic capacitance 104 is ΔV1 and the noise voltage applied via the parasitic capacitance 102 is ΔV2, the input resistance elements 22 and 24 have the same value. Are equal, the potential difference (ΔV2−ΔV1) corresponding to the noise voltage is zero. Therefore, since the noise voltage is canceled by the differential amplifier, the noise voltages ΔV1 and ΔV2 do not affect the output voltage of the differential amplifier.

  FIG. 4 is a diagram illustrating a state in which the vicinity of the input of the arithmetic processing element unit 30 is enlarged. The same elements as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted. The parasitic capacitance adjustment unit 70 is a wiring width adjustment unit for setting the values of the parasitic capacitance 102 and the parasitic capacitance 104 to the same value. The wiring width adjustment unit which is the parasitic capacitance adjustment unit 70 is arranged between the element arrangement land 48 and the first calculation terminal unit 82. Here, the capacitance value of the parasitic capacitance formed by the adjacent electrodes is proportional to the area of the electrodes and inversely proportional to the distance between the electrodes. Since the wiring width adjusting unit which is the parasitic capacitance adjusting unit 70 has a larger width than the wiring pattern 46 and increases the area, it is possible to increase the value of the parasitic capacitance with the conductor 2 having a potential. it can. Therefore, the parasitic capacitance 102 and the parasitic capacitance 104 can be set to the same value.

  Here, referring again to FIG. 2, the differential amplifier in the mounting wiring board 100 performs amplification based on the voltage output from the Hall element that is the magnetic sensor 6 via the input signal terminal portion 60. Here, as described above, the voltage input by the first input unit 66 is V2, and the voltage input by the second input unit 68 is V1. Therefore, if the noise voltage is not taken into account, as described above, the voltage Vo output by this differential amplifier is (V2−V1) × Rf / R1.

  In addition, as described above, in the parasitic capacitance between the conductor 2 and the first wiring portion 40 and the second wiring portion 50 of the mounting wiring board 100, the noise voltage ΔV1 is particularly generated when the capacitance values of the parasitic capacitances 102 and 104 are different. Since a potential difference is generated in ΔV2, and Vo = {(V2 + ΔV2) − (V1 + ΔV1)} × Rf / R1, a potential difference corresponding to a noise voltage is output by the differential amplifier.

  FIG. 5 is a diagram illustrating a state before and after attaching the parasitic capacitance adjusting unit 70 to the mounting wiring board 100. Elements similar to those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof is omitted. As shown in FIG. 5, in the wiring pattern 46, when comparing the parasitic capacitance 102 before the parasitic capacitance adjustment unit 70 is provided with the parasitic capacitance 104 between the wiring pattern 56 and the conductor 2, the wiring pattern 46 has the following characteristics. The area is small by a region for forming a part of the element arrangement land 59 connected to the. Therefore, before the parasitic capacitance adjustment unit 70 is provided, the capacitance value of the parasitic capacitance 102 is smaller than the capacitance value of the parasitic capacitance 104.

  However, when the parasitic capacitance adjusting unit 70 is provided in the wiring pattern 46, the parasitic capacitance adjusting unit 70 can change the wiring width as described above, and can compensate for the shortage of the area of the wiring pattern 46. it can. Therefore, since the area of the wiring pattern 46 and the area of the wiring pattern 56 can be made equal, the parasitic capacitance 102 and the parasitic capacitance 104 can have the same value. In this case, the noise voltages ΔV1 and ΔV2 have the same potential, and the noise voltage is canceled by the differential amplifier, so that the potential difference between the noise voltages can be prevented from being output by the differential amplifier.

  FIG. 6 is a diagram illustrating a current detector 11 according to another embodiment. FIG. 7 is a circuit diagram showing the connection relationship of the current detector 11. Elements similar to those in FIGS. 1 to 5 are denoted by the same reference numerals, and detailed description thereof is omitted. The current detector 11 has substantially the same configuration as that of the current detector 10, and the difference is that the parasitic capacitance adjusting unit 70 is not configured with a wiring width adjusting unit like the current detector 10. This is a point including a dummy circuit element 71 and a dummy circuit element arrangement land 72. The dummy circuit element arrangement land 72 is arranged in parallel with the element arrangement land 48 where the ground resistance element 28 is arranged. The dummy circuit element 71 is a resistance element arranged on the dummy circuit element arrangement land 72 and has a larger resistance value than the ground resistance element 28 so as not to affect the amplification action of the differential amplifier. be able to.

  FIG. 8 is a diagram illustrating a state before and after attaching the parasitic capacitance adjusting unit 70 to the mounting wiring board 100. Elements similar to those in FIGS. 1 to 7 are denoted by the same reference numerals, and detailed description thereof is omitted. As described above, the wiring pattern 46 has a small area by a region for forming a part of the element placement land 59 connected to the wiring pattern 56. Therefore, before the parasitic capacitance adjustment unit 70 is provided, the capacitance value of the parasitic capacitance 102 is smaller than the capacitance value of the parasitic capacitance 104.

  However, when the parasitic capacitance adjusting unit 70 is provided in the wiring pattern 46, the parasitic capacitance adjusting unit 70 has the dummy circuit element placement land 72, and can compensate for the shortage of the area of the wiring pattern 46. 102 and the parasitic capacitance 104 can have the same value. In this case, the noise voltages ΔV1 and ΔV2 have the same potential, and the noise voltage is canceled by the differential amplifier, so that the potential difference between the noise voltages can be prevented from being output by the differential amplifier.

  FIG. 9 is a diagram showing still another embodiment. Elements similar to those in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description thereof is omitted. The current detector 12 has substantially the same configuration as that of the current detector 10, and the difference is that the parasitic capacitance adjustment unit 70 is not configured with a wiring width adjustment unit like the current detector 10. This is a point that includes the conductor piece 74 and the conductor piece arrangement land 73. The conductor piece arrangement land 73 is arranged on the wiring pattern 46. The conductor piece 74 is a conductor piece whose area parallel to the surface of the mounting wiring board 100 and a vertical height can be changed, and adjusting the parasitic capacitance generated between the conductor 2 and the conductor piece 74. Can do.

  FIG. 10 is a diagram illustrating a state before and after attaching the parasitic capacitance adjusting unit 70 to the mounting wiring board 100. Elements similar to those in FIGS. 1 to 9 are denoted by the same reference numerals, and detailed description thereof is omitted. As described above, the wiring pattern 46 has a small area by a region for forming a part of the element placement land 59 connected to the wiring pattern 56. Therefore, before the parasitic capacitance adjustment unit 70 is provided, the capacitance value of the parasitic capacitance 102 is smaller than the capacitance value of the parasitic capacitance 104.

  However, when the parasitic capacitance adjusting unit 70 is provided in the wiring pattern 46, the parasitic capacitance adjusting unit 70 can arrange the conductor piece 74 on the wiring pattern and adjust the height thereof. By making them close, the capacitance value of the parasitic capacitance 102 can be increased, and the parasitic capacitance 102 and the parasitic capacitance 104 can have the same value. In this case, the noise voltages ΔV1 and ΔV2 have the same potential, and the noise voltage is canceled by the differential amplifier, so that the potential difference between the noise voltages can be prevented from being output by the differential amplifier.

It is a figure which shows the current detector which concerns on this invention. It is a circuit diagram which connected the magnetic sensor to the differential amplifier. It is a figure which shows a printed wiring board. It is a figure which shows a mode that the input vicinity of the arithmetic processing element part was expanded. It is a figure which shows the mode before and behind attaching a parasitic capacitance adjustment part to a mounting wiring board. It is a figure which shows the current detector in other embodiment. It is a circuit diagram which shows the connection relation of the current detector in other embodiment. It is a figure which shows the mode before and behind attaching a parasitic capacitance adjustment part to a mounting wiring board. It is a figure which shows another embodiment. It is a figure which shows the mode before and behind attaching a parasitic capacitance adjustment part to a mounting wiring board.

Explanation of symbols

  2 conductors, 4 magnetic cores, 6 magnetic sensors, 8 voltage sources, 10, 11, 12 current detectors, 20 circuit element units, 22, 24 input resistance elements, 26 feedback resistance elements, 28 ground resistance elements, 29 feedback capacitances Element, 30 Arithmetic processing element part, 40 First wiring part, 42, 46, 52, 56 Wiring pattern, 44, 48, 54, 58, 59 Element arrangement land, 50 Second wiring part, 60 Input signal terminal part, 61 63, 81, 83 Input wiring, 62 Power supply terminal, 64 Ground terminal, 65, 67, 85 Output wiring, 66 First input section, 68 Second input section, 69 Ground wiring, 70 Parasitic capacitance adjustment section, 71 Dummy circuit Element, 72 Dummy circuit element arrangement land, 73 Conductor piece arrangement land, 74 Conductor piece, 80 Operation input terminal section, 82 First operation terminal section, 84 Second operation terminal section, 86 Calculation Output terminal section, 92 output wiring section, 99 printed wiring board, 100 mounting wiring board, 101, 102, 103, 104 parasitic capacitance.

Claims (9)

A printed wiring board in which an outer conductor having a potential is arranged close to each other,
A plurality of input signal terminals for receiving a plurality of input signals respectively;
One end is connected to each input signal terminal unit, and the other end is connected to an arithmetic processing element that performs arithmetic processing based on each input signal, and a plurality of wiring units for connecting via a plurality of arithmetic input terminal units,
A parasitic capacitance adjusting unit provided in at least one wiring unit and having the same value as each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit;
A printed wiring board comprising: A mounting wiring board in which an outer conductor having a potential is arranged close to each other,
A plurality of input signal terminals each receiving a plurality of input signals;
An arithmetic processing element for performing arithmetic processing based on each input signal;
One end is connected to each input signal terminal portion, the other end is connected to the arithmetic processing element via a plurality of arithmetic input terminal portions, and a plurality of wiring portions connecting one or more circuit elements;
A parasitic capacitance adjusting unit provided in at least one wiring unit and having the same value as each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit;
A mounting wiring board comprising: A conductor through which the current to be detected flows;
An annular magnetic circuit for passing a magnetic flux generated by a current flowing through a conductor, and a magnetic core provided with a gap in a part thereof;
A magnetic sensor disposed in the magnetic gap of the magnetic core;
A mounting wiring board disposed close to the conductor;
With
The mounting wiring board is
A plurality of input signal terminals each receiving a plurality of input signals;
An arithmetic processing element for performing arithmetic processing based on each input signal;
One end is connected to each input signal terminal unit, one or more circuit elements are connected, and the other end is connected to the arithmetic processing element via a plurality of arithmetic input terminal units, and a plurality of wiring units,
A parasitic capacitance adjusting unit provided in at least one wiring unit and having the same value as each parasitic capacitance formed by electrostatic coupling between the external conductor and each wiring unit;
A current detector. The printed wiring board according to claim 1,
The printed wiring board, wherein the parasitic capacitance adjusting unit changes a wiring width of the wiring unit so that each parasitic capacitance has the same value. The printed wiring board according to claim 1,
The printed wiring board, wherein the parasitic capacitance adjusting unit is provided with a dummy pad for arranging dummy circuit elements having the same value of each parasitic capacitance in at least one wiring unit. The printed wiring board according to claim 1,
The printed wiring board, wherein the parasitic capacitance adjusting unit is provided with a conductor piece pad for arranging conductor pieces having the same value of each parasitic capacitance in at least one wiring portion. The mounting wiring board according to claim 2,
A mounting wiring board, wherein the parasitic capacitance adjusting unit changes a wiring width of the wiring unit so that each parasitic capacitance has the same value. The mounting wiring board according to claim 2,
The parasitic capacitance adjusting unit is configured to connect a dummy circuit element having the same value of each parasitic capacitance to at least one wiring unit when the number of circuit elements connected to each wiring unit is different from each other. Mounting wiring board. The mounting wiring board according to claim 2,
The mounting wiring board characterized in that the parasitic capacitance adjusting unit changes the size or height of the conductor piece so that the conductor piece is connected to at least one wiring part and the value of each parasitic capacitance is the same value.

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