JP2009064836A - Layout method and layout program for integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout method and a layout program for an integrated circuit which has differential signal wiring and multi-bit bus signal wiring which are made resistance to noise. <P>SOLUTION: One bridge BR or a plurality of bridges BR are inserted to differential signal wiring DATA[0] and DATAX[0], DATA[1] and DATAX[1], DATA[2] and DATAX[2], and DATA[3] and DATAX[3] formed, and each of the differential signal wiring is so as to be twisted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit layout method and layout program, and more particularly, to an integrated circuit layout method and layout program having differential signal wiring and multi-bit bus signal wiring.

  Conventionally, in a layout process in digital design, a circuit module defined in the netlist is chipped based on a netlist generated by logically synthesizing an RTL (Register transfer level) file described in HDL (Hardware Description Language). Arranged above, wiring layout between circuit modules was performed.

  The wiring layout includes a clock wiring layout and a data wiring layout. Timing verification based on the circuit delay time and the wiring delay time is performed on these wiring layouts to check that the designed circuit operates normally. If the timing verification cannot be passed, circuit module placement and wiring layout are repeated until the timing verification is passed.

  In recent years, with an increase in the speed of integrated circuits, it has become common to propagate clock signals and data signals as small-amplitude differential signals. In the case of differential signals, it is required that the differential signal wirings have the same length in order to reduce the skew between the differential signals. That is, the layout of the differential signal wiring is more restricted than the layout of the normal single-ended wiring.

  Further, with respect to the multi-bit bus signal wiring, it is desirable to reduce the skew between the signals and make the arrival timing of the multi-bit bus signal substantially coincide at the input of the circuit module that receives these signals. In other words, the layout of the multi-bit bus signal wiring is more restricted than the layout of the normal single-ended wiring.

  Conventionally, as a differential signal wiring layout method, it has been proposed to lay out a pair of differential signal wirings as a single virtual wiring and then replace the virtual wiring with a pair of wirings (for example, a patent). Reference 1). That is, in the layout method of the differential signal wiring, first, after arranging the circuit modules, a pair of wirings are laid out as virtual wirings, and then the virtual wirings are replaced with a pair of wirings. Layout is to be performed. Here, the wiring width of the virtual wiring can be replaced with a pair of wirings by keeping the sum of the wiring width of the pair of wirings and the wiring interval, thereby laying out the pair of wirings in parallel. can do. This makes it possible to realize an equal-length differential signal wiring.

  Conventionally, although it relates to a bit line of a ferroelectric memory, a plurality of bit line pairs are crossed, and the positions of the intersecting twist regions are alternately shifted between adjacent bit line pairs. There has been proposed a technique for reducing crosstalk given through parasitic capacitance between a pair of bit lines (see, for example, Patent Document 2).

  Furthermore, conventionally, with regard to crosstalk, which is noise caused by a certain signal to other signals, consideration has also been made regarding crosstalk in capacitive signal lines caused by capacitance between wirings (for example, Non-Patent Document 1). reference).

JP 2002-217302 A JP 2003-263886 A William J. Dally, by John W. Poulton, directed by Tadahiro Kuroda, “Digital System Engineering Fundamentals”, Maruzen Co., Ltd., pp.331-334, published in March 2003

  By the way, in order to realize the small-amplitude differential signal wiring by the layout program, there is a problem regarding handling of noise in addition to the above-described equal length of the differential signal wiring.

  In other words, conventional layout programs for single ends with full amplitude corresponding to the potential difference between the power supply voltage and ground not only have a low transmission speed but also a sufficiently large signal amplitude, so that noise related to interference between wirings is handled. Even a certain range was sufficient.

  However, in the case of a small-amplitude differential signal, it is necessary to consider noise caused by crosstalk between multi-bit bus wirings and potential fluctuations in adjacent power supply lines, and it is necessary to determine whether the wiring layout is acceptable or not accordingly. .

  Here, there are two ways to handle noise. One idea is to handle noise quantitatively, and the other idea is to make a layout that does not require quantitative analysis of noise and eliminate the need for quantitative treatment of noise.

  As a layout that eliminates the need for quantitative treatment of noise, a twisted differential signal wiring as shown in Patent Document 2 can be considered. Patent Document 2 is an example in which a twisted differential signal wiring is applied in a ferroelectric memory cell array, but there is a description regarding crosstalk resistance due to the twisting of the differential signal wiring.

  And by making a differential signal wiring into a twist structure like patent document 2, the propagation of a noise-free small amplitude differential signal is realizable in principle.

  In recent years, with an increase in the speed of integrated circuits, a layout program capable of handling a small amplitude differential signal is required even in digital design. However, since the current layout program for digital design is intended for full amplitude single-ended wiring, it cannot satisfy the requirements for small amplitude differential signal wiring. That is, in order to realize the small amplitude differential signal wiring by the layout program, it is necessary to handle the noise resistance in consideration of ensuring the equal length.

  As shown in Patent Document 1 described above, although there is a method for realizing equal length of differential signal wiring, consideration on noise resistance is insufficient. And as what improves this noise tolerance, there exists a differential signal wiring of the twist structure as shown in patent document 2 mentioned above.

  That is, in Patent Document 1, although a small-amplitude differential signal wiring can be realized by a layout program, noise resistance is not considered. In Patent Document 2, noise resistance can be improved by a twist structure. It is not realized by a layout program.

  SUMMARY OF THE INVENTION In view of the above-described problems of the related art, the present invention provides a layout method for an integrated circuit having a differential signal wiring and a multi-bit bus signal wiring that are resistant to noise without carrying out substantial quantitative handling of noise. And to provide a layout program.

  According to the first aspect of the present invention, an integrated circuit layout is characterized in that one or a plurality of bridges are inserted into the formed differential signal wiring and the differential signal wiring is twisted. A method is provided.

  According to the second aspect of the present invention, the computer is caused to execute a procedure of inserting one or a plurality of bridges into the formed differential signal wiring and twisting the differential signal wiring. There is provided an integrated circuit layout program characterized in that a circuit layout is performed.

  According to the present invention, it is possible to provide a layout method and a layout program for an integrated circuit having differential signal wiring and multi-bit bus signal wiring having noise tolerance without performing quantitative treatment of substantial noise. it can.

  First, before explaining in detail an embodiment of an integrated circuit layout method and a layout program according to the present invention, the principle of the integrated circuit layout method according to the present invention will be described with reference to FIGS.

  1 to 4 are diagrams for schematically explaining the principle of an integrated circuit layout method according to the present invention. For example, in order to eliminate quantitative handling of noise, a small amplitude differential signal wiring is twisted. An integrated circuit layout program to be (twisted) will be described.

  First, as shown in FIG. 1, for example, a plurality of differential signal wirings DATA [0] and DATAX [0] formed between the output side of the preceding circuit and the input side of the succeeding circuit are equal in length; DATA [1], DATAX [1]; DATA [2], DATAX [2]; DATA [3], DATAX [3] are prepared. The equal-length differential signal wiring can be formed by applying the method described in Patent Document 1 described above or various methods such as a method described later with reference to FIGS.

  Next, as shown in FIG. 2, a certain distance (for example, differential signal wirings DATA [0], DATAX [0] and DATA [1], DATAX [1]) with respect to adjacent differential signal wirings ( A bridge (intersection) BR is inserted for each bridge insertion basic wiring length E to twist each differential signal wiring. Here, as shown in FIG. 2, the positions of the bridges to be inserted into each differential signal wiring are inserted alternately in adjacent differential signal wirings.

  That is, for example, in the differential signal wiring DATA [0] and DATAX [0] in FIG. 2, the position of the positive logic signal wiring DATA [0] is changed in a state of being connected in the region of the bridge BR, and the negative logic The signal wiring DATAX [0] is cut in the region of the bridge BR, and has a twist structure (twisted) so that the position is changed via the vias VHX00 and VHX01 and the lower wiring LXB0. Note that the lower layer wiring may be used as the layout of the bridge BR, but it goes without saying that the upper layer wiring can also be used.

  Then, as shown in FIG. 2, for example, one bridge BR is inserted into one of a pair of adjacent differential signal wirings (DATA [0], DATAX [0]), and the other (DATA [1] , DATAX [1]), a configuration in which two bridges BR shifted by a certain distance (bridge insertion basic wiring length) E are inserted as a twisted basic configuration U. The twist basic configuration U is not limited to that shown in FIG. 2, and various patterns can be applied.

  Next, referring to FIG. 3, when attention is paid to the differential signal wirings DATA [2] and DATAX [2], the differential signal wirings DATA [1] and DATAX [1] adjacent to the lower side in FIG. Influence on signal due to capacitive coupling (parasitic capacitance between wirings), and influence on signal due to capacitive coupling between differential signal wirings DATA [3] and DATAX [3] adjacent to the upper side in FIG. Will be explained. Here, the signal wirings DATA [1], DATA [2] and DATA [3] are low level “0”, and the signal wirings DATAX [1], DATAX [2] and DATAX [3]) are high level “1”. Assume that

  First, the signal wiring DATA [2] is pulled up by the signal wiring DATAX [3] in the region Ru21 by capacitive coupling between the differential signal wirings DATA [3] and DATAX [3] adjacent to the upper side in FIG. (Function to increase the potential of the signal wiring) and pull-down (function to decrease the potential of the signal wiring) by the signal wiring DATA [3] in the region Rd21. As a result, the signal wiring DATA [2] The effect of capacitive coupling between the differential signal lines DATA [3] and DATAX [3] is offset.

  Further, the signal wiring DATAX [2] is pulled down by the signal wiring DATA [3] in the region Rdx21 due to capacitive coupling between the differential signal wirings DATA [3] and DATAX [3] which are adjacent to each other in the upper part in FIG. As a result, the signal line DATAX [3] is pulled up in the region Rux21. As a result, the influence of capacitive coupling between the differential signal lines DATA [3] and DATAX [3] on the signal line DATAX [2] is canceled out. Is done.

  Further, the signal wiring DATA [2] is pulled up by the signal wiring DATAX [1] in the region Ru11 by capacitive coupling between the differential signal wirings DATA [1] and DATAX [1] adjacent to the lower side in FIG. At the same time, the signal line DATA [1] is pulled down in the region Rd11. As a result, the influence of capacitive coupling between the differential signal lines DATA [1] and DATAX [1] on the signal line DATAX [2] is canceled out. Is done.

  Further, the signal wiring DATAX [2] is pulled down by the signal wiring DATA [1] in the region Rdx11 due to capacitive coupling between the differential signal wirings DATA [1] and DATAX [1] adjacent to the lower side in FIG. As a result, the signal line DATAx [1] is pulled up in the region Rux11. As a result, the influence of capacitive coupling between the differential signal lines DATA [1] and DATAX [1] on the signal line DATA [2] is canceled out. Is done.

  In addition, the influence on the signal due to capacitive coupling between the other differential signal wiring and the differential signal wiring adjacent thereto is similarly canceled.

  FIG. 4 shows a change in signal amplitude by simulation in order to show the effect of countermeasures against crosstalk by twisting, and FIG. 4 (a) uses a differential signal wiring twisted by inserting a bridge. 4 (b) shows a configuration using parallel differential signal wirings without being twisted, and FIG. 4 (c) shows a signal waveform (between differential signals) of both configurations. Potential difference).

  That is, as shown in FIG. 4 (c), the signal amplitude via the twisted differential signal wiring of FIG. 4 (a) passes only through the parallel differential signal wiring of FIG. 4 (b). It can be seen that it is much larger than the signal amplitude. Specifically, in FIG. 4C, as indicated by the curve C2, the signal amplitude via the parallel differential signal wiring that is not twisted is 0.87 V, whereas it is indicated by the curve C1. As described above, the signal amplitude via the twisted differential signal wiring is 1.31 V, and the decrease in signal amplitude (waveform dullness) due to capacitive coupling between adjacent wirings can be greatly improved. I understand.

  As described above, according to the present invention, it is possible to perform layout of an integrated circuit having differential signal wiring and multi-bit bus signal wiring having noise resistance without performing quantitative treatment of substantial noise. .

  Embodiments of an integrated circuit layout method and layout program according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 5 is a flowchart for explaining the processing as one embodiment of the integrated circuit layout method according to the present invention. FIGS. 6 and 7 are for explaining the bridge insertion threshold wiring length B in the flowchart shown in FIG. FIG. FIG. 6 corresponds to the diagram shown in Non-Patent Document 1 described above.

  First, when the layout processing of the integrated circuit according to the first embodiment is started, the length A of the differential signal wiring laid out between the circuit modules is derived in step ST10, and the process proceeds to step ST11. Then, a bridge insertion threshold wiring length B, which is a wiring length threshold for bridge insertion, is derived. Here, the bridge insertion threshold wiring length B can be obtained, for example, by applying the logical expression described in Non-Patent Document 1 described above.

Here, for example, in the two signal wirings LA and LB as shown in FIG. 6, when one signal wiring LA is driven and the other signal wiring LB is floating, the wiring LA is connected to the wiring LB and the parasitic coupling capacitance. Is coupled with C _C , the line LB is coupled with a line other than the line LA (including the ground) with capacitance C ₀ , and the signal line LB is driven with the output impedance R ₀ , the above-mentioned non-patent Applying the logical expression described in Document 1,

ΔV _{LB, max} = K _C (τ _xp / t _r ) {1-exp (−t _r / τ _xp )}
K _C = C _C / (C _C + C ₀ ), τ _xp = R ₀ (C _C + C ₀ )
It can be asked. Here, K _C represents the capacitive coupling coefficient, t _r represents the rise time of V _LA.

Further, by setting R ₀ = 1.1 [KΩ], C _C = 9.1 [pF / m], C ₀ = 2.5 [pF / m], the wiring LA as shown in FIG. The relationship between the influence on the wiring LB and the wiring length (bridge insertion threshold wiring length B) is obtained.

  Then, as shown in FIG. 7, in order to make the potential fluctuation from the signal line LA to the signal line LB less than 10% of the signal amplitude propagated through the signal line LB, the wiring length (bridge insertion threshold wiring length B) is set. It can be seen that it must be within 100 μm. As described above, the bridge insertion threshold wiring length B is not limited to that obtained by applying the logical expression described in Non-Patent Document 1, and can be derived as an appropriate length by various methods. .

  In the flowchart of FIG. 5 again, when the process proceeds to step ST12, it is determined whether or not the differential signal wiring length A is longer than the bridge insertion threshold wiring length B (A> B?). In step ST12, when it is determined that the differential signal wiring length A is equal to or less than the bridge insertion threshold wiring length B (A ≦ B), the process proceeds to step ST19, and the processing is terminated as no bridge insertion. That is, when the differential signal wiring length A is shorter than the bridge insertion threshold wiring length B serving as a threshold value, it is determined that there is no need to insert a bridge to make a twist, and the process ends.

  On the other hand, if it is determined in step ST12 that the differential signal wiring length A is longer than the bridge insertion threshold wiring length B (A> B), the process proceeds to step ST13, and the process proceeds to step ST14 with the bridge insertion. That is, when the differential signal wiring length A is longer than the bridge insertion threshold wiring length B which is a threshold value, it is determined that it is necessary to insert a bridge to make a twist.

  Here, when twisting is necessary, it is necessary to determine the location and the number of bridges to be inserted. In the first embodiment, as shown in FIG. Is a bridge insertion basic wiring length E, and two sets of differential signal wirings corresponding to four times the length (4 × E) are a twist basic configuration U. In addition, due to the principle of the twist structure, there is no mutual interference due to crosstalk in the twist basic configuration U. Then, when determining the number D of bridge BR insertions, the number of twisted basic components U is determined.

  That is, in step ST14, the initial wiring length (wiring length) C is set to the differential signal wiring length A (C = A), and the basic configuration number (number of bridges BR to be inserted) D is set to 1 (D = 1). The process proceeds to step ST15.

  In step ST15, it is determined whether or not the wiring length C is shorter than four times the bridge insertion threshold wiring length B (C <4B?).

  If it is determined in step ST15 that the wiring length C is four times or more of the bridge insertion threshold wiring length B (C ≧ 4B), the process proceeds to step ST16, and the wiring length C is four times the bridge insertion threshold wiring length B. Is subtracted to obtain a new wiring length C (C = C-4B), and the basic configuration number D is incremented by 1 to obtain a new basic configuration number D (D = D + 1), and step ST15. Returning to step S3, the same processing is repeated until it is determined that C <4B. As a result, the number of twisted basic configurations U to be inserted can be obtained as D. Based on the calculation so far, the bridge insertion basic wiring length E is determined.

  That is, if it is determined in step ST15 that the wiring length C is shorter than four times the bridge insertion threshold wiring length B (C <4B), the process proceeds to step ST17, where the bridge insertion basic wiring length E, E = A ÷ D ÷ 4 is determined, and the process proceeds to step ST18.

  In step ST18, a bridge is inserted according to the bridge insertion basic wiring length E calculated in step ST17, the differential signal wiring is twisted, and the process ends.

  8 to 10 are diagrams for schematically explaining an example of processing for performing layout of multi-bit bus wiring to which the present invention is applied.

  As described above, the existing integrated circuit layout program is intended for single-ended wiring and normally cannot handle differential signal wiring. However, FIGS. 8 to 10 show such existing integrated circuit layout programs. The differential signal wiring is formed without significantly changing the above.

  That is, as shown in FIG. 8, first, for an actual circuit module having differential input / output terminals, single-ended terminals (DATA [0], DATA [1], DATA [2], DATA [3]) are set. The dummy circuit modules are replaced by thick wirings.

  Thereafter, as shown in FIG. 9, a dummy circuit module having a single-ended terminal is connected to differential input / output terminals (DATA [0], DATAX [0]; DATA [1], DATAX [1]; DATA [2]. , DATAX [2]; DATA [3], DATAX [3]).

  Subsequently, as shown in FIG. 10, the thick wiring wired using the terminal information of the dummy circuit module is cut out to the width along the terminal information of the actual circuit module, that is, at the center of one thick wiring. Grooves are formed to form two differential signal wirings, thereby realizing equal length of the differential signal wirings.

  Needless to say, the differential signal wiring forming process is not limited to the above-described method, and other methods such as the method described in Patent Document 1 described above can be applied.

  FIG. 11 is a flowchart for explaining processing as another embodiment of the integrated circuit layout method according to the present invention, and FIG. 12 is a diagram for explaining segments in the flowchart shown in FIG.

  As is clear from the comparison between FIG. 11 and FIG. 5 described above, the second embodiment segments the differential signal wiring and applies the processing shown in FIG. 5 to each segment.

  That is, when the integrated circuit layout process according to the second embodiment is started, the differential signal wiring is segmented in step ST20, the number of segments F is derived, and the process proceeds to step ST10. Here, the processing of steps ST10 to ST19 executed in segment units is the same as the processing described with reference to FIG. 5, and the description thereof is omitted.

  When the twisting process for the first segment (F = 1) is completed, the process proceeds to step ST21, the segment number F is decremented by 1 (F = F-1), the process proceeds to step ST22, and the last segment The same processing is performed until the number of segments F = 0, and the processing is terminated.

  Note that the differential signal wiring segmentation process in step ST20 is, for example, dividing a bent differential signal wiring into segments at linear portions, and performing a twisting process on each segment.

  Specifically, in the example shown in FIG. 12, the bent differential signal wiring is divided into three linear segments SEG1, SEG2, and SEG3, and only the central second segment SEG2 is twisted.

  Here, in the second segment SEG2, it can be considered that there is no influence of crosstalk between the differential signal wiring sets. On the other hand, since the first segment SEG1 and the third segment SEG3 are not twisted structures, there is some interference due to the influence of crosstalk, but the influence of the crosstalk is small and the twisting is not performed.

  That is, for example, when the reference of the bridge insertion threshold wiring length B used for the determination of twisting is 5%, the example of FIG. 12 shows the differential signal wiring set in the first segment SEG1 and the third segment SEG3. This corresponds to a case where the mutual interference due to the crosstalk is within 5%.

  As a result, in the example of FIG. 12, for example, it is considered that the mutual interference due to crosstalk between the entire differential signal wiring sets is within 10%. As described above, even when the differential signal wiring is bent instead of being a straight line, it is possible to sufficiently reduce the influence of the entire interference by determining the twisting in units of segments.

  That is, even when the differential signal wiring is not linear, it is possible to realize a wiring layout that is highly resistant to noise and can have the effect within the assumption. Note that the differential signal wiring segmentation processing is not limited to dividing the bent differential signal wiring into straight portions.

  FIG. 13 is a flowchart for explaining processing as still another embodiment of the integrated circuit layout method according to the present invention, and FIG. 14 is a diagram for explaining twisting in the flowchart shown in FIG.

  As is apparent from the comparison between FIG. 13 and FIG. 11 described above, the third embodiment is obtained by replacing steps ST14 to ST18 in FIG. 13 with new steps ST24 and ST25.

  That is, in the third embodiment, when the differential signal wiring length A is determined to be longer than the bridge insertion threshold wiring length B (A> B) in step ST12, and bridge insertion is determined in step ST13, That is, if the differential signal wiring length A is longer than the bridge insertion threshold wiring length B, which is a threshold value, it is determined that a bridge needs to be inserted and twisted, and the process proceeds to step ST24.

  In step ST24, the distance between the centers of the bridges is determined for the bridge insertion basic wiring length E. In the third embodiment, the bridge insertion basic wiring length E is derived as E = A / B / 4, and step ST25 is performed. Then, twist processing is performed from one end of the differential signal wiring.

  That is, in the first and second embodiments described above, the bridge insertion basic wiring length E is derived as E = A / D / 4, and the bridge BR is inserted evenly with respect to the differential signal wiring to be twisted. However, in the third embodiment, the calculation for evenly inserting the bridges is omitted, and the bridge insertion basic wiring length E is set as the bridge insertion threshold wiring length B. Are equal.

  Specifically, as shown in FIG. 14, a bridge BR is inserted from the left end of the drawing with the bridge insertion threshold wiring length B as a basic unit for the differential signal wiring to be twisted. In this case, naturally, the surplus region RR is generated, but the mutual interference due to the crosstalk between the differential signal wiring sets by the surplus region RR is equal to or less than the interference amount applied when the bridge insertion threshold wiring length B is derived. It should be no problem to ignore it.

  As described above, according to the third embodiment, it is possible to realize a wiring layout that can further simplify the processing, have high noise resistance, and can have the effect within the assumption.

  In the above first to third embodiments according to the present invention, the timing verification may be performed before the differential signal wiring is twisted, or may be performed after the differential signal wiring is twisted. Is possible. Further, as described above, the position of the bridge to be inserted into the differential signal wiring can be automatically determined (by the layout program). However, in consideration of various other conditions (the operator of the layout program) It can also be determined manually).

  FIG. 15 is a diagram for explaining a twisted structure in the integrated circuit layout method according to the present invention.

  As is clear from the comparison between FIG. 15 and FIG. 2 described above, as the layout of the bridge BR, the lower layer wiring (LxB01) may be used as shown in FIG. 2, but as shown in FIG. In addition, both the lower layer wiring (LxB01) and the upper layer wiring (LxB00) may be used. Of course, only the upper layer wiring (LxB00) can be used. In addition, a plurality of upper layer wirings and / or lower layer wirings can be used by using other wiring layers, and connection by vias may be performed at a plurality of locations. This is effective in reducing the resistance of the connection point by the via because the signal wiring generally has a large resistance at the connection point by the via (VHx00, VHx01).

  As described above, according to each embodiment of the present invention, it is possible to realize a small-amplitude differential signal wiring having a twist structure by a layout program without quantitatively handling noise. As a result, a layout program that can be handled only up to several hundred megahertz can be handled up to several tens of gigahertz.

  As a result, it is possible to easily realize a digital circuit in the tens of gigahertz realized by manual layout by a layout program, and it is possible to significantly reduce the man-hours in the digital circuit design.

  Therefore, according to the present invention, for example, the characteristics of an existing layout program for the layout of a full-amplitude single-ended wiring are sufficiently considered, and the differential signal wiring and noise resistance are considered using the characteristics. An integrated circuit layout method and layout program having multi-bit bus signal wirings can be provided.

  FIG. 16 is a diagram for explaining an example of a medium recording an integrated circuit layout program to which the present invention is applied. In FIG. 16, reference numeral 10 denotes an integrated circuit layout processing apparatus (computer), 20 denotes a program (data) provider, and 30 denotes a portable recording medium.

  For example, the present invention is given as a program (data) for the processing apparatus 10 as shown in FIG. The processing device 10 includes an arithmetic processing device main body 11 including a processor, and a processing device side memory (for example, a RAM (Random Access Memory) that stores a result of giving or processing a program (data) to the arithmetic processing device main body 11. ) Or hard disk) 12 or the like. The program provided to the processing device 10 is loaded and executed on the main memory of the processing device 10.

  The program provider 20 has means (line destination memory: for example, DASD (Direct Access Storage Device)) 21 for storing the program, and provides the program to the processing apparatus 10 via a line such as the Internet, or The data is provided to the processing apparatus 10 via a portable recording medium 30 such as an optical disk such as a CD-ROM or DVD, a magnetic disk, or a magnetic tape. Needless to say, the medium on which the layout program of the integrated circuit according to the present invention is recorded includes the processing device side memory 12, the line destination memory 21, the portable recording medium 30, and the like.

(Appendix 1)
An integrated circuit layout method, wherein one or a plurality of bridges are inserted into a formed differential signal wiring, and the differential signal wiring is twisted. (1, FIG. 2, FIG. 5, FIG. 11 to FIG. 14)

(Appendix 2)
The integrated circuit layout method according to attachment 1, wherein the bridge layout uses an upper layer, a lower layer, or upper and lower wiring layers in which the differential signal wiring is formed. Circuit layout method. (2, Fig. 2, Fig. 15)

(Appendix 3)
3. The integrated circuit layout method according to claim 1, wherein selection of the bridge layout is automatically or manually determined. (FIGS. 5 to 11)

(Appendix 4)
4. The integrated circuit layout method according to claim 1, wherein the position of the bridge to be inserted into the differential signal wiring is determined automatically or manually. (FIGS. 5 to 11)

(Appendix 5)
In the integrated circuit layout method according to any one of appendices 1 to 3, when the position of the bridge to be inserted into the differential signal wiring is automatically determined, the differential signal wiring to be twisted is added to the differential signal wiring. On the other hand, it is possible to select whether to arrange the bridges equally or to arrange the bridges at a fixed interval from one end of the differential signal wiring. (3, FIG. 5, FIG. 11 to FIG. 14)

(Appendix 6)
In the integrated circuit layout method according to any one of appendices 1 to 5, when the differential signal wiring is not linear, the linear portion of the differential signal wiring is divided into segments, and An integrated circuit layout method, wherein the differential signal wiring is twisted. (4, 11 and 12)

(Appendix 7)
On the computer,
An integrated circuit characterized in that one or a plurality of bridges are inserted into the formed differential signal wiring, the procedure for twisting the differential signal wiring is executed, and the layout of the integrated circuit is performed. Layout program. (5, FIG. 2, FIG. 5, FIG. 11 to FIG. 14, FIG. 16)

(Appendix 8)
A medium on which the integrated circuit layout program according to appendix 7 is recorded. (Fig. 16)

  The present invention is preferably applied to a layout of an integrated circuit that handles differential signals that have been increased in speed and reduced in amplitude. However, the present invention is not limited thereto, and various types having differential signal wiring, multi-bit bus signal wiring, and the like. The present invention can be widely applied as a layout technology for various integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram (part 1) for schematically explaining the principle of an integrated circuit layout method according to the present invention; FIG. 3 is a diagram (part 2) for schematically explaining the principle of the integrated circuit layout method according to the present invention; FIG. 6 is a third diagram for schematically explaining the principle of the integrated circuit layout method according to the present invention; FIG. 6 is a diagram (part 4) for schematically explaining the principle of the integrated circuit layout method according to the invention; 6 is a flowchart for explaining processing as one embodiment of a layout method of an integrated circuit according to the present invention. FIG. 6 is a diagram (part 1) for explaining a bridge insertion threshold wiring length in the flowchart shown in FIG. 5; FIG. 6 is a (second) diagram for explaining a bridge insertion threshold wiring length in the flowchart shown in FIG. 5; It is FIG. (1) for demonstrating schematically an example of the process which performs the layout of the multi-bit bus wiring which this invention is applied to. It is FIG. (2) for demonstrating schematically an example of the process which performs the layout of the multi-bit bus wiring which this invention is applied to. It is FIG. (3) for demonstrating schematically an example of the process which performs the layout of the multi-bit bus wiring which this invention is applied to. It is a flowchart for demonstrating the process as another Example of the layout method of the integrated circuit which concerns on this invention. It is a figure for demonstrating the segment in the flowchart shown in FIG. It is a flowchart for demonstrating the process as another Example of the layout method of the integrated circuit which concerns on this invention. It is a figure for demonstrating twisting in the flowchart shown in FIG. It is a figure for demonstrating the twist structure in the layout method of the integrated circuit which concerns on this invention. It is a figure for demonstrating the example of the medium which recorded the design program of the semiconductor integrated circuit to which this invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Processing device 11 Arithmetic processing device main body 12 Processing device side memory 20 Program (data) provider 21 Means for storing program (line destination memory)
30 Portable recording media

Claims (5)

  An integrated circuit layout method, wherein one or a plurality of bridges are inserted into the formed differential signal wiring, and the differential signal wiring is twisted.   2. The integrated circuit layout method according to claim 1, wherein the bridge layout uses an upper layer, a lower layer, or upper and lower wiring layers in which the differential signal wiring is formed. Integrated circuit layout method.   3. The integrated circuit layout method according to claim 1, wherein when the position of the bridge to be inserted into the differential signal wiring is automatically determined, the differential signal wiring to be twisted is A method of laying out an integrated circuit, characterized in that it is possible to select whether to arrange each bridge equally or to arrange each bridge at a constant interval from one end of the differential signal wiring.   4. The integrated circuit layout method according to claim 1, wherein when the differential signal wiring is not linear, the linear portion of the differential signal wiring is divided into segments, A method for laying out an integrated circuit, wherein the differential signal wiring is twisted. On the computer,
An integrated circuit characterized in that one or a plurality of bridges are inserted into the formed differential signal wiring, the procedure for twisting the differential signal wiring is executed, and the layout of the integrated circuit is performed. Layout program.

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