JP2009064360A5

JP2009064360A5 -

Info

Publication number: JP2009064360A5
Application number: JP2007233377A
Authority: JP
Filing date: 2007-09-07
Publication date: 2010-08-26
Anticipated expiration: 2027-09-07

Claims

In a memory controller that reads and writes data to multiple memory devices with different access cycles,
Holding means for holding memory access requests for the plurality of memory devices;
When issuing a memory access request held in the holding means to a memory device, the order of issuing the memory access request is changed based on wiring delay information indicating a wiring delay between the memory controller and each memory device. And a control means for controlling the memory controller.

In a memory controller that reads and writes data to multiple memory devices with different access cycles,
Holding means for holding memory access requests for the plurality of memory devices;
Control for controlling to change the order in which the memory access requests are issued based on the latency information indicating each latency in the plurality of memory devices when issuing the memory access request held in the holding means to the memory device And a memory controller.

A register that holds the latency information;
The memory controller according to claim 2, wherein the control unit performs control so as to change an order of issuing the memory access requests based on latency information held in the register.

A register for holding the wiring delay information;
The memory controller according to claim 1, wherein the control unit performs control so as to change an order of issuing the memory access requests based on wiring delay information held in the register.

An external terminal for supplying the wiring delay information from the outside;
The memory controller according to claim 1, wherein the control unit performs control so as to change an order of issuing the memory access requests based on wiring delay information supplied from the external terminal.

The control means uses the wiring delay information for the first memory access request held in the holding means and the wiring delay information for the second memory access request held in the holding means to determine whether the first memory access request is the 2 6. The memory controller according to claim 4, wherein when the access waiting time is longer than that of the first memory access request, the order is changed so that the second memory access request is issued.

A method of controlling a memory controller that reads and writes data to a plurality of memory devices having different access cycles,
Holding a memory access request for the plurality of memory devices; and
When issuing the memory access request held in the holding step to the memory device, the order of issuing the memory access request is changed based on the wiring delay information indicating the wiring delay between the memory controller and each memory device. And a control process for controlling the memory controller.

A method of controlling a memory controller that reads and writes data to a plurality of memory devices having different access cycles,
Holding a memory access request for the plurality of memory devices; and
A control step of controlling to change the order of issuing the memory access requests based on latency information indicating the latency in the plurality of memory devices when issuing the memory access request held in the holding step to the memory device And a method for controlling the memory controller.