JP2009064360A5 - - Google Patents
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- JP2009064360A5 JP2009064360A5 JP2007233377A JP2007233377A JP2009064360A5 JP 2009064360 A5 JP2009064360 A5 JP 2009064360A5 JP 2007233377 A JP2007233377 A JP 2007233377A JP 2007233377 A JP2007233377 A JP 2007233377A JP 2009064360 A5 JP2009064360 A5 JP 2009064360A5
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- memory
- access request
- memory access
- issuing
- wiring delay
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Claims (8)
前記複数のメモリデバイスに対するメモリアクセス要求を保持する保持手段と、
前記保持手段に保持されたメモリアクセス要求をメモリデバイスに発行する際に、前記メモリコントローラと各メモリデバイスとの間の配線遅延を示す配線遅延情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御する制御手段とを有することを特徴とするメモリコントローラ。 In a memory controller that reads and writes data to multiple memory devices with different access cycles,
Holding means for holding memory access requests for the plurality of memory devices;
When issuing a memory access request held in the holding means to a memory device, the order of issuing the memory access request is changed based on wiring delay information indicating a wiring delay between the memory controller and each memory device. And a control means for controlling the memory controller.
前記複数のメモリデバイスに対するメモリアクセス要求を保持する保持手段と、
前記保持手段に保持されたメモリアクセス要求をメモリデバイスに発行する際に、前記複数のメモリデバイスにおける各レイテンシを示すレイテンシ情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御する制御手段とを有することを特徴とするメモリコントローラ。 In a memory controller that reads and writes data to multiple memory devices with different access cycles,
Holding means for holding memory access requests for the plurality of memory devices;
Control for controlling to change the order in which the memory access requests are issued based on the latency information indicating each latency in the plurality of memory devices when issuing the memory access request held in the holding means to the memory device And a memory controller.
前記制御手段は、前記レジスタに保持されているレイテンシ情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御することを特徴とする請求項2記載のメモリコントローラ。 A register that holds the latency information;
The memory controller according to claim 2, wherein the control unit performs control so as to change an order of issuing the memory access requests based on latency information held in the register.
前記制御手段は、前記レジスタに保持されている配線遅延情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御することを特徴とする請求項1記載のメモリコントローラ。 A register for holding the wiring delay information;
The memory controller according to claim 1, wherein the control unit performs control so as to change an order of issuing the memory access requests based on wiring delay information held in the register.
前記制御手段は、前記外部端子から供給された配線遅延情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御することを特徴とする請求項1記載のメモリコントローラ。 An external terminal for supplying the wiring delay information from the outside;
The memory controller according to claim 1, wherein the control unit performs control so as to change an order of issuing the memory access requests based on wiring delay information supplied from the external terminal.
前記複数のメモリデバイスに対するメモリアクセス要求を保持する保持工程と、
前記保持工程で保持されたメモリアクセス要求をメモリデバイスに発行する際に、前記メモリコントローラと各メモリデバイスとの間の配線遅延を示す配線遅延情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御する制御工程とを有することを特徴とするメモリコントローラの制御方法。 A method of controlling a memory controller that reads and writes data to a plurality of memory devices having different access cycles,
Holding a memory access request for the plurality of memory devices; and
When issuing the memory access request held in the holding step to the memory device, the order of issuing the memory access request is changed based on the wiring delay information indicating the wiring delay between the memory controller and each memory device. And a control process for controlling the memory controller.
前記複数のメモリデバイスに対するメモリアクセス要求を保持する保持工程と、
前記保持工程で保持されたメモリアクセス要求をメモリデバイスに発行する際に、前記複数のメモリデバイスにおけるレイテンシを示すレイテンシ情報に基づき、前記メモリアクセス要求を発行する順序を変更するように制御する制御工程とを有することを特徴とするメモリコントローラの制御方法。 A method of controlling a memory controller that reads and writes data to a plurality of memory devices having different access cycles,
Holding a memory access request for the plurality of memory devices; and
A control step of controlling to change the order of issuing the memory access requests based on latency information indicating the latency in the plurality of memory devices when issuing the memory access request held in the holding step to the memory device And a method for controlling the memory controller.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007233377A JP5349775B2 (en) | 2007-09-07 | 2007-09-07 | Memory controller and control method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007233377A JP5349775B2 (en) | 2007-09-07 | 2007-09-07 | Memory controller and control method thereof |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009064360A JP2009064360A (en) | 2009-03-26 |
JP2009064360A5 true JP2009064360A5 (en) | 2010-08-26 |
JP5349775B2 JP5349775B2 (en) | 2013-11-20 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007233377A Active JP5349775B2 (en) | 2007-09-07 | 2007-09-07 | Memory controller and control method thereof |
Country Status (1)
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JP (1) | JP5349775B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5393270B2 (en) * | 2009-06-09 | 2014-01-22 | キヤノン株式会社 | Memory control circuit, memory system, and control method |
JP5393289B2 (en) * | 2009-06-24 | 2014-01-22 | キヤノン株式会社 | Memory control circuit, memory system, and control method |
US8707002B2 (en) | 2009-06-09 | 2014-04-22 | Canon Kabushiki Kaisha | Control apparatus |
JP5448595B2 (en) * | 2009-06-18 | 2014-03-19 | キヤノン株式会社 | Control apparatus and control method |
JP7197998B2 (en) | 2018-05-02 | 2022-12-28 | キヤノン株式会社 | Memory controllers and methods implemented in memory controllers |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4019056B2 (en) * | 2004-02-25 | 2007-12-05 | エヌイーシーコンピュータテクノ株式会社 | Read request arbitration control system and method |
US7222224B2 (en) * | 2004-05-21 | 2007-05-22 | Rambus Inc. | System and method for improving performance in computer memory systems supporting multiple memory access latencies |
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2007
- 2007-09-07 JP JP2007233377A patent/JP5349775B2/en active Active
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