JP2009055123A - Threshold setting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for setting the threshold of an input buffer at a desired value while suppressing power consumption. <P>SOLUTION: The threshold setting circuit includes a first threshold control circuit for controlling the threshold voltage of a buffer circuit, a reference buffer circuit having the characteristics substantially identical to those of the buffer circuit, a second threshold control circuit having the characteristics substantially identical to those of the first threshold control circuit and controlling the threshold voltage of the reference buffer circuit depending on a digital signal, and a digital control circuit for supplying a digital signal to the second threshold control circuit, wherein the digital control circuit monitors a differential voltage between the threshold voltage of the reference buffer circuit and a predetermined reference voltage while changing the digital signal, stores the value of the digital signal when the differential voltage becomes substantially zero, and sets the threshold voltage of the buffer circuit by supplying a digital signal having the value identical to the stored value to the first threshold control circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention generally relates to electronic circuits, and more particularly to a threshold setting circuit that controls a threshold of an input buffer.

  An input buffer provided in a signal input portion to the semiconductor integrated circuit outputs a HIGH or LOW logic value corresponding to the signal level of the input signal. VIH and VIL are defined as input signal standards. If the voltage value of the input signal is higher than VIH, it is regarded as a logical value HIGH, and if the voltage value of the input signal is lower than VIL, it is regarded as a logical value LOW. Normal operation is guaranteed.

  FIG. 1 is a diagram illustrating a general configuration of an input buffer. The input buffer 10 in FIG. 1 includes a PMOS transistor 11 and an NMOS transistor 12. The channel of the PMOS transistor 11 and the channel of the NMOS transistor 12 are connected in series, and the gate of the PMOS transistor 11 and the gate of the NMOS transistor 12 are connected to the input terminal 13. A coupling point between the drain of the PMOS transistor 11 and the drain of the NMOS transistor 12 functions as an output node. An input signal VIN input to the input terminal 13 is inverted by an inverter composed of a PMOS transistor 11 and an NMOS transistor 12, and is output from the output node as an output signal VOUT. The input buffer 10 is driven by the power supply voltage VDD and the ground voltage VSS.

  FIG. 2 is a diagram for explaining the VIH / VIL standard of the input signal of the input buffer. When an input signal such as that shown in FIG. 2 that changes between the power supply voltage VDD and the ground voltage VSS is input to the input buffer, a signal that is higher than the VIH level shown in FIG. 2 is recognized as HIGH and a signal that is lower than the VIL level. Is recognized as LOW. That is, in the case of the input buffer 10 in which the input / output is inverted as shown in FIG. 1, the output signal VOUT becomes a LOW level digital signal in response to the input signal VIN higher than the VIH level, and responds to the input signal VIN lower than the VIL level. Thus, the output signal VOUT becomes a high level digital signal. In order to realize this, it is necessary to set the threshold value of the input buffer 10 between VIH and VHL. If the voltage difference between VIH and VIL is required to be small due to system specifications or the like, it may be difficult to set the threshold value of the input buffer 10 between VIH and VHL.

  FIG. 3 is a diagram for explaining fluctuations in the threshold value of the input buffer due to process variations. Waveforms 21 to 23 shown in FIG. 3 are input / output waveforms showing the relationship between the input voltage VIN and the output voltage VOUT of the input buffer 10, and show how the output voltage VOUT decreases as the input voltage VIN increases. Yes. A plurality of input / output waveforms 21 to 23 show variations in characteristics of the input buffer 10 due to process variations. On the straight line shown as VIN = VOUT, the input voltage VIN and the output voltage VOUT are equal. Therefore, the intersection of this straight line and the input / output waveform may be considered as the threshold voltage of the input buffer 10.

  In the input buffer 10 as shown in FIG. 1, the value of the threshold voltage depends on the current driving power (ON resistance value) of the PMOS transistor 11 and the current driving power (ON resistance value) of the NMOS transistor 12. When the current driving capability of the PMOS transistor 11 is strong (when the ON resistance value is small), the threshold voltage increases as shown by the input / output waveform 23 of FIG. When the current driving capability of the PMOS transistor 11 is strong (when the ON resistance value is small), the threshold voltage becomes low as shown by the input / output waveform 21 of FIG. Since the driving power of each transistor varies due to process variations, it is not easy to set the threshold voltage of the input buffer 10 to a desired value.

  FIG. 4 is a diagram illustrating a configuration of a circuit that adjusts the threshold voltage of the input buffer 10. In the circuit shown in FIG. 4, a plurality of input buffers 10 are provided, and NMOS transistors 14 are connected in series to each input buffer 10. In the case of a plurality of input / output waveforms 21 to 23 shown in FIG. 3, the driving force for pulling the buffer output to the ground potential side through the NMOS transistors 12 and 14 is changed by adjusting the ON resistance value of the NMOS transistor 14. Thus, the threshold voltage can be made different.

  The reference circuit 30 includes a PMOS transistor 31, an NMOS transistor 32, and an NMOS transistor 33. The PMOS transistor 31, NMOS transistor 32, and NMOS transistor 33 are configured to have the same size as the PMOS transistor 11, NMOS transistor 12, and NMOS transistor 14, respectively. The channel of the PMOS transistor 31 and the channel of the NMOS transistor 32 are connected in series. The gate of the PMOS transistor 31 and the gate of the NMOS transistor 32 are combined and connected to the coupling point between the drain of the PMOS transistor 31 and the drain of the NMOS transistor 32. As a result, the input / output of the inverter composed of the PMOS transistor 31 and the NMOS transistor 32 is short-circuited, and the threshold voltage of the inverter appears at the input / output short-circuit point.

  The differential amplifier 34 receives the threshold voltage at its non-inverting input terminal and the reference voltage VREF at its inverting input terminal. The differential amplifier 34 outputs a voltage corresponding to the difference between the threshold voltage and the reference voltage VREF. The output voltage of the differential amplifier 34 is applied to the gates of the NMOS transistor 14 and the NMOS transistor 33.

  As described above, the PMOS transistor 31, the NMOS transistor 32, and the NMOS transistor 33 are the same size as the PMOS transistor 11, the NMOS transistor 12, and the NMOS transistor 14, respectively. The NMOS transistor 14 and the NMOS transistor 33 are controlled by the same gate voltage. Therefore, the threshold voltage of the reference circuit 30 is equal to the threshold voltage of the input buffer 10. With this configuration, when the threshold voltage of the reference circuit 30 is adjusted to be equal to the reference voltage VREF based on feedback control via the differential amplifier 34, the threshold voltage of the input buffer 10 is set to be equal to the reference voltage VREF. The

As shown in FIG. 4, a configuration for adjusting a threshold value based on feedback control of a reference circuit is disclosed in, for example, Patent Document 1 and Patent Document 2. However, in the threshold adjustment circuit as shown in FIG. 4, a current always flows through the reference circuit 30 and the differential amplifier 34 in order to set the threshold value of the input buffer to the adjustment value. Therefore, power is constantly consumed, which is not suitable for applications that require low power consumption.
JP 2002-368601 A Japanese Patent No. 2800711 Japanese Patent No. 2861608

  In view of the above, an object of the present invention is to provide a threshold control circuit capable of setting a threshold value of an input buffer to a desired value while suppressing power consumption.

  The threshold setting circuit includes a buffer circuit, a first threshold control circuit for controlling a threshold voltage of the buffer circuit, a reference buffer circuit having substantially the same characteristics as the buffer circuit, and the first threshold control. A second threshold control circuit having substantially the same characteristics as the circuit and controlling the threshold voltage of the reference buffer circuit according to the digital signal; and a digital for supplying the digital signal to the second threshold control circuit The digital control circuit monitors a difference voltage between a threshold voltage of the reference buffer circuit and a predetermined reference voltage while changing the digital signal, and the difference voltage becomes substantially zero. The threshold value of the buffer circuit is set by storing the value of the digital signal at the time and supplying a digital signal having the same value as the stored value to the first threshold value control circuit. The features.

  According to at least one embodiment of the present invention, the threshold value setting circuit sets the threshold value of the input buffer by digital control. By using digital control instead of analog control, the digital control circuit detects and stores a digital code that makes the threshold voltage of the reference buffer circuit equal to the reference voltage, and controls the threshold voltage of the input buffer. The control circuit can be supplied with a digital code equal to the stored digital code. Since the digital code for achieving an appropriate threshold voltage is already stored, it is not necessary to drive the reference buffer circuit and the second threshold control circuit during the normal operation of the input buffer. That is, once the digital code of the first threshold control circuit is set, the digital control circuit sets the digital code supplied to the second threshold control circuit to a predetermined value, thereby setting the reference buffer circuit and the second threshold control. The amount of current flowing through the circuit can be set to zero. Thus, by setting it as the structure which sets a threshold voltage based on digital control, the extra power consumption in a reference circuit can be eliminated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 5 is a diagram showing an example of the configuration of a semiconductor integrated circuit including a threshold setting circuit according to the present invention. A semiconductor integrated circuit 40 shown in FIG. 5 includes an LSI-IO area 41 and an LSI core area 42. The LSI-IO area 41 is provided with a plurality of input buffers 43 and a plurality of output buffers (not shown), and the LSI core area 42 is a core circuit (for example, for realizing the intended function of the semiconductor integrated circuit 40). A CPU, a memory circuit, and related control circuits (not shown) are provided. Input / output of signals between the core circuit and the outside of the semiconductor integrated circuit 40 is performed via an input buffer and an output buffer provided in the LSI-IO area 41.

  The LSI-IO area 41 is further provided with a threshold control circuit 44 that controls the threshold voltage of the input buffer 43. The LSI core area 42 is further provided with a reference buffer circuit 45, a threshold control circuit 46, and a digital control circuit 47 according to the present invention. The reference buffer circuit 45 has substantially the same characteristics as the input buffer 43. The threshold control circuit 46 has substantially the same characteristics as the threshold control circuit 44 and controls the threshold voltage of the reference buffer circuit 45 according to the digital signal. The digital control circuit 47 supplies a digital signal to the threshold control circuit 46.

  The digital control circuit 47 monitors the difference voltage between the threshold voltage of the reference buffer circuit 45 and a predetermined reference voltage while changing the digital signal, and the value of the digital signal when the difference voltage becomes substantially zero. Remember. The digital control circuit 47 further sets a threshold voltage of the input buffer 43 by supplying a digital signal having the same value as the stored value to the threshold control circuit 44.

  As described above, the input buffer 43 and the threshold control circuit 44 have the same characteristics as the reference buffer circuit 45 and the threshold control circuit 46, respectively. The threshold control circuit 44 and the threshold control circuit 46 are controlled by digital signals having the same value. Therefore, the threshold voltage of the input buffer 43 is equal to the threshold voltage of the reference buffer circuit 45. Since the threshold voltage of the reference buffer circuit 45 is adjusted to be equal to the reference voltage based on the control by the digital control circuit 47, the threshold voltage of the input buffer 43 is set to be equal to the reference voltage.

  Compared with the conventional configuration of FIG. 4, the threshold setting circuit shown in FIG. 5 is different in that the threshold of the input buffer 43 is set by digital control. By using digital control instead of analog control, the digital control circuit 47 detects and stores a digital code to the threshold control circuit 46 so that the threshold voltage of the reference buffer circuit 45 becomes equal to the reference voltage. A digital code equal to the stored digital code can be supplied to the threshold control circuit 44 for controlling the threshold voltage. Since the digital code for achieving an appropriate threshold voltage is already stored, it is not necessary to drive the reference buffer circuit 45 and the threshold control circuit 46 during the normal operation of the semiconductor integrated circuit 40. That is, once the digital code of the threshold control circuit 44 is set, the digital control circuit 47 sets the digital code to be supplied to the threshold control circuit 46 to a predetermined value, and thereby the current flowing through the reference buffer circuit 45 and the threshold control circuit 46. The amount can be set to zero. Thus, by setting it as the structure which sets a threshold voltage based on digital control, the extra power consumption in a reference circuit can be eliminated.

  FIG. 6 is a diagram for explaining the detailed configuration of the reference buffer circuit 45, the threshold control circuit 46, and the digital control circuit 47. The comparator 57 and the up counter 58 shown in FIG. 6 correspond to the digital control circuit 47 of FIG.

  The reference buffer circuit 45 includes a PMOS transistor 51 and an NMOS transistor 52. The gate and drain of the PMOS transistor 51 and the gate and drain of the NMOS transistor 52 are all connected to one common node A, and the voltage appearing at this node A is used as the threshold voltage of the reference buffer circuit 45, and the non-inversion of the comparator 57 Supply to the input end. A reference voltage VREF is supplied to the inverting input terminal of the comparator 57.

  The threshold control circuit 46 includes a plurality of NMOS transistors 53 to 56 provided in parallel between the source of the NMOS transistor 52 and the ground voltage VSS. Bits C0 to C3 of the digital signal output from the up counter 58 are supplied to the gates of the plurality of NMOS transistors 53 to 56, respectively. The gate widths W of the NMOS transistors 53 to 56 are 1, 2, 4, and 8 as relative values, respectively. When the ON resistance value of each of the NMOS transistors 53 to 56 is substantially inversely proportional to the gate width W, the digital signal composed of the bits C0 to C3 is expressed as a binary number, and the ON resistance value corresponding to the binary value is expressed. Can be realized. That is, for example, if (C3, C2, C1, C0) is (0, 0, 1, 1), the NMOS transistors 53 and 54 are in a conducting state, and the NMOS transistors 55 and 56 are in a non-conducting state. The resistance value is 1/3. For example, if (C3, C2, C1, C0) is (1, 0, 0, 1), the NMOS transistors 53 and 56 are in a conductive state and the NMOS transistors 54 and 55 are in a non-conductive state, and the relative ON resistance is The value is 1/9.

  The up counter 58 counts up binary numbers represented by bits C0 to C3. That is, (C3, C2, C1, C0) starts from (0, 0, 0, 0), and (0, 0, 0, 1), (0, 0, 1, 0), (0, 0 , 1, 1), (0, 1, 0, 0), (0, 1, 0, 1),... This count-up operation is started by asserting the start signal Start and is performed in synchronization with the clock signal Clock. During the count-up operation, the up counter 58 activates the comparator 57 by setting the activation signal supplied to the comparator 57 to the enable state.

  The overall ON resistance value of the threshold control circuit 46 gradually decreases as the count value of the up counter 58 increases. As the ON resistance value of the threshold control circuit 46 decreases, the threshold voltage (potential of the node A) of the reference buffer circuit 45 decreases. When the threshold voltage of the reference buffer circuit 45 is larger than the reference voltage VREF, the output of the comparator 57 is HIGH. The up counter 58 continues the count up operation while the output of the comparator 57 is HIGH.

  When the threshold voltage of the reference buffer circuit 45 decreases as the count value of the up counter 58 increases, the threshold voltage of the reference buffer circuit 45 becomes equal to or lower than the reference voltage VREF at a certain time. When the threshold voltage of the reference buffer circuit 45 becomes equal to or lower than the reference voltage VREF, the output of the comparator 57 (determination signal Judge) becomes LOW. The change of the output of the comparator 57 to LOW is adjusted so that the difference voltage between the threshold voltage of the reference buffer circuit 45 and the reference voltage VREF becomes substantially zero and the threshold voltage becomes equal to the reference voltage VREF. It shows that.

  In response to the LOW output of the comparator 57, the up counter 58 stops the count up operation and stores the count value at that time. The up-counter 58 supplies a digital signal having the same value as the stored count value to the threshold control circuit 44 (see FIG. 5) and sets the digital signal value supplied to the threshold control circuit 46 to a predetermined value (in this case, “ By setting it to 0 "), the amount of current flowing through the reference buffer circuit 45 is made zero. Further, the up counter 58 sets the activation signal supplied to the comparator 57 to the disabled state, and deactivates the comparator 57. As a result, after the threshold setting of the input buffer 43 via the threshold control circuit 44 is completed, the current flowing through the reference buffer circuit 45, the threshold control circuit 46, and the comparator 57 is set to zero to eliminate unnecessary power consumption. be able to.

  FIG. 7 is a diagram illustrating an example of the circuit configuration of the up counter 58. 7 includes NAND circuits 61 to 63, an inverter 64, a start / stop control circuit 65, a 4-bit counter 66, and a latch 67. The NAND circuit 61 and the NAND circuit 62 configure an RS latch by using the output of each other as one of the inputs.

  The start / stop control circuit 65 controls the start / stop of the count-up operation of the 4-bit counter 66 by controlling the supply of the clock signal CK to the 4-bit counter 66. It also has a function of resetting the 4-bit counter 66 and setting the count value to “0000”. The operation of the start / stop control circuit 65 is controlled by the output of the NAND circuit 62 and the output of the NAND circuit 63.

  The latch 67 latches the count value of the 4-bit counter 66 in response to the change of the output of the NAND circuit 61 to HIGH according to the change of the determination signal Judge from the comparator 57 (see FIG. 6) to LOW. The value held by the latch 67 is supplied to the threshold control circuit 44 (see FIG. 5) as digital signals C0 ′ to C3 ′.

  FIG. 8 is a timing chart for explaining the operation of the up counter 58. Hereinafter, the operation of the up counter 58 will be described with reference to FIGS. 7 and 8.

  When the circuit is activated by turning on the power, a LOW pulse is input to one input of the NAND circuit 61 as a reset signal. As a result, the output of the NAND circuit 61 becomes HIGH. At this time, the operation start signal Start is LOW, and the output of the NAND circuit 63 is HIGH. Accordingly, the two inputs of the NAND circuit 62 are HIGH, and the output of the NAND circuit 62 is LOW. The reset signal at startup is fixed to HIGH after becoming LOW at circuit startup. This is the initial state of the up counter 58.

  In the initial state, the operation start signal Start changes from LOW to HIGH to instruct the start of the count-up operation. In response to this, the output of the NAND circuit 63 becomes LOW for a predetermined time (the delay time of the inverter 64). In response to the LOW pulse output from the NAND circuit 63, the start / stop control circuit 65 starts supplying the clock signal CK to the 4-bit counter 66, and causes the 4-bit counter 66 to perform a count-up operation. The initial value of the 4-bit counter 66 is “0000”, and the count value increases by one in synchronization with the clock signal CK. In FIG. 8, this count value is shown as C [3: 0].

  Further, the output of the NAND circuit 62 becomes HIGH in response to the LOW pulse of the output of the NAND circuit 63, and the HIGH output of the NAND circuit 62 is supplied to the comparator 57 as the comparator control signal ENcontrol. As a result, the comparator 57 is activated. At the start of the count-up operation, as shown in FIG. 8, since the voltage at the node A (the threshold voltage of the reference buffer circuit 45) is higher than the reference voltage VREF, the determination signal Judge that is the output of the comparator 57 is HIGH. Since the startup reset signal is also HIGH, the output of the NAND circuit 61 is LOW.

  As shown in FIG. 8, when the voltage at the node A decreases as the count value C [3: 0] of the 4-bit counter 66 increases, the voltage at the node A becomes equal to or lower than the reference voltage VREF at a certain time. When the voltage at the node A becomes equal to or lower than the reference voltage VREF, the output of the comparator 57 (determination signal Judge) becomes LOW. The change of the judgment signal Judge to LOW is adjusted so that the difference voltage between the threshold voltage of the reference buffer circuit 45 and the reference voltage VREF becomes substantially zero and the threshold voltage becomes equal to the reference voltage VREF. Indicates.

  In response to the change of the determination signal Judge to LOW, the output of the NAND circuit 61 changes to HIGH. In response to this change, the latch 67 latches the count value of the 4-bit counter 66. In the example of FIG. 8, the count value C [3: 0] when the voltage at the node A becomes equal to or lower than the reference voltage VREF is “0101”, and this value “0101” is stored in the latch 67. When the latch 67 stores “0101”, the output C [3: 0] ′ of the latch 67 is set to “0101” as shown in FIG. As a result, the digital signal to the threshold control circuit 44 that sets the threshold of the input buffer 43 (see FIG. 5) is set to a desired value.

  When the output of the NAND circuit 61 changes to HIGH in response to the change of the determination signal Judge to LOW, the output of the NAND circuit 62 becomes LOW. The output of the NAND circuit 62 is a comparator control signal ENcontrol. As shown in the lowermost stage of FIG. 8, the comparator control signal ENcontrol maintains the HIGH level during the counting operation, and then the voltage at the node A is lower than the reference voltage VREF. It changes to LOW in response to becoming. As a result, the comparator 57 is deactivated and power consumption by the comparator 57 is eliminated.

  When the output of the NAND circuit 62 becomes LOW, the start / stop control circuit 65 stops the supply of the clock signal CK to the 4-bit counter 66 in response to this, and the count value of the 4-bit counter 66 is set to “0000”. Reset to. This reset operation is shown as a change of the count value C [3: 0] to “0000” in FIG. Thus, by setting the value of the digital signal supplied to the threshold control circuit 46 (see FIG. 6) to a predetermined value (in this case, “0000”), the amount of current flowing through the reference buffer circuit 45 is made zero.

  With the above operation, the threshold voltage of the input buffer 43 is adjusted to be equal to the reference voltage VREF. After this adjustment, the current flowing through the reference buffer circuit 45, the threshold control circuit 46, and the comparator 57 can be set to zero, and unnecessary power consumption can be eliminated.

  FIG. 9 is a diagram for explaining a modification of the threshold control circuit. In FIG. 9, the same components as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.

  The reference buffer circuit 45, the comparator 57, and the up counter 58 shown in FIG. 9 have the same configuration as that shown in FIG. 6 and perform the same operation. In FIG. 9, a threshold control circuit 71 is provided instead of the threshold control circuit 46.

  The threshold control circuit 71 includes a plurality of PMOS transistors 73 to 76 provided in parallel between the source of the PMOS transistor 51 and the power supply voltage VDD. Bits C0 to C3 of the digital signal output from the up counter 58 are supplied to the gates of the plurality of PMOS transistors 73 to 76, respectively. The gate widths W of the PMOS transistors 73 to 76 are 1, 2, 4, and 8 as relative values, respectively. When the ON resistance value of each of the PMOS transistors 73 to 76 is approximately inversely proportional to the gate width W, the digital signal composed of the bits C0 to C3 is expressed as a binary number, so that the ON resistance value corresponding to the binary value is represented. Can be realized. That is, for example, if (C3, C2, C1, C0) is (0, 0, 1, 1), the PMOS transistors 73 and 74 are in a non-conductive state, and the PMOS transistors 75 and 76 are in a conductive state. The resistance value is 1/12. For example, if (C3, C2, C1, C0) is (1, 0, 0, 1), the PMOS transistors 73 and 76 are in a non-conductive state and the PMOS transistors 74 and 75 are in a conductive state. The value is 1/6.

  The up counter 58 counts up binary numbers represented by bits C0 to C3. That is, (C3, C2, C1, C0) starts from (0, 0, 0, 0), and (0, 0, 0, 1), (0, 0, 1, 0), (0, 0 , 1, 1), (0, 1, 0, 0), (0, 1, 0, 1),... The overall ON resistance value of the threshold control circuit 71 gradually increases as the count value of the up counter 58 counts up. As the ON resistance value of the threshold control circuit 71 increases, the threshold voltage (potential of the node A) of the reference buffer circuit 45 decreases. When the threshold voltage of the reference buffer circuit 45 is larger than the reference voltage VREF, the output of the comparator 57 is HIGH. The up counter 58 continues the count up operation while the output of the comparator 57 is HIGH.

  When the threshold voltage of the reference buffer circuit 45 decreases as the count value of the up counter 58 increases, the threshold voltage of the reference buffer circuit 45 becomes equal to or lower than the reference voltage VREF at a certain time. When the threshold voltage of the reference buffer circuit 45 becomes equal to or lower than the reference voltage VREF, the output of the comparator 57 (determination signal Judge) becomes LOW. The change of the output of the comparator 57 to LOW is adjusted so that the difference voltage between the threshold voltage of the reference buffer circuit 45 and the reference voltage VREF becomes substantially zero and the threshold voltage becomes equal to the reference voltage VREF. It shows that.

  In response to the LOW output of the comparator 57, the up counter 58 stops the count up operation and stores the count value at that time. The up counter 58 supplies a digital signal having the same value as the stored count value to the threshold control circuit of the input buffer. At this time, the input buffer may have the same configuration as that of the input buffer 43 shown in FIG. It may be a provided PMOS transistor. The up counter 58 further sets the value of the digital signal supplied to the threshold control circuit 71 to a predetermined value (in this case, “1111”), thereby reducing the amount of current flowing through the reference buffer circuit 45 to zero. Further, the activation signal supplied to the comparator 57 is set to a disabled state, and the comparator 57 is deactivated. As a result, the current flowing through the reference buffer circuit 45, the threshold control circuit 71, and the comparator 57 can be made zero, and unnecessary power consumption can be eliminated.

As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
(Appendix 1)
A buffer circuit;
A first threshold control circuit for controlling a threshold voltage of the buffer circuit;
A reference buffer circuit having substantially the same characteristics as the buffer circuit;
A second threshold control circuit having substantially the same characteristics as the first threshold control circuit and controlling the threshold voltage of the reference buffer circuit according to a digital signal;
A digital control circuit for supplying the digital signal to the second threshold control circuit, wherein the digital control circuit changes a difference between the threshold voltage of the reference buffer circuit and a predetermined reference voltage while changing the digital signal; And storing the value of the digital signal when the differential voltage becomes substantially zero, and supplying the digital signal having the same value as the stored value to the first threshold value control circuit. A threshold setting circuit characterized by setting a threshold voltage of a buffer circuit.
(Appendix 2)
The buffer circuit operates based on a first power supply voltage and a second power supply voltage, and the first threshold control circuit controls a resistance value provided between the buffer circuit and the second power supply voltage. The reference buffer circuit operates based on the first power supply voltage and the second power supply voltage, and the second threshold control circuit includes the reference buffer circuit and the second power supply voltage. The threshold value setting circuit according to claim 1, wherein the threshold value setting circuit is a resistance value control circuit that controls a resistance value provided between the two power supply voltages.
(Appendix 3)
The buffer circuit
A first transistor of a first conductivity type;
A second transistor of a second conductivity type having a drain connected to the drain of the first transistor, the first threshold control circuit between the source of the second transistor and the second power supply voltage; A second transistor of the second conductivity type provided in parallel to each other,
The reference buffer circuit is
A fourth transistor of the first conductivity type;
A fifth transistor of a second conductivity type having a drain connected to the drain of the first transistor, the second threshold control circuit between the source of the fifth transistor and the second power supply voltage; A second transistor of the second conductivity type provided in parallel with each other,
The threshold value according to claim 2, wherein each bit of the digital signal output from the digital control circuit is supplied to each gate of the plurality of third transistors and each gate of the plurality of sixth transistors. Setting circuit.
(Appendix 4)
The reference buffer circuit connects the gate and drain of the fourth transistor and the gate and drain of the fifth transistor to one common node, and supplies the voltage appearing at the one node to the reference buffer. The threshold value setting circuit according to appendix 3, wherein the threshold value voltage of the circuit is used.
(Appendix 5)
The digital control circuit supplies a digital signal having the same value as the stored value to the first threshold control circuit, and sets a value of the digital signal supplied to the second threshold control circuit to a predetermined value. The threshold value setting circuit according to any one of appendices 2 and 3, wherein the amount of current flowing through the reference buffer circuit is set to zero.
(Appendix 6)
The comparator further includes a comparator that receives the threshold voltage of the reference buffer circuit and the predetermined reference voltage, and the digital control circuit sequentially outputs the values of the digital signals supplied to the second threshold control circuit by a counter. The threshold value setting circuit according to appendix 1, wherein the output of the comparator is monitored while being changed to.
(Appendix 7)
The threshold setting circuit according to appendix 6, wherein the digital control circuit supplies a digital signal having the same value as the stored value to the first threshold control circuit and deactivates the comparator.
(Appendix 8)
The first conductivity type is P-type, the second conductivity type is N-type, the first power supply voltage is a positive power supply voltage, and the second power supply voltage is a ground voltage. The threshold value setting circuit according to Supplementary Note 3.
(Appendix 9)
The first conductivity type is N-type, the second conductivity type is P-type, the first power supply voltage is a ground voltage, and the second power supply voltage is a positive power supply voltage. The threshold value setting circuit according to Supplementary Note 3.

It is a figure which shows the general structure of an input buffer. It is a figure for demonstrating the VIH / VIL specification of the input signal of an input buffer. It is a figure for demonstrating the fluctuation | variation of the threshold value of an input buffer by process variation. It is a figure which shows the structure of the circuit which adjusts the threshold voltage of an input buffer. It is a figure which shows an example of a structure of the semiconductor integrated circuit containing the threshold value setting circuit by this invention. It is a figure for demonstrating the detailed structure of a reference buffer circuit, a threshold value control circuit, and a digital control circuit. It is a figure which shows an example of the circuit structure of an up counter. It is a timing diagram for demonstrating operation | movement of an up counter. It is a figure for demonstrating the modification of a threshold value control circuit.

Explanation of symbols

41 LSI-IO area 42 LSI core area 43 Input buffer 44 Threshold control circuit 45 Reference buffer circuit 46 Threshold control circuit 47 Digital control circuit 57 Comparator 58 Up counter

Claims (5)

A buffer circuit;
A first threshold control circuit for controlling a threshold voltage of the buffer circuit;
A reference buffer circuit having substantially the same characteristics as the buffer circuit;
A second threshold control circuit having substantially the same characteristics as the first threshold control circuit and controlling the threshold voltage of the reference buffer circuit according to a digital signal;
A digital control circuit for supplying the digital signal to the second threshold control circuit,
The digital control circuit monitors a difference voltage between a threshold voltage of the reference buffer circuit and a predetermined reference voltage while changing the digital signal, and the digital signal when the difference voltage becomes substantially zero And a threshold voltage of the buffer circuit is set by supplying a digital signal having the same value as the stored value to the first threshold control circuit. The buffer circuit operates based on the first power supply voltage and the second power supply voltage,
The first threshold control circuit is a resistance value control circuit that controls a resistance value provided between the buffer circuit and the second power supply voltage;
The reference buffer circuit operates based on the first power supply voltage and the second power supply voltage;
2. The threshold value setting circuit according to claim 1, wherein the second threshold value control circuit is a resistance value control circuit for controlling a resistance value provided between the reference buffer circuit and the second power supply voltage. . The buffer circuit
A first transistor of a first conductivity type;
A second transistor of the second conductivity type having a drain connected to the drain of the first transistor;
The first threshold value control circuit is a third transistor of the second conductivity type provided in parallel between the source of the second transistor and the second power supply voltage,
The reference buffer circuit is
A fourth transistor of the first conductivity type;
A second transistor of the second conductivity type having a drain connected to the drain of the first transistor;
The second threshold control circuit is a sixth transistor of the second conductivity type provided in parallel between the source of the fifth transistor and the second power supply voltage,
The bit of the digital signal output from the digital control circuit is supplied to each gate of the plurality of third transistors and each gate of the plurality of sixth transistors. Threshold setting circuit.   The digital control circuit supplies a digital signal having the same value as the stored value to the first threshold control circuit, and sets a value of the digital signal supplied to the second threshold control circuit to a predetermined value. 4. The threshold value setting circuit according to claim 2, wherein the amount of current flowing through the reference buffer circuit is set to zero. A comparator that inputs the threshold voltage of the reference buffer circuit and the predetermined reference voltage;
2. The threshold setting circuit according to claim 1, wherein the digital control circuit monitors the output of the comparator while sequentially changing the value of the digital signal supplied to the second threshold control circuit by a counter. .

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