JP2009054824A - Method of manufacturing substrate with penetrating wiring - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the peel-off of penetrating wirings 16a-16c from a substrate 18 and form an insulating film having a uniform film thickness on the internal wall surface of a through-hole 44 with excellent film thickness controllability. <P>SOLUTION: In the method of manufacturing a substrate with a penetrating wiring, a through-hole 44 penetrates the front and rear surfaces of a substrate 18 composed of silicon, the inside of the through-hole 44 is filled with the penetrating wiring 16 composed of wiring metal 47 via a thermally-oxidized film 45, a buffer film 17 is laminated on the front surface of the substrate 18, and the penetrating wiring 16 penetrates the cushion film 17 and is extended on the buffer film 17. The method includes the first step of etching the substrate 18, and thereby forming the through-hole 44, the second step of heating the substrate 18, and thereby forming the thermally-oxidized film 45 on the internal wall of the through-hole 44 formed in the first step, the third step of, after the second step, applying a buffer material 48 onto the front surface of the substrate 18 and heat curing the material, and thereby forming the buffer film 17, and the fourth step of, after the third step, filling the inside of the through-hole 44 with the wiring metal 47, and thereby forming penetrating wirings 16a-16c. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a substrate with through wiring, in which a buffer film is formed on one main surface of a substrate, and a through wiring penetrating the substrate and the buffer film is formed.

  In recent years, in order to satisfy the demand for miniaturization of semiconductor devices such as semiconductor sensors, integrated circuits, and semiconductor optical elements, elements are formed via a wiring board, a circuit board, an interposer, etc. (hereinafter, taken as an example of a circuit board). CSP (chip size package) technology for directly mounting a semiconductor substrate on a mounting substrate has been researched and developed in various places (for example, see Patent Documents 1 to 4).

  Since the semiconductor substrate, the circuit board, and the mounting board are stacked in a direction perpendicular to the board surface, a through-wiring that penetrates the front and back surfaces is formed on the circuit board, and this through-wiring electrically connects the semiconductor substrate and the mounting board. Connected to. The through wiring is formed by filling the through hole formed in the circuit board with the wiring metal, but the inner wall surface of the through hole has an insulating film for electrically insulating the through wiring from the circuit board. Is formed.

In addition, a buffer film made of resin or a stress relaxation layer (hereinafter referred to as a buffer film is taken as an example) is formed on the circuit board, and between the semiconductor substrate and the mounting substrate having different linear expansion coefficients during mounting accompanied by heat treatment. By relieving the stress caused by thermal expansion and contraction, connection failures caused by cracks in the external connection terminals that occur during mounting are suppressed.
JP 2005-317704 A JP 2006-278906 A Japanese Patent Laid-Open No. 2004-039864 JP 2007-134735 A

  As described above, in the method of manufacturing a circuit board in which the buffer film is formed on one main surface of the substrate and the through wiring penetrating the substrate and the buffer film is formed, the wiring metal is first filled in the through hole. Thereafter, a buffer film may be formed (see Patent Documents 2 and 3). In this case, since the buffer film is formed by applying a resin and curing it by heat treatment, thermal stress due to thermal expansion or contraction due to the difference in the linear expansion coefficient between the circuit board and the wiring metal during the thermal curing of the resin. The thermal stress generated between the circuit board and the wiring metal causes a connection failure in which the through wiring is peeled off from the circuit board.

On the other hand, as disclosed in FIG. 9 of Patent Document 1, the buffer film (wiring layer) is first formed, and then the through holes are formed and the through holes are filled with the wiring metal. is there. In this case, since the buffer film is formed before the wiring metal is filled, the above-described problem of thermal stress between the circuit board and the wiring metal does not occur. However, the insulating film formed on the inner wall surface of the through hole is not an insulating film formed by heat treatment, but a TEOS (Si (OC ₂ H ₅ ) ₄ ) film deposited by a plasma CVD method (chemical vapor deposition method). (See Patent Document 1, paragraph 0039). For this reason, an insulating film having a uniform film thickness cannot be formed on the inner wall surface of the through hole with good film thickness controllability compared to a thermal insulating film formed by a thermal oxidation method or a thermal nitridation method. The reliability of the through wiring decreases, such as a short circuit between the circuit board and the circuit board, and an increase in resistance of the through wiring.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to suppress peeling of the through wiring from the circuit board and to form an insulating film having a uniform thickness on the inner wall surface of the through hole. It is providing the manufacturing method of the board | substrate with a through wiring which forms this with sufficient film thickness controllability.

  A method of manufacturing a substrate with a through wiring according to the present invention includes a semiconductor substrate, a through hole penetrating the front and back surfaces of the semiconductor substrate, and a through hole made of a wiring metal filled in the through hole with a thermal insulating film interposed therebetween. This is a method for manufacturing a substrate with through wiring, comprising a wiring and a buffer film laminated on the surface of the semiconductor substrate, wherein the through wiring extends through the buffer film and onto the buffer film. This method includes a first step of selectively etching a semiconductor substrate to form a through hole, and heating the semiconductor substrate to form a thermal insulating film on the inner wall of the through hole formed in the first step. A second step of forming a film, a third step of applying a buffer film material to the surface of the semiconductor substrate after the second step, and thermosetting the buffer film material to form a buffer film; And a fourth step of forming the through wiring by filling the inside of the through hole with the wiring metal after the step.

  The method for manufacturing the substrate with through wiring further includes a step of forming a base insulating film on at least the surface of the semiconductor substrate before the first step, and in the first step, the semiconductor substrate is moved from the back side to the front side. Etching is started and the etching is terminated when the base insulating film appears on the surface side of the semiconductor substrate. In the third step, it is preferable to form a buffer film on the base insulating film. Thereby, a buffer film can be formed also on the base insulating film left on the through hole in the third step.

  In the third step, after the buffer film material applied on the through hole is selectively removed to form an opening having a diameter smaller than that of the through hole, the buffer film material is thermally cured to have the buffer film having the opening. In the manufacturing method of the substrate with through wiring, the opening that continues to the through hole is formed by selectively etching the base insulating film exposed from the opening between the third step and the fourth step. It is preferable to further include a step of Even when the through hole of the semiconductor substrate and the opening of the buffer film are formed in different processes, the wiring is formed through the insulating film without exposing the semiconductor substrate by forming an opening having a diameter smaller than that of the through hole. Metal can be filled.

  According to the present invention, by thermally curing the buffer film material before filling the through hole with the wiring metal, no thermal stress is applied to the semiconductor substrate in which the through hole is filled with the wiring metal. It is possible to suppress the through wiring from being peeled off from the semiconductor substrate due to the difference in thermal expansion coefficient between the metal and the semiconductor substrate. In addition, since the through hole is formed before the buffer film is formed, a heat insulating film can be formed on the inner wall of the through hole by heat treatment. Therefore, an insulating film having a uniform thickness can be formed in the through hole with good film thickness controllability as compared with an insulating film deposited by a CVD method or the like.

Embodiments of the present invention will be described below with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals and description thereof is omitted.
(Embodiment of the present invention)
FIG. 1A is a cross-sectional view showing the overall configuration of an acceleration sensor including a substrate 2 with through wiring according to an embodiment of the present invention, and FIG. 1B is a diagram of the sensor substrate 1 of FIG. It is a top view along the AA plane.

  As shown in FIG. 1A, an acceleration sensor according to an embodiment of the present invention is bonded to a sensor substrate 1 that is an acceleration sensor body on which a gauge resistance described later is formed, and one main surface of the sensor substrate 1. And a cover substrate 3 bonded to the other main surface opposite to the one main surface of the sensor substrate 1. The through wiring substrate 2 and the cover substrate 3 are formed in the same outer peripheral shape and outer dimensions as the sensor substrate 1 and are made of the same material as the sensor substrate 1 (for example, silicon).

  The sensor substrate 1 includes a frame portion 11 that is mechanically and electrically connected to the substrate 2 with penetrating wiring and the cover substrate 3, a weight portion 13 disposed inside the frame portion 11, a frame portion 11, and a weight portion 13. And a strip-like bent portion 12 that connects the two. The weight portion 13 and the bent portion 12 are connected to each other at the connecting portion 14. Since the bending part 12 is formed thinner than the frame part 11 and has flexibility, the bending part 12 bends and the weight part 13 is displaced according to the acceleration applied to the acceleration sensor. A slit (gap) is formed between the weight portion 13 and the frame portion 11 and between the weight portion 13 and the bent portion 12 so that the weight portion 13 can be displaced inside the frame portion 11.

  As shown in FIG. 1B, the sensor substrate 1 includes a frame portion 11 having a frame shape (rectangular frame shape in the present embodiment), and a weight portion 13 with a predetermined gap inside the frame portion 11. Has been placed. Four flexible portions 12 a to 12 d having flexibility are extended from the center of each side of the frame portion 11 toward the center of the weight portion 13, and the four flexible portions 12 a to 12 d are connected to the center of the weight portion 13. 14 is connected to the weight part 13 via 14. As described above, the weight portion 13 disposed inside the frame-shaped frame portion 11 is swingably supported by the frame portion 11 via the four flexure portions 12a to 12d extending from the weight portion 13 in four directions. Yes. The frame part 11, the bending parts 12a to 12d, the weight part 13 and the connection part 14 are an SOI substrate in which a silicon active layer is formed on a semiconductor substrate or a support substrate made of single crystal silicon or the like via an insulating layer. What is necessary is just to form by processing using a known lithography technique and an etching technique.

Piezoresistors Ra ₁ , Ra ₂ , Rb ₁ , Rb ₂ , Rc ₁ , Rc ₂ , Rd ₁ , and Rd ₂ are formed at predetermined positions on the flexures 12a to 12d, respectively. The respective accelerations in the X-axis direction, the Y-axis direction, and the Z-axis direction can be obtained from the change in resistance value of each piezoresistor accompanying the bending of the bending portions 12a to 12d. Thus, the piezo resistors Ra ₁ , Ra ₂ , Rb ₁ , Rb ₂ , Rc ₁ , Rc ₂ , Rd ₁ , Rd ₂ constitute a gauge resistance in the sensor substrate 1. Although not shown, each piezoresistor is connected by a diffusion layer wiring or a metal wiring formed on the sensor substrate 1 to constitute a predetermined bridge circuit.

  As shown in FIG. 1A, a recess 22 having a predetermined depth that forms a displacement space of the weight 13 is formed on the surface of the cover substrate 3 that faces the sensor substrate 1. A portion of the facing surface of the cover substrate 3 where the recess 22 is not formed is bonded to the frame portion 11 of the sensor substrate 1. The recess 22 may be formed using a known lithography technique and etching technique. If the total thickness of the bent portion 12, the connecting portion 14, and the weight portion 13 in FIG. 1A is made thinner by the allowable displacement amount of the weight portion 13 than the thickness of the frame portion 11, the cover substrate. 3 does not have to be formed with the recess 22.

The substrate 2 with through wiring includes a semiconductor substrate 18, a through wiring 16 penetrating the front and back surfaces of the semiconductor substrate 18, and a buffer film 17 stacked on the surface of the semiconductor substrate 18. The through wiring 16 is electrically connected to a bridge circuit of piezoresistors Ra ₁ , Ra ₂ , Rb ₁ , Rb ₂ , Rc ₁ , Rc ₂ , Rd ₁ , Rd ₂ formed on the sensor substrate 1. The through wiring 16 extends through the buffer film 17 and is connected to an electrode pad (not shown) in the mounting substrate 4 via the external connection terminal 5. A concave portion 21 having a predetermined depth that forms a displacement space of the bending portion 12 is formed on the main surface of the substrate 2 with through wiring facing the sensor substrate 1. Here, the “front surface” of the substrate 2 with through wiring and the semiconductor substrate 18 indicates a main surface facing the mounting substrate 4, and the “back surface” of the substrate 2 with through wiring and the semiconductor substrate 18 faces the sensor substrate 1. The main surface is shown. The external connection terminal 5 is made of, for example, solder or lead-free solder.

  FIG. 2 is a cross-sectional view showing a detailed configuration of substrate 2 with through wiring in FIG. A buffer film 17 having a uniform thickness is formed on the surface of the semiconductor substrate 18. A recess 21 is formed in the central portion of the back surface of the semiconductor substrate 18. A through wiring 16 is embedded in the semiconductor substrate 18 so as to penetrate the front and back surfaces of the semiconductor substrate 18 and the buffer film 17 in the outer peripheral portion of the semiconductor substrate 18. Insulating films (for example, silicon oxide film and silicon nitride film) 41 a and 41 b having a uniform film thickness are formed on the front and back surfaces of the semiconductor substrate 18, respectively, and between the through wiring 16 embedded in the semiconductor substrate 18 and the semiconductor substrate 18. In addition, an insulating film 45 having a uniform thickness is formed.

  The through wiring 16 includes a filling portion 16 a embedded in the semiconductor substrate 18, an external electrode pad portion 16 b extending from the filling portion 16 a through the buffer film 17 onto the buffer film 17, and the filling portion 16 a to the semiconductor substrate. 18 and an internal electrode pad portion 16c extended on the back surface. The filling portion 16a, the external electrode pad portion 16b, and the internal electrode pad portion 16c are electrically insulated from the semiconductor substrate 18 by insulating films 45, 41a, and 41b, respectively.

  In the embodiment of the present invention, the diameter of the filling portion 16 a embedded in the semiconductor substrate 18 is wider than the diameter of the filling portion 16 a embedded in the buffer film 17. Further, a Ni / Au layer 31 is formed on the external electrode pad portion 16b. The Ni / Au layer 31 includes a Ni layer stacked on the external electrode pad portion 16b and an Au layer stacked on the Ni layer. Instead of the Ni layer, for example, a conductive layer made of Ti, Cr, Nb, Zr, TiN, TaN or the like may be used.

  Next, an example of a manufacturing method of the substrate 2 with through wiring of FIG. 2 will be described with reference to the respective drawings of FIGS.

  (A) The silicon substrate 18 is heated in an atmosphere containing oxygen to form thermal oxide films 41a and 41b each having a thickness of about 1 μm on the front and back surfaces of the silicon substrate 18 as shown in FIG. . In this manner, the base insulating film (thermal oxide film) 41 b is formed on at least the surface of the semiconductor substrate (silicon substrate) 18.

(B) Resist films 42a and 42b are formed on the thermal oxide films 41a and 41b, respectively, and the resist film 42a in the region where the through wiring 16 is formed is selectively removed by photolithography to pattern the windows 43. Ning. The thermal oxide film 41a exposed from the window 43 is selectively etched. The etching method may be wet etching using a hydrogen fluoride (HF) solution or dry etching using a CF gas such as CF ₄ . At this time, the thermal oxide film 41b on the surface side of the silicon substrate 18 is not etched because it is covered with the resist film 42b. As shown in FIG. 3B, an etching mask for forming a through hole for the through wiring 16 is formed in the resist film 42 a and the thermal oxide film 41 a on the back surface side of the semiconductor substrate 18.

  (C) The silicon substrate 18 exposed from the window 43 of the resist film 42a and the thermal oxide film 41a is selectively etched using an anisotropic etching method such as a Deep-RIE method, and the result is shown in FIG. As shown, a through hole 44 for embedding the through wiring 16 is formed. In this etching step (first step), etching starts from the back surface side to the front surface side of the silicon substrate 18, and when the thermal oxide film (underlying insulating film) 41b appears on the front surface side of the silicon substrate 18. The etching is finished. At this time, since the resist film 42b is formed on the thermal oxide film 41b having a thickness of about 1 μm, the thermal oxide film 41b remains on the through hole 44 without being etched together with the silicon substrate 18. Can be made.

  (D) After the first step, the resist films 42a and 42b on the front and back surfaces of the silicon substrate 18 are removed. Thereafter, a thermal oxidation process is performed to heat the silicon substrate 18 in an atmosphere containing oxygen, and a thermal oxide film (thermal insulating film) having a thickness of about 0.5 μm is formed on the inner wall of the through hole 44 as shown in FIG. ) 45 is formed (second step).

  (E) After the second step, a buffer film material 48 made of a photosensitive thermosetting resin is spin-coated on the surface of the silicon substrate 18. Specifically, as shown in FIG. 3E, a buffer film material 48 is applied with a uniform film thickness on the thermal oxide film 41 b on the surface side of the silicon substrate 18. The buffer film material 48 is also applied to the thermal oxide film 41 b remaining on the through hole 44.

  (F) Using a photolithography method (exposure / development), a part of the buffer film material 48 applied on the through hole 44 is selectively removed, and the buffer film material 48 on the through hole 44 has an opening 46. Form. The diameter of the opening 46 is narrower than the diameter of the through hole 44. Then, by heating the buffer film material 48 to about 350 ° C. in a nitrogen atmosphere, the buffer film material 48 is thermally cured to form the buffer film 17 having the openings 46 (third step). Thereafter, using the buffer film 17 as an etching mask, the thermal oxide film 41b exposed from the opening 46 is selectively etched from the back surface side by dry etching using a CF-based gas. By the above processing, as shown in FIG. 3 (f), the opening 46 is connected to the through hole 44, that is, the opening 46 continuing to the through hole 44 is formed.

  (G) A copper (Cu) film is deposited on the front and back surfaces of the silicon substrate 18 and the inner wall surfaces of the through-hole 44 and the opening 46 through the insulating films 41a, 41b, and 45 by sputtering. This copper film serves as a seed layer when the wiring metal (copper film) 47 is filled in the through hole 44 by an electroplating method to be described later. Thereafter, as shown in FIG. 3G, the wiring metal (copper film) 47 is filled in the through hole 44 and the opening 46 by the electroplating method, and at the same time, the wiring metal 47 is deposited on the front and back surfaces of the silicon substrate 18.

  (H) Thereafter, a predetermined resist pattern is formed on the wiring metal 47 on the front and back surfaces of the silicon substrate 18 by a photolithography method, and the wiring metal 47 is selectively etched by an anisotropic etching method such as RIE. As shown in FIG. 3H, the external electrode pad portion 16b and the internal electrode pad portion 16c are patterned. Through the above processing, the through wiring 16 including the filling portion 16a, the external electrode pad portion 16b, and the internal electrode pad portion 16c filled in the through hole 44 and the opening 46 is formed (fourth step). Then, a Ni / Au layer is formed on the external electrode pad portion 16b. Through the above steps, the substrate 2 with through wiring shown in FIGS. 1A and 2 is completed.

  As described above, according to the embodiment of the present invention, the through hole 44 is filled with the wiring metal 47 by thermally curing the buffer film material 48 before filling the through hole 44 with the wiring metal 47. Thermal stress is no longer applied to the silicon substrate 18 in this state, and the through wiring 16 can be prevented from peeling off from the silicon substrate 18 due to the difference in thermal expansion coefficient between the wiring metal 47 and the silicon substrate 18. Further, since the through hole 44 is formed before the buffer film 17 is formed, the thermal insulating film 45 can be formed on the inner wall of the through hole 44 by heat treatment. Therefore, an insulating film having a uniform film thickness can be formed in the through hole 44 with good film thickness controllability as compared with an insulating film deposited by a CVD method or the like.

  Prior to the etching step (first step) in FIG. 3C, a thermal oxide film 41b is formed on at least the surface of the silicon substrate 18. In the etching step in FIG. Etching is started toward the surface side, and is terminated when the thermal oxide film 41b is exposed on the surface side of the silicon substrate 18. In the third step of FIG. 3F, the buffer film material 48 is applied on the thermal oxide film 41b and thermally cured to form the buffer film 17. Thereby, the buffer film material 48 is also applied onto the thermal oxide film 41 b remaining on the through hole 44, and the buffer film 17 is formed also on the thermal oxide film 41 b remaining on the through hole 44. be able to.

In the third step of FIG. 3F, after the buffer film material 48 applied on the through hole 44 is selectively removed to form an opening 46 having a diameter smaller than that of the through hole 44, the buffer film material is formed. The buffer film 17 having the opening 46 is formed by thermally curing 48, and the thermal oxide film 41 b exposed from the opening 46 is selectively etched to form the opening 46 continuous with the through hole 44. Even when the through hole 44 of the silicon substrate 18 and the opening 46 of the buffer film 17 are formed in different steps, the silicon substrate 18 is not exposed by forming the opening 46 having a diameter smaller than that of the through hole 44. The wiring metal 47 can be filled through the insulating film.
(Comparative example)
A comparative example of a method for manufacturing a substrate with through wiring will be described with reference to the respective drawings of FIGS.

  (Ii) Thermal oxidation treatment of the silicon substrate 68 is performed to form thermal oxide films 91a and 91b on the front and back surfaces of the silicon substrate 68, respectively, as shown in FIG.

  (R) Resist films 92a and 92b are formed on the thermal oxide films 91a and 91b, respectively, and the resist film 92b in the region where the through wiring is formed is selectively removed by photolithography to pattern the window 93. To do. The thermal oxide film 91b exposed from the window 93 is selectively etched. As shown in FIG. 4B, an etching mask for forming a through hole for through wiring is formed in the resist film 92b and the thermal oxide film 91b on the surface side of the semiconductor substrate 68.

  The silicon substrate 68 exposed from the window 43 of the resist film 92b and the thermal oxide film 91b is selectively etched to form a through hole 94 for embedding the through wiring as shown in FIG. To do. The thermal oxide film 91a and the resist films 92a and 92b on the through hole 94 are removed. Thereafter, a thermal oxidation process is performed on the silicon substrate 68 to form a thermal oxide film 95 on the inner wall of the through hole 94 as shown in FIG.

  (I) As shown in FIG. 4 (e), the wiring metal (copper film) 97 is filled in the through hole 94, and at the same time, the wiring metal 97 is deposited on the front and back surfaces of the silicon substrate 68.

  (E) The wiring metal 97 on the front and back surfaces of the silicon substrate 68 is selectively etched to pattern the external electrode pad portion 66b and the internal electrode pad portion 66c as shown in FIG. A through wiring including a filling portion 66a, an external electrode pad portion 66b, and an internal electrode pad portion 66c filled in the through hole 44 is formed.

  (F) A buffer film material is applied to the surface of the silicon substrate 68. The buffer film material is also applied on the external electrode pad portion 66b. A part of the buffer film material applied on the external electrode pad portion 66b is selectively removed to form an opening 96 in the buffer film material on the external electrode pad portion 66b. Then, as shown in FIG. 4E, the buffer film material 48 is thermally cured to form the buffer film 67 having the openings 96.

  (And) The electrode material is deposited on the inside of the opening 96 and on the buffer film 67, and patterned into a predetermined shape, whereby the external connected to the external electrode pad portion 66b as shown in FIG. An electrode 81 (pad) is formed.

  As described above, in the comparative example, the buffer film 67 is formed after the through hole 94 is filled with the wiring metal 97. For this reason, a thermal stress due to thermal expansion or contraction due to a difference in expansion coefficient between the silicon substrate 68 and the wiring metal 97 is generated when the buffer film 67 is thermally cured, and the thermal stress between the silicon substrate 68 and the wiring metal 97 is generated. As a result, a connection failure occurs in which the through wirings 66 a to 66 c are separated from the silicon substrate 68.

  On the other hand, in the embodiment of the present invention, the wiring metal 47 is filled into the through hole 44 after the buffer film 17 is formed. For this reason, the wiring metal 47 does not receive the thermal stress at the time of the thermosetting of the buffer film 17, and the problem of peeling due to the thermal stress as described above does not occur.

  As described above, the present invention has been described according to one embodiment. However, it should not be understood that the description and the drawings, which form a part of this disclosure, limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.

  In the embodiment of the present invention, the thermal oxide film 45 (silicon oxide film) is exemplified as the thermal insulating film formed in the through hole 44. However, other than this, a thermal nitride film such as a silicon nitride film, silicon oxide, etc. A thermal oxynitride film such as a nitride film may be used. In addition, although the thermal oxide film 41b (silicon oxide film) is illustrated as the base insulating film, a silicon oxide film deposited by CVD or the like, a silicon nitride film, or a silicon oxynitride film may be used.

  Although copper (Cu) was illustrated as the wiring metal 47, nickel (Ni) may be used in addition to this.

  In the embodiment of the present invention, the substrate 2 with through wiring has been described by taking an acceleration sensor as an example. However, a semiconductor substrate on which other semiconductor sensors, integrated circuits, semiconductor optical elements, and the like are formed is used as a wiring substrate and a circuit substrate. Alternatively, the present invention can also be applied to a packaging technology that directly mounts on a mounting substrate via an interposer or the like.

  Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters according to the scope of claims reasonable from this disclosure.

FIG. 1A is a cross-sectional view showing an overall configuration of an acceleration sensor including a substrate 2 with through wiring according to an embodiment of the present invention, and FIG. 1B is a sensor substrate 1 of FIG. It is a top view along the AA plane. It is sectional drawing which shows the detailed structure of the board | substrate 2 with a penetration wiring of Fig.1 (a). FIG. 3A to FIG. 3H are process cross-sectional views illustrating main manufacturing steps in an example of a method for manufacturing the substrate 2 with through wiring in FIG. 2. 4A to 4H are process cross-sectional views illustrating main manufacturing steps in the method for manufacturing a substrate with through wiring according to the comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Sensor substrate 2 ... Substrate with wiring 3 ... Cover substrate 4 ... Mounting substrate 5 ... External connection terminal 11 ... Frame part 12a-12d ... Deflection part 13 ... Weight part 14 ... Connection part 16 ... Through-wiring 16a ... Filling part 16b ... External electrode pad portion 16c ... Internal electrode pad portion 17 ... Buffer film 18 ... Silicon substrate (semiconductor substrate)
21, 22 ... concave portion 31 ... Ni / Au layer 41 a ... thermal oxide film 41 b ... thermal oxide film (underlying insulating film)
42a, 42b ... resist film 43 ... window 44 ... through hole 45 ... thermal oxide film (thermal insulating film)
46 ... Opening 47 ... Wiring metal 48 ... Buffer film material

Claims (3)

A semiconductor substrate, a through-hole penetrating the front and back surfaces of the semiconductor substrate, a through-wiring made of a wiring metal filled in the through-hole via a thermal insulating film, and a buffer laminated on the surface of the semiconductor substrate A through wiring is a method of manufacturing a substrate with a through wiring that extends through the buffer film and extends over the buffer film,
A first step of selectively etching the semiconductor substrate to form the through hole;
A second step of forming the thermal insulating film on the inner wall of the through hole formed in the first step by heating the semiconductor substrate;
After the second step, a third step of applying a buffer film material to the surface of the semiconductor substrate and thermosetting the buffer film material to form the buffer film;
And a fourth step of forming the through wiring by filling the through hole with a wiring metal after the third step. Before the first step, further comprising a step of forming a base insulating film on at least the surface of the semiconductor substrate;
In the first step, etching is started from the back surface side to the front surface side of the semiconductor substrate, and the etching is terminated when the base insulating film is exposed on the front surface side of the semiconductor substrate,
In the third step, the buffer film is formed on the base insulating film. The method for manufacturing a substrate with through wiring according to claim 1, wherein: In the third step, after the buffer film material applied on the through hole is selectively removed to form an opening having a diameter smaller than that of the through hole, the buffer film material is thermally cured. Forming the buffer film having the opening;
The method further includes a step of selectively etching the base insulating film exposed from the opening to form an opening continuous with the through hole between the third step and the fourth step. A method for manufacturing a substrate with through wiring according to claim 2.

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