JP2009049887A - Packet processing apparatus, method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packet processing apparatus capable of appropriately suppressing power consumption in accordance with the variation of the traffic volume of arrival packets. <P>SOLUTION: A plurality of processing lines 14 can be started and stopped operating respectively. During operation, a processor 21 is operated by an operating clock capable of adjusting a clock speed to access a memory 13, thereby processing packets preserved in the memory 13. A line control section 15 determines the number of processing lines to be operated and the clock speed of the operating clocks for the processing lines, based on traffic volume of packets to be inputted and power consumption of the processing lines during the operation, in such a way as to process inputted packets without loss and to minimize power consumption of a packet processing device 10, and controls operation of the processing lines and the operating clocks on the basis of the determination. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a packet processing apparatus that processes a packet in parallel by a plurality of processors.

  In recent years, the amount of traffic flowing in the network has increased, and accordingly, packet processing devices such as routers are required to process packets at high speed. In a packet processing apparatus having a mechanism for sequentially processing packets by one processor, the amount of packet processing (packet processing performance) per unit time can be improved by increasing the operating clock. However, if the operation clock is increased in speed, the power consumption of the processor increases in proportion to the cube of the operation clock, and the power consumption of the packet processing device becomes enormous.

  As means for solving this problem, there is a packet processing apparatus provided with a mechanism for processing packets in parallel by a plurality of processors. For example, there is a network processor that includes a plurality of small processors called processor elements and processes packets in parallel (see Non-Patent Document 1). By using this network processor, a packet processing device such as a router that processes packets in parallel can be configured.

By processing the packets in parallel with a plurality of processors, the packet processing performance can be improved without increasing the operating clock. Since a plurality of processing lines including a processor for processing a packet and an interface corresponding to the processor operate simultaneously, the power consumption of the packet processing device increases by the number of processing lines. However, according to a packet processing device that processes packets in parallel by a plurality of processors, the power consumption accompanying the improvement in packet processing performance compared to a packet processing device in which the power consumption increases in proportion to the cube of the operating clock. The rise of is suppressed.
Eiji Kawai, Yuki Kadobayashi, Hide Yamaguchi, “Survey on Network Processor Technology,” IEICE Technical Report Internet Architecture, vol. 103, no. 62, pp. 55-60, May 2003

  A device that processes packets in parallel using a network processor is provided with as many processing lines as possible even if the packets arrive at the maximum rate. In general, in such a device, all modules constituting the processing line always operate regardless of changes in the amount of packets that arrive. For this reason, when the amount of packets that arrive is small, there is a margin in the processing capacity of the processing line. However, since all the processing lines are always operating, the packet parallel processing device consumes as much power as when packets arrive at the maximum rate even when there are few packets arriving. Therefore, even in a packet processing device that processes packets in parallel by a plurality of processors, power consumption is wasted when the amount of packets arriving varies.

  An object of the present invention is to provide a packet processing apparatus capable of appropriately suppressing power consumption in accordance with fluctuations in the traffic volume of arriving packets.

In order to achieve the above object, the packet processing device of the present invention provides:
A packet processing device for processing input packets in parallel by a plurality of processors,
A memory for storing the packet;
Each includes a processor and an interface for the processor to access the memory, and can start and stop the operation. During the operation, the processor is operated with an operation clock capable of adjusting the clock speed. A plurality of processing lines for accessing the memory and processing packets stored in the memory;
Based on the amount of traffic of the input packet and the power consumption of the processing line in operation, the processing line that can operate the input packet without loss and has the minimum power consumption of the packet processing device. A line control unit that determines the number and the clock speed of the operation clock of the processing line, and controls the operation of the processing line and the operation clock based on the determination.

The line control unit
Calculating the number of processing lines to be operated, in which the power consumption of the packet processing device is minimized;
Based on the calculated number of processing lines to be operated, calculating the clock speed of the operation clock that minimizes the power consumption of the packet processing device,
The processing lines may be controlled based on the calculated number of operating processing lines and the clock speed of the operating clock.

The line control unit
From the measured value of the traffic amount of the input packet and the number of processing lines in operation, a first clock speed at which the power consumption of the packet is minimized is calculated,
The operating processing line is operated at the first clock speed, and a new number of operating processing lines is calculated from the power consumption of the operating processing line at that time,
From the measured value of the traffic amount of the input packet and the new number of processing lines to be operated, a second clock speed at which the power consumption of the packet is minimized is calculated,
The processing lines may be controlled based on the new number of processing lines to be operated and the second clock speed.

Further, the processing line separately measures the power consumption of the processor and the power consumption of the interface,
The line control unit is derived from the measured value of the power consumption of the processor and the measured value of the power consumption of the interface, and represents a relational expression representing the power consumption of the processor processing device with respect to the number of operating processing lines. The number of operating processing lines that have the smallest value may be set as the new number of operating processing lines.

In addition, a value obtained by multiplying the sum of the measured values of the power consumption of the processor in each processing line by the square of the number of operating processing lines is W _1, and the power consumption of the interface in each processing line is If the average value of the measured values is W _m , the new number of processing lines to be operated may be expressed as (2W ₁ / (W _m )) ^(1/3) .

  According to the present invention, an operation of a processing line that can process an input packet without any loss and minimizes the power consumption of the packet processing device, based on the traffic amount of the input packet and the power consumption of the active processing line. Since the number and the clock speed of the operation clock are determined, it is possible to appropriately suppress the power consumption of the packet processing device according to the fluctuation of the traffic amount.

  Embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing the configuration of the packet processing apparatus of this embodiment. Referring to FIG. 1, the packet processing apparatus 10 includes an input port 11, an output port 12, a memory 13, a processing line 14, a line control unit 15, and a traffic measurement unit 16.

  The input port 11 and the output port 12 serve as an interface for inputting / outputting packets to / from an external network (not shown). A packet received from the external network is input to the input port 11. Packets sent to the external network are output from the output port.

  The traffic measurement unit 16 measures the traffic amount of the packet that arrives at the input port 11.

  The memory 13 temporarily stores a packet input from the input port 11 or a packet output from the output port 12. The memory 13 has an interface 31 and is accessed from the processing line 14 via the interface 31.

  A plurality of processing lines 14 are provided in the packet processing apparatus 10. Not all the processing lines 14 are always operating, but only the number of processing lines 14 determined by the line control unit 15 are operating. Therefore, each processing line 14 has a function of starting and stopping itself in accordance with an instruction from the line control unit 15. The operating processing line 14 has a function of measuring its own power consumption and a function of adjusting the clock speed of its own operation clock.

  Further, the processing line 14 in operation processes a packet. Packet processing includes acquiring and analyzing a packet input from the input port 11 via the memory 13 and generating a packet to be transmitted and outputting the packet from the output port 12 via the memory 13.

  Referring further to FIG. 1, the processing line 14 includes a processor 21, an interface 22, an operation clock adjustment unit 23, a start / stop processing unit 24, and a power measurement unit 25.

  The processor 21 inputs and outputs packets to and from the memory 13 via the interface 22 and processes the packets.

  The interface 22 is a memory access interface for exchanging packet data to be processed with the memory.

  The operation clock adjustment unit 23 adjusts the operation clock of the processor 21 to the clock speed instructed from the line control unit 15.

  The start / stop processing unit 24 starts or stops devices in the processing line 14 in accordance with an instruction from the line control unit 15.

  The power measuring unit 25 measures the power consumption of the processor 21 and the interface 22.

  The line control unit 15 changes the number of operation lines 14 to be operated and the clock speed of the operation clock so that the power consumption of the packet processing device 10 is reduced according to the traffic amount of the arriving packet.

  At that time, the line control unit 15 performs an operation to minimize the power consumption of the packet processing device 10 from the power consumption measured by each processing line 14 and the traffic amount measured by the traffic measurement unit 16. The number of lines 14 is determined.

  Subsequently, the line control unit 15 operates the processing line 14 so that the power consumption of the packet processing apparatus 10 is minimized based on the number of processing lines 14 to be operated and the traffic amount measured by the traffic measurement unit 16. Determine the clock speed of the clock.

  When the number of processing lines 14 to be operated and the clock speed of the operation clock of the processing line 14 are determined, the line control unit 15 instructs each processing line 14 to start or stop based on the determination, and determines the determined clock. Instruct each processing line 14 to operate at speed.

  For example, even if the amount of traffic of the arriving packets is the same, the number of processing lines 14 operating in parallel is increased, and the clock speed of the operation clock of the processor 21 in the processing line 14 is decreased, thereby processing the packet processing apparatus 10 as a whole. Power consumption can be reduced while maintaining performance. As described above, the power consumption of the processor 21 increases in proportion to the cube of the operation clock. Therefore, by reducing the clock speed of the operation clock, it is possible to obtain a power consumption reduction effect that can compensate for the increase in the number of operating processing lines 14.

  However, some devices in the processing line 14 preferably do not change the clock speed. For example, it is preferable that the interface 22 for reading / writing data with the memory 13 does not change the clock speed. The amount of data exchanged between the memory 13 and the processor 21 corresponds to this when the number of operating processing lines 14 does not change even if it changes. In this case, in order to process a data amount that does not change depending on the number of operating processing lines 14, it is preferable to keep the operation clock of the interface 22 constant regardless of the number of operating processing lines. When the number of operating processing lines 14 is increased, the number of operating interfaces 22 is increased, so that the power consumption is increased by the increased number of interfaces 22. Since the power consumption of the interface 22 increases as the number of operating processing lines 14 increases, the power consumption of the processor 21 reduced by decreasing the clock speed of the operating clock while increasing the number of operating processing lines 14 is increased. There is a trade-off relationship.

  In the present embodiment, the power measurement unit 25 measures the power consumption of both the processor 21 and the interface 22, and the line control unit 15 determines the number of processing lines 14 to be operated and the clock speed of the operation clock based on the measurement result. Therefore, it is possible to perform control such that the power consumption is minimized in consideration of the trade-off between the power consumption of the processor 21 and the power consumption of the 22 interfaces.

  FIG. 2 is a flowchart showing a method of determining the number of processing lines 14 to be operated and the clock speed of the operation clock. Referring to FIG. 2, first, the traffic measurement unit 16 periodically measures the traffic amount of packets that arrive at the packet processing apparatus 10 (step 101). If the fluctuation range compared to the previous measurement value is small, the fluctuation range compared to the previous measurement value exceeds a predetermined threshold considering that the number of processing lines 14 to be operated and the clock speed of the operation clock do not change greatly. The subsequent processing may be executed only when it is. Further, the subsequent processing is executed only when the fluctuation range compared to the measured value when the number of the operating processing lines 14 and the current clock speed of the operating clock are determined exceeds a predetermined threshold. It may be.

  Next, in order to measure the power consumption when operating at the lowest clock speed within the range in which packets of the measured traffic volume can be processed, the range in which the packet of the measured traffic volume can be processed by the operating processing line 14 To calculate the minimum clock speed and set the operation clock to the clock speed (step 102).

  As an example of setting the clock speed of the operation clock at this time, {(measured traffic volume) × (minimum clock speed when the maximum traffic volume is processed by one processing line)} / {(maximum traffic volume) × (Number of active processing lines)} is used. The maximum traffic volume is an assumed maximum traffic volume of a packet arriving at the packet processing apparatus 10 and is a value that can be determined in advance. According to the value, the minimum clock speed when the maximum traffic amount is processed by one processing line can be determined in advance.

  Thereafter, the power consumption in the processor 21 and the interface 22 is measured in each processing line 14 in operation (step 103).

  Subsequently, the number of operating processing lines 14 that minimizes the power consumption of the packet processing apparatus 10 is calculated from the measured power consumption (step 104). Details of the calculation method at that time will be described later.

  Further, the lowest clock speed is calculated within a range in which the packet of the measured traffic volume can be processed by the number of processing lines 14 calculated in step 104 (step 105).

  As an example of setting the clock speed of the operation clock at this time, {(measured traffic volume) × (minimum clock speed when the maximum traffic volume is processed by one processing line)} / {(maximum traffic volume) × (Calculated number of processing lines)} is used.

  Finally, each processing line 14 is controlled so that the number of operating processing lines 14 is the number calculated in step 104 and the operating clock is the clock speed calculated in step 105 (step 106).

  As described above, the number of processing lines 14 to be operated and the clock speed of the operation clock are determined.

FIG. 3 is a flowchart showing a method for calculating the number of operating processing lines 14 in step 104 described above. Referring to FIG. 3, first, from the power consumption of each processor 21 measured in step 103, W ₁ that is a value obtained by multiplying the sum of them by the square of the number of parallel processing lines is calculated (step 201). This W ₁ is an index value (processor index value) indicating the degree of contribution of the power consumption of the processor 21 to the power consumption of the packet processing device 10.

Also, from the power consumption of each interface 21 measured in step 103, W _m that is an average value thereof is calculated (step 202). This W _m is an index value (interface index value) indicating the degree of contribution of the power consumption of the interface 22 to the power consumption of the packet processing apparatus 10. The order of step 201 and step 202 is not particularly limited.

Subsequently, by substituting the processor index value W ₁ calculated in step 201 and the interface index value W _m calculated in step 202 into the equation (1), the packet processing device for the number n of operating processing lines 14 A function expression (power consumption expression) indicating 10 power consumption is determined (step 203). In equation (1), W _b is the power consumption of the buffer for accessing the memory 13.

  Finally, the value of n that minimizes the power consumption formula determined in step 203 is calculated and used as the number of processing lines 14 that operate (step 204).

  As described above, the number of operating processing lines 14 is calculated. Next, the meaning of calculating the number of processing lines 14 will be described in detail.

  The packet processing apparatus 10 shown in FIG. 1 consumes power mainly by the processor 21, the interface 22, and the memory 13. Since the processor 21 and the interface 22 are provided for each processing line 14, the power consumption increases by the amount of the processing line 14 that operates.

When a plurality of processing lines 14 process packets independently, the product of the number n of operating processing lines 14 and the clock speed C _p of the operating clock of the processor 21 in the processing line 14 is all in one processing line 14. No packet loss occurs on any processing line 14 as long as the minimum clock speed C can be processed without loss.

Since the power consumption is reduced as the clock speed of the operation clock is lower, in order to reduce the power consumption, the number n of the operating processing lines 14 and the clock speed C _p of the operation clock of the processor 21 in the processing line 14 It is desirable that the product be equal to the clock speed C.

Here, the value of the clock speed C is measured with respect to the minimum clock speed C ₁ at which all packets can be processed without loss in one processing line 14 when the packet arrival rate is maximum, and the maximum traffic amount. It is given by the product of the traffic volume ratio α.

Therefore, the product of the number n of processing lines 14 in operation and the clock speed C _p is equal to C ₁ α. If all the packets are processed by one processing line 14 and the power consumption when the processor 21 of the processing line 14 is operating at the clock speed C ₁ α is W ₁ (α), the same number of packets are n. The power consumption per processor 21 in the case of processing with one processing line 14 is W ₁ (α) / n ³ . This is because the clock speed of the operation clock of the processor 21 in one processing line 14 is C ₁ α / n. W ₁ (α) is the same as W ₁ described above, but clearly shows that the value of W ₁ depends on α.

Since the power consumption W ₁ (α) / n ³ of one processor 21 is measured by the power measuring unit 25, W ₁ (α) can be calculated from the measured value.

  Here, it is considered to obtain the number n of operating processing lines 14 that minimizes the power consumption of the entire packet processing apparatus 10. Therefore, the power consumption of the entire packet processing apparatus 10 is derived as a function of the number of lines n.

Power consumption per one processing line 14 is the sum of the power consumption W _m of power and interface 22 of the processor 21. The power consumption of the processor 21 is represented by W ₁ (α) / n ³ as described above. Therefore, the power consumption per processing line 14 can be expressed as (W _m + W ₁ (α) / n ³ ). If there are n processing lines 14 that operate, the power consumption in the processing line 14 of the entire packet processing apparatus 14 is represented by n (W _m + W ₁ (α) / n ³ ).

Further, as the power consumed by the memory 13, there is a power W _b dissipated by the memory capacity is provided for the buffer for input and output. The power consumption of the entire packet processing apparatus 10 including this can be expressed as n (W _m + W ₁ (α) / n ³ ) + W _b (formula (1)).

In order to determine the number n of operating processing lines 14 that minimizes the power consumption of the entire packet processing apparatus 10, it is only necessary to obtain n that minimizes the power (n) expressed by Equation (1).
For this purpose, the equation (1) is differentiated by n, and n is calculated such that it becomes 0. As a result, the number of processing lines 14 that minimizes the power consumption of the packet processing apparatus 10 is expressed by Expression (2).

In Expression (2), the power consumption W _m of the interface 22 is measured by the power measurement unit 25 corresponding to each interface 22. Further, as described above, W ₁ (α) can be derived from the power consumption of the processor 21 measured by the power measuring unit 25.

Next, an example in which the number of processing lines 14 to be operated is actually calculated using specific numerical values will be described. If W _m = 0.0001 and W ₁ = 70, the number of processing lines 14 to be operated is 111.86... Since the number of the processing lines 14 is an integer value, when the value after the decimal point is rounded off or rounded up, the number of processing lines 14 to be operated becomes 112. Further, when the decimal part is rounded down, the number of processing lines 14 to be operated becomes 111.

  Thus, by starting or stopping the processing line 14 so that the number of processing lines becomes 111 or 112, the packet processing apparatus 10 can be operated with a minimum power consumption.

  As described above, according to the present embodiment, the input packet can be processed without loss from the amount of traffic of the input packet and the power consumption of the processing line 14 in operation, and the consumption of the packet processing apparatus 10 Since the number of operations of the processing line that minimizes the power and the clock speed of the operation clock are determined, it is possible to appropriately suppress the power consumption of the packet processing device 10 according to the fluctuation of the traffic amount. Further, when designing the packet processing device 10, the number of processing lines 14 with the minimum power consumption can be evaluated from the assumed traffic volume, and the packet processing device 14 with low power consumption can be designed.

  Note that the line control unit 15 and the traffic measurement unit 16 of the present embodiment can also be realized by a processor included in a computer reading and executing a software program from a recording medium.

It is a block diagram which shows the structure of the packet processing apparatus of this embodiment. It is a flowchart which shows the method of determining the number of the process lines 14 to operate | move, and the clock speed of an operation clock. It is a flowchart which shows the method of calculating the number of the process lines 14 which operate | move in step 104 mentioned above.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Packet processing apparatus 11 Input port 12 Output port 13 Memory 14 Processing line 15 Line control part 16 Traffic measurement part 21 Processor 22 Interface 23 Operation clock adjustment part 24 Start / stop processing part 25 Power measurement part

Claims (7)

A packet processing device for processing input packets in parallel by a plurality of processors,
A memory for storing the packet;
Each includes a processor and an interface for the processor to access the memory, and can start and stop the operation. During the operation, the processor is operated with an operation clock capable of adjusting the clock speed. A plurality of processing lines for accessing the memory and processing packets stored in the memory;
Based on the amount of traffic of the input packet and the power consumption of the processing line in operation, the processing line that can operate the input packet without loss and has the minimum power consumption of the packet processing device. And a line control unit that determines the number and the clock speed of the operation clock of the processing line, and controls the operation and operation clock of the processing line based on the determination. The line control unit
Calculating the number of processing lines to be operated, in which the power consumption of the packet processing device is minimized;
Based on the calculated number of processing lines to be operated, calculating the clock speed of the operation clock that minimizes the power consumption of the packet processing device,
The packet processing device according to claim 1, wherein the processing line is controlled based on the calculated number of operating processing lines and the clock speed of the operating clock. The line control unit
From the measured value of the traffic amount of the input packet and the number of processing lines in operation, a first clock speed at which the power consumption of the packet is minimized is calculated,
The operating processing line is operated at the first clock speed, and a new number of operating processing lines is calculated from the power consumption of the operating processing line at that time,
From the measured value of the traffic amount of the input packet and the new number of processing lines to be operated, a second clock speed at which the power consumption of the packet is minimized is calculated,
The packet processing device according to claim 2, wherein the processing line is controlled based on the new number of processing lines to be operated and the second clock speed. The processing line measures power consumption of the processor and power consumption of the interface separately,
The line control unit is derived from the measured value of the power consumption of the processor and the measured value of the power consumption of the interface, and represents a relational expression representing the power consumption of the processor processing device with respect to the number of operating processing lines. 4. The packet processing device according to claim 3, wherein the number of operating processing lines having a minimum value is the new number of operating processing lines. A value obtained by multiplying the sum of measured values of the power consumption of the processor in each processing line by the square of the number of active processing lines is W _1, and a measured value of the power consumption of the interface in each processing line The packet processing apparatus according to claim 4, wherein a new number of the processing lines to be operated is represented as (2W ₁ / (W _m )) ^(1/3) , where W _m is an average value. A memory for storing an input packet; a processor; and a plurality of processing lines each having an interface for allowing the processor to access the memory and accessing the memory and processing the packets stored in the memory in parallel A packet processing method in a packet processing device,
Measure the traffic amount of the input packet and the power consumption of the processing line in operation,
From the measured traffic amount and power consumption of the operating processing line, the number of operating processing lines that can process the input packet without loss and minimize the power consumption of the packet processing device; Determining the clock speed of the operation clock of the processing line;
A packet processing method for controlling the operation and operation clock of the processing line based on the determination. A memory for storing an input packet; a processor; and a plurality of processing lines each having an interface for allowing the processor to access the memory and accessing the memory and processing the packets stored in the memory in parallel A program for operating a computer as a packet processing device,
A procedure for measuring the traffic amount of the input packet and the power consumption of the processing line in operation;
From the measured traffic amount and power consumption of the operating processing line, the number of operating processing lines that can process the input packet without loss and minimize the power consumption of the packet processing device; Determining a clock speed of an operation clock of the processing line;
A program for causing a computer to execute an operation of the processing line and a procedure for controlling an operation clock based on the determination.

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