JP2009044508A - Reception circuit, and binary-signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reception circuit that suppresses the occurrence of noise when reproducing a digital signal from a received signal while suppressing an increase in power consumption with a simple circuit configuration. <P>SOLUTION: When a level of a baseband signal S1 becomes higher than that of a reference signal S2, a digital signal Dout outputted from a comparator 50 is changed from "0" to "1" while a gain of a hysteresis amplifier 40 is dropped and a level of the reference signal S2 inputted to the comparator 50 becomes low. When a level of the baseband signal S1 becomes lower than that of the reference signal S2, the digital signal Dout is changed to "0" while a gain of the hysteresis amplifier 40 is increased and a level of the reference signal S2 inputted to the comparator 50 becomes high. In each case, a voltage difference between the baseband signal S1 and the reference signal S2 is widened while maintaining a value of the digital signal Dout. Therefore, malfunction of the comparator 50 hardly occurs. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a receiving circuit that reproduces a digital signal from a received signal, and more particularly to a receiving circuit and a binary signal generating circuit that can suppress noise generated in a digital signal when there is no signal.

  For example, in infrared communication, the level of the received signal may change by several tens of dB. Therefore, it is necessary to appropriately change the threshold value that is referred to when the digital signal is reproduced from the received signal after detection according to the level of the received signal. Generally, this threshold value is obtained by averaging the received signal after detection by an integrating circuit.

FIG. 8 is a diagram showing an example of a general receiving circuit that detects a signal modulated by ASK (amplitude shift keying) and reproduces a digital signal. The receiving circuit shown in FIG. 8 includes an amplifier 110, a detection circuit 120, an integration circuit 130, and a comparator 140.
The amplifier 110 amplifies the reception signal RFin modulated by ASK. The detection circuit 120 separates the baseband signal S11 from the reception signal amplified by the amplifier 110. The integration circuit 130 integrates the baseband signal S11 separated in the detection circuit 120, and outputs the average to the comparator 140 as a reference signal S12. The comparator 140 compares the voltages of the baseband signal S11 and the reference signal S12, and outputs a high level or low level digital signal Dout according to the comparison result.

In the receiving circuit shown in FIG. 8, the reference signal S12 is generated by integrating the baseband signal S11. Therefore, the reference signal S12 approaches the baseband signal S11 when there is no signal in which no carrier wave is transmitted. On the other hand, since the baseband signal S11 and the reference signal S12 are directly compared in the comparator 140, if the two voltage values approach each other, the comparator 140 is likely to malfunction due to the influence of the noise component included in the baseband signal S11. Become. As a result, noise occurs in the digital signal Dout of the comparator 140 when there is no signal.
In addition, even when a carrier wave is transmitted, if a carrier wave having a longer duration than the time constant of the integration circuit 130 is transmitted, the reference signal S12 approaches the baseband signal S11. At this time, the baseband signal S11 includes a ripple of a carrier wave in addition to the noise described above. Therefore, when the voltage values of both approaches, noise is generated in the digital signal Dout.

  FIG. 9 is a diagram illustrating waveforms of input signals (S11, S12) of the comparator 140 in the receiving circuit shown in FIG. As shown in FIG. 9, noise and ripple components are superimposed on the baseband signal S11. Therefore, when the reference signal S12 asymptotically approaches the baseband signal S11 when there is no signal or during carrier wave transmission, the output of the comparator 140 is likely to change according to noise.

If the output of the comparator 140 changes according to noise, it causes a communication error rate to increase. Moreover, since the comparator 140 operates during a period during which it should be stopped, useless power consumption increases.
In order to suppress such a malfunction of the comparator, for example, in Patent Document 1 below, an ASK demodulator is configured using a comparator having hysteresis.
JP 2004-135306 A

  When the comparator has hysteresis, the malfunction of the comparator can be effectively prevented by setting the hysteresis range wider than the noise amplitude. However, a comparator with hysteresis generally has the disadvantage of high power consumption.

  The ripple of the carrier wave included in the baseband signal varies in proportion to the level of the received signal. For this reason, when the level fluctuation of the received signal becomes too large, it becomes difficult to set the hysteresis insensitive range wider than the ripple amplitude. In such a case, in the conventional receiving circuit, the automatic gain control is performed in the amplifier 110 so that the amplitude of the received signal input to the detection circuit 120 is within a certain range. However, if the amplifier 110 is provided with an automatic gain control function, the circuit becomes complicated and the power consumption increases.

  Furthermore, there is a method for reducing power consumption by detecting the state of no signal and stopping the operation of the comparator. However, this method requires a detection circuit for the state of no signal and complicates the configuration. There are disadvantages.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a receiving circuit and a binary signal that can effectively suppress the generation of noise when a digital signal is reproduced from the received signal with a simple circuit configuration. It is to provide a signal generation circuit.

  The receiving circuit according to the first aspect of the present invention integrates the detected received signal and outputs the integration result as a reference signal, and when the level of the received signal is higher than the level of the reference signal Has a first value and outputs a digital signal having a second value when the level of the received signal is lower than the level of the reference signal, and the reference signal input to the comparison circuit or A first amplifying circuit for amplifying the received signal input to the integrating circuit, wherein the gain is reduced when the digital signal changes from the second value to the first value; A first amplifier circuit that increases the gain when the value changes from 1 to the second value.

According to the receiving circuit according to the first aspect, when the level of the received signal becomes higher than the level of the reference signal, the digital signal output from the comparison circuit is changed from the second value to the first value. To change. When the digital signal changes to the first value, the gain of the first amplifier circuit decreases, and the level of the reference signal input to the comparison circuit decreases. As a result, the level difference between the reference signal input to the comparison circuit and the received signal is widened while the digital signal is maintained at the first value. When the level difference between both signals widens, malfunction of the comparison circuit due to the influence of noise components included in the received signal is less likely to occur, and noise of the digital signal is suppressed.
In addition, when the level of the received signal becomes lower than the level of the reference signal, the digital signal changes to the second value, and the gain of the first amplifier circuit increases and the comparison is reversed. The level of the reference signal input to the circuit is increased. As a result, the level difference between the reference signal input to the comparison circuit and the received signal is widened while the digital signal is maintained at the second value. Also in this case, the level difference between the two signals widens, so that the malfunction of the comparison circuit is less likely to occur, and the noise of the digital signal is suppressed.

  Preferably, the first amplifier circuit has a gain less than 1 when the digital signal has the first value and a gain greater than 1 when the digital signal has the second value. You may have to.

Preferably, the receiving circuit according to the first aspect may further include a second amplifying circuit for amplifying the received signal input to the comparison circuit. The second amplifier circuit increases the gain when the digital signal changes from the second value to the first value, and increases the gain when the digital signal changes from the first value to the second value. You can lower it.
When the digital signal changes to the first value, the gain of the second amplifier circuit increases, and the level of the received signal input to the comparison circuit increases. As a result, the level difference between the reference signal input to the comparison circuit and the received signal is widened while the digital signal is maintained at the first value. When the level difference between the two signals widens, malfunction of the comparison circuit is less likely to occur, and noise of the digital signal is suppressed.
When the digital signal changes to the second value, the gain of the second amplifier circuit decreases, and the level of the received signal input to the comparison circuit decreases. As a result, the level difference between the reference signal input to the comparison circuit and the received signal is widened while the digital signal is maintained at the second value. When the level difference between the two signals widens, malfunction of the comparison circuit is less likely to occur, and noise of the digital signal is suppressed.

  A receiving circuit according to a second aspect of the present invention integrates a detected received signal and outputs the integration result as a reference signal, and when the level of the received signal is higher than the level of the reference signal Has a first value, and when the level of the received signal is lower than the level of the reference signal, a comparison circuit that outputs a digital signal having a second value and the received signal input to the comparison circuit An amplification circuit for amplifying, wherein the gain is increased when the digital signal changes from the second value to the first value, and the gain is increased when the digital signal changes from the first value to the second value. And an amplifier circuit for lowering.

According to the receiving circuit according to the second aspect, when the level of the received signal becomes higher than the level of the reference signal, the digital signal output in the comparison circuit is changed from the second value to the first value. To change. When the digital signal changes to the first value, the gain of the amplifier circuit increases, and the level of the reception signal input to the comparison circuit increases. As a result, the level difference between the reference signal input to the comparison circuit and the received signal is widened while the digital signal is maintained at the first value. When the level difference between both signals widens, malfunction of the comparison circuit due to the influence of noise components included in the received signal is less likely to occur, and noise of the digital signal is suppressed.
Also, when the level of the received signal becomes lower than the level of the reference signal, the digital signal changes to the second value, and the gain of the amplifier circuit decreases and is input to the comparison circuit. The level of the received signal is reduced. As a result, the level difference between the reference signal input to the comparison circuit and the received signal is widened while the digital signal is maintained at the second value. Also in this case, the level difference between the two signals widens, so that the malfunction of the comparison circuit is less likely to occur, and the noise of the digital signal is suppressed.

  Preferably, the amplifier circuit has a gain greater than 1 when the digital signal has the first value and has a gain less than 1 when the digital signal has the second value. You can do it.

  A binary signal generation circuit according to a third aspect includes a comparison circuit that compares an input signal including digital information with a reference signal and outputs a binary signal, and a logic of the binary signal output from the comparison circuit. A reference signal control circuit that controls the level of the reference signal in response to the level, and the reference signal becomes the first signal level when the binary signal is at the first logic level, and the binary value When the signal is at the second logic level, the reference signal has a second signal level different from the first signal level.

Preferably, the binary signal generation circuit according to the third aspect includes an amplifier circuit in which the reference signal control circuit amplifies the reference signal, and the gain of the amplifier circuit is in accordance with the logic level of the binary signal. Change.
Preferably, the binary signal generation circuit according to the third aspect further includes an integration circuit that integrates the input signal to generate the reference signal.
Preferably, in the binary signal generation circuit according to the third aspect, when the binary signal is at the first logic level, the reference signal is low, and when the binary signal is at the second logic level. The reference signal is controlled to be high.
Preferably, the binary signal generation circuit according to the third aspect further includes an infrared detection circuit that converts infrared light into an electrical signal, and a detection circuit that detects the electrical signal and generates the input signal.

  According to the present invention, it is possible to effectively suppress the occurrence of noise when reproducing a digital signal from a received signal, with a simple circuit configuration using an amplifier circuit that switches the gain according to the value of the digital signal.

FIG. 1 is a diagram illustrating an example of a configuration of a receiving circuit according to the first embodiment of the present invention.
The receiving circuit illustrated in FIG. 1 includes an amplifier 10, a detection circuit 20, an integration circuit 30, a hysteresis amplifier 40, and a comparator 50.
The integrating circuit 30 is an example of an integrating circuit in the present invention.
The comparator 50 is an example of a comparison circuit in the present invention.
The hysteresis amplifier 40 is an example of a first amplifier circuit in the present invention.

  The amplifier 10 is a circuit that amplifies an input received signal RFin, and can be configured by a simple circuit such as a voltage amplifier having a constant gain.

  The detection circuit 20 removes the high frequency component of the carrier wave from the reception signal amplified by the amplifier 10 and extracts the baseband signal S1. For example, as shown in FIG. 1, the detection circuit 20 includes a diode 21, a resistor 22, and a capacitor 23. The diode 21 inputs the reception signal amplified by the amplifier 10 to the anode, and outputs the baseband signal S1 from the cathode. The resistor 22 and the capacitor 23 are connected in parallel between the anode of the diode 21 and the ground potential G, and attenuate the high frequency component of the carrier wave included in the signal rectified by the diode 21.

  The integration circuit 30 integrates the received signal (baseband signal S1) after detection output from the detection circuit 20. The integration circuit 30 includes a resistor 31 and a capacitor 32 as shown in FIG. The baseband signal S1 from the detection circuit 20 is input to one terminal of the resistor 31, and the other terminal is connected to the ground potential G via the capacitor 32. The integration result of the integration circuit 30 is generated as a voltage in the capacitor 32.

  The comparator 50 compares the baseband signal S1 separated in the detection circuit 20 with the reference signal S2 input from the hysteresis amplifier 40, and generates a digital signal corresponding to the result. That is, the comparator 50 has the value “1” when the level of the baseband signal S1 is higher than the level of the reference signal S2, and the value “0” when the level of the baseband signal S1 is lower than the level of the reference signal S2. ”Is output.

  The hysteresis amplifier 40 amplifies the signal (voltage of the capacitor 32) integrated in the integration circuit 30 and inputs the amplified signal to the comparator 50. The hysteresis amplifier 40 switches the gain according to the digital signal Dout from the comparator 50. That is, the gain is decreased when the digital signal Dout changes from “0” to “1”, and the gain is increased when the digital signal Dout changes from “1” to “0”.

FIG. 2 is a diagram illustrating an example of the configuration of the hysteresis amplifier 40.
The hysteresis amplifier 40 shown in FIG. 2 includes a differential amplifier circuit 41, resistors 42, 43, and 44, and a selector circuit 45.
The differential amplifier circuit 41 has a positive input terminal and a negative input terminal, and amplifies and outputs a voltage between the terminals. A signal Sin to be amplified (an output signal of the integrating circuit 30 in the example of FIG. 1) is input to the positive input terminal. The output signal of the differential amplifier circuit 41 is fed back to the negative input terminal via the resistor 42. Resistors 43 and 44 are connected in series between the negative input terminal and the ground potential G.
The selector circuit 45 selects the node NA of the output of the differential amplifier circuit 41 or the node NB at the connection point of the resistors 43 and 44 according to the digital signal Dout, and the selected node becomes the output node NC of the hysteresis amplifier 40. Connecting. The selector circuit 45 selects the node NB when the digital signal Dout is “1”, and selects the node NA when the digital signal Dout is “0”. The selector circuit 45 includes switch circuits 46 and 47, for example, as shown in FIG. The switch circuit 46 is connected between the nodes NA and NC, and is turned off when the digital signal Dout is “1” and turned on when it is “0”. The switch circuit 47 is connected between the nodes NB and NC, and is turned on when the digital signal Dout is “1” and turned off when it is “0”.

Assuming that the gain of the differential amplifier circuit 41 is sufficiently high, the voltages at the positive input terminal and the negative input terminal become substantially equal by negative feedback through the resistor 42. Therefore, the output node NA of the differential amplifier circuit 41 has a higher potential than the input signal Sin, and the node NB at the connection point of the resistors 43 and 44 has a lower potential than the input signal Sin.
When the digital signal Dout becomes “1”, the node NB at the connection point of the resistors 43 and 44 is selected, so that the output signal Sout has a lower potential than the input signal Sin. In this case, the gain of the hysteresis amplifier 40 is smaller than “1”. On the other hand, when the digital signal Dout becomes “0”, since the output node NA of the differential amplifier circuit 41 is selected, the output signal Sout becomes higher in potential than the input signal Sin. In this case, the gain of the hysteresis amplifier 40 is larger than “1”.

  Here, the operation of the receiving circuit having the above-described configuration will be described with reference to FIG. FIG. 3 is a diagram illustrating the waveform of the input signal of the comparator 50 in the receiving circuit shown in FIG.

The reception signal RFin is modulated by, for example, ASK, and carries a signal depending on the presence or absence of a carrier wave. The baseband signal S1 separated from the reception signal RFin in the detection circuit 20 includes external noise and carrier wave ripple as shown in FIG.
In a period in which no carrier wave is received, the baseband signal S1 is at a low level, and the digital signal Dout output from the comparator 50 is “0”. If this period continues for a long time, the signal integrated by the integration circuit 30 becomes substantially equal to the average value of the baseband signal S1. However, when the digital signal Dout is “0”, the gain of the hysteresis amplifier 40 is higher than “1” (high gain). Therefore, the reference signal S2 output from the hysteresis amplifier 40 is higher than the average value of the baseband signal S1 as shown in FIG. That is, the voltage difference between the average value of the baseband signal S1 and the reference signal S2 is widened while maintaining the digital signal Dout at “0”. By setting the gain (high gain) of the hysteresis amplifier 40 so that this voltage difference becomes larger than the noise amplitude, it is difficult for the comparator 50 to malfunction due to the influence of noise.
On the other hand, during the period in which the carrier wave is received, the baseband signal S1 is at a high level, and the digital signal Dout output from the comparator 50 is “1”. Even when this period lasts for a long time, the signal integrated by the integrating circuit 30 becomes substantially equal to the average value of the baseband signal S1. However, when the digital signal Dout is “1”, the gain of the hysteresis amplifier 40 is lower than “1” (low gain). Therefore, the reference signal S2 output from the hysteresis amplifier 40 is lower than the average value of the baseband signal S1 as shown in FIG. That is, the voltage difference between the average value of the baseband signal S1 and the reference signal S2 is widened while maintaining the digital signal Dout at “1”. By setting the gain (low gain) of the hysteresis amplifier 40 so that this voltage difference becomes larger than the ripple component and the amplitude of the noise, it is difficult for the comparator 50 to malfunction due to the influence of noise.

As described above, according to the receiving circuit of the present embodiment, when the level of the detected baseband signal S1 becomes higher than the level of the reference signal S2, the digital signal Dout output from the comparator 50 is changed from “0”. It changes to “1”, the gain of the hysteresis amplifier 40 decreases, and the level of the reference signal S2 input to the comparator 50 decreases. In this case, since the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “1”, malfunction of the comparator 50 due to noise and ripple components is less likely to occur. Further, when the level of the baseband signal S1 becomes lower than the level of the reference signal S2, the digital signal Dout changes from “1” to “0”, the gain of the hysteresis amplifier 40 increases, and the reference signal input to the comparator 50 The level of S2 becomes high. In this case, since the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “0”, the comparator 50 is less likely to malfunction due to noise.
As described above, in the receiving circuit according to the present embodiment, by using the simple hysteresis amplifier 40 instead of the hysteresis comparator with large power consumption, malfunction of the comparator 50 due to noise or the like can be suppressed. The power consumption can be reduced.
In addition, since an automatic gain control amplifier for adjusting the level of the received signal input to the detection circuit 20 and a circuit for detecting a no-signal state can be prevented, malfunction of the comparator 50 can be suppressed. In this respect, the circuit configuration can be simplified and the power consumption can be reduced.

Further, according to the receiving circuit according to the present embodiment, the reference signal S2 is generated by amplifying the signal obtained by averaging the baseband signal S1 by the integrating circuit 30, so that the reference signal S2 is referred to according to the level change of the received signal RFin. The signal S2 can be changed. Therefore, the correct digital signal Dout can be reproduced even when the variation of the reception signal RFin is large.
In addition, since the level difference between the average value of the baseband signal S1 and the reference signal S1 is generated by switching the gain of the hysteresis amplifier 40, the level difference can be changed in accordance with the change of the ripple component of the carrier wave. it can. That is, if the ripple component of the carrier wave increases in accordance with the reception level, the hysteresis insensitive range becomes wider accordingly. Therefore, even when the ripple component changes greatly according to the reception level, the malfunction of the comparator 50 can be effectively suppressed.

  Furthermore, according to the receiving circuit according to the present embodiment, even when a carrier wave having a duration longer than the time constant of the integrating circuit 30 is input, malfunction of the comparator 50 is effectively suppressed, and noise of the digital signal Dout is reduced. Can be suppressed. As a result, it is possible to cope with various communication protocols having different carrier durations without switching the time constant of the integrating circuit 30. Therefore, a highly compatible receiving circuit can be provided with a simple configuration.

  Further, according to the hysteresis amplifier 40 shown in FIG. 2, the gain is set by the resistance ratio of the resistors 42, 43 and 44. In general, since the resistance ratio of the resistance element formed on the semiconductor substrate has high accuracy and good temperature characteristics, according to the present embodiment, a high-accuracy gain can be set without providing a precise reference voltage circuit.

FIG. 4 is a diagram illustrating an example of the configuration of a receiving circuit for infrared communication according to the present embodiment.
The infrared communication receiver circuit shown in FIG. 4 is provided with an infrared detector 70 in front of the receiver circuit shown in FIG. For example, as illustrated in FIG. 4, the infrared detection unit 70 includes a photodiode 71, a capacitor 72, and a resistor 73. The cathode of the photodiode 71 is connected to the power supply line Vcc. The anode of the photodiode 71 is connected to the ground potential G through the resistor 73 and is connected to the input of the amplifier 10 through the capacitor 72.
The infrared signal received by the photodiode 71 is converted into a current signal corresponding to the light intensity. This current signal flows through the resistor 73 to be converted into a voltage signal and input to the amplifier 10 through the capacitor 72.

  Next, another embodiment of the present invention will be described.

FIG. 5 is a diagram illustrating an example of a configuration of a receiving circuit according to the second embodiment of the present invention.
The receiving circuit shown in FIG. 5 is obtained by moving the hysteresis amplifier 40 in the receiving circuit shown in FIG. That is, in the example of FIG. 5, the hysteresis amplifier 40 amplifies the detected baseband signal S <b> 1 input to the integrating circuit 30. As described above, the gain of the hysteresis amplifier 40 is switched according to the digital signal Dout of the comparator 50. The output of the integrating circuit 30 is input to the comparator 50 as it is as the reference signal S2.

In the receiving circuit shown in FIG. 5, when the level of the baseband signal S1 becomes higher than the level of the reference signal S2, the digital signal Dout changes from “0” to “1”, and the gain of the hysteresis amplifier 40 decreases. As the gain decreases, the level of the signal input to the integration circuit 30 decreases, so the level of the reference signal S2 output from the integration circuit 30 decreases. Thus, the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “1”.
On the other hand, when the level of the baseband signal S1 becomes lower than the level of the reference signal S2, the digital signal Dout changes from “1” to “0”, and the gain of the hysteresis amplifier 40 increases. As the gain increases, the level of the signal input to the integration circuit 30 increases, so the level of the reference signal S2 output from the integration circuit 30 increases. Thus, the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “0”.
Therefore, also in the receiving circuit shown in FIG. 5, the malfunction of the comparator 50 due to the influence of the noise component can be effectively suppressed as in the receiving circuit shown in FIG.

FIG. 6 is a diagram illustrating an example of a configuration of a receiving circuit according to the third embodiment of the present invention.
The receiver circuit shown in FIG. 6 is obtained by adding a hysteresis amplifier 60 to the receiver circuit shown in FIG.
The hysteresis amplifier 60 is a circuit that amplifies the baseband signal S1 input to the comparator 50, and switches the gain in accordance with the output of the comparator (digital signal Dout), similar to the hysteresis amplifier 40 described above. However, the switching direction of the gain by the hysteresis amplifier 60 is opposite to that of the hysteresis amplifier 40. When the digital signal Dout changes from “0” to “1”, the gain is increased, and the digital signal Dout changes from “1” to “0”. Then lower the gain. The hysteresis amplifier 60 can be realized, for example, with a simple circuit configuration shown in FIG.
The hysteresis amplifier 60 is an embodiment of the second amplifier circuit in the present invention.

In the receiving circuit shown in FIG. 6, when the level of the baseband signal S1 becomes higher than the level of the reference signal S2, the digital signal Dout output from the comparator 50 changes from “0” to “1”, and the gain of the hysteresis amplifier 40 Decreases, and the gain of the hysteresis amplifier 60 increases. When the gain of the hysteresis amplifier 40 decreases, the level of the reference signal S2 input to the comparator 50 decreases. Further, when the gain of the hysteresis amplifier 60 increases, the level of the baseband signal S1 input to the comparator 50 increases. Thus, the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “1”.
On the other hand, when the level of the baseband signal S1 becomes lower than the level of the reference signal S2, the digital signal Dout changes from “1” to “0”, the gain of the hysteresis amplifier 40 increases, and the gain of the hysteresis amplifier 60 decreases. When the gain of the hysteresis amplifier 40 increases, the level of the reference signal S2 input to the comparator 50 increases. Further, when the gain of the hysteresis amplifier 60 decreases, the level of the baseband signal S1 input to the comparator 50 decreases. As a result, the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “0”, so that the comparator 50 is unlikely to malfunction.
Therefore, in the receiving circuit shown in FIG. 6, similarly to the receiving circuit shown in FIG. 1, the malfunction of the comparator 50 due to the influence of the noise component can be effectively suppressed.
Further, since the relative level difference between the two input signals (S1, S2) of the comparator 50 can be arbitrarily set by the two hysteresis amplifiers (40, 60), the degree of freedom in design is improved.

FIG. 7 is a diagram illustrating an example of a configuration of a receiving circuit according to the fourth embodiment of the present invention.
The receiving circuit shown in FIG. 7 is obtained by omitting the hysteresis amplifier 40 in the receiving circuit shown in FIG.

In the receiving circuit shown in FIG. 7, when the level of the baseband signal S1 becomes higher than the level of the reference signal S2, the digital signal Dout output from the comparator 50 changes from “0” to “1”, and the gain of the hysteresis amplifier 60 is increased. Will rise. When the gain of the hysteresis amplifier 60 increases, the level of the baseband signal S1 input to the comparator 50 increases. Thus, the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “1”.
On the other hand, when the level of the baseband signal S1 becomes lower than the level of the reference signal S2, the digital signal Dout changes from “1” to “0”, and the gain of the hysteresis amplifier 60 decreases. When the gain of the hysteresis amplifier 60 decreases, the level of the baseband signal S1 input to the comparator 50 decreases. As a result, the voltage difference between the baseband signal S1 and the reference signal S2 is widened while the digital signal Dout is maintained at “0”, so that the comparator 50 is unlikely to malfunction.
Therefore, in the receiving circuit shown in FIG. 6, similarly to the receiving circuit shown in FIG. 1, the malfunction of the comparator 50 due to the influence of the noise component can be effectively suppressed.

  As mentioned above, although embodiment of this invention was described, this invention is not limited only to said embodiment, Various variations are included.

For example, in the above embodiment, the gain of the hysteresis amplifier 40 (60) is switched to create a level difference between the two input signals of the comparator 50 to prevent the comparator from malfunctioning. However, the present invention is not limited to this. . For example, a circuit that adds a fixed offset to one or both of the two input signals (baseband signal S1 or reference signal S2) of the comparator 50 according to the value of the digital signal Dout may be further added. For example, when the value of the digital signal Dout changes to “1”, the level of the baseband signal S1 is increased or the level of the reference signal S2 is decreased, and when the value of the digital signal Dout changes to “0” A circuit for generating a fixed offset is provided so as to decrease the level of the signal S1 or increase the level of the reference signal S2. As a result, even when the level of the received signal fluctuates in a wide range, a level difference between the baseband signal S1 and the reference signal S2 can be more appropriately generated, so that the malfunction of the comparator 50 due to noise can be effectively suppressed. it can.
In the above-described embodiment, the reference signal is generated based on the baseband signal. However, the reference signal may be supplied to the comparator as an independent reference signal unrelated to the baseband signal. In this case, a predetermined offset voltage may be applied to the reference signal in accordance with the output of the comparator.
Further, the comparator may be configured to supply the baseband signal to the negative input terminal and supply the reference signal to the positive input terminal.

  In the above-described embodiment, an example in which the present invention is applied to a receiving circuit for infrared communication is given. However, the present invention is not limited to this, and various communication fields such as a radio communication device using RFID (Radio Frequency IDentification), for example. Widely applicable to.

It is a figure which shows an example of a structure of the receiver circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of a structure of a hysteresis amplifier. It is a figure which illustrates the waveform of the input signal of the comparator in the receiving circuit shown in FIG. It is a figure which shows an example of a structure of the receiving circuit for infrared communication which concerns on this embodiment. It is a figure which shows an example of a structure of the receiver circuit which concerns on the 2nd Embodiment of this invention. It is a figure which shows an example of a structure of the receiving circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows an example of a structure of the receiver circuit which concerns on the 4th Embodiment of this invention. It is a figure which shows an example of the general receiver circuit which detects the signal by which ASK was modulated, and reproduces | regenerates a digital signal. It is a figure which illustrates the waveform of the input signal of the comparator in the receiving circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Amplifier 10, 20 ... Detection circuit, 30 ... Integration circuit, 40, 60 ... Hysteresis amplifier, 50 ... Comparator, 70 ... Infrared detector, 21 ... Diode, 22, 31, 42-44, 73 ... Resistance, 23, 32, 72... Capacitor, 41... Differential amplifier circuit, 46, 47... Switch circuit, photodiode 71

Claims (8)

An integration circuit that integrates the detected received signal and outputs the integration result as a reference signal;
A digital signal having a first value is output when the level of the received signal is higher than the level of the reference signal, and a second value is output when the level of the received signal is lower than the level of the reference signal. A comparison circuit;
A first amplifier circuit that amplifies the reference signal input to the comparison circuit or the received signal input to the integration circuit, wherein the digital signal changes from the second value to the first value. A first amplifying circuit that lowers the gain and increases the gain when the digital signal changes from the first value to the second value. A second amplifying circuit for amplifying the received signal input to the comparison circuit, wherein the gain is increased when the digital signal changes from the second value to the first value; A second amplifying circuit that lowers the gain when the value changes from the value of 1 to the second value;
The receiving circuit according to claim 1. An integration circuit that integrates the detected received signal and outputs the integration result as a reference signal;
A digital signal having a first value is output when the level of the received signal is higher than the level of the reference signal, and a second value is output when the level of the received signal is lower than the level of the reference signal. A comparison circuit;
An amplifying circuit for amplifying the received signal input to the comparison circuit, wherein the gain is increased when the digital signal changes from the second value to the first value, and the digital signal is the first value. An amplifying circuit that reduces the gain when the value changes from 1 to the second value. A comparison circuit that compares a reference signal with an input signal including digital information and outputs a binary signal;
A reference signal control circuit for controlling the level of the reference signal in response to the logic level of the binary signal output from the comparison circuit;
Have
The reference signal is at a first signal level when the binary signal is at a first logic level, and the reference signal is different from the first signal level when the binary signal is at a second logic level. 2 signal level,
A binary signal generation circuit.   The binary signal generation circuit according to claim 4, wherein the reference signal control circuit includes an amplification circuit that amplifies the reference signal, and a gain of the amplification circuit changes according to a logic level of the binary signal.   6. The binary signal generation circuit according to claim 4, further comprising an integration circuit for integrating the input signal to generate the reference signal.   7. The control according to claim 6, wherein the reference signal is controlled to be low when the binary signal is at a first logic level, and the reference signal is controlled to be high when the binary signal is at a second logic level. A binary signal generation circuit. The binary signal generation circuit according to any one of claims 4 to 7, further comprising: an infrared detection circuit that converts infrared light into an electrical signal; and a detection circuit that detects the electrical signal and generates the input signal.