JP2009044481A - Data processing apparatus and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of transferring data by preventing the data from being stolen without requiring a data processing time, and to provide an image forming apparatus. <P>SOLUTION: The image processing apparatus includes: an image processing part 302 for processing image data inputted from image data input means; an image control part 308 for receiving the image data processed by the image processing part 302 via a versatile bus 305, and processing the image data to be the desired image data; the versatile bus 305; first and second versatile bus I/Fs 303, 307 respectively arranged in the image processing part 302 and the image control part 308; and a scramble device 304 arranged between the first versatile bus I/F 303 and the versatile bus 305, so as to perform scramble processing in a transfer signal from the image processing part 302 to the image control part 308. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image data processing device that processes a digital image signal and converts it into a signal for image formation, or a data processing device that handles measurement data such as a measuring instrument, and input data is image data. The present invention relates to an image forming apparatus that reproduces an image on a transfer paper after processing.

  As a conventional technique related to a digital image processing apparatus, for example, a technique described in Patent Document 1 is known. In this prior art, an original image is read by a reading unit, the read signal is digitally converted, the digitally converted image signal is subjected to image processing by an image processor, and then the image data control unit is connected to a parallel bus. (PCI) is used to transmit to the memory in the system controller.

  A multi-function device having a plurality of functions such as a printer device including a digital image processing device and a copying machine is generally provided with a connector for connecting an optional function on a parallel bus. When the bus is a general general-purpose bus (PCI, USB, ATAPI, etc.), data flowing on the parallel bus can be stolen. On the other hand, as a technique for encrypting image data flowing on a parallel bus, a technique described in Patent Document 2 is known.

The invention described in Patent Document 2 aims to prevent the misuse of data by preventing the contents of the stolen data from being understood even when the image data is stolen from the parallel bus of the digital image processing apparatus. In the image processing apparatus including an image data control unit that exchanges image data with various functional devices via a parallel bus, the image data control unit and the one or more functional devices are configured in parallel. It is characterized by having an encryption means for converting image data to be sent to the bus into a data format in which the contents of the data are not known.
JP 2000-316063 A JP 2005-094643 A

By the way, in order to prevent data from being stolen, the invention of Patent Document 2
1) It takes time to process the data.
2) The amount of data to be transferred increases, but the data is stolen although it is encrypted.
There is a drawback.

  Accordingly, an object of the present invention is to provide a data processing apparatus and an image forming apparatus capable of transferring data without requiring data processing time and preventing data from being stolen.

  In order to solve the above problem, the first means includes a first data processing means for processing data input from the data input means side, and input data processed by the first data processing means on a general-purpose bus. A second data processing means for receiving and processing desired data, and transmitting and receiving data to and from various functional devices via the general-purpose bus. The first and second general-purpose bus interfaces provided in the general-purpose bus and the first and second data processing units, respectively, and provided between the first general-purpose bus interface and the general-purpose bus; Scramble processing means for scrambling a transfer signal from the data processing means side to the second data processing means side.

  The second means includes a descrambling means provided between the general-purpose bus and the second general-purpose bus interface in the first means, for descrambling the scrambled transfer signal. Features.

  The third means is characterized in that, in the first or second means, the scramble processing means performs a scramble process by exchanging bits of the transfer signal.

  The fourth means is characterized in that, in the first or second means, the scramble processing means has several patterns for changing the bit of the transfer signal, and scrambles in an arbitrary pattern by switching the user. .

  The fifth means is characterized in that, in the first or second means, the scramble process is performed by EXORing the scramble key set by the scramble means.

  Sixth means is characterized in that, in the first or second means, scramble processing is performed by EXORing a scramble key that changes every cycle, using the transfer signal output by the scramble means in the previous cycle as a scramble key. A data processing device.

  The seventh means is characterized in that, in the first or second means, the user comprises setting means for setting the presence / absence of scramble processing.

  According to an eighth means, in any one of the first to seventh means, the data is image data.

  The ninth means is characterized in that the image forming apparatus includes the data processing apparatus according to the eighth means as an image processing apparatus.

  In the embodiment described later, the first data processing means is in the image processing section 302, the general purpose bus is in reference numeral 305, the second data processing means is in the image control section 308, and the first general purpose bus interface is in the general purpose bus. The second general-purpose bus interface corresponds to the general-purpose bus I / F 307, the scramble processing means corresponds to the scramble device 304, the scramble release means corresponds to the descramble device 306, and the setting means corresponds to the CPU 310.

  According to the present invention, the scrambling process and the descrambling process are performed by the general-purpose bus interface, so that data transfer is possible without requiring data processing time and preventing data from being stolen.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In the present embodiment, in order to simplify the description, a description will be given by taking as an example a bus in which data transfer is performed using the protocol of FIG. As can be seen from the protocol of FIG. 1, in the next cycle when the FRAME signal becomes L, a transfer destination address is transferred to the AD signal, and a memory write or memory read command is transferred to the C / BE signal. From the next cycle, transfer data is transferred to the AD signal, byte enable data is transferred to the C / BE signal, and data when both the IRDY signal and the TRDY signal are L are transferred as valid data. The command of the C / BE signal is assumed to be memory read when it is 6, and memory write when it is 7.

  FIG. 2 shows the actual transfer protocol state. The transfer in FIG. 2 indicates that the AD signal value of the cycle in which the FRAME signal is L is 0 and the C / BE signal value is 7, so that the data is written to address 0. Since the IRDY signal TRDY signal is both L from the next cycle, effective data transfer is performed, and data 1, 2, and 3 are sequentially written from address 0.

  FIG. 3 is a block diagram showing the overall system configuration of the image processing apparatus according to this embodiment. In this figure, this image processing system is composed of an image reading device 301, an image processing device 300, and an image writing device 311. The image processing apparatus 300 includes an image processing unit 302, a scramble unit 304, a descrambling unit 306, an image control unit 308, a storage device 309, and a CPU 310. Between the image processing unit 302 and the scramble unit 304, a descrambling unit 306 is provided. The first and second general-purpose bus I / Fs 303 and 307 are provided between the image control unit 308 and the image control unit 308, respectively. The scramble unit 304 and the descrambling unit 306 are connected by a general-purpose bus 305, and the CPU 310 controls the scramble unit 304 and the descrambling unit 307.

  In the system configured in this way, the image processing unit 302 performs necessary image processing on the data read by the image reading device 301 in FIG. Thereafter, a signal transferred from the general-purpose bus I / F 303 using the transfer protocol of the general-purpose bus is input to the scrambler 304. In order to simplify the explanation, the transfer protocol of the general-purpose bus here is the transfer protocol shown in FIG.

  The CPU 310 performs setting so that the scrambler 304 scrambles before the data transfer starts and the scrambler 306 executes descrambling.

  The scrambler 304 scrambles the input signal and outputs the scrambled signal to the general-purpose bus 305. In order to simplify the description, it is assumed that the scramble method in the scramble unit 304 is simply replacing the lower 4 bits of the AD signal and the C / BE signal. When the transfer of FIG. 2 is scrambled to replace the lower 4 bits of the AD signal and the C / BE signal, the data output to the general-purpose bus 305 is as shown on the right side of FIG.

  When stealing data, the general-purpose bus 305 is monitored, and the data acquisition is performed using the AD signal value and the C / BE signal value of the next cycle when the FRAME signal becomes L as a trigger. Since the value of the C / BE signal in the next cycle when FRAME becomes L is 0 in the flowing signal, it appears that no data access to the memory has occurred. Therefore, data cannot be stolen from the general-purpose bus 305.

  The descrambling unit 306 that has received the scrambled signal from the general-purpose bus 305 cancels the scramble process and transfers the signal to the general-purpose bus I / F 307. In this case, the cancellation of the scramble process is to replace the lower 4 bits of the AD signal of the signal received from the general-purpose bus 305 with the C / BE signal. The data transfer between the descrambling unit 306 and the general-purpose bus I / F 307 is performed according to the protocol shown in FIG. 2, so that the general-purpose bus I / F 307 can correctly receive data. The general-purpose bus I / F 307 transfers the received data to the image control unit 308, and the image control unit 308 transfers the data to the storage device 309.

  In this embodiment, in order to simplify the description, the scrambling method is merely the replacement of the lower 4 bits of the AD signal and the C / BE signal. However, the number of scrambling method patterns between two blocks is determined. It is also conceivable to change the signal to be replaced for each pattern. For example, when no pattern is set, the lower 4 bits of the AD signal and the C / BE signal are exchanged. In the case of the pattern 1, the upper 4 bits of the AD signal and the C / BE signal are exchanged. For example, the lower 1 bit and the IRDY signal, the lower 1 bit of the C / BE signal and the TRDY signal are exchanged.

  FIG. 5 is a block diagram showing an embodiment of a scramble processing apparatus comprising a scramble unit 304, a scramble release unit 306, and a CPU 310.

  In this embodiment, scrambling and descrambling are performed according to a pattern set by the CPU 501. The scrambler 304 includes a register 304r, and further includes an input switching unit 304a and an output switching unit 304b, and pattern holding units 304c1,... Having scramble patterns of patterns 1 to n (n: an integer of 2 or more) between them. .. 304 cn is provided. Similarly, the descrambling unit 306 includes a register 306r, an input switching unit 306a, an output switching unit 306b, and pattern holding units 306c1,.

  The CPU 310 sets the same scramble pattern in the register 304r in the scramble unit 304 and the register 306r in the scramble release unit 306. The input switching device 304a in the scramble unit 304 outputs data to one of the pattern holding units 304c1 to 304cn corresponding to the pattern set in the register 304r, and the output switching device 304b outputs the pattern set in the register 304r. Data is input from any one of the pattern holding units 304c1 to 304cn, and the data is output to the general-purpose bus 305.

  Similarly to the scrambler 304, the input switching device 306a in the scramble release unit 306 outputs data to any one of the release pattern holding units 306c1 to 306cn in accordance with the pattern set in the register 306r. The output switching device 306b outputs the data input from any of the pattern cancellation pattern holding units 306c1 to 306cn set in the register 306r.

  Further, it is possible to set the scramble key in the scramble unit 304 and the scramble release unit 306 before transfer, EXOR the scramble key to the transmission signal by the scramble unit 304, and EXOR the scramble key to the received signal by the scramble release unit 306.

  FIG. 6 is a block diagram illustrating a configuration of a scramble processing apparatus according to the second embodiment using a key. In the scramble processing apparatus according to this embodiment, the scrambler 304 includes a register 304s and a scramble processor 304d, and the scrambler 306 includes a register 306s and a scrambler 306d.

  The CPU 310 sets key values in the register 304s of the scrambler 304 and the register 306s of the descrambler 306. The scramble processing unit 304 performs an EXOR process on the input data with the value of the register 304 s and outputs the data to the general-purpose bus 305. The descrambling processing unit 306d of the descrambling unit 306 performs an EXOR process on the data input from the general-purpose bus 305 and outputs the result.

In addition, the scramble key can be changed for each transfer as a transfer signal in which the scramble key is output one cycle before.
FIG. 7 is a block diagram showing the configuration of the scramble processing apparatus according to the third embodiment using the transfer signal output one cycle before as a key. The third embodiment is different from the second embodiment in that the scrambler 304 and the descrambler 306 are provided with data holding registers 304f and 306f connected to the scrambler 304e and the descrambler 306e, respectively.

  In this embodiment, the CPU 310 sets a value to be the initial value of the key in the register 304d of the scrambler 304 and the register 306d of the descrambler 306. The scramble processing unit 304e performs EXOR processing on the value of the register 304d for the first input data and outputs the result to the general-purpose bus 305. At this time, the data output to the general-purpose bus 305 is held in the data holding register 304f.

  The scramble processing unit 304e performs an EXOR process on the data input in the next cycle, and outputs the value to the general-purpose bus 305. At this time, the data output to the general-purpose bus 305 is held in the data holding register 304f. Thereafter, the output data is similarly held in the data holding register 304f and used as a key when the next input data is scrambled.

  The descrambling unit 306 performs an EXOR process on the value of the register 306d for the first input from the general-purpose bus 305, and outputs the result. At this time, the data input from the general-purpose bus 305 is held in the data holding register 306f. The descrambling unit 306 performs an EXOR process on the data input in the next cycle and outputs the value. At this time, the data input from the general-purpose bus 305 is held in the data holding register 306f. Thereafter, similarly, the input data from the general-purpose bus 305 is held in the data holding register 306f, and the next input data is used as a key for the descrambling process.

  In the first to third embodiments, an example in which the scramble process is performed has been described. However, in order to acquire data at the time of analysis when there is a malfunction in a device, a mode in which the scramble process is not performed can be set according to user settings.

  FIG. 8 is a block diagram illustrating a configuration of a scramble processing apparatus according to a fourth embodiment having a mode in which scramble processing is not performed. In the fourth embodiment, the registers 304r and 306r in the first embodiment are changed to registers 304t and 306t for setting whether or not to execute the scramble process, and the input switching devices 304a and 306a and the output switching devices 304b and 306b are changed. Are provided with scramble processing units 304g and 306g and through mode units 304h and 306h. Other parts are the same as those of the first embodiment shown in FIG.

  In the fourth embodiment configured as described above, the CPU 310 sets whether to execute the scramble processing in the register 304 t of the scramble unit 304 and the register 306 t of the descramble unit 306. The input switching device 304a of the scrambler 304 outputs data to the scramble processor 304g when the setting of the register 304t performs scramble processing, and outputs data to the through mode unit 306h when scramble processing is not performed.

  The output switching device 807 inputs data from the scramble processing unit 805 when the setting of the register 803 performs scramble processing, and inputs data from the through mode 806 when not performing scramble processing, and outputs the data to the general-purpose bus 808. . The input switching device 811 of the descrambling device 809 outputs data to the scramble processing unit 812 when the setting of the register 810 performs scramble processing, and outputs data to the through mode 813 when not performing scramble processing. The output switching device 814 inputs data from the scramble processing unit 812 when the setting of the register 810 performs the scramble processing, and inputs data from the through mode 813 when the scramble processing is not performed, and outputs the data.

As described above, according to the present embodiment,
1) It is possible to realize a scrambled portion of an image processing apparatus that does not require data processing time, does not increase the amount of transferred data, and does not steal data from a general-purpose bus.
2) The descrambling of the scrambled signal can be realized.
3) An image processing apparatus that does not require control, does not require data processing time, does not increase the amount of data to be transferred, and does not steal data from a general-purpose bus can be realized.
4) By providing a plurality of scrambling means, an image processing apparatus with higher security can be realized.
5) By providing a scramble means using a key, an image processing apparatus with higher security can be realized.
By providing scramble means for changing 6) for each cycle, an image processing apparatus with higher security can be realized.
7) It is possible to realize an image processing apparatus that can easily analyze even when there is a problem in data transfer on the general-purpose bus.
8) It is possible to provide an image forming apparatus that does not require data processing time, does not increase the amount of transferred data, and prevents data from being stolen from the general-purpose bus.
There are effects such as.

It is a timing chart which shows the example of the bus | bath with which data transfer is performed by a protocol. It is a timing chart which shows the state of an actual transfer protocol. 1 is a block diagram illustrating an overall system configuration of an image processing apparatus according to an embodiment. FIG. 3 is a timing chart showing a comparison between the timing chart of transfer shown in FIG. 2 and the timing in the case of performing scrambling to replace the lower 4 bits of the AD signal and the C / BE signal with respect to the example of FIG. 2. It is a block diagram which shows the scramble processing apparatus which concerns on Example 1 which consists of a scramble part, a scramble release part, and CPU. It is a block diagram which shows the structure of the scramble processing apparatus which concerns on Example 2 using a key. It is a block diagram which shows the structure of the scramble processing apparatus which concerns on Example 3 which used the transfer signal output 1 cycle before as a key. It is a block diagram which shows the structure of the scramble processing apparatus which concerns on Example 4 with the mode which does not perform a scramble process.

Explanation of symbols

300 Image Processing Device 301 Image Reading Device 302 Image Processing Unit 303 First General Bus I / F
304 Scrambler 305 General purpose bus 306 Scramble release unit 307 Second general purpose bus I / F
308 Image control unit 309 Storage device 310 CPU
311 Image writing device

Claims (9)

First data processing means for processing data input from the data input means side;
Second data processing means for receiving the input data processed by the first data processing means via a general-purpose bus and processing it into desired data;
In a data processing apparatus that performs data processing by sending and receiving data to and from various functional devices via the general-purpose bus,
First and second general-purpose bus interfaces respectively provided in the general-purpose bus and the first and second data processing means;
A scramble processing unit provided between the first general-purpose bus interface and the general-purpose bus, and scrambles a transfer signal from the first data processing unit side to the second data processing unit side;
An image processing apparatus comprising: The data processing apparatus according to claim 1, wherein
A data processing apparatus, comprising: a descrambling unit provided between the general purpose bus and the second general purpose bus interface, for descrambling the scrambled transfer signal. The data processing device according to claim 1 or 2,
The scramble processing means performs scramble processing by exchanging bits of a transfer signal. The data processing device according to claim 1 or 2,
The scramble processing means has several patterns of means for exchanging bits of a transfer signal, and performs scramble processing with an arbitrary pattern by switching between users. The data processing device according to claim 1 or 2,
The scramble means performs scramble processing by EXORing a set scramble key. The data processing device according to claim 1 or 2,
The scramble means performs a scramble process by EXORing a scramble key that changes every cycle using the transfer signal output in the previous cycle as a scramble key. The data processing device according to claim 1 or 2,
A data processing apparatus comprising setting means for a user to set the presence or absence of a scramble process. The data processing device according to any one of claims 1 to 7,
A data processing apparatus, wherein the data is image data.   An image forming apparatus comprising the data processing apparatus according to claim 8.

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