JP2009044096A - Semiconductor apparatus and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the nonuniformity of the etching speed when a gap exists between an electrode and substrate to be processed composed of an insulator, in an etching device. <P>SOLUTION: A multilayer film composed of a conductive thin film and a base insulating film is formed on an entire surface of the substrate to be treated 1 comprised of the insulator. The conductive thin film and electrode of an etching device for carrying out patterning processing are on the same potential while they are being etched, so that a thin film transistor including a semiconductor layer 4 divided into an island on a base insulating layer 3, a gate insulating film 5, a gate electrode 6, an interlayer dielectric film 7 and source/drain electrodes are formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, a thin film transistor and a thin film electronic circuit using the thin film transistor can be used to form an electronic functional circuit on various substrates such as a glass substrate, and are already used as a part of a pixel switching element of a liquid crystal display device or a display signal driving circuit. It is used.

  FIG. 13 shows a configuration example of a conventional thin film transistor formed on a quartz substrate. The thin film transistor 100 is formed around a semiconductor layer 104 provided on an insulating quartz substrate 1. That is, the thin film transistor 100 includes a semiconductor layer 104, which is an element region separated into islands, a gate insulating film 105, a gate electrode 106, and an interlayer insulating film 7, and a semiconductor layer formed in a hole shape from the upper surface. A source / drain electrode 110 composed of a laminated film of a Ti film 108 and an aluminum film 109 reaching 104 is formed.

  These manufacturing processes are as follows: (1) Formation of a thin film (semiconductor film, insulating film, conductor film) to be an active element and modification and processing thereof (2) Thin film to be a passive element and inter-element wiring (conductor film, Insulating film) and processes related to modification and processing thereof, and there are many parts similar to the process of forming a large scale integrated circuit (LSI) on a semiconductor substrate such as Si. However, in a thin film transistor and a thin film electronic circuit using the thin film transistor, an amorphous Si thin film, a poly Si thin film formed on an arbitrary substrate, or a modification that improves the crystallinity of the film is formed on a semiconductor portion serving as an active element. A membrane is used. Therefore, if high performance and miniaturization of active elements and the like in thin film transistors and thin film electronic circuits have progressed to the same level as LSIs, it is possible to form various highly functional electronic circuits directly on substrates of various materials and dimensions such as large glass substrates. Have sex.

  In order to realize high performance and miniaturization in a thin film transistor, not only control of physical properties of various thin films constituting the element but also technology for processing the dimensions and shape of each thin film with high precision is indispensable. Taking an MOS transistor as an example of an active element, high-precision processing including cross-sectional shape control in processing a minute width of a gate electrode that is a conductor and processing a minute deep contact hole in an interlayer insulating film that is an insulator Technology is required.

  In response to these processing accuracy requirements, in precision processing of LSI on a Si substrate, as disclosed in Non-Patent Document 1 or Non-Patent Document 2, reactive ion etching (RIE), which is one of plasma processes. Technology is widely used.

In this RIE technique, ions and radicals formed in plasma simultaneously act on a thin film to perform physical and chemical etching processes. That is, this RIE technique enables anisotropic etching that can control the processing shape of the thin film, and the etching rate ratio (selection ratio) between the thin film that is to be processed and the underlying film that is desired to be processed under the thin film. There is a feature that can be increased. In recent years, various mass production apparatuses for realizing such a machining process have been developed.
"Basics of Microfabrication-Semiconductor Manufacturing Technology", Nikkan Kogyo Shimbun, 1993, P73-P83 “Basics of Silicon Micromachining” Springer Fairlark Tokyo, 2001, P297

  A thin film processing method using the RIE technique will be described with reference to FIG. 14A. FIG. 14A is a schematic cross-sectional view showing a state where the substrate to be processed 101 is etched by a reactive etching apparatus (RIE apparatus). As shown in FIG. 14A, the substrate to be processed 101 is directly mounted on the RF electrode 14 of the RIE apparatus during the etching process. In view of production efficiency, the RIE apparatus performs handling of a substrate to be processed by using an automatic transfer mechanism that can be mounted and collected at a processing position in a processing chamber. Therefore, as will be described later, the RF electrode 14 needs, for example, a protruding pin that moves up and down to automatically deliver the substrate 101 to be processed, and there is a gap portion 17 for the space of these components. Here, the gap portion is not only a gap necessary for the operation of the parts such as the protrusion pin, but also when the protrusion pin part is electrically insulated from the electrode as in most RIE apparatuses, Since the volume of the closed part does not function as an electrode, it is regarded as a gap. That is, the gap generated with respect to the protruding pin mechanism is simplified and shown in a rectangular cross section, and is illustrated as a gap 17 where it does not work effectively as a high-frequency electrode. Next, returning to FIG. 14A, the problem in the RIE process will be described using this figure and related figures.

  As is well known, in the RIE apparatus, the processing chamber 301 is filled with a process gas atmosphere, and then high frequency power is applied to the RF electrode 14 from the high frequency power source 19 through the blocking capacitor 18. Then, the bulk plasma region 12 and the sheath region 13 are generated in the processing chamber 301, and a self-bias potential Vdc that contributes to an improvement in the etching rate is generated. When the substrate 101 of the substrate to be processed 101 is an insulator such as a glass substrate or quartz, the self-bias potential related to this region in the substrate is reduced due to the capacity of the gap 17 existing in the RF electrode 14. As a result, when the film to be etched 203 is an insulator, the etching rate is slower for the insulator etching film of the substrate 101 in the upper region of the gap 17. 14A, reference numeral 16 denotes a patterned resist serving as an etching mask. In this cross-sectional view, there are 12 portions of the resist 16 covered, and 13 corresponding resist openings are shown. As for the six resist openings at the center above the inner space 17, the film to be etched of the insulator to-be-etched film 203 is small and the etching rate is reduced. In this way, an etching rate distribution corresponding to the gap 17 between the RF electrode 14 and the substrate is generated, which becomes an impediment to high-precision processing. It should be noted that this problem does not occur on the Si substrate, that is, the conductive substrate, as in the general LSI process. This is because, in a conductive substrate, if a part of the substrate surface is in contact with the electrode surface, the potential of the substrate is basically the same as the potential of the electrode anywhere in the entire substrate. Because it is good.

  In addition, even if the substrate 101 is an insulator, if the film to be etched is a conductor, the entire film to be etched can be obtained as long as the film to be etched covering the entire top surface of the substrate is covered at the initial stage of etching. Since the potential is the same, non-uniformity in the etching rate due to the gap portion 17 of the RF electrode 14 does not occur. However, since the etching progresses and the film to be etched is isolated in an island shape, the effect of bringing the entire film to be etched to the same potential by the film to be etched, which is a conductor, disappears and the etching rate becomes non-uniform. This phenomenon will be described in more detail when the etching target film 203 is a conductive gate electrode 106. FIG. 14B is a cross-sectional view showing a state in which the gate electrode 106 of the film to be etched is being etched by RIE on the substrate 101 which is an insulator. 14B is the same as FIG. 14A except that the film to be etched is an insulator in FIG. 14A, and the same reference numerals denote the same components. In FIG. 14B, since the conductive film to be etched covers the entire surface of the substrate at the initial stage of etching, the potential is the same in the substrate surface, and the in-plane distribution of the etching rate does not occur. FIG. 14C is a schematic cross-sectional view at a stage where the etching process further proceeds and the exposure of the base is about to start. In the plasma dry etching process including RIE, the etching rate tends to decrease as the size of the groove or hole to be etched becomes smaller and deeper. This is because the particle components having chemical species or kinetic energy involved in the etching reaction do not easily reach the bottom of the narrow and deep groove, and the product after the reaction is difficult to be removed. That is, as shown in FIG. 4C, the pattern portion that etches a wide area has a high etching rate, so the base is already exposed, but the thin groove portion has a low etching rate, but the film to be etched remains. This situation can easily occur. In such a case, the gate electrode films 106A and 106B, which are the films to be etched at the center, are separated from the surrounding gate electrode films 106C or 106D to form island-shaped films, and the regions above the island-shaped gaps 17 are formed. Vdc becomes lower than the peripheral portion, and the etching rate decreases. As a result, as shown in FIG. 14D, the gate electrode film 106A is formed in the central portion where the gap portion 17 exists between the substrate and the electrode even though the processing of the gate electrode is completed in the peripheral portion in the state where the etching processing is further advanced. , 106B still remains.

  Next, a supplementary explanation regarding the gap 17 in the RF electrode will be given.

For example, as shown in FIG. 15, the RF electrode 14 is provided with, for example, a protruding pin 202 that moves up and down as a lift mechanism for automatically delivering the substrate 101 to be processed.

  After the substrate to be processed 101 is moved above the protrusion pin 202 by the transport mechanism, the substrate to be processed 101 is transferred onto the protrusion pin 202 by protruding the protrusion pin 202 upward. Here, the transport mechanism is a generally well-known fork-like mechanism in which a substrate is mounted thereon, and the substrate is transported vertically and horizontally, and is not shown. Thereafter, the transport mechanism is retracted so as not to contact the ejection pin 202. Next, the protrusion pin 202 descends into the RF electrode 14 to place the substrate 101 to be processed at a predetermined position of the RF electrode 14 as shown in FIG.

  Next, when the etching process is completed and the substrate to be processed 101 is unloaded, the protrusion pin 202 moves upward from within the RF electrode 14 and lifts the substrate 101 to be processed from above the RF electrode 14. In this state, after the transport mechanism is moved below the substrate 101 to be processed, the ejection pin 202 is lowered, whereby the transport mechanism receives the substrate 101 to be processed from the ejection pin 202 and transports it to the next position (unloading). ).

  In order to load and unload the substrate 101 to be processed on the RF electrode 14 in this way, a hole having a diameter that allows the protrusion pin 202 to move is opened in the RF electrode 14. As shown, a protruding pin 202 is disposed inside the hole. In order to raise and lower the protruding pin 202 smoothly, a predetermined clearance (gap) is provided between the protruding pin 202 and the hole. The clearance is about several tens of μm and the area of the channel region is equivalent to several to dozens of thin film transistors having a size of about several μm square.

  Further, while the RIE process is being performed, adjustment is made so that the tip of the lowered protrusion pin 202 does not protrude from the upper surface of the RF electrode 14, but it is difficult to adjust the tip of the protrusion pin 202 and the electrode upper surface to be exactly the same. Furthermore, since the tip position may be displaced due to the accuracy of parts as it is repeatedly driven, it is necessary to adjust the bottom surface of the substrate 101 and the top surface of the protrusion 202 with a gap. Due to the mechanical limitations described above, there is a non-contact portion (gap) between the bottom surface of the substrate 101 to be processed and the RF electrode 14.

  Further, in most cases, the projecting pin is electrically insulated from the RF electrode. In this case, as a function of the RF electrode, the hole provided for the projecting pin 202 itself is the RF electrode 14. It becomes a space | gap (The space | gap 17 in FIG. 14A-FIG. 14D). In order to reduce this gap, even when the protruding pin 202 is electrically connected to the RF electrode by using a complicated mechanism, the gap corresponding to the clearance necessary for operating the protruding pin 202 as described above is the RF electrode. Will exist. As described above, when trying to process the thin film on the insulator substrate 1 with high accuracy using the conventional RIE technique, the gap 17 existing between the substrate 101 to be processed and the RF electrode 14 is affected. Thus, an etching rate distribution is generated in the surface to be processed of the substrate 101 to be processed, which is an impediment to highly accurate etching processing.

  Therefore, the present invention provides a semiconductor device capable of uniformly and highly accurately processing a thin film on an insulating substrate even when a gap exists in an electrode of the plasma processing apparatus, and a method for manufacturing the same. Objective.

In order to achieve the above object, a plurality of transistor elements each including a semiconductor layer, a gate insulating film layer, a gate electrode, a source electrode, and a drain electrode are provided on one main surface of an insulating substrate. A thin film transistor, comprising: a laminated film formed of an insulating film layer in contact with the semiconductor layer and interposed between the transistor elements on the insulating substrate and a conductive thin film in contact with the insulating substrate A thin film transistor is provided.

  A step of forming a conductive thin film on the entire surface of one main surface of the substrate to be processed made of an insulator; a step of forming a base insulating layer for element region separation on the conductive thin film; Forming a thin film transistor element on the base insulating layer by plasma treatment including etching, and electrically connecting the conductive thin film to an electrode for generating the plasma under the plasma treatment. Provided is a method for manufacturing a thin film transistor in which the potential of the conductive thin film is the same as that of the electrode for generating plasma and a uniform potential.

  According to the present invention, even if there is a gap between the upper surface of the electrode of the RIE apparatus and the bottom surface of the substrate, the Vdc in the substrate surface during the RIE process is made uniform, and the in-plane uniformity of the etching rate is improved. The upper thin film can be processed with high accuracy by RIE processing, and a high-definition and high-quality thin film transistor and a method for manufacturing the same can be provided.

  Furthermore, in the present invention, a conductor thin film is formed on the surface of the insulator substrate on the side where the thin film transistor is formed. When the conductor thin film is configured to have the same potential as the electrode, the thickness of the insulator substrate is reduced. Variation in the etching rate due to variation can be eliminated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In the first embodiment, a conductive thin film is provided on an insulating substrate, an insulating layer is provided on the conductive thin film, a plurality of semiconductor thin films are formed in an island shape on the insulating layer, an insulating layer, A semiconductor device in which a wiring layer is formed and processed into a thin film transistor. This embodiment will be specifically described with reference to FIGS. FIG. 1 is a cross-sectional view for enlarging and explaining one of a plurality of thin film transistors formed on a substrate made of an insulator, and a cross-sectional structure of a thin film transistor (TFT) according to a first embodiment of the present invention. Indicates. The thin film transistor 50 includes a laminated substrate comprising a substrate made of an insulator, for example, a quartz substrate 1, a conductive thin film 2 provided on one surface of the quartz substrate 1, and a base insulating layer 3 provided on the conductive thin film 2. Formed on top of structure 51.

The thin film transistor 50 includes a semiconductor layer 4 separated in an island shape on a base insulating layer 3, a gate insulating film 5 such as a SiO ₂ film, a gate electrode 6 such as a MoW alloy, an interlayer insulating film 7 such as a SiO ₂ film, and the like. The upper wiring layers of the source electrode 10 and the drain electrode 11 disposed on the upper layer are laminated and formed.

  Here, as in the prior art, a part of the predetermined positions matching the source / drain regions of the interlayer insulating film 7 and the gate insulating film 5 is plasma etched into a hole shape to expose the semiconductor layer 4. A contact hole is formed. The contact hole is filled with a source electrode 10 and a drain electrode 11 made of a laminated film of a Ti barrier metal 8 and aluminum (containing 1.5% Si) 9, and the semiconductor layer 4 and the upper wiring layer are electrically connected. It has become.

  A feature of this embodiment is that an insulating layer 3 for electrically separating the conductive thin film 2 and the thin film transistor 50 is provided on the substrate 1 side where the thin film transistor 50 is provided. Among these, the effect of the insulating layer 3 is that the semiconductor layer 4 is not electrically short-circuited with other semiconductor layers (not shown in FIG. 2) forming other thin film transistors even when the conductive thin film 2 is provided. This is so-called element isolation. On the other hand, the effect of the conductive thin film 2 is as described below. The conductive thin film 2 is particularly effective in improving the processing dimensional accuracy of the gate electrode 6 in the thin film transistor 50 of FIG. The operation and effect will be described with reference to a configuration example of the RIE apparatus used for processing the gate electrode 6 shown in FIG.

  In FIG. 2, the same components as those in FIG. 14A described above are denoted by the same reference numerals, and the description thereof is omitted. However, as described in FIG. A sheath region 13 and a bulk plasma 12 are formed. In FIG. 2, the conductive thin film 2, the base insulating layer 3, the MoW film 6, and the resist mask 16 are illustrated on the surface of the insulating substrate 1 as the configuration of the substrate 101 to be processed. Other films such as the semiconductor thin film 4 shown in FIG. 1 are not directly involved in the function and effect described here, and are omitted in FIG. 2 to avoid complexity. The pattern of the resist mask 16 is modeled for explanation and is different from the actually used pattern. In addition, a gap 17 necessary for the substrate transport mechanism having a diameter of 40 mm and a depth of about 10 mm exists at the center of the RF electrode 14 on which the substrate 101 to be processed of the present embodiment is placed.

  When the RIE process is performed in this manner, even if there is a lifter pin mechanism installation recess, that is, a gap portion 17 for handling the substrate to be processed, for example, at the center of the RF electrode 14, a conductive thin film is formed on the substrate to be processed. 2 is provided, a uniform electric field is formed on the surface of the substrate to be processed, and etching is performed uniformly. That is, it is possible to avoid the problem that the etching rate of the region of the substrate to be processed facing the recess 17 of the RF electrode 14 is delayed.

  Next, referring to the manufacturing process diagram of the thin film transistor shown in FIGS. 3A to 3E and FIGS. 4A and 4B and the manufacturing process flow chart shown in steps S1 to S15 in FIG. An embodiment of a manufacturing process of the thin film transistor shown in FIG. In the present embodiment, an example in which circuit elements are formed on a quartz substrate having a diameter of 150 mm and a thickness of t0.625 mm will be described as an example of an insulator substrate.

  First, as shown in FIG. 3A, a conductive thin film 2 is formed on one surface of a substrate 1 made of an insulator (in this embodiment, a quartz substrate) using a sputtering apparatus [FIG. 5: Step S1. , S2 step]. Of course, other film forming methods may be used, for example, a CVD method or a vapor deposition method. Although the specification of the conductive thin film 2 at this time will be described later, in this embodiment, a film of MoW (W: 30 atm%) having a thickness of 200 nm is used.

Next, as shown in FIG. 3B, the base insulating layer 3, for example, a SiO ₂ film having a thickness of about 1 μm is formed on the upper surface of the conductive thin film 2 by the CVD method [FIG. 5: Step S 3 step ]. Next, an a-Si film (amorphous silicon thin film) to be the semiconductor thin film 4 is formed on the upper surfaces of the base insulating layer 3 and the conductive thin film 2 by a CVD method [FIG. 5: Step S4]. Then, if necessary, the a-Si thin film is crystallized using a heat treatment, for example, a laser irradiation method [FIG. 5: Step S5], and electrically as shown in FIG. 3C by photolithography etching. An island of the divided semiconductor thin film 4 is formed [FIG. 5: Step S6]. In FIG. 3C, an island of one semiconductor thin film 4 is shown as a representative of a plurality of islands. Further, a polysilicon thin film may be used as the semiconductor thin film 4 instead of the a-Si thin film.

  Next, as shown in FIG. 3D, a gate insulating film 5 having a thickness of 30 nm is formed on the surfaces of the conductive thin film 2, the base insulating layer 3, and the semiconductor thin film 4 on the substrate 1 by the CVD method [FIG. 5: Step S7 step]. At this time, the thickness of the gate insulating film 5 formed on the semiconductor thin film 4 is measured at a critical portion within the substrate surface described later. The thickness of the gate insulating film 4 can be measured nondestructively with a spectroscopic ellipsometer. This state is shown in FIG.

  Next, a MoW film 60 having a film thickness of, for example, 200 nm is formed as shown in FIG. 3E by sputtering to form a gate electrode [FIG. 5: Step S8 step]. A process of processing the MoW film 60 into a gate electrode pattern will be described with reference to FIGS. As shown in FIG. 4A, after a resist mask 16 for forming a gate pattern is formed on the MoW film 60 by a photolithography process, an etching process is performed by the RIE method described above [FIG. 5: Step S9]. Process]. For the etching, a magnetron type microwave plasma etching apparatus that can apply an RF output to the electrode and can also introduce a microwave to improve the plasma density was used. In the etching process by the RIE method, as shown in FIG. 4A, the substrate pressing member 31 suppresses the MoW film 60 at the edge of the substrate from above. In the present embodiment, the substrate pressing member 31 includes a terminal plate 31B that is electrically connected to the structural portion 31A and the electrode 14. As a result, the terminal plate 31B is electrically connected to the conductive thin film 2 through the MoW film 60, so that the conductive thin film 2 has substantially the same potential as the electrode 14. The substrate pressing member 31 also has a function for bringing the substrate 1 into close contact with the temperature-adjusted RF electrode and clamping it.

  4 (a) and 4 (b), 32 is. It is a gate film remaining detection terminal, and the MoW film 60 and the tip are in contact with each other. The gate film remaining detection terminals 32 are provided at a plurality of substrate end portions of the substrate, and detect and judge the progress of etching due to the increase in resistance. For example, it may be provided at four locations every 1 / 2π (rad). It is determined that the etching has progressed due to the increase in resistance between these gate film remaining detection terminals 32 and the film thickness has decreased. The etching conditions are changed when it is determined that the gate film is almost gone. That is, the anisotropic etching and the highly selective etching are made compatible by changing from the RIE of the anisotropic etching to a chemical etching condition having a low RF power and therefore a low Vdc and a good selectivity. The remaining gate detection mechanism using the remaining gate film detection terminal 32 is for uniformizing Vdc in the substrate surface during the RIE process, which is the effect of the present invention, and improving in-plane uniformity of the etching rate. It is not intended to improve the selectivity in the RIE process. Therefore, the results were compared using the conditions of both the embodiment in which the gate film remaining detection terminal 32 is not used and the embodiment in which the gate film remaining detection terminal 32 is used as the etching process. Specifically, the MoW film 60 was etched under the etching conditions shown in FIG. FIG. 6 also shows etching conditions in a comparative example described later.

  When the etching process is completed, the MoW film 60 is processed into the gate electrode 6 as shown in FIG. Thereafter, the resist mask 16 is removed using a resist ashing apparatus. Here, in order to evaluate the selectivity in this etching process, the film thickness of the gate insulating film 5 at the same place as that measured before the etching is measured by a spectroscopic ellipsometer. With this measurement, the gate insulating film corresponding to the base in the etching process of the MoW film 60 can be evaluated for film slip, and the etching selectivity can be evaluated.

Next, P ⁺ ions are implanted by ion implantation using the MoW film 6 as a mask to form the source region 4S and the drain region 4D in the semiconductor thin film 4 as shown in FIG. 1 [Step in FIG. 5: Step S10]. Next, an interlayer insulating film 7 made of a SiO ₂ film is formed by using the CVD method [FIG. 5: Step S11 step]. Further, after the crystallinity of the semiconductor layers 4S and 4D damaged by the previous ion implantation process or the like is recovered by annealing, holes are formed at predetermined positions on the interlayer insulating film 7 by photolithography etching. Then, a part of the source region 4S and the drain region 4D of the semiconductor thin film 4 is exposed [FIG. 5: Step S12 step].

  Thereafter, in order to form source and drain electrodes, a conductive film, for example, a laminated film of a Ti film 8 and an aluminum film 9 (containing 1.5% Si) is formed [FIG. 5: Step S13]. Finally, the source electrode 10 and the drain electrode 11 are formed by photolithography etching as shown in FIG. 1 [FIG. 5: Step S14]. Thereafter, transistor characteristics are measured [FIG. 5: Step S15].

  FIG. 7 is a plan view of the substrate 1 used in this embodiment. Areas with symbols B1, C1, etc. correspond to an exposure area of about 20 mm □ per photomask. That is, the above-described thin film transistor 50 having the same design dimensions (the thin film layer pattern exposed with the same photomask) is replaced with A2-A5, B1-B6, C1-C6, D1-D6, E1-E6. It can be made for each block (32 blocks in total) indicated by F2 to F5. Therefore, if the physical properties and film thickness of each thin film forming the thin film transistor are uniform in the plane of the substrate 1 and the processing dimensions and processing shape in patterning of each thin film are also uniform in the plane, 32 sets of the same characteristics A transistor can be obtained. In the following characteristic evaluation, whether the uniformity of the characteristics in the substrate surface is achieved by comparing the characteristics of the thin film transistor formed in the D3 region corresponding to the central portion of the substrate and the thin film transistor formed in the A4 region corresponding to the end portion of the substrate. To verify.

FIG. 8 shows the characteristics of the thin film transistor formed by performing the etching process according to the etching conditions of the gate electrodes of Examples 1 to 4 and Comparative Examples 1 to 3 shown in FIG. Examples according to this embodiment are Examples 1 to 4, and those according to the prior art are Comparative Examples 1 to 3. Comparative Examples 1 to 3 are thin film transistors having the structure shown in FIG. 12, and differ from the thin film transistor of this embodiment shown in FIG. 1 in that there is no conductive thin film 2 and base insulating layer 3. In each example and each comparative example, the gate length and gate width of the TFT have the same specifications as 1 μm and 5 μm, respectively. Further, except for the fourth embodiment, the same process conditions as the gate electrode etching process conditions are used. Only in Example 4, as shown in FIG. 6, the etching of the gate electrode is performed under the condition of 2 STEP using the gate remaining detection mechanism.
As shown in FIG. 7, in the comparison between the D3 block and the A4 block in the OFF current of the transistor, in Examples 1 to 4, good results with substantially the same characteristics and little variation were obtained. On the other hand, the OFF current values of the transistors in the D3 region of Comparative Examples 1 to 3 were two to three orders of magnitude higher than those of Examples 1 to 4, and a clear deterioration in characteristics was observed. In addition, regarding the ON current, each example and each comparative example show generally good values.

In the RIE process at the end of the processing of the gate electrode film in Comparative Example 1, as shown in FIG. 14D, the lift pin electrode gap 17 exists between the RF electrode 14 facing the central portion of the substrate 101 (used). Since the gap in the electrode of the RIE apparatus has a size of 40 mmΦ at the center of the electrode, the area D3 block is affected by this gap), and the contribution of ion bombardment in the RIE etching is reduced on the substrate surface in the center so that the etching speed is Slowly, the ability to remove etching residues is decreasing. As a result, in the thin film transistor in the block D3 at the center of the substrate 1, the W residue of the conductor remains on the SiO ₂ surface of the gate insulating film 5 after processing the gate electrode 6 (MoW film 60), which leads to an increase in OFF current. Estimated.

  On the other hand, in the RIE process of Example 1, the same potential is applied over the entire surface of the substrate 1 by the action of the conductive thin film 2 provided on the substrate 1 shown in FIG. It is presumed that the equivalent ion bombardment effect of the same level worked and no etching residue remained. As described above, in Examples 1 to 4, good transistor characteristic values were obtained with little variation in the surface of the insulating substrate 1.

  Next, the result of film removal of the gate insulating film 5 after etching the gate electrode 6 (FIG. 4B) will be described. Regarding the thin film transistors in the regions D3 and A4 in the substrate surface, the thickness of the gate insulating film 5 at a position about 0.1 μm away from the end of the gate electrode is measured before and after the gate electrode etching process as described above, and the amount of film slippage Asked. The results are shown in FIG. As this value is smaller, the etching process can be performed without affecting the base, that is, with good selectivity.

As can be seen from the amount of film slippage of the gate oxide film shown in FIG. 9, it can be seen that Example 4 uses a gate film remaining detection mechanism to reduce the amount of film slip and provide good selectivity.
In the fourth embodiment, the gate film remaining detection terminal 32 is used to detect the time when the MoW film 60 (the film that becomes the gate electrode 6) is etched, and the conditions up to that point are 1st STEP of a general RIE condition, Since the subsequent conditions are set to 2nd STEP corresponding to chemical plasma etching with the RF power cut off, the selectivity is improved.

  Summarizing the results thus far, the thin film transistor according to the present embodiment improves the uniformity of characteristics in the substrate surface as is clear from the transistor characteristic results of Examples 1 to 4 and Comparative Examples 1 to 3 (FIG. 8). There is an effect, and as shown in the evaluation results of Example 4, it is possible to simultaneously achieve improvement in selectivity.

  As described above, in the gate electrode processing, the reduction in variation in the characteristics in the substrate surface also leads to an improvement in process accuracy in an ion implantation process or the like in a later manufacturing process, thereby improving TFT characteristics and reliability. A big contribution.

  In Example 4, the method of measuring the resistance of the in-plane gate electrode film was used for detecting the end point of etching. However, the method is not limited to this method, and detection is performed by a change in emission spectrum in plasma that is generally used. Needless to say, a method and a general method for detecting a plasma state change by measuring a potential in a plasma and an effective load voltage can be used. In this embodiment, P + ions are ion-implanted into the semiconductor thin film layer 4 to form source / drain regions to obtain an n-MOS thin film transistor. Of course, for example, B + ions are used instead of P + ions. If ordered, a p-MOS thin film transistor can be constructed.

Next, a second embodiment will be described with reference to FIGS. 10A, 10B and FIG.
10A, 10B, and FIG. 11, the same reference numerals are assigned to the same components as those described in the first embodiment, and the detailed description thereof is omitted.
In the second embodiment, in the first embodiment described above, a mechanism relating to a gate film remaining detection terminal that may cause a device complexity can be omitted.

  A manufacturing flow chart of the second embodiment is shown in FIG. This flowchart shows the conductive film patterning process [FIG. 11: Step S22] and the gate insulating film after the conductive film deposition process [FIG. 11: Step S22] in the flowchart shown in FIG. 5 of the first embodiment. This is a manufacturing process in which two processes of a through-hole forming process [FIG. 11: Step S29] are added after the film forming process [FIG. 11: Step S28].

FIGS. 10A and 10B are cross-sectional views for explaining the main points of the manufacturing process of the second embodiment, and FIG. 10B (g) is a plan view of FIG. 10B (f). It is.
FIG. 10A (a) shows a cross-sectional view after the gate insulating film is formed in the manufacturing process flowchart shown in FIG. 10 (g) showing the second embodiment. At the end of the substrate, no film is formed by the clamp ring when forming the gate insulating film. FIG. 10B (g) is a cross-sectional view that is apparently the same as FIG. 4D of the first embodiment. However, since the conductive thin film patterning step shown in step S23 of FIG. 11 in the flowchart is performed, the conductive thin film 2 is different in that planar patterning is performed.

  That is, after forming the conductive thin film 2 on the insulating substrate 1, the conductive thin film 2 is formed by photolithography etching only in a predetermined necessary region, for example, a region below each TFT formation region. ing.

  Next, the insulating film 3 is formed on the exposed surface of the conductive thin film 2 and the surface of the glass substrate 1. The peripheral edge of the insulating film 3 is selectively etched. A semiconductor thin film 4 is formed on the insulating film 3. A plurality of island-like semiconductor thin films 4 are formed by selectively etching the semiconductor thin film 4 with a pattern in which a predetermined necessary portion remains, for example, a pattern in which the semiconductor thin film 4 is formed in each TFT formation region.

  Next, as shown in FIG. 10A (b), a through hole 20 is formed by photolithography etching up to the surface of the insulating substrate 1. Even if the through hole 20 does not reach the surface of the insulating substrate 1, it is sufficient if the through hole 20 is opened until the conductive thin film 2 is exposed. The through hole 20 is formed at a position that does not overlap with the gate electrode pattern formed in a later step. Next, a MoW film 6 for a gate electrode film is formed on the insulating film 5 (FIG. 10A (c)).

The MoW film 60 is also filled in the through hole 20 and needs to be electrically joined to the conductive thin film 2. In other words, the dimension of the through hole 20 (the diameter in the case of a circular through hole) is set to a size sufficient for the MoW film 6 to be formed up to the bottom surface of the through hole 20 (in a normal sputtering film formation). 2 μm or more is sufficient). As described above (FIG. 10A (c)), the MoW film 6 and the lower patterned conductive thin film 2 become conductive.

Next, a resist mask 21 for forming a gate electrode pattern is formed, and a substrate to be processed 101 for performing an RIE process is formed (FIG. 10A (d)). The substrate 101 to be processed is handled in the plasma etching apparatus, and is placed at a predetermined position of the RF electrode 14 (FIG. 10B (e)). The MoW film 6 is plasma-etched using the mask 21 as a mask (FIG. 10B (f)). This plasma etching starts with the conductive thin film 2 set to the same potential as the RF electrode 14 by bringing the RF electrode terminal / substrate holding member 31 into contact with the MoW film 6. As a result, the plasma etching can be performed uniformly over the entire surface even when lift pin holes are present on the surface of the RF electrode 14 by the action of the conductive thin film 2 as in the first embodiment.

Furthermore, in this embodiment, in a state where the etching has progressed and the MoW film 6 at the bottom of the through hole 20 not covered with the resist mask 21 has disappeared (FIG. 10A (f)), the plan view of the substrate is shown in FIG. The patterning of each thin film is designed to be as shown in g). The X-X ′ cross section in FIG. 10B (g) corresponds to FIG. If the etching is continued in the state of FIG. 10B (f), the portion on the left side in the drawing, that is, the TFT formation portion is not electrically connected to the RF electrode by the through hole 20 of FIG. 10B (f). Vdc is lowered, and an etching state with high selectivity is obtained.

  More specifically, the effect of the through hole 20 will be described. At the start of the etching of the MoW film 6, as shown in FIG. 10B (e), the regions of these patterned conductive thin films are not covered with resist. The film 6 conducts at the position of the through hole 20. Accordingly, in the RIE process of the MoW film 6, when the MoW film 6 still remains in the portion covered with the resist mask, the region to be the gate electrode pattern is electrically connected to the RF electrode below it. Due to the presence of the conductive patterned conductive thin film 2, high Vdc is applied and anisotropic etching is realized.

  When this plasma etching process proceeds and the MoW film 6 filled in the through hole 20 disappears, the patterned conductive thin film 2 under the gate electrode pattern region to be the gate electrode pattern is formed on the insulating substrate 1. Since it is isolated, the Vdc in that region decreases.

Therefore, since the etching with a high selectivity is realized, even if the over-etching time is extended, the film insulation of the gate insulating film 5 is suppressed. By providing the through hole 20 in the vicinity of the gate electrode pattern, switching from the RIE condition to the highly selective etching is automatically and accurately performed even when the etching rate in the substrate 1 and the film thickness of the MoW film 6 vary greatly. . In this embodiment, a residue film containing W may be formed on the surface of the substrate 1 after etching. At that time, the residue film is treated with a residue treatment solution (for example, using an aqueous alkali tetraethoxyhydroxide ammonium solution). Went.
A gate electrode is formed as described above. The source / drain region forming step in the next step is the same as that in the first embodiment, and a description thereof will be omitted because it is redundant.

  Using the second embodiment, a thin film transistor was manufactured under the same conditions as the gate electrode etching conditions (the conditions of Examples 1 to 3 in FIG. 6) without the gate film remaining detection mechanism employed in the first embodiment. As a result, the film thickness of the gate oxide film in the D3 region was about 0.2 nm, and a good value equivalent to that in Example 4 implemented using the gate remaining detection mechanism was obtained. In addition, the TFT characteristics were as good as those of Examples 1 to 4 in FIG.

  In both the first embodiment and the second embodiment, the conductive thin film 2 is electrically connected to the electrode when placed on the RF electrode of the RIE apparatus. Therefore, even if the thickness of the insulating substrate 1 varies, the potential on the surface of the substrate becomes almost the same as the potential of the RF electrode 14, so that thin film transistors having uniform characteristics are formed even on substrates having different thicknesses. be able to. Further, as a means for electrically connecting the conductive thin film 2 and the RF electrode 14, the substrate pressing member 31 having the terminal plate 31B is used, but as shown in the modification of FIG. 12A, the conductive thin film 2 is insulated. The film may be formed so as to extend to the back surface of the conductive substrate 1.

Next, a third embodiment will be described.
The present embodiment is similar to the first embodiment in which the present invention is implemented without a gate film remaining detection mechanism, but the conductive thin film 2 is formed on the back surface of the insulating substrate 1.
FIG. 12B shows a cross-sectional structure of the thin film transistor according to the third embodiment. In the constituent members of the present embodiment, the same reference numerals are assigned to the same constituent members as those of the above-described first embodiment, and detailed description thereof is omitted.

  The thin film transistor of the present embodiment has a configuration in which the conductive thin film 2 is formed on the main surface (non-circuit element forming surface) on which the circuit element is not formed on the insulating substrate 1, that is, the back surface side. The configuration of the present embodiment is formed for element isolation between the conductive thin film 2 and the thin film transistor as compared with the first embodiment described above, but the base insulating layer 3 is unnecessary. The conductive thin film 2 may be formed as it is after the circuit element is formed, or may be deleted by etching the back surface of the insulating substrate 1.

  In this embodiment, in addition to the effects of the first embodiment described above, the manufacturing process for forming the base insulating layer can be omitted. However, in the present embodiment, when the thickness of the insulating substrate 1 varies, Vdc varies between the substrates. Therefore, it is desirable to apply when the variation of the substrate thickness between the substrates is small. In the first and second embodiments, the substrate pressing member 31 having the terminal plate 31B is used, but this can be said similarly when the substrate pressing member 31 without the terminal plate 31B is used instead. is there. That is, in the first and second embodiments of the present invention, even if the conductive thin film 2 is not electrically connected to the electrode 14, it has a constant potential through the insulating substrate 1, so that the uniformity of Vdc in the substrate surface is ensured. It is obvious that the effect of the present invention is manifested. However, if the substrate plate thickness varies, the potential of the conductive thin film 2 during RIE varies accordingly. Therefore, it is desirable to use the substrate pressing member 31 without the terminal plate 31B in the first and second embodiments when the variation between the substrates is small.

  The embodiments of the present invention have been described above. However, the embodiments of the present invention are not limited to the above-described embodiments, and have an LDD structure, a C-MOS structure, and the like other than the above-described thin film transistors. Needless to say, it can also be applied to more complex and high-performance thin film transistors. In order to improve the characteristics of the thin film transistor, it is necessary to realize finer processing with high accuracy. Therefore, the present invention exhibits a greater effect as the semiconductor crystallization technology, the wiring technology, etc. in the thin film transistor progress.

The conductive thin film formed on the insulating substrate which is the most important element of the present invention is not limited to the material specified in the embodiment. The conductive film that can be used in the present invention will be described. The conductive film can be any conductive metal, semiconductor, or compound from the viewpoint of having the same potential as the electrode, but the end contact part and the center of the substrate determined by its specific resistance, shape, and film thickness. When the resistance value of the film between the parts is very high, a high-frequency delay or the like occurs, which may adversely affect plasma generation. When the relationship between the approximate delay amount of the high frequency signal and the film resistance is obtained, in the case of the high frequency of 2 MHz in the present embodiment, there is no problem even if the MoW film has a film thickness of 1 nm or less in calculation. Further, it can be confirmed that 10 nm or more is sufficient even for a conductive thin film having a high specific resistance. When the conductive film is 200 nm, a material having a specific resistance of 5 × 10 ⁵ μΩ · cm or less can be generally used.

  In addition, the conductive thin film in each embodiment does not necessarily have to be formed on the entire surface of the substrate. As described in the second embodiment, a uniform Vdc can be obtained in a range where high-precision processing of a thin film transistor is required, that is, in the RIE process. An effect can be acquired by forming in this required range. As in the second embodiment, the range may be a continuous film in the substrate covering the area corresponding to the pattern area of the film to be processed, and the details of the area design value are determined experimentally. You can also. Further, such partial formation of the conductive thin film can avoid impairing the transparency of a portion where the substrate is required to be transparent, such as a pixel portion of a liquid crystal display. However, at that time, it is obvious that it is necessary to have a structure in which the corresponding conductive thin films are electrically joined with respect to the transistor elements for which uniformity of characteristics is desired.

  In the future, in order to improve the characteristics of thin film transistors, it is necessary to realize finer processing with high precision, and to reduce the restrictions on the manufacturing equipment as much as possible in order to increase the mass productivity and supply the thin film transistor circuit devices at a low cost. It is also necessary. The present invention can be applied to all thin film transistors manufactured using a general RIE apparatus, and can meet these requirements. It is also obvious that the present invention can be used not only for thin-film semiconductors but also for all devices that perform microfabrication using a plasma process on an insulating substrate.

1 is a diagram illustrating a cross-sectional structure of a thin film transistor (TFT) according to a first embodiment. It is a figure which shows notionally the state of the board | substrate with which the thin-film transistor of 1st Embodiment was mounted | worn with the RF electrode of the RIE apparatus, and was etched. 3A to 3E are views for explaining a manufacturing process of the thin film transistor according to the first embodiment. 4A and 4B are views showing a cross-sectional configuration in the manufacturing process of the thin film transistor, following FIGS. 3A to 3E. It is a flowchart which shows the manufacturing process of the thin-film transistor in 1st Embodiment. It is a figure which shows the form of the RIE etching conditions in the Example by this embodiment, and a comparative example. It is a figure which shows the example of arrangement | positioning of the thin-film transistor formed on the board | substrate. It is a figure which shows the characteristic result of the thin-film transistor formed by this embodiment and the prior art. It is a figure which shows the base film sliding evaluation result in the Example by this embodiment, and a comparative example. It is a figure which shows the cross-section in the manufacturing process of the thin-film transistor which concerns on 2nd Embodiment. It is a figure which shows the cross-section in the manufacturing process of the thin-film transistor which concerns on 2nd Embodiment, and a top view. It is a flowchart which shows the manufacturing process of the thin-film transistor in 2nd Embodiment. It is a figure which shows notionally the state of the board | substrate with which the RF electrode of the RIE apparatus in the modification is mounted | worn and etched. It is a figure which shows the cross-section of the thin-film transistor which concerns on 3rd Embodiment. It is a figure which shows the structural example of the thin-film transistor formed on the conventional board | substrate. It is a figure which shows notionally the state by which the board | substrate was mounted | worn with the RF electrode and the thin film of the insulator was etched in the process by the RIE apparatus of the conventional thin film transistor. It is a figure which shows notionally the state (etching initial state) in which the board | substrate was mounted | worn with the RF electrode and the conductive thin film was etched in the process by the conventional RIE apparatus of a thin-film transistor. It is a figure which shows notionally the state (etching middle stage state) in which the board | substrate was mounted | worn with the RF electrode and the conductive thin film was etched in the process by the conventional RIE apparatus of a thin-film transistor. It is a figure which shows notionally the state (etching final state) in which the board | substrate was mounted | worn with the RF electrode and the electroconductive thin film was etched in the process by the RIE apparatus of the conventional thin film transistor. It is sectional drawing for demonstrating the gap | interval which generate | occur | produces in RF electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Quartz substrate (substrate), 2 ... Conductive thin film, 3 ... Base insulating layer, 4 ... Semiconductor layer, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... Interlayer insulating film, 8 ... Ti film, 9 ... Aluminum Membrane, 10 ... source electrode, 11 ... drain electrode.

Claims (7)

A thin film transistor in which a plurality of transistor elements including a semiconductor layer, a gate insulating film layer, a gate electrode, a source electrode, and a drain electrode are provided on one main surface of an insulating substrate,
An insulating film layer interposed between the transistor element on the insulating substrate and in contact with the semiconductor layer side;
A thin film transistor comprising a laminated film including a conductive thin film in contact with the insulating substrate side. In the thin film transistor,
2. The thin film transistor according to claim 1, wherein a second conductive thin film connected to the conductive thin film and extending to the other main surface of the insulating substrate is provided at least when the transistor element is formed. A thin film transistor in which a plurality of transistor elements including a semiconductor layer, a gate insulating film layer, a gate electrode, a source electrode, and a drain electrode are provided on one main surface of an insulating substrate,
A thin film transistor comprising: a conductive thin film provided at least when the transistor element is formed on the other main surface of the insulating substrate. In the thin film transistor,
The conductive thin film is electrically connected to an electrode for holding the substrate to be processed and generating plasma when exposed to plasma under plasma treatment on the substrate to be processed, and on the surface of the insulating substrate. 4. The thin film transistor according to claim 1, wherein the applied potential is made uniform.   The electrode for generating the plasma is a plasma etching to which a high-frequency power is applied in a reactive ion etching apparatus in which a gap exists between a part of the electrode surface and a contact surface of the mounted substrate to be processed. The thin film transistor according to any one of claims 1 to 3, wherein the thin film transistor is one of electrodes. Forming a conductive thin film on one main surface of a substrate to be processed made of an insulator;
Forming a base insulating layer for element region isolation on the conductive thin film;
Forming a thin film transistor element on the base insulating layer by plasma treatment including etching,
Under the plasma treatment, the conductive thin film is electrically connected to the electrode that generates the plasma, and the potential of the conductive thin film is set to the same potential as the negative electrode that generates the plasma, and to a uniform potential. A method of manufacturing a thin film transistor, comprising: A conductive thin film formed on one main surface of the substrate to be processed through a contact hole formed in a part of the gate electrode film in a region to be etched in processing of the gate electrode film in the base insulating layer for element isolation; By electrical connection,
7. The method of manufacturing a thin film transistor according to claim 6, wherein the etching is performed with the potential of the gate electrode film in the etched region being the same as that of the conductive thin film.

Images