JP2009038704A - Imaging data recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep flexibility of a system without increasing a load of a CPU when coded video and audio data are recorded in the form of a transport stream, to reduce the scale of a circuit, to reduce power consumption, and to reduce cost. <P>SOLUTION: Control of the amounts of codes in a video coding circuit 13 and an audio coding circuit 16 is executed by code amount control signals S11 and S12 based on the control of a CPU 11. A recording process in a medium recording part 21 is executed based on the control of the CPU 11. In contrast, processes from the video coding circuit 13 to a multiplication circuit 19, and from the audio coding circuit 16 to the multiplication circuit 19 such as a scheduling process in a transport stream multiplication schedule circuit 18, a generation process of a transport stream in the multiplication circuit 19 are executed without using the CPU 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a photographing data recording apparatus that generates a transport stream of an MPEG2 system from a video stream or an audio stream.

  In recent years, when recording a moving image with a digital camera or camcorder, for example, it is necessary to encode video data and audio data in consideration of consistency with other video devices and store them in the MPEG2 system transport stream format. There are many requests.

  Here, MPEG2 (Moving Picture Experts Group Phase2) is one of video data compression methods and forms part of the MPEG standard. The MPEG2 system multiplexes video data compressed by the MPEG2 method and the like. The transport stream is used as one of the formats of the MPEG2 system.

  In addition, the transport stream of the MPEG2 system uses a 188-byte fixed-length TS packet including a 4-byte header and a 184-byte payload (including a variable-length adaptation field), Audio data is multiplexed and sent in a transport stream. Such a transport stream of the MPEG2 system is described in, for example, Patent Documents 1 to 3.

  FIG. 3 shows an example of a conventional camcorder that encodes video data and audio data, multiplexes them in the form of a transport stream, and records them on a memory card.

  As shown in FIG. 3, such a conventional camcorder includes a CPU (Central Processing Unit) 211, an input video data buffer 212, a video encoding circuit 213, an encoded video data buffer 214, and an input audio data buffer. 215, an audio encoding circuit 216, an encoded audio data buffer 217, a multiplexing circuit 219, a FIFO (First-In First-Out) memory 220, and a medium recording unit 221. A memory card (for example, an SD card) 222 is attached to the medium recording unit 221.

  The video encoding circuit 213 reads out the image data from the input video data buffer 121 with the encoding start command from the CPU 211 as a trigger, and encodes it, for example, in the MPEG2 system. The code amount of the video data is controlled by a code amount control signal S211 from the CPU 211. Then, the encoded video data V211 is sent to the encoded video data buffer 214. When the encoding is completed, the video encoding circuit 213 notifies the CPU 211 of an encoding completion notification S221. At that time, the encoded data size (encoded bit amount), picture type, and decoding time stamp are also notified.

  The audio encoding circuit 216 reads audio data from the input audio data buffer 215 using an encoding start command from the CPU 211 as a trigger, and encodes the data by, for example, the MPEG2 system. The code amount of the audio data is controlled by a code amount control signal S212 from the CPU 211. The encoded audio data A211 is sent to the encoded audio data buffer 217. When the encoding is completed, the audio encoding circuit 216 notifies the CPU 211 of an encoding completion notification S222. At that time, the encoded data size (encoded bit amount) and the decoding time stamp are also notified.

  The CPU 211 is defined by the MPEG2 system transport stream based on the encoding completion notifications S221 and S222 from the video encoding circuit 213 and the audio encoding circuit 216 and the information sent from the respective encoding circuits. Determine how to generate the signal sequence. Based on this, it is determined what TS packet should be generated at the present time.

  If the determination result is generation of a video packet, the CPU 211 transfers the encoded video data V211 from the encoded video data buffer 214 to the multiplexing circuit 219 and instructs the multiplexing circuit 219 to generate a video TS packet. At this time, the CPU 211 controls the switch circuit 223 to set the code amount of the encoded video data to be transferred.

  On the other hand, if the determination result is generation of an audio TS packet, the CPU 211 transfers the encoded audio data A211 from the encoded audio data buffer 217 to the multiplexing circuit 219, and the multiplexing circuit 219 transmits the audio TS packet. Directs generation. At this time, the CPU 211 controls the switch circuit 224 to set the code amount of the encoded audio data to be transferred.

  If the determination result is the generation timing of the PCR packet, the CPU 211 instructs the multiplexing circuit 219 to generate the PCR packet.

The multiplexing circuit 219 generates a video TS packet, an audio TS packet, and a PCR packet according to an instruction from the CPU 211. The multiplexing circuit 219 outputs a transport stream in which these TS packets are multiplexed. This transport stream is sent to the FIFO memory 220 and stored therein. The CPU 220 sequentially reads data from the FIFO memory 220, sends it as recording data WD 211 to the medium recording unit 221, and writes it to the memory card 222.
JP 2001-44957 A JP 2002-152161 A Japanese Patent Laid-Open No. 11-341056

  As described above, conventionally, based on the control of the CPU 211, the control of the code amount at the time of video encoding and audio encoding, the transfer control of encoded video data and encoded audio data, and the multiplexing to the transport stream Processing, recording control on a memory card, and the like are performed in parallel. Further, the CPU 211 performs not only these processes but also various processes such as a user I / F process, zoom / focus control, and exposure control in parallel.

  However, in a portable device such as a camcorder, it is desired that processing be performed by one CPU 211 because of demands for low cost, low power consumption, and device miniaturization. However, in order to cope with recent HD (High Definition) moving image shooting and high-speed moving image shooting, the control of the encoding bit amount becomes complicated, or the data transfer processing load increases due to the increase of the encoding bit amount. As a result, the load on the CPU 211 is increasing. Therefore, a high-speed CPU is required as the CPU 211. However, if a high-speed CPU is used as the CPU 211, the cost is increased, the power consumption is increased, and this is an obstacle to reduction in size and weight.

  On the other hand, as shown in FIG. 4, an encoded bit amount control circuit 331, a transport stream multiplexing schedule circuit 332, and a memory card write control circuit 333 are added so that each circuit is not controlled by the CPU 311. If the operation is enabled, the load on the CPU 311 can be reduced.

  In the camcorder having the configuration shown in FIG. 4, the CPU 311, the input video data buffer 312, the video encoding circuit 313, the encoded video data buffer 314, the input audio data buffer 315, the audio encoding circuit 316, and the encoding The audio data buffer 317, the multiplexing circuit 319, the FIFO memory 320, the encoded bit amount control circuit 331, the transport stream multiplexing schedule circuit 332, and the memory card write control circuit 333 are configured.

  In the configuration shown in FIG. 3, the CPU 211 controls the code amount of the video encoding circuit 213 and the audio encoding circuit 216. However, in the configuration shown in FIG. 4, the video encoding circuit 313 and the audio encoding circuit 316 include The encoded video data V311 and the encoded audio data A311 are generated, and the encoded bit amount control circuit 331 sends the encoded amount control signals S311 and S312 to the video encoding circuit 313 and the audio encoding circuit 316 without using the CPU 311. To control the amount of code.

  In the configuration shown in FIG. 3, the CPU 211 determines a method for generating a signal sequence defined by the transport stream of the MPEG2 system, controls the switch circuits 223 and 224, and encodes video data and audio data. In the configuration shown in FIG. 4, the transport stream multiplexing schedule circuit 332 receives the encoding completion notifications S321 and S322 and does not depend on the CPU 311. Control of transfer of encoded video data and encoded audio data is performed.

  In the configuration shown in FIG. 3, the medium recording unit 221 records recording data on the memory card 222 under the control of the CPU 211. However, in the configuration shown in FIG. The control circuit 333 controls writing of the write data WD 311 from the FIFO memory 320.

  As described above, dedicated hardware independent of the CPU 311 (encoded bit amount control circuit 331, transport stream, etc.) is used for controlling the amount of code, data transfer control for generating a transport stream, data recording control, and the like. If it is performed by the multiplexing schedule circuit 332 and the memory card writing control circuit 333), the CPU 311 can concentrate on processing such as user I / F processing, zoom / focus control, and exposure control. However, such a configuration has a drawback that the power consumption of the circuit increases and the flexibility of the system is lost.

  In the case where the flexibility of the system is given top priority, there is also a method in which all processes from the encoding process of the input data to the recording to the memory card are realized by software by the CPU process. In order to realize this, it is necessary to increase the CPU clock frequency and to construct a system with multiple CPUs. However, there are problems such as an increase in power consumption accompanying the increase in the frequency of the CPU clock and an increase in mounting area by mounting a plurality of CPUs on a circuit board (PCB).

  That is, it can be said that the system configuration is not suitable for a battery-driven portable device such as a camcorder. On the other hand, if no measures are taken by hardware, in order to reduce the CPU load, it is necessary to take measures to reduce the amount of transferred data between the circuits by controlling the amount of encoded data more than necessary. . However, if such measures are taken, there will be a problem that the quality level of the recorded image as a product is lowered.

  Therefore, the present invention has been made in view of the above-described problems, and reduces the burden on the CPU and keeps the system flexible when recording encoded video and audio data in the form of a transport stream. Another object of the present invention is to provide a video recording apparatus and a multiplexed data generation apparatus capable of reducing the cost.

The present invention proposes the following items in order to solve the above-described problems.
(1) The present invention includes an encoding circuit that encodes captured data to generate a plurality of encoded data, and a procedure for multiplexing the plurality of encoded data generated by the encoding circuit to obtain multiplexed data. A procedure setting circuit to be set and a multiplexing for generating multiplexed data by multiplexing a plurality of pieces of encoded data generated by the encoding circuit in a predetermined multiplexing format based on the procedure set by the procedure setting circuit An encoding circuit, a recording control unit that records the multiplexed data generated by the multiplexing circuit on a recording medium, the amount of encoded data generated by the encoding circuit, and the type of the recording medium And a control unit that controls different recording operations of the multiplexed data on the recording medium by the recording control unit.

  (2) In the imaging data recording apparatus according to (1), the control unit transmits a first control signal for controlling a generation amount of the encoded data to the encoding circuit, and the type of the recording medium In response, the imaging data recording apparatus is proposed, which is a microprocessor that transmits a second control signal for controlling different recording operations of the multiplexed data to the recording medium to the recording control unit. .

  (3) In the imaging data recording device according to (1) or (2), the procedure setting circuit includes at least the encoded data in the multiplexed data in order to multiplex the encoded data. An imaging data recording apparatus is proposed in which the setting of the timing of incorporation and the setting of the array of the encoded data in the multiplexed data are controlled.

  (4) According to the present invention, in the photographing data recording apparatus of (1) or (2), the control unit incorporates at least the encoded data into the multiplexed data in order to multiplex the encoded data. 3. The photographing data recording apparatus according to claim 1, wherein a third control signal for controlling timing setting and setting of an array of the encoded data in the multiplexed data is transmitted to the procedure setting circuit. is suggesting.

  (5) The present invention relates to the photographic data recording device according to (1) to (4), wherein the encoding circuit encodes video data included in the photographic data and generates video encoded data. And a second encoding circuit that encodes audio data included in the shooting data to generate audio encoded data, and the multiplexing circuit is based on the procedure set by the procedure setting circuit. The video encoded data generated by the first encoding circuit and the audio encoded data generated by the second encoding circuit are multiplexed by multiplexing in a multiplexing format defined by the transport stream of the MPEG2 system. An imaging data recording apparatus characterized by generating digitized data has been proposed.

  According to the present invention, there is an effect that the flexibility of the system can be maintained without increasing the burden on the microprocessor. Further, since the load on the microprocessor can be reduced, a high-speed microprocessor is not required, and there is an effect that a reduction in size, weight, power consumption, and cost can be achieved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the constituent elements in the present embodiment can be appropriately replaced with existing constituent elements and the like, and various variations including combinations with other existing constituent elements are possible. Therefore, the description of the present embodiment does not limit the contents of the invention described in the claims.

<First Embodiment>
FIG. 1 shows a configuration of a camcorder according to the present embodiment. As shown in FIG. 1, the camcorder of this embodiment includes a CPU 11, an input video data buffer 12, a video encoding circuit 13, an encoded video data buffer 14, an input audio data buffer 15, and an audio encoding circuit. 16, an encoded audio data buffer 17, a transport stream multiplexing schedule circuit 18, a multiplexing circuit 19, a FIFO memory 20, and a medium recording unit 21. In addition, a memory card (for example, an SD card) 22 is attached to the medium recording unit 21.

  The input video data buffer 12 temporarily stores captured video data. In the present embodiment, the input video data buffer 12 transfers video data to the video encoding circuit 13 in accordance with a request from the video encoding circuit 13.

  The video encoding circuit 13 encodes video data based on a method adopted by the camcorder. Here, for example, MPEG2 video data encoding is used as the video data encoding method. MPEG2 video data encoding is performed by combining interframe prediction, discrete cosine transform (DCT), quantization, and entropy encoding to combine Y (luminance), Cr (color difference RY), Cb ( Video data composed of color difference BY is compression-encoded.

  There are three types of MPEG2 picture types: I-picture (Intra-coded picture), B-picture (Bidirectionally-predictive-coded picture), and P-picture (Bidirectionally-predictive-coded picture). In the present embodiment, the video encoding circuit 13 receives the code amount control signal S11 from the CPU 11, and can control the code amount, that is, the generation amount of the encoded video data V11 to be generated.

  The video encoding circuit 13 reads out the video data from the input video data buffer 12 using the encoding start command from the CPU 11 as a trigger, encodes it according to the MPEG2 system, and generates encoded video data V11. The encoded video data V11 is sent to the encoded video data buffer 14. In the video encoding circuit 13, one encoded data V11 is generated for each image frame in the video data. When the encoding is completed, the video encoding circuit 13 notifies the transport stream multiplexing schedule circuit 18 of the encoding completion notification S21.

  The input audio data buffer 15 temporarily stores audio data. In the present embodiment, the input audio data buffer 15 transfers audio data to the audio encoding circuit 16 in accordance with a request from the audio encoding circuit 16.

  The audio encoding circuit 16 encodes audio data based on a method adopted by the camcorder. Here, for example, MPEG2 audio encoding is used as audio data encoding. In the present embodiment, the video encoding circuit 13 receives the code amount control signal S11 from the CPU 11, and can control the code amount, that is, the generation amount of the encoded video data V11 to be generated.

  The audio encoding circuit 16 reads audio data from the input audio data buffer 15 using an encoding start command from the CPU 11 as a trigger, and compresses and encodes the encoded audio using an encoding method employed by the camcorder, for example, the MPEG2 method. Data A11 is generated, and this encoded audio data A11 is sent to the encoded audio data buffer 17.

  In the audio encoding circuit 16, one encoded audio data A11 is generated every 20 milliseconds, for example. When the encoding is completed, the audio encoding circuit 16 notifies the transport stream multiplexing schedule circuit 18 of an encoding completion notification S22. At that time, the encoded data size (encoded bit amount) and the decoding time stamp are also notified.

  The transport stream multiplexing schedule circuit 18 receives encoding completion notifications S21 and S22 from the video encoding circuit 13 and the audio encoding circuit 16, and information output from the video encoding circuit 13 and the audio encoding circuit 16, respectively. Based on this, a method for generating a signal sequence defined by the transport stream of the MPEG2 system is determined. Here, the transport stream of the MPEG2 system is one of multiple signal formats, and is adopted as a multiple signal format applied to, for example, digital broadcasting.

  Its major feature is that individual streams such as video, audio, and data can be handled in a common signal format regardless of the type of application or transmission path and transmitted as a single stream. The transport stream is a signal sequence in which TS packets of a fixed length of 188 bytes are continuous, and each TS packet has 4 bytes having a packet identifier indicating the packet type (data type information such as video data and audio data). Packet header is added.

  That is, the transport stream multiplexing schedule circuit 18 generates a TS stream (video TS packet, audio TS packet, PCR packet, which will be described later) when generating the transport stream, and each TS packet in the transport stream. And the number of TS packets generated per unit time are determined. These generation methods in the signal sequence defined by the transport stream are determined by, for example, the ratio of the data amount of video data and the data amount of audio data. The transport stream multiplexing schedule circuit 18 determines which TS packet should be generated among the TS packets at this time, and sends a multiplexing control signal S31 to the multiplexing circuit 19.

  At this time, if the determination result is the generation of a video TS packet, the transport stream multiplexing schedule circuit 18 transfers the encoded video data V11 from the encoded video data buffer 14 to the multiplexing circuit 19, and the multiplexing circuit 19 A multiplexing control signal S31 is transmitted to instruct the generation of the video TS packet. Here, the video TS packet is a TS packet that encodes video data and forms a signal sequence of a transport stream.

  If the determination result is the generation of an audio TS packet, the transport stream multiplexing schedule circuit 18 transfers the encoded audio data A11 from the encoded audio data buffer 17 to the multiplexing circuit 19, and the multiplexing circuit A multiplexing control signal S31 for instructing generation of an audio TS packet is transmitted to 19. Here, the audio TS packet is a TS packet that encodes audio data and forms a signal sequence of a transport stream.

  Further, if the determination result is the generation timing of the PCR packet, the transport stream multiplexing schedule circuit 18 transmits a multiplexing control signal S31 instructing the multiplexing circuit 19 to generate the PCR packet. Here, a PCR (Program Clock Reference) packet is a packet having time information regarding data to be recorded, and this time information is used when reproducing the recorded data. In addition, PCR packets must be generated at time intervals within 100 milliseconds.

  In this embodiment, the transport stream multiplexing schedule circuit 18 performs scheduling, that is, generation timing of TS packets, arrangement of TS packets in the transport stream, and generation per unit time without being controlled by the CPU 11. It is a dedicated circuit that determines the number of TS packets to be processed. Data transfer from the encoded video data buffer 14 and the encoded audio data buffer 17 to the transport stream multiplexing schedule circuit 18 is performed without the CPU 11.

  For example, when the recording mode of the recording data recorded by the camcorder according to the present embodiment is the highest image quality mode, the video encoding amount of the video data by the video encoding circuit 13 is 4 Mbps or less, and the audio encoding circuit 16 It is assumed that the code amount for encoding data is 128 kbps or less.

  In this case, the transport stream multiplexing schedule circuit 18 performs scheduling so that the ratio of the number of video TS packets to the number of audio TS packets in the transport stream generated by the multiplexing circuit 19 is 33: 1. I do. That is, the multiplexing circuit 19 generates one video TS packet from one encoded video data V11 and one audio TS packet from one encoded audio data A11. When the stream multiplexing schedule circuit 16 transfers the encoded video data V11 33 times from the encoded video data buffer 14 by video encoding, the stream multiplexing schedule circuit 16 transfers the encoded audio data A11 once from the encoded audio data buffer 17. Schedule so that This prevents the encoded video data buffer 14 and the encoded audio data buffer 17 from overflowing.

  The multiplexing circuit 19 generates each TS packet (video TS packet, audio TS packet, PCR packet) based on the scheduling in the transport stream multiplexing schedule circuit 18. Each TS packet is generated by adding a packet header having a packet identifier indicating the type of packet to encoded video data V11, encoded audio data A11, or the like. Then, the multiplexing circuit 19 multiplexes these TS packets to generate an MPEG2 system transport stream.

  In the present embodiment, the multiplexing circuit 19 generates TS packets (video TS packet, audio TS packet, PCR packet) without being controlled by the CPU 11, and multiplexes these TS packets to obtain the MPEG2 system. It is a dedicated circuit for generating a transport stream.

  In the FIFO memory 20, the transport stream generated by the multiplexing circuit 19 is sequentially stored. The CPU 11 sequentially reads out data from the FIFO memory 20 and sends it to the CPU 11 as recording data WD11. The CPU 11 writes the recording data WD11 sent from the multiplexing circuit 19 by the medium recording unit 21 according to the recording format of the recording medium. Here, a memory card 22 is mounted as a recording medium, and the medium recording unit 21 writes a transport stream according to the recording format of the memory card 22.

  The CPU 11 controls the code amount in the video encoding circuit 13 and the audio encoding circuit 16 in parallel with the recording process to the memory card 22. Furthermore, the CPU 11 can perform user interface processing, zoom, focus control, exposure control, and other processes in parallel.

  As described above, in the present embodiment, the control of the code amount in the video encoding circuit 13 and the audio encoding circuit 16 is performed based on the control of the CPU 11 by the code amount control signals S11 and S12. Further, the control for recording the multiplexed data on the recording medium by different recording operations according to the type of the recording medium is executed based on the control of the CPU 11 by the recording control signal S13.

  On the other hand, from the video encoding circuit 13 to the multiplexing circuit 19 and the audio encoding circuit 16 such as a scheduling process in the transport stream multiplexing schedule circuit 18 and a transport stream generating process in the multiplexing circuit 19. To the multiplexing circuit 19 are performed without using the CPU 11. Thereby, the burden on the CPU 11 can be reduced and the system can be flexibly dealt with. In addition, since the load on the CPU 11 can be reduced, a high-speed CPU 11 is not required, and a reduction in size, weight, and power consumption can be achieved. This will be described below.

  First, focusing on the product specifications of the camcorder, the camcorder provides a plurality of recording modes (for example, the highest image quality mode, standard image quality mode, long-time recording mode, etc.), and the user can freely select them. I am doing so. This is to control the encoded bit amount as the processing of the camcorder. For example, in the case of video data, the product specifications such as 4 Mbps in the highest image quality mode, 2 Mbps in the standard image quality mode, and 1 Mbps in the long-time recording mode are determined as product specifications, and the encoding bit amount is controlled accordingly. I have to. The relationship between the recording mode and the set value of the encoded bit amount largely depends on experience and know-how.

  The recording quality and the recording time are in a trade-off relationship, and this set value is one factor that determines the quality of the product. For this reason, this setting is usually adjusted through trial and error until the final stage of product development. Considering such a situation, it can be said that it is desirable that the control of the encoded bit amount is realized by CPU processing as a system configuration for the camcorder.

  Recently, various recording media such as a memory card, an HDD (Hard Disk Drive), and a DVD (Digital Versatile Disc) -RAM have been developed. When considering a configuration suitable for a camcorder, it is important to make the system configuration compatible with these existing recording media and unknown recording media that will be developed in the future.

  However, depending on the recording medium, the file system to be used is different (for example, FAT file system or universal disk format (UDF)), the unit of the write data size is different (for example, writing in units of 512 bytes, There is a difference of (writing in units of 1024 bytes).

  In order to absorb such a difference and flexibly cope with the selection of a recording medium suitable for the product specification of the camcorder, it is better that the CPU performs a writing process on the recording medium. As a result, various file systems, write data sizes, and the like can be supported. With a single system configuration, it is possible to support both camcorders that record on a memory card and camcorders that record on a DVD-R.

  Further, a predetermined communication protocol is determined between the memory card (for example, an SD card) and the CPU. And a controller corresponding to this has been developed. Similarly, there is an ATA / ATAP host controller for communication between the HDD or CD drive and the CPU. Naturally, these can also be used as the medium recording unit 21 of the present embodiment.

  Also, in the present embodiment, even when using these controllers, the part that depends on the file system (control of write, read unit, control of data write, read (use of DMA, Program I / O, etc.)) It is important to perform control by CPU software. Accordingly, it is possible to flexibly cope with different file systems for each recording medium. The memory card controller and the ATA / ATAP controller may be included in the CPU, or may be connected to the outside of the CPU as a host controller LSI.

  On the other hand, in the data transfer from the encoded video data buffer 14 or the encoded audio data buffer 17 to the multiplexing circuit 19, it can be said that there is little need to consider flexibility. This is because the multiplexing method (transport stream, program stream, etc.) adopted in a certain camcorder is almost always adopted in succeeding models.

  In order to ensure compatibility of recorded data, adopting the same multiplexing method in the succeeding model is also beneficial for users who use camcorders. If the successor model is released and the multiplexing method is changed, the user cannot use the video assets recorded by the preceding model.

  As described above, since it is not necessary to support various multiplexing methods for multiplexing, the encoded video data buffer 14 and the encoded audio data buffer 17 to the multiplexing circuit 19 use the multiplexing method employed. Realized by a suitable dedicated circuit, the load on the CPU 11 is reduced.

  Also, multiplexing from the video encoding circuit 13 to the multiplexing circuit 19 and from the audio encoding circuit 16 such as scheduling processing in the transport stream multiplexing schedule circuit 18 and generation processing of the transport stream in the multiplexing circuit 19 is performed. The processing up to the circuit 19 may be possible to reduce the circuit scale and reduce power consumption by making a dedicated circuit suitable for the employed multiplexing method, compared to a circuit that can handle various multiplexing methods. Can also be expected.

  For the same reason, it is considered that a dedicated circuit is better for the input video data buffer 12 to the video encoding circuit 13 and the input audio data buffer 15 to the audio encoding circuit 16. That is, the encoding method once adopted is also adopted in the successor model. In addition, by using a dedicated circuit suitable for the employed encoding method, the circuit scale may be reduced compared to a circuit that can handle various encoding methods, and a reduction in power consumption can be expected.

<Second Embodiment>
FIG. 2 shows the configuration of the camcorder of this embodiment. As shown in FIG. 2, the camcorder of this embodiment includes a CPU 111, an input video data buffer 112, a video encoding circuit 113, an encoded video data buffer 114, an input audio data buffer 115, and an audio encoding circuit. 116, an encoded audio data buffer 117, a multiplexed data transfer circuit 118, a multiplexing circuit 119, a FIFO memory 120, and a medium recording unit 121. In addition, a memory card (for example, an SD card) 122 is attached to the medium recording unit 121.

  In the first embodiment, the transport stream multiplexing schedule circuit 18 is prepared, and the transport stream multiplexing schedule circuit 18 transfers data from the encoded video data buffer 14 and the encoded audio data buffer 17. Scheduling to be performed without using the CPU 11.

  On the other hand, in the present embodiment, scheduling processing is performed by the multiplexed data transfer circuit 118 under the control of the CPU 111. By determining the signal sequence generation method defined by the transport stream of the MPEG2 system by the CPU 111, the multiplexing schedule of the transport stream can be simplified. In this case, the load on the CPU 111 is expected to increase, but for the reason described later, this may not be a problem.

  The present embodiment will be described with reference to FIG. The difference between this embodiment and the first embodiment described above is that the transport stream multiplexing schedule circuit 18 is eliminated and a multiplexed data transfer circuit 118 is added. Along with this, signal connection is also changed.

  That is, in FIG. 2, the input video data buffer 112 temporarily stores captured video data. The input video data buffer 112 transfers video data to the video encoding circuit 113 in accordance with a request from the video encoding circuit 113.

  The video encoding circuit 113 encodes video data based on a method adopted by the camcorder. Here, for example, MPEG2 video data encoding is used as the video data encoding method. The video encoding circuit 113 can control the code amount in response to the code amount control signal S111 from the CPU 11.

  The video encoding circuit 113 reads out the video data from the input video data buffer 112 using the encoding start command from the CPU 111 as a trigger, encodes it according to the MPEG2 system, and stores the encoded video data V111 in the encoded video data buffer 114. send. When the encoding is completed, the video encoding circuit 113 notifies the CPU 111 of an encoding completion notification S121. At that time, the encoded data size (encoded bit amount), picture type, and decoding time stamp are also notified.

  The input audio data buffer 115 temporarily stores audio data. The input audio data buffer 115 transfers the audio data to the audio encoding circuit 116 in accordance with a request from the audio encoding circuit 16.

  The audio encoding circuit 116 encodes audio data based on a method adopted by the camcorder. Here, for example, MPEG2 audio encoding is used as audio data encoding. The audio encoding circuit 116 can control the code amount in response to the code amount control signal S112 from the CPU 111.

  The audio encoding circuit 116 reads out the audio data from the input audio data buffer 115 using the encoding start command from the CPU 11 as a trigger, performs compression encoding using an encoding method employed by the camcorder, for example, the MPEG2 method, and this encoding. The audio data A111 is sent to the encoded audio data buffer 117. When the encoding is completed, the audio encoding circuit 116 notifies the CPU 111 of an encoding completion notification S122. At that time, the encoded data size (encoded bit amount) and the decoding time stamp are also notified.

  Thus, in the present embodiment, the encoded data size information and the encoding completion notification S121 are transmitted from the video encoding circuit 113 to the CPU 111, and the encoded data size information and the encoding code are transmitted from the audio encoding circuit 116 to the CPU 111. Notification of the completion of notification S122. Then, the CPU 111 grasps the data amount of the transport stream generated by the multiplexing circuit 119 based on the notified encoded data size and encoding completion notification. The CPU 111 also knows the storage capacity of the memory card 122. The CPU 111 compares the data amount of the transport stream and the storage capacity of the memory card 122, and determines the compression rate of the encoding (the amount of data before encoding and the data data after encoding). In order to adjust the amount ratio), the code amount control signal S111 is transmitted to the video encoding circuit 113, and the code amount control signal S112 is transmitted to the audio encoding circuit 116.

  The video encoding circuit 113 and the audio encoding circuit 116 receive the code amount control signals S111 and S112 from the CPU 111 and increase the compression rate of the data by encoding, so that the transport stream generated by the multiplexing circuit 119 is generated. It is possible to reduce the data amount so that the data amount of the transport stream fits in the storage capacity of the memory card 122.

  Further, the CPU 111 determines a signal sequence generation method defined by the transport stream of the MPEG2 system based on these pieces of information. Based on this, the CPU 111 determines what kind of TS packet should be generated at this time, and based on this, transmits the multiplexing control signal S131.

  Here, if the determination result is generation of a video TS packet, the CPU 111 transmits a multiplexed control signal S131 for generating a video TS packet to the multiplexed data transfer circuit 118 and the multiplexing circuit 119. Further, when instructing the generation of a video TS packet, the CPU 111 also designates the total number of bytes of data to be converted into a TS packet.

  If the determination result is generation of an audio TS packet, the CPU 111 transmits a multiplexing control signal S131 for generating an audio TS packet to the multiplexed data transfer circuit 118 and the multiplexing circuit 119. Further, when instructing generation of an audio TS packet, the CPU 111 also specifies the total number of bytes of data to be converted into a TS packet.

  Further, if the determination result is the PCR packet generation timing, the CPU 111 transmits a multiplexing control signal S131 for instructing the multiplexing circuit 119 to generate the PCR packet.

  A TS packet is a packet of 188 bytes, of which 4 bytes are included in the header. Therefore, the CPU 111 designates the data amount that is an integral multiple of 188−4 = 184 bytes as the total number of bytes of data to be TS packetized.

  When the multiplexed data transfer circuit 118 receives an instruction to generate a video TS packet from the CPU 111, the multiplexed data transfer circuit 118 reads out the encoded video data V 111 for the total number of bytes designated by the CPU 111 from the encoded video data buffer 114. And transferred to the multiplexing circuit 119. Upon receiving an instruction to generate a video TS packet from the CPU 111, the multiplexing circuit 119 waits for the video encoded data to be transferred from the multiplexed data transfer circuit 118, and generates a video TS packet after receiving the data. To do.

  When the multiplexed data transfer circuit 118 receives an instruction to generate an audio TS packet from the CPU 111, the multiplexed data transfer circuit 118 reads out the data corresponding to the total number of bytes designated by the CPU 111 from the encoded audio data buffer 117, and the multiplexing circuit Forward to 119. When the multiplexing circuit 119 receives an instruction to generate an audio TS packet from the CPU 111, the multiplexing circuit 119 waits for the encoded audio data A111 to be transferred from the multiplexed data transfer circuit 118, and receives the audio TS packet after receiving the data. Generate.

  Here, when generating either a video TS packet or an audio TS packet, the total number of bytes specified by the CPU 111 may not be reached. The encoded data to be TS packetized is a PES packet, which is not always an integral multiple of 184 bytes. Therefore, at the final end of the PES packet, the transfer data to the multiplexing circuit 119 is not an integral multiple of 184 bytes, and the data is insufficient. Here, a PES (Packetized Elementary Stream) packet is a packet obtained by dividing encoded audio data and encoded audio data into appropriate sizes. A packet obtained by adding a packet header or the like to a PES packet is a TS packet.

  In such a case, the multiplexed data transfer circuit 118 notifies the multiplexing circuit 119 of the lack of PES packet data, and also notifies the number of missing bytes less than 184 bytes. When this notification is received by the multiplexing circuit 119, a TS packet with a packet header corresponding to the number of insufficient bytes is filled with stuffing bytes.

  The transport stream TS packet generated in this way is stored in the FIFO memory 120 and then recorded in the medium recording unit 121 as the recording data WD111 based on the control of the CPU 111, as in the first embodiment. Sent to the memory card 122 by the medium recording unit 121.

  In the present embodiment, the CPU 111 determines a transboat stream generation method. Such a configuration provides the following advantages.

  In the first embodiment described above, it is assumed that a transport stream is generated. However, not all camcorders use transport streams. For example, the MP4 file format of ISO / IEC 14496-12 may be adopted.

  One TS packet of the transport stream is in units of 188 bytes, but the BOX in the MP4 file format has a larger unit (for example, video encoded data for 1 second and audio encoded data for 1 second). In this case, there are various types of BOX), and it may be possible for the CPU to determine the file format generation method. That is, the frequency with which the CPU determines the file format generation method can be reduced. In the above example, it may be determined every second.

  However, even in such a case, it is necessary to reduce the load on the CPU 111 by designating the transfer size from the CPU 111 and performing the transfer process itself by the multiplexed data transfer circuit 118.

  In the first embodiment and the present embodiment described above, the transport stream and MP4 file format of the MPEG2 system have been described as examples, but the present invention does not depend on the multiplexing method.

  In the first embodiment and the present embodiment described above, the recording medium is a memory card (for example, an SD card), but the present invention does not depend on the type of the recording medium.

  In the first embodiment and the present embodiment, the case of a camcorder is taken as an example. However, the present invention is effective when applied to a device that records recorded data on a recording medium that operates with low power consumption. There is something.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications and applications are possible without departing from the gist of the present invention.

1 is a block diagram of a camcorder according to a first embodiment of the present invention. It is a block diagram of the camcorder which concerns on the 2nd Embodiment of this invention. FIG. 11 is a block diagram illustrating an example of a conventional camcorder that records data using a transport stream of an MPEG2 system. FIG. 10 is a block diagram showing another example of a conventional camcorder that records data in the transport stream of the MPEG2 system.

Explanation of symbols

11, 111, 211, 311 ... CPU,
12, 112, 212, 312 ... input video data buffer,
13, 113, 213, 313 ... video encoding circuit,
14, 114, 214, 314 ... encoded video data buffer,
15, 115, 215, 315... Input audio data buffer,
16, 116, 216, 316 ... audio encoding circuit,
17, 117, 217, 317 ... encoded audio data buffer,
18, 332... Transport stream multiplexing schedule circuit,
19, 119, 219, 319 ... multiplexing circuit,
20, 120, 220, 320 ... FIFO memory,
21, 121, 221... Medium recording section,
22, 122, 222, 322 ... memory card,
223, 224 ... switch circuit,
331... Encoded bit amount control circuit,
333: Write control circuit

Claims (5)

An encoding circuit that encodes shooting data to generate a plurality of encoded data;
A procedure setting circuit for setting a procedure for multiplexing a plurality of pieces of encoded data generated by the encoding circuit to obtain multiplexed data;
A multiplexing circuit that multiplexes a plurality of encoded data generated by the encoding circuit based on a procedure set by the procedure setting circuit in a predetermined multiplexing format to generate multiplexed data;
A recording control unit for recording the multiplexed data generated by the multiplexing circuit on a recording medium;
A control unit for controlling a generation amount of encoded data generated by the encoding circuit and a different recording operation of the multiplexed data on the recording medium by the recording control unit according to a type of the recording medium; ,
An imaging data recording apparatus comprising: The controller is
Transmitting a first control signal for controlling a generation amount of the encoded data to the encoding circuit;
2. The microprocessor according to claim 1, wherein the microprocessor transmits a second control signal for controlling a different recording operation of the multiplexed data to the recording medium according to a type of the recording medium to the recording control unit. Shooting data recording device.   The procedure setting circuit controls at least setting of a timing for incorporating the encoded data into the multiplexed data and setting of an array of the encoded data in the multiplexed data in order to multiplex the encoded data. The photographing data recording apparatus according to claim 1 or 2, wherein   In order to multiplex the encoded data, the control unit controls at least a setting of a timing for incorporating the encoded data into the multiplexed data and a setting of an array of the encoded data in the multiplexed data. 3. The photographing data recording apparatus according to claim 1, wherein a third control signal is transmitted to the procedure setting circuit. The encoding circuit includes:
A first encoding circuit that encodes video data included in the shooting data and generates video encoded data;
A second encoding circuit that encodes audio data included in the photographed data to generate audio encoded data;
The multiplexing circuit includes: video encoded data generated by the first encoding circuit and audio encoded data generated by the second encoding circuit based on the procedure set by the procedure setting circuit. 5. The photographing data recording apparatus according to claim 1, wherein multiplexed data is generated by multiplexing in a multiplexing format defined by a transport stream of the MPEG2 system.

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