JP2009037321A - Transfer quantity control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently control a bus without correcting any circuit at an IP macro or a bus arbiter side in a system in which a plurality of functional blocks can perform access through a bus to a common resource. <P>SOLUTION: A transfer quantity control device 1 is inserted between an access request source 2 and a memory bus (bus arbiter) 3. A one frame period transfer quantity observing part 11 observes the transfer data quantity (cumulative value) of an access request source 2 in one frame period. Transferrable data quantity per unit time is specified in a transfer quantity schedule table 13, and an accumulation addition part 14 calculates the cumulative value. A subtracter 15 calculates the surplus data quantity of actual transfer data quantity (cumulative value) over transferable data quantity (cumulative value), and when the surplus data quantity exceeds the threshold of a threshold storage part 16, a request blocking circuit 18 blocks the transfer request of an access request source 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transfer amount control device that controls the amount of data transfer between a plurality of functional blocks and a bus, the occupation rate of the bus, and the like.

  In general, IP macros (designed circuit modules) that perform still image processing for digital cameras are often designed to complete processing in the shortest time. On the other hand, IP macros that perform moving image processing are often designed to perform processing over one frame period, that is, the entire period of 1/30 second or 1/60 second.

  When designing a moving image processing system in which these existing IP macros are newly integrated and the still image processing IP macro performs pre-processing or post-processing of the moving image processing IP macro, the still image processing IP macro Will operate in synchronization with the video processing. Therefore, if these IP macros are simply connected to the memory bus, the peak bandwidth may be insufficient during the operation of the still image processing IP macro.

  Conventionally, the bandwidth of the memory bus is increased, or the still picture processing IP macro circuit is modified to be compatible with a new system. However, in any case, since a large modification of the IP macro is required, a new design period and verification period occur. In addition, it may be necessary to change the type and grade of a memory element including a memory element connected to the outside of the LSI, such as SDRAM, and the advantage of diverting the IP macro is lost.

  Therefore, an access system has been proposed that adjusts the amount of access data for each data processing unit at a time in response to access requests to the memories of a plurality of data processing units. The access system includes a high-order image data processing unit with high priority that can access a shared resource, a low-order image data processing unit with low priority that can access the shared resource, and sharing by a high-order image data processing unit in one line period. An access request detecting means for detecting the number of access requests to the resource; a data amount determining means for determining the amount of data that the low-order image data processing unit can transfer within the line period according to the detected number of access requests; Transfer permission means for permitting data transfer based on the determined data amount in accordance with the priority order (see, for example, Patent Document 1).

JP 2000-330933 A (paragraph [0014])

  However, in the access system disclosed in Patent Document 1, the function for adjusting the access data amount is not optimized for a new application destination of an existing IP macro. However, there is no guarantee that the access data amount adjustment function works effectively. Therefore, even when this access system is used, there is a problem that it is necessary to modify an existing IP macro or a circuit on the bus arbiter side. Further, since the increase / decrease pattern of the transfer data amount in one frame period differs for each IP macro as in the above-described still image processing IP macro and moving image processing IP macro, the memory bus can be efficiently performed only by the conventional arbitration control. There is a problem that access to the Internet cannot be controlled.

  In order to solve the above-described problems caused by the prior art, the present invention provides a memory in which a plurality of functional blocks can access a common resource via a bus without modifying an IP macro or a circuit on the bus arbiter side. An object of the present invention is to provide a transfer amount control device capable of efficiently controlling a bus.

  In order to solve the above-described problems and achieve the object, a transfer amount control device according to the present invention has the following features. FIG. 1 is a diagram for explaining the principle of a transfer amount control apparatus according to the present invention.

  As shown in FIG. 1, the transfer amount control device 1 is connected between an access request source 2 composed of functional blocks such as an IP macro and a memory bus and bus arbiter (hereinafter referred to as a memory bus (bus arbiter)) 3. Inserted. The transfer amount control device 1 is supplied with a frame synchronization signal from, for example, a frame synchronization signal generator 4 present in the moving image processing LSI. The frame synchronization signal generator 4 may be built in the transfer amount control device 1. Further, a field synchronization signal may be used instead of the frame synchronization signal. In that case, in the description of this specification, the frame synchronization signal may be read as the field synchronization signal. A memory control unit 5 is connected to the memory bus (bus arbiter) 3.

  The logical request lines and data transfer procedures of the access request source 2 and the memory bus (bus arbiter) 3 to the transfer amount control device 1 are the same as the access request source without providing the transfer amount control device 1. This is the same as when 2 is directly connected to the memory bus (bus arbiter) 3. That is, the transfer amount control device 1 is transparent to the access request source 2 and the memory bus (bus arbiter) 3, and no circuit modification is required on either the IP macro side or the bus arbiter side.

  The transfer amount control apparatus 1 includes a 1-frame period transfer amount observation unit 11 that is a transfer amount observation unit, a 1-frame period counter 12, a transfer amount schedule table 13 that is a transfer amount schedule unit, a cumulative addition unit 14, and a subtraction that is a subtraction unit. 15, a threshold holding unit 16, a comparator 17, and a request cutoff circuit 18 that is a request cutoff unit. The one-frame period transfer amount observation unit 11 observes the amount of data transferred during one frame period between the access request source 2 and the memory bus (bus arbiter) 3. At that time, the one-frame period transfer amount observation unit 11 may observe the data transfer amount between the access request source 2 and the request cut-off circuit 18 as shown in the illustrated example. The amount of data transferred between the memory bus 18 and the memory bus (bus arbiter) 3 may be observed.

  The one frame period counter 12 measures the elapsed time during one frame period. In the transfer amount schedule table 13, the amount of data that can be transferred per unit time is defined corresponding to the count value of the one-frame period counter 12. The cumulative addition unit 14 cumulatively adds the output values of the transfer amount schedule table 13. The subtracter 15 subtracts the output value of the cumulative addition unit 14 from the output value of the 1 frame period transfer amount observation unit 11.

  The threshold value holding unit 16 holds a threshold value for blocking the transfer request of the access request source 2. The comparator 17 compares the output value of the subtracter 15 with the output value (threshold value) of the threshold holding unit 16. The request blocking circuit 18 blocks the transfer request from the access request source 2 based on the output value of the comparator 17.

  The transfer amount control device 1 operates as follows. When a frame synchronization signal is given from the frame synchronization signal generator 4, the 1-frame period transfer amount observation unit 11 and the 1-frame period counter 12 are initialized. Then, the one-frame period transfer amount observation unit 11 starts observing the data transfer amount between the access request source 2 and the memory bus (bus arbiter) 3. At the same time, the update of the count value of the one-frame period counter 12 is started.

  From the transfer amount schedule table 13, a transferable data amount corresponding to the count value at that time is output at a predetermined timing in accordance with the update of the count value of the one-frame period counter 12. The output value of the transfer amount schedule table 13 is cumulatively added by the cumulative addition unit 14. The output value of the cumulative adder 14 is the total amount of data that can be transferred between the access request source 2 and the memory bus (bus arbiter) 3 up to that point.

  Then, the subtracter 15 subtracts the total transferable data amount from the data transfer amount (cumulative value) observed by the one-frame period transfer amount observation unit 11. As a result, a portion of the actual data transfer amount (cumulative value) that exceeds the transfer schedule defined by the transfer amount schedule table 13 is obtained. Then, the comparator 17 compares the amount exceeding the transfer schedule with the threshold value of the threshold holding unit 16, and if the amount exceeding the transfer schedule exceeds the threshold value of the threshold holding unit 16, the request blocking circuit 18 causes the access request source 2 to The transfer request is blocked. As a result, data transfer between the access request source 2 and the memory bus (bus arbiter) 3 is stopped.

  The transfer amount control device 1 may be inserted between the memory bus (bus arbiter) 3 and all access request sources 2 connected thereto, or may be connected to the memory bus (bus arbiter) 3. It may be inserted only for the access request source 2 of the copy. FIG. 2 is a diagram showing an insertion example of the transfer amount control device according to the present invention. In the example illustrated in FIG. 2, the transfer amount control device 1 is inserted into the first access request source 6 and the second access request source 7, and the nth access request source 8 and the [n + 1] th access request source 7. The access request source 9 is not inserted.

  According to the transfer amount control device of the present invention, in a system in which a plurality of functional blocks can access a common resource via a bus, the bus can be efficiently connected without modifying an IP macro or a circuit on the bus arbiter side. There is an effect that it can be controlled.

  Exemplary embodiments of a transfer amount control apparatus according to the present invention will be explained below in detail with reference to the accompanying drawings. In the following description, the same components as those shown in FIG.

  FIG. 3 is a diagram showing the configuration of the transfer amount control apparatus according to the embodiment of the present invention. FIG. 4 is a diagram illustrating an example of the configuration of the 1-frame period transfer amount observation unit, and FIG. 5 is a diagram illustrating another example of the configuration of the 1-frame period transfer amount observation unit. FIG. 6 is a diagram illustrating an example of the configuration of a transfer amount schedule table, a control unit, an overflow range calculation unit, and a request cutoff circuit.

  As shown in FIG. 3, the transfer amount control device 21 includes a 1-frame period transfer amount observation unit 11, a 1-frame period counter 12, a scaler circuit 22 that is a scaler means, a transfer amount schedule table 23, a subtracter 15, and a control unit 24. , An overflow range calculation unit 25, a comparator 17, and a request cutoff circuit 18. The transfer amount control device 21 is transparent to the access request source 2 and the memory bus (bus arbiter) 3, and no circuit modification is required on either the IP macro side or the bus arbiter side.

  As shown in FIG. 4 or 5, the 1-frame period transfer amount observation unit 11 includes an observer 31 and a cumulative adder 32. In the example shown in FIG. 4, the observation device 31 observes an RW (read / write) data bus and a data control signal. Alternatively, as shown in FIG. 5, the observer 31 may observe a transfer request request signal, a parameter corresponding to the request, and a transfer request acceptance signal. The cumulative adder 32 cumulatively adds the observation values of the observer 31 and outputs the result. As shown in FIG. 3, in the present embodiment, a frame synchronization signal is input to the control unit 24 from the outside. The cumulative adder 32 of the one-frame period transfer amount observation unit 11 is initialized by the initialization signal output from the control unit 24 (see FIG. 4 or FIG. 5).

  As shown in FIGS. 3 and 6, the one-frame period counter 12 updates the count value in response to the input of the clock signal. The 1-frame period counter 12 is initialized by the initialization signal output from the control unit 24. The scaler circuit 22 multiplies the count value of the one-frame period counter 12 by the scaler value given from the control unit 24. This scaler value may be changed every frame period, or may be changed every fixed period shorter than one frame. The control unit 24 outputs a scaler value setting signal to the scaler circuit 22.

  The transfer amount schedule table 23 includes a transfer amount table 41, a threshold table 42, and a hysteresis table 43. The transfer amount table 41 has a function of combining the transfer amount schedule table 13 and the cumulative addition unit 14 shown in FIG. 1 and cumulatively adds the transferable data amount per unit time corresponding to the output value of the scaler circuit 22. And output. The subtracter 15 subtracts the output value of the transfer amount table 41 from the output value of the one frame period transfer amount observation unit 11.

  The threshold table 42 outputs a threshold corresponding to the output value of the scaler circuit 22. The hysteresis table 43 defines values for setting hysteresis with respect to a threshold for blocking or connecting the transfer request of the access request source 2, and outputs a hysteresis value corresponding to the output value of the scaler circuit 22. . The threshold value table 42, the hysteresis table 43, and the overflow range calculation unit 25 have the function of the threshold value holding unit 16 shown in FIG. Note that the threshold table 42, the hysteresis table 43, and the overflow range calculation unit 25 may be combined into a table.

  Each of the transfer amount table 41, the threshold value table 42, and the hysteresis table 43 has a plurality of different patterns. Each table is switched based on an instruction from an external host CPU (arithmetic processing unit) (not shown) connected to the host interface of the control unit 24. The control unit 24 outputs a table setting signal for switching the table to the transfer amount schedule table 23. The host CPU or the like appropriately switches the table used in the next frame and the scaler value based on the status of the entire system.

  Also, each table is based on the final result of one frame period, or the content of moving image processing, for example, MPEG (Moving Picture Experts Group) intra picture processing, one-way prediction picture processing, two-way prediction picture processing, encoding Switching is performed for each processing content such as decoding. The same applies to the scaler value. The scaler value is changed independently for each table.

  The overflow range calculation unit 25 includes an ON comparator value generation unit 44, an OFF comparator value generation unit 45, and a selector 46. Based on the output value of the threshold value table 42 and the output value of the hysteresis table 43, the ON comparator value generation unit 44 is a threshold value when the switch 48 of the request cutoff circuit 18 is ON (hereinafter referred to as an ON threshold value). Is generated. Based on the output value of the threshold value table 42 and the output value of the hysteresis table 43, the off comparator value generation unit 45 is a threshold value when the switch 48 of the request cutoff circuit 18 is off (hereinafter referred to as an off threshold value). Is generated.

  The selector 46 selects and outputs either the on threshold or the off threshold based on the hysteresis control signal given from the control unit 24. The control unit 24 uses the state observation unit 47 to observe the state of the switch 48 of the request cutoff circuit 18. When the switch 48 is in the on state, the selector 46 selects the on threshold value and the switch 48 is in the off state. In some cases, the selector 46 is controlled to select an off threshold.

  The comparator 17 compares the output value of the subtractor 15 with the output value (threshold value) of the selector 46 of the overflow range calculation unit 25, and based on the comparison result, an ON signal or an OFF signal is sent to the switch 48 of the request cutoff circuit 18. Is output. When the output signal of the comparator 17 is an OFF signal, the switch 48 cuts off the transfer request request signal, the parameter corresponding to the request, and the transfer request acceptance signal. When the output signal of the comparator 17 is an ON signal, the switch 48 passes the transfer request request signal, the parameter corresponding to the request, and the transfer request acceptance signal.

  FIG. 7 is a diagram for explaining the operation of the one-frame period transfer amount observation unit. As shown in FIG. 7, first, the one-frame period transfer amount observation unit 11 determines whether or not an initialization signal is input (step S1). When the initialization signal is input (step S1: Yes), the one-frame period transfer amount observation unit 11 initializes the value of the cumulative adder 32 (step S2) and returns to step S1. On the other hand, in the state where the initialization signal is not input (step S1: No), the 1-frame period transfer amount observation unit 11 determines the presence / absence of data transfer (step S3). If there is data transfer (step S3: Yes), the one-frame period transfer amount observation unit 11 cumulatively adds the data transfer amount by the cumulative adder 32 (step S4). If there is no data transfer (step S3: No), the process returns to step S1.

  FIG. 8 is a diagram for explaining operations of the request cutoff circuit, the control unit, the overflow range calculation unit, and the comparator. As shown in FIG. 8, first, the control unit 24 determines whether or not the request cutoff circuit 18 is in an on state (step S11). If it is in the ON state (step S11: Yes), the ON threshold value is output from the overflow range calculation unit 25 by the hysteresis control signal output from the control unit 24. Accordingly, the comparator 17 compares the ON threshold value with the output value of the subtractor 15 (step S12). On the other hand, if it is in the off state (step S11: No), the comparator 17 compares the off threshold value output from the overflow range calculation unit 25 with the output value of the subtractor 15 (step S13).

  Then, the comparator 17 determines whether or not the output value of the subtracter 15 exceeds the threshold value as a result of the comparison in step S12 or step S13 (step S14). When the threshold value is not exceeded (step S14: No), the comparator 17 outputs an ON signal and instructs the request cutoff circuit 18 to turn on (step S15). On the other hand, when the threshold value is exceeded (step S14: Yes), the comparator 17 outputs an off signal and instructs the request cutoff circuit 18 to turn off (step S16).

  Upon receiving the on signal or the off signal, the request cutoff circuit 18 switches the switch 48 on and off in units of data transfer transactions (step S17). Then, the process returns to step S11. As described above, by using the ON threshold value and the OFF threshold value smaller than the ON threshold value, it is possible to provide hysteresis for switching the request cutoff circuit 18 between ON and OFF. Therefore, once the request cutoff circuit 18 is turned off, it is possible to realize a function of stopping data transfer for a while, or once being turned on, allowing a certain amount of data transfer to some extent.

  FIG. 9 is a diagram for explaining the operation of the control unit, the one-frame period counter, and the one-frame period transfer amount observation unit. As shown in FIG. 8, first, the control unit 24 determines whether or not a frame synchronization signal has been input (step S21). If there is an input of a frame synchronization signal (step S21: Yes), the control unit 24 outputs an initialization signal. As a result, the value of the cumulative adder 32 of the one-frame period transfer amount observation unit 11 and the count value of the one-frame period counter 12 are initialized (step S22). Then, the process returns to step S21.

  On the other hand, if no frame synchronization signal is input (step S21: No), the control unit 24 observes the count value of the one-frame period counter 12, and determines whether or not the count value is equal to or greater than a preset threshold value. Is determined (step S23). If the count value is not greater than or equal to the threshold value (step S23: No), the process returns to step S21. If the count value is equal to or greater than the threshold value (step S23: Yes), the control unit 24 performs control so that the switch 48 of the request cutoff circuit 18 is always on (step S24). At that time, the control unit 24 initializes only the value of the cumulative adder 32 of the one-frame period transfer amount observation unit 11. Then, the process returns to step S21.

  Next, taking the case where the access request source of channel 0 (CH0) and the access request source of channel 1 (CH1) are respectively connected to the transfer amount control device having the above-described configuration, the transfer amount in each channel An example of a transfer schedule or transfer data amount realized by the control device will be described. FIG. 10 is a diagram illustrating repetition of the transfer schedule. As shown in FIG. 10, the transfer schedule 51 controlled by the transfer amount schedule table of channel 0 (CH 0) and the transfer schedule 52 controlled by the transfer amount schedule table of channel 1 (CH 1) are transmitted to the frame synchronization signal 53. Repeated synchronously.

  FIG. 11 is a diagram schematically showing a data transfer amount (cumulative value) when there is no transfer amount control device, and FIG. 12 is a schematic diagram showing a data transfer amount (cumulative value) when there is a transfer amount control device. FIG. In the example shown in FIGS. 11 and 12, channel 0 (CH0) is an IP macro (for example, an IP macro for moving image processing) designed to operate periodically at regular intervals with a frame synchronization signal as a base point. The channel 1 (CH1) is an IP macro designed to operate in the shortest processing time (for example, an IP macro for still image processing of a digital camera).

  In the example shown in FIG. 11, since data transfer is requested for both channel 0 (CH0) and channel 1 (CH1) in the period t1, the data transfer amount 54 of channel 0 (CH0) and channel 1 ( Both the data transfer amount 55 of CH1) are increasing. Therefore, there is a possibility that a peak band shortage occurs during the period t1. However, channel 0 (CH0) does not require data transfer in period t2. Further, the processing of channel 1 (CH1) is completed in the period t1.

  In this case, as in the example shown in FIG. 12, the transfer schedule of channel 1 (CH1) is transferred so that the data transfer amount 56 of channel 1 (CH1) decreases in period t1 and increases in the period t2. What is necessary is just to control by a quantity control apparatus. Then, the peak band in the period t1 can be suppressed.

  FIG. 13 is a diagram schematically illustrating a relationship between a transfer schedule and a data transfer amount by control using a threshold value. In FIG. 13, a solid line 57 represents a transfer schedule, and a dotted line 58 represents an actual data transfer amount. As described above, according to the transfer amount control device, when the actual data transfer amount exceeds the transfer schedule exceeds the threshold, the data transfer is stopped. Accordingly, for example, as shown by the reference numeral 59 in FIG. 13, the actual data transfer amount is allowed to exceed the transfer schedule by the threshold value.

  FIG. 14 is a diagram schematically illustrating the data transfer amount when the scaler control is applied. In FIG. 14, a solid line 60 represents a state in which the time axis of the transfer schedule is shortened when there is a margin in the band, and a dotted line 61 represents a state in which the time axis of the transfer schedule is expanded in a case where there is no bandwidth. Represents. The expansion and contraction of the time axis by the scaler function can be feedback controlled in a predetermined unit, for example, a frame unit. The scaler function can be used to absorb the change when the requested bandwidth changes due to sudden factors or the like with respect to the density of the data transfer amount assumed in advance in the transfer schedule.

  FIG. 15 is a diagram schematically showing a transfer schedule when switching according to picture types such as MPEG. As shown in FIG. 15, the transfer schedule 62 for channel 0 (CH0) and the transfer schedule 63 for channel 1 (CH1) correspond to the granularity in units of frames, that is, the change for the contents of rough processing. The table is switched in the order of a table, a table for two-way reference frames, a table for two-way reference frames, and a table for one-way reference frames. Note that table switching may be performed in accordance with an operation mode in which the characteristics of memory access greatly change.

  FIG. 16 is a diagram schematically illustrating a transfer schedule in the case of using a timing that is an integral multiple of the synchronization signal. In the example illustrated in FIG. 16, the cycle of the transfer schedule 65 of channel 1 (CH 1) is the same as that of the synchronization signal 53, whereas the cycle of the transfer schedule 64 of channel 0 (CH 0) is twice that of the synchronization signal 53. It is. Such an example corresponds to a case where a moving image display process is performed on channel 0 (CH0) and an even line and an odd line MPEG process are alternately performed on channel 1 (CH1).

  FIG. 17 is a diagram schematically showing a change in the transfer schedule by the scaler control. As shown in FIG. 17, the transfer schedule 66 of each frame changes due to the expansion and contraction of the time axis of each frame by the scaler function. FIG. 18 is a diagram schematically showing a change in the transfer schedule by the control using the threshold value. As shown in FIG. 18, the transfer schedule 67 of each frame changes by changing the threshold value of each frame.

  Here, the transfer schedule of each channel is designed in advance by a designer based on design level information such as the usage status of the bandwidth of the entire system, processing time, and processing flow. Also, parameters such as feedback control sensitivity and gain are determined so that dynamic fluctuations with respect to the designed transfer schedule can be absorbed by the scaler function. Note that after operation in the market, various tables and parameters such as feedback control sensitivity and gain can be rewritten by updating the firmware.

  As described above, according to the embodiment, by designating the transfer schedule of each channel according to the processing sequence in each channel and the amount of buffer of the access request source, the operation mode and usage status of the IP macro Accordingly, the bus can be finely controlled in units of frames while giving feedback on the overall balance. Therefore, the bus can be controlled efficiently. In addition, since the peak performance of each channel can be controlled for each operation mode or system, it is possible to avoid the occurrence of insufficient peak bandwidth. Furthermore, since the transfer amount control device 21 is transparently inserted between the access request source 2 and the memory bus (bus arbiter) 3, there is no need to modify the IP macro or the bus arbiter side circuit. Therefore, it is easy to mount and the IP macro divertability is improved.

(Supplementary note 1) Transfer amount observation means for observing the amount of data transferred during the reference period between the access request source and the bus arbiter,
A transfer amount schedule means for defining the amount of data that can be transferred between the access request source and the bus arbiter as a function of time;
Subtracting means for subtracting the transferable data amount obtained by the transfer amount schedule means from the transfer data amount obtained by the transfer amount observation means;
According to the result obtained by comparing the value obtained by the subtracting means and the threshold, the request blocking means for blocking the transfer request of the access request source and switching the connection;
A transfer amount control apparatus comprising:

  (Supplementary Note 2) When the value obtained by the subtracting unit exceeds the threshold value, the request blocking unit blocks the transfer request of the access request source, and when the value obtained by the subtracting unit falls below the threshold value The transfer amount control apparatus according to appendix 1, wherein the transfer request is made by the access request source.

  (Additional remark 3) The said transfer amount schedule means prescribes | regulates the schedule for 1 reference | standard period, and outputs the said schedule repeatedly synchronizing with a predetermined | prescribed timing signal, The transfer amount control of Additional remark 1 characterized by the above-mentioned apparatus.

  (Supplementary note 4) The transfer amount control device according to supplementary note 2, wherein the transfer amount scheduling means has a plurality of schedules, and performs switching of the schedule in synchronization with the timing signal.

  (Supplementary Note 5) The transfer amount control apparatus according to Supplementary Note 2 or 3, further comprising a scaler unit that changes a cycle of the timing signal.

  (Supplementary Note 6) The logical connection and data transfer procedures for the access request source and the bus arbiter are the same as those for connecting the access request source directly to the bus arbiter. The transfer amount control device according to any one of 1 to 4.

  As described above, the transfer amount control device according to the present invention is useful for a system in which a plurality of IP macros share one memory element, and particularly in a moving image processing system including a still image processing macro and a moving image processing macro. Is suitable.

It is a figure explaining the principle of the transfer amount control apparatus concerning this invention. It is a figure which shows the example of insertion of the transfer amount control apparatus concerning this invention. It is a figure which shows the structure of the transfer amount control apparatus concerning embodiment of this invention. It is a figure which shows an example of a structure of the 1 frame period transfer amount observation part. It is a figure which shows the other example of a structure of the 1 frame period transfer amount observation part. It is a figure which shows an example of a structure of the principal part containing a transfer amount schedule table and an overflow range calculation part. It is a figure explaining operation | movement of the 1 frame period transfer amount observation part. It is a figure explaining operation | movement of a request | requirement interruption | blocking circuit, a control part, an overflow range calculation part, and a comparator. It is a figure explaining operation | movement of a control part, 1 frame period counter, and 1 frame period transfer amount observation part. It is a figure explaining repetition of a transfer schedule. It is a figure which shows typically the data transfer amount when there is no transfer amount control apparatus. It is a figure which shows typically the data transfer amount in case there exists a transfer amount control apparatus. It is a figure which shows typically the relationship between the transfer schedule by control using a threshold value, and data transfer amount. It is a figure which shows typically the data transfer amount in the case of applying scaler control. It is a figure which shows typically the transfer schedule in the case of switching according to picture types, such as MPEG. It is a figure which shows typically the transfer schedule in the case of using the integral multiple of a synchronizing signal. It is a figure which shows typically the change of the transfer schedule by scaler control. It is a figure which shows typically the change of the transfer schedule by control using a threshold value.

Explanation of symbols

1, 21 Transfer amount control device 2 Access request source 3 Bus arbiter 13, Transfer amount schedule table 15 Subtractor 18 Request cut-off circuit 22 Scaler circuit

Claims (5)

A transfer amount observation means for observing the amount of data transferred during the reference period between the access request source and the bus arbiter;
A transfer amount schedule means for defining the amount of data that can be transferred between the access request source and the bus arbiter as a function of time;
Subtracting means for subtracting the transferable data amount obtained by the transfer amount schedule means from the transfer data amount obtained by the transfer amount observation means;
According to the result obtained by comparing the value obtained by the subtracting means and the threshold, the request blocking means for blocking the transfer request of the access request source and switching the connection;
A transfer amount control apparatus comprising:   The request blocking means blocks the transfer request of the access request source when the value obtained by the subtraction means exceeds the threshold value, and the access request source when the value obtained by the subtraction means falls below the threshold value The transfer amount control apparatus according to claim 1, wherein the transfer request is made.   2. The transfer amount control apparatus according to claim 1, wherein the transfer amount schedule means defines a schedule for one reference period, and repeatedly outputs the schedule in synchronization with a predetermined timing signal.   3. The transfer amount control apparatus according to claim 2, wherein the transfer amount schedule unit has a plurality of schedules, and performs schedule switching in synchronization with the timing signal. 4. The transfer amount control apparatus according to claim 2, further comprising scaler means for changing a cycle of the timing signal.

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