JP2009033580A - Gamma correcting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gamma correcting circuit capable of securing the amplitude of a picture signal and capable of improving an intermediate intensity. <P>SOLUTION: A fundamental constituent signal proportional to Vin and an enhancement constituent signal which is changed by a gain larger than the Vin are produced based on an input picture signal Vin. A differential amplifier circuit 4 produces current Idf in accordance with a difference between the Vin and a reference voltage Vp, as the enhancement constituent signal. When the terminal voltage Ven of a resistor Rr in accordance with the current Idf has exceeded a Vh, a limiter circuit 6 is operated to suppress the increase of the Idf and mitigate the change of the Ven. An addition circuit 8 effects the summing composite of the fundamental constituent signal and the Ven to produce an output picture signal Vout. According to this operation, the Vout can be increased within the range of intermediate level of the Vin while securing the amplitude of Vout with respect to the maximum input level. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a gamma correction circuit that performs gradation correction when an image is displayed on a display device such as a television receiver based on an image signal.

  FIG. 6 is a circuit diagram of a conventional gamma correction circuit. The input image signal Vin is input to the base of the npn transistor Q1. Q1 constitutes a buffer circuit, and in a range where Vin is low, a voltage signal generated at the emitter of Q1 and proportional to Vin is taken out from the output terminal OUT as an output image signal Vout via the resistor R2. A current path including a resistor R3 and a pnp transistor Q2 is provided between the output terminal OUT and the ground potential GND. Q2 is turned on in a region where Vout exceeds the base voltage Vb of Q2, and a current flows through R2 via R3. As a result, when Vin exceeds a certain threshold value, a voltage drop occurs at R2 by turning on Q2, and the rise of Vout is suppressed accordingly. As a result, as shown in FIG. 7, the change in Vout with respect to Vin has a limiter characteristic in which the slope decreases in a region where Vin is high. In this circuit, the limiter characteristic can be changed in accordance with Vb. As Vb is set lower, Vin at which the suppression of the rise in Vout is started decreases, and Vout is suppressed to a lower voltage.

As described above, the gradation correction corresponding to the nonlinear input / output characteristics of the display device can be achieved by suppressing the change in the image signal level in the high luminance region and performing the image display using the obtained Vout.
JP-A-7-74984

  In gamma correction that simply uses a limiter circuit and suppresses Vout in the high Vin region, there are problems that the amplitude of the image signal decreases as the limiter is applied more strongly, and the gradation at the intermediate level cannot be adjusted.

  The present invention has been made in order to solve the above-described problems, and it is preferable that the amplitude of the image signal is ensured with a simple circuit configuration, the dynamic range of the display device can be effectively used, and the intermediate luminance is improved. An object of the present invention is to provide a gamma correction circuit that enables image reproduction.

  The gamma correction circuit according to the present invention includes an enhancement component generator that generates an enhancement component signal that changes with an enhancement gain larger than a predetermined reference gain with respect to a change in the signal level of the input image signal, and the enhancement component signal is a predetermined value. A limiter unit that operates when an upper limit level is exceeded and generates a suppression emphasis component signal that suppresses changes in the emphasis component signal above the upper limit level, and a basic component that is proportional to the signal level of the input image signal with the reference gain A combining unit that adds and combines the suppression emphasis component signal to the signal to generate an output image signal.

  According to the present invention, the basic component signal changes with a predetermined reference gain over the entire range of the input image signal, and the reference gain is set according to the desired amplitude of the output image signal, thereby the amplitude of the image signal. Is secured. By adding and combining this basic component signal with a suppression enhancement component signal having a value that exceeds the basic component signal in the intermediate region of the input image signal, the intermediate luminance is improved.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic circuit diagram showing a schematic configuration of a gamma correction circuit according to an embodiment of the present invention. The gamma correction circuit 2 includes a differential amplifier circuit 4, a limiter circuit 6, and an adder circuit 8. The gamma correction circuit 2 performs a process of converting the signal level on the image signal Vin input to the input terminal IN, and the obtained image signal Vout is output from the output terminal OUT, for example, a CRT (Cathode Ray Tube: cathode ray tube). ) Etc. to the display device.

  The differential amplifier circuit 4 receives the input image signal Vin and the reference voltage Vp from the reference voltage circuit 10, and is basically proportional to the voltage difference (Vin−Vp) when Vin exceeds Vp. Output current Idf. Idf can be increased or decreased according to the driving capability of the current generating circuit 12, and the driving capability is switched by the control signal Sg. The reference voltage circuit 10 is configured to be able to change Vp according to the control signal Sp.

  The output terminal of the differential amplifier circuit 4 is connected to one end of the resistor Rr. The potential Ven at the one end of Rr is input to the adder circuit 8. The other end of Rr is connected to GND through transistor Qr. The transistor Qr basically keeps the on state, allows Idf to flow to GND, and sets the potential of the other end of Rr connected to the emitter to a potential corresponding to Vin applied to the base.

  A limiter circuit 6 is connected to the output terminal of the differential amplifier circuit 4. The limiter circuit 6 includes a transistor Qlm and a voltage source 14. Qlm has an emitter connected to the output terminal of the differential amplifier circuit 4, a collector connected to GND, and a predetermined voltage Vh applied from the voltage source 14 to the base. Qlm is an npn transistor, which is turned on when the potential of the output terminal of the differential amplifier circuit 4 exceeds Vh and bypasses a part of Idf. Vh is set higher than Vp.

  When Vin is equal to or lower than Vp, Idf basically does not flow, and the limiter circuit 6 does not operate, so Ven basically becomes the potential of the emitter of Qr. That is, in the region where the input image signal Vin is Vin ≦ Vp, Ven is a potential corresponding to Vin.

  When Vin exceeds Vp, Ven becomes higher than the emitter potential of Qr by the amount of potential difference Vr generated at both ends of Rr. That is, in a region where Ven <Vh where the input image signal Vin is Vin> Vp and the limiter circuit 6 does not operate, Ven changes with a steeper slope than Vin ≦ Vp with respect to a change in Vin.

  When Ven exceeds Vp, the limiter circuit 6 operates, and the change in Ven with respect to the change in Vin becomes gentler than in the above-described region where Vin ≦ Vp and Ven <Vh.

FIG. 2 is a schematic graph showing a change in Ven with respect to Vin. FIG. 2 shows Ven characteristic curves 20-1 to 20-3 for three types of Vp values. Characteristic curves 20-1 to 20-3 represent cases where Vp is α _{1 to} α ₃ (α ₁ <α ₂ <α ₃ ), respectively. As shown in this figure, for example, the slope k of the characteristic curve 20-1, the Vin ≦ alpha ₁ for example, is a k = 1, the k> 1 exceeds alpha _1. The state in which the slope k is large is maintained until Ven reaches β corresponding to Vr, and when the limiter circuit 6 reaches β, the limiter circuit 6 starts to operate, so that the slope k decreases. For example, k becomes smaller than 1. Configured. Thereby, the amount that Ven exceeds Vin is larger in the intermediate region than in the region where Vin is small or large.

  The adder circuit 8 adds and synthesizes Vin and Ven to generate an output image signal Vout. For example, the adding circuit 8 adds and synthesizes Vin and Ven so that Vout becomes Vmax when Vin is the maximum value Vmax. For example, the addition circuit 8 can be configured to perform addition synthesis such that Vout is (1/2) Vin + (1/2) Ven, and FIG. 3 shows a change in Vout with respect to Vin in this case. It is a typical graph. FIG. 3 shows Vout characteristic curves 22-1 to 22-3 corresponding to the Ven characteristic curves 20-1 to 20-3 of FIG. The change in Vout with respect to the change in Vin has the same characteristics as the change in Ven, and basically takes a value corresponding to Vin in a region where Vin is smaller than Vp. After reaching the point where the operation starts, the slope becomes gentle.

  FIG. 4 is a circuit diagram showing an example of a specific configuration of the gamma correction circuit 2. The differential amplifier circuit 4 includes transistors Q1 and Q2 connected in parallel with each other between a power supply Vcc and a common current source 30. Vin is applied to the base of Q1, and Vp generated by the reference voltage circuit 10 is applied to the base of Q2. The differential amplifier circuit 4 is configured to operate in a linear region. When Vin> Vp, a current Iff0 proportional to Vin−Vp is generated in the path on the Q1 side.

  The reference voltage circuit 10 divides Vcc by resistance to generate Vp. Specifically, the reference voltage circuit 10 includes a resistor R1 having one end connected to Vcc, resistors R2 to R4 connected in parallel between the other end of R1 and GND, and the resistors R2 to R4. Are connected in series, and the potential at the other end of R1 is applied to Q2 as Vp. SW1 to SW3 can be individually controlled by the control signal Sp. The reference voltage circuit 10 can change the combined resistance value between R1 and GND and change Vp by the combination of ON / OFF of SW1 to SW3.

  A transistor Q3 is connected between Q1 and Vcc. Q3 constitutes the input side of the current mirror circuit, and transistors Q4 to Q6 constituting the output side of the current mirror circuit are connected in parallel to Q3. The emitters of Q4 to Q6 are connected to Vcc, and the collectors are connected to one end of a resistor Rr via switches SW4 to SW6, respectively.

  SW4 to SW6 are configured to be individually controllable on / off by a control signal Sg. Q4 to Q6 can generate mirror currents Im1 to Im3 corresponding to Iff0 flowing in Q3 in a state where the corresponding SW4 to SW6 are turned on, respectively. The generated Im1 to Im3 are combined and taken out as the output current Iff of the differential amplifier circuit 4. That is, Q4 to Q6 constituting the output side of the current mirror circuit correspond to the current generation circuit 12, and the driving capability thereof can be switched by a combination of ON / OFF of SW4 to SW6.

  As described in the description of FIG. 1, the limiter circuit 6 is connected to one end of the resistor Rr, and Qr is connected to the other end. Further, the potential Ven at one end of Rr is input to the adder circuit 8 via the transistor Q8.

  Adder circuit 8 has resistors R7 and R8 connected in series between the emitters of transistors Q7 and Q8. The series connection body of the resistors R7 and R8 substantially constitutes a synthesis unit that performs addition synthesis of Vin and Ven. On the other hand, transistors Q7 and Q8 each function as a buffer. Specifically, the collector of Q7 is connected to Vcc, the emitter is connected to GND via a resistor R5, and the base is connected to the input terminal IN. The collector of Q8 is connected to Vcc, the emitter is connected to GND through a resistor R6, and the base is connected to one end of Rr. The current path including Q7 and the current path including Q8 formed between Vcc and GND are basically symmetrical. Q7 and Q8 are basically configured to be in an on state. Q7 causes a potential change in the emitter proportional to Vin applied to the base, and an emitter voltage signal (basic component signal) corresponding to this Vin is input to one end of R7. In Q8, Ven is applied to the base, and an emitter voltage signal corresponding to this Ven is input to one end of R8. Here, due to the above-described amplification function of the differential amplifier circuit 4, Ven changes with a steeper slope than Vin when Vin exceeds Vp. Correspondingly, the emitter voltage of Q8 also has a larger gain than that of Q7 ( It changes with emphasis gain). Note that Ven varies with the emphasis gain in a range smaller than Vh (enhancement component signal), but when Ven is higher than Vh, the limiter circuit 6 starts operating and the gain is suppressed (suppression emphasis component signal).

  The series connection body of R7 and R8 combines the voltage signals of the emitters of Q7 and Q8 applied to both ends thereof, and generates a voltage obtained by proportionally dividing Vin and Ven by R7 and R8 at the connection point of R7 and R8. This connection point becomes the output terminal of the adder circuit 8 and the output terminal OUT of the gamma correction circuit 2. The synthesis ratio of Vin and Ven can be adjusted by the resistance values of R7 and R8. For example, by making the resistance values of R7 and R8 equal, the output image signal Vout obtained by adding and combining Vin and Ven at 1: 1 can be taken out from the output terminal OUT. For example, as described above, Ven in FIG. Corresponding to the non-linear input / output characteristics of the image signal as shown in FIG.

  Usually, the distribution of luminance values of pixels constituting an image has a peak on the relatively low side of the input signal level. Corresponding to this distribution, the gamma correction circuit 2 has a region (knee region) having a steep slope with respect to a relatively low input signal level range including its peak position, as shown by the characteristic curve 22 in FIG. On the other hand, a small slope is set in a relatively high input signal level range. In this intermediate region, Vout is made higher than Vin and the characteristic curve 22 is convex upward so that the amplitude of the image signal can be maintained, and a reproduced image that effectively utilizes the dynamic range of the display device. On the other hand, a large gradient is realized at a signal level with a high distribution of pixel values, so that gradation can be expressed favorably.

  Also, the low input signal level of the image signal includes noise components due to random noise, dark current, and the like. On the other hand, the gamma correction circuit 2 suppresses the slope of the characteristic curve 22 when Vin ≦ Vp, and suppresses the deterioration of the S / N (Signal to Noise ratio) due to the expansion of the signal level of the noise component. be able to.

  FIG. 5 is a schematic graph showing input / output characteristics of the gamma correction circuit 2 when the gain of Iff relative to Iff0 is changed by switching SW4 to SW6 by Sg. FIG. 5 shows a characteristic curve 22-1 shown in FIG. 3 and a characteristic curve 24 in which the gain of Idf is lowered with respect to the characteristic curve 22-1 at the same reference voltage Vp. In this way, the gamma correction circuit 2 can adjust the intermediate level gradation by the gain of Idf while suppressing a decrease in the signal amplitude.

  In the above-described embodiment, the voltage signal generated at the emitter based on Vin applied to the base of Q7 corresponds to the basic component signal proportional to the signal level of the input image signal Vin, but the basic component signal is Vin itself. It may be.

1 is a schematic circuit diagram showing a schematic configuration of a gamma correction circuit according to an embodiment of the present invention. It is a typical graph which shows the change of Ven with respect to the input image signal Vin. It is a typical graph which shows the input-output characteristic of the gamma correction circuit which is embodiment of this invention. It is a circuit diagram which shows an example of the specific structure of the gamma correction circuit which is embodiment of this invention. 4 is a schematic graph showing a difference in input / output characteristics depending on a gain of an output current of a differential amplifier circuit in a gamma correction circuit according to an embodiment of the present invention. It is a circuit diagram of the conventional gamma correction circuit. It is a graph which shows the input-output characteristic of the conventional gamma correction circuit.

Explanation of symbols

  2 gamma correction circuit, 4 differential amplifier circuit, 6 limiter circuit, 8 adder circuit, 10 reference voltage circuit, 12 current generation circuit, 14 voltage source, 30 current source.

Claims (4)

A gamma correction circuit for converting the signal level of an image signal,
An emphasis component generation unit that generates an emphasis component signal that changes with an emphasis gain larger than a predetermined reference gain with respect to a change in the signal level of the input image signal;
A limiter unit that operates when the enhancement component signal exceeds a predetermined upper limit level and generates a suppression enhancement component signal that suppresses a change in the enhancement component signal at the upper limit level or higher;
A synthesis unit that adds and synthesizes the suppression emphasis component signal to a basic component signal proportional to the signal level of the input image signal with the reference gain, and generates an output image signal;
A gamma correction circuit comprising: The gamma correction circuit according to claim 1,
The enhancement component generation unit changes the enhancement component signal with the enhancement gain in a state where the input image signal exceeds a predetermined reference level;
A gamma correction circuit characterized by. In the gamma correction circuit according to claim 1 or 2,
A gamma correction circuit configured to be able to control the reference level. The gamma correction circuit according to claim 1, wherein:
A gamma correction circuit configured to control the enhancement gain.

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